K40P100M100SF2
K40 Sub-Family Data Sheet
Supports the following:
MK40DN512ZVLL10
Features
•Operating Characteristics
–Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
•Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
•Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
•Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
•System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 63
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
•Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
•Human-machine interface
– Segment LCD controller supporting up to 40
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes, depending on the package size
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
•Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– 12-bit DAC
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
•Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
•Communication interfaces
– USB full-/low-speed On-the-Go controller with on-
chip transceiver
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Five UART modules
– Secure Digital host controller (SDHC)
– I2S module
Freescale Semiconductor Document Number: K40P100M100SF2
Data Sheet: Technical Data Rev. 7, 02/2013
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2011–2013 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3Terminology and guidelines......................................................5
3.1 Definition: Operating requirement......................................5
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................6
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................7
3.6 Relationship between ratings and operating
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
3.9 Typical value conditions....................................................9
4Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................10
4.3 ESD handling ratings.........................................................10
4.4 Voltage and current operating ratings...............................10
5 General.....................................................................................11
5.1 AC electrical characteristics..............................................11
5.2 Nonswitching electrical specifications...............................11
5.2.1 Voltage and current operating requirements......12
5.2.2 LVD and POR operating requirements...............13
5.2.3 Voltage and current operating behaviors............13
5.2.4 Power mode transition operating behaviors.......15
5.2.5 Power consumption operating behaviors............16
5.2.6 EMC radiated emissions operating behaviors....19
5.2.7 Designing with radiated emissions in mind.........20
5.2.8 Capacitance attributes........................................20
5.3 Switching specifications.....................................................20
5.3.1 Device clock specifications.................................20
5.3.2 General switching specifications.........................20
5.4 Thermal specifications.......................................................21
5.4.1 Thermal operating requirements.........................21
5.4.2 Thermal attributes...............................................22
6 Peripheral operating requirements and behaviors....................23
6.1 Core modules....................................................................23
6.1.1 Debug trace timing specifications.......................23
6.1.2 JTAG electricals..................................................23
6.2 System modules................................................................26
6.3 Clock modules...................................................................26
6.3.1 MCG specifications.............................................26
6.3.2 Oscillator electrical specifications.......................28
6.3.3 32 kHz Oscillator Electrical Characteristics........31
6.4 Memories and memory interfaces.....................................31
6.4.1 Flash electrical specifications.............................31
6.4.2 EzPort Switching Specifications.........................33
6.5 Security and integrity modules..........................................34
6.6 Analog...............................................................................34
6.6.1 ADC electrical specifications..............................34
6.6.2 CMP and 6-bit DAC electrical specifications......42
6.6.3 12-bit DAC electrical characteristics...................44
6.6.4 Voltage reference electrical specifications..........47
6.7 Timers................................................................................48
6.8 Communication interfaces.................................................48
6.8.1 USB electrical specifications...............................48
6.8.2 USB DCD electrical specifications......................49
6.8.3 USB VREG electrical specifications...................49
6.8.4 CAN switching specifications..............................50
6.8.5 DSPI switching specifications (limited voltage
range).................................................................50
6.8.6 DSPI switching specifications (full voltage
range).................................................................51
6.8.7 Inter-Integrated Circuit Interface (I2C) timing.....53
6.8.8 UART switching specifications............................54
6.8.9 SDHC specifications...........................................54
6.8.10 I2S switching specifications................................55
6.9 Human-machine interfaces (HMI)......................................58
6.9.1 TSI electrical specifications................................58
6.9.2 LCD electrical characteristics.............................59
7 Dimensions...............................................................................60
7.1 Obtaining package dimensions.........................................60
8 Pinout........................................................................................60
8.1 K40 Signal Multiplexing and Pin Assignments..................60
8.2 K40 Pinouts.......................................................................64
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
2 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK40 and MK40 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
K## Kinetis family • K40
A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
Ordering parts
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
4 Freescale Semiconductor, Inc.
Field Description Values
FFF Program flash memory size • 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB
R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK40DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
Terminology and guidelines
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 5
3.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
Terminology and guidelines
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
6 Freescale Semiconductor, Inc.
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
3.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Terminology and guidelines
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 7
3.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
Terminology and guidelines
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
8 Freescale Semiconductor, Inc.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
Terminology and guidelines
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 9
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
Solder temperature, leaded — 245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Ratings
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
10 Freescale Semiconductor, Inc.
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 185 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB_DP USB_DP input voltage –0.3 3.63 V
VUSB_DM USB_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 11
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICDIO Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V -5 — mA
1
IICAIO Analog2, EXTAL, and XTAL pin DC injection current —
single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
-5
—
—
+5
mA
3
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
-25
—
—
+25
mA
VODPU Open drain pullup voltage level VDD VDD V4
VRAM VDD voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
4. Open drain outputs must be pulled to VDD.
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
12 Freescale Semiconductor, Inc.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 13
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ.1Max. Unit Notes
VOH Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT Output high current total for all ports — — 100 mA
VOL Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
—
—
0.5
0.5
V
V
2
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — — 100 mA
IINA Input leakage current, analog pins and digital
pins configured as analog inputs
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
—
—
—
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
3, 4
IIND Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
• All digital pins
• VIN = VDD
• All digital pins except PTD7
• PTD7
—
—
—
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
4, 5
IIND Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
18
12
8
3
26
49
13
6
μA
μA
μA
μA
4, 5, 6
Table continues on the next page...
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
14 Freescale Semiconductor, Inc.
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ.1Max. Unit Notes
IIND Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
1
50
μA
4, 5
ZIND Input impedance examples, digital pins
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
4, 7
RPU Internal pullup resistors 20 35 50 kΩ 8
RPD Internal pulldown resistors 20 35 50 kΩ 9
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to VDD.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V.
8. Measured at VDD supply voltage = VDD min and Vinput = VSS
9. Measured at VDD supply voltage = VDD min and Vinput = VDD
+
–
Digital input
Source
ZIND
IIND
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 15
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
—
—
300
1.7 V / (VDD
slew rate)
μs 1
• VLLS1 → RUN — 134 μs
• VLLS2 → RUN — 96 μs
• VLLS3 → RUN — 96 μs
• LLS → RUN — 6.2 μs
• VLPS → RUN — 5.9 μs
• STOP → RUN — 5.9 μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
45
47
70
72
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
—
—
61
63
72
85
71
87
mA
mA
mA
3, 4
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 35 — mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
— 15 — mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— N/A — mA 6
Table continues on the next page...
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
16 Freescale Semiconductor, Inc.
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— N/A — mA 7
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
— N/A — mA 8
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.59
2.26
5.94
1.4
7.9
19.2
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
93
520
1350
435
2000
4000
μA
μA
μA
IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
4.8
28
126
20
68
270
μA
μA
μA
9
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
3.1
17
82
8.9
35
148
μA
μA
μA
9
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.2
7.1
41
5.4
12.5
125
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.1
6.2
30
7.6
13.5
46
μA
μA
μA
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.33
0.60
1.97
0.39
0.78
2.9
μA
μA
μA
Table continues on the next page...
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 17
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
—
—
—
0.71
1.01
2.82
0.84
1.17
3.16
0.81
1.3
4.3
0.94
1.5
4.6
μA
μA
μA
μA
μA
μA
10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral
clocks disabled.
3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash.
7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
9. Data reflects devices with 128 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
18 Freescale Semiconductor, Inc.
Figure 2. Run mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors as measured on 144LQFP and
144MAPBGA packages
Symbol Description Frequency
band (MHz)
144LQFP 144MAPBGA Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 23 12 dBμV 1 , 2
VRE2 Radiated emissions voltage, band 2 50–150 27 24 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 28 27 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 14 11 dBμV
VRE_IEC IEC level 0.15–1000 K K — 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 19
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock — 100 MHz
fSYS_USB System and core clock when Full Speed USB in
operation
20 — MHz
fBUS Bus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
20 Freescale Semiconductor, Inc.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
12
6
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
12
6
36
24
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
5.4 Thermal specifications
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 21
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
5.4.2 Thermal attributes
Board type Symbol Description 100 LQFP Unit Notes
Single-layer (1s) RθJA Thermal
resistance, junction
to ambient (natural
convection)
47 °C/W 1
Four-layer (2s2p) RθJA Thermal
resistance, junction
to ambient (natural
convection)
35 °C/W 1
Single-layer (1s) RθJMA Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
37 °C/W 1
Four-layer (2s2p) RθJMA Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
29 °C/W 1
— RθJB Thermal
resistance, junction
to board
20 °C/W 2
— RθJC Thermal
resistance, junction
to case
9 °C/W 3
—ΨJT Thermal
characterization
parameter, junction
to package top
outside center
(natural
convection)
2 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
General
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
22 Freescale Semiconductor, Inc.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 — ns
Twh High pulse width 2 — ns
TrClock and data rise time — 3 ns
TfClock and data fall time — 3 ns
TsData setup 3 — ns
ThData hold 2 — ns
Figure 3. TRACE_CLKOUT specifications
Th
Ts Ts Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 4. Trace data specifications
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 23
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
0
0
0
10
25
50
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
50
20
10
—
—
—
ns
ns
ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 0 — ns
J7 TCLK low to boundary scan output data valid — 25 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1 — ns
J11 TCLK low to TDO data valid — 17 ns
J12 TCLK low to TDO high-Z — 17 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
Table 14. JTAG full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
0
0
0
10
20
40
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
50
25
12.5
—
—
—
ns
ns
ns
J4 TCLK rise and fall times — 3 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
24 Freescale Semiconductor, Inc.
Table 14. JTAG full voltage range electricals (continued)
Symbol Description Min. Max. Unit
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 0 — ns
J7 TCLK low to boundary scan output data valid — 25 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns
J11 TCLK low to TDO data valid — 22.1 ns
J12 TCLK low to TDO high-Z — 22.1 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
J2
J3 J3
J4 J4
TCLK (input)
Figure 5. Test clock input timing
J7
J8
J7
J5 J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 6. Boundary scan (JTAG) timing
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 25
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 7. Test Access Port timing
J14
J13
TCLK
TRST
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
26 Freescale Semiconductor, Inc.
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) — user
trimmed — over fixed voltage and temperature
range of 0–70°C
31.25 — 38.2 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
— ± 0.3 ± 0.6 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
— ± 1.5 ± 4.5 %fdco 1
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
— 4 — MHz
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20 20.97 25 MHz 2, 3
Mid range (DRS=01)
1280 × ffll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × ffll_ref
80 83.89 100 MHz
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
— 23.99 — MHz 4, 5
Mid range (DRS=01)
1464 × ffll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × ffll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × ffll_ref
— 95.98 — MHz
Jcyc_fll FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
—
—
180
150
—
—
ps
tfll_acquire FLL target frequency acquisition time — — 1 ms 6
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 27
Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
PLL
fvco VCO operating frequency 48.0 — 100 MHz
Ipll PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
— 1060 — µA 7
Ipll PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
— 600 — µA 7
fpll_ref PLL reference frequency range 2.0 — 4.0 MHz
Jcyc_pll PLL period jitter (RMS)
• fvco = 48 MHz
• fvco = 100 MHz
—
—
120
50
—
—
ps
ps
8
Jacc_pll PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
• fvco = 100 MHz
—
—
1350
600
—
—
ps
ps
8
Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 %
Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 %
tpll_lock Lock detector detection time — — 150 × 10-6
+ 1075(1/
fpll_ref)
s9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
28 Freescale Semiconductor, Inc.
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
1.5
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 29
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 50 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
30 Freescale Semiconductor, Inc.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit
VBAT Supply voltage 1.71 — 3.6 V
RFInternal feedback resistor — 100 — MΩ
Cpara Parasitical capacitance of EXTAL32 and XTAL32 — 5 7 pF
Vpp1Peak-to-peak amplitude of oscillation — 0.6 — V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2 32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal — 32.768 — kHz
tstart Crystal start-up time — 1000 — ms 1
fec_extal32 Externally provided input clock frequency — 32.768 — kHz 2
vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 31
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversblk256k Erase Block high-voltage time for 256 KB — 416 3616 ms 1
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1blk256k
Read 1s Block execution time
• 256 KB program/data flash
—
—
1.7
ms
trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs
tersblk256k
Erase Flash Block execution time
• 256 KB program/data flash
—
435
3700
ms
2
tersscr Erase Flash Sector execution time — 14 114 ms 2
tpgmsec512
tpgmsec1k
tpgmsec2k
Program Section execution time
• 512 bytes flash
• 1 KB flash
• 2 KB flash
—
—
—
2.4
4.7
9.3
—
—
—
ms
ms
ms
trd1all Read 1s All Blocks execution time — — 1.8 ms
trdonce Read Once execution time — — 25 μs 1
tpgmonce Program Once execution time — 65 — μs
tersall Erase All Blocks execution time — 870 7400 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
32 Freescale Semiconductor, Inc.
Table 21. Flash command timing specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
tswapx01
tswapx02
tswapx04
tswapx08
Swap Control execution time
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 24. EzPort switching specifications
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
EP1 EZP_CK frequency of operation (all commands except
READ)
— fSYS/2 MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 33
Table 24. EzPort switching specifications (continued)
Num Description Min. Max. Unit
EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz
EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns
EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns
EP7 EZP_CK low to EZP_Q output valid — 16 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns
EP9 EZP_CS negation to EZP_Q tri-state — 12 ns
EP2
EP3 EP4
EP5 EP6
EP7 EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
34 Freescale Semiconductor, Inc.
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 27 and
Table 28.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 25. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD - VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS - VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
V
CADIN Input capacitance • 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF
RADIN Input resistance — 2 5 kΩ
RAS Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 18.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
—
818.330
Ksps
5
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 35
Table 25. 16-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
—
461.467
Ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS
CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PININPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 10. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
36 Freescale Semiconductor, Inc.
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
fADACK
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
-1.1 to +1.9
-0.3 to 0.5
LSB45
INL Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
-2.7 to +1.9
-0.7 to +0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
-4
-1.4
-5.4
-1.8
LSB4VADIN =
VDDA
5
EQQuantization
error
• 16-bit modes
• ≤13-bit modes
—
—
-1 to 0
—
—
±0.5
LSB4
ENOB Effective number
of bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD Signal-to-noise
plus distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
–94
-85
—
—
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
82
78
95
90
—
—
dB
dB
7
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 37
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
38 Freescale Semiconductor, Inc.
Figure 12. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 27. 16-bit ADC with PGA operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
VREFPGA PGA ref voltage VREF_OU
T
VREF_OU
T
VREF_OU
T
V2, 3
VADIN Input voltage VSSA — VDDA V
VCM Input Common
Mode range
VSSA — VDDA V
RPGAD Differential input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
—
—
—
128
64
32
—
—
—
kΩ IN+ to IN-4
RAS Analog source
resistance
— 100 — Ω 5
TSADC sampling
time
1.25 — — µs 6
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 39
Table 27. 16-bit ADC with PGA operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
Crate ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
18.484 — 450 Ksps 7
16 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
37.037 — 250 Ksps 8
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
Table 28. 16-bit ADC with PGA characteristics
Symbol Description Conditions Min. Typ.1Max. Unit Notes
IDDA_PGA Supply current Low power
(ADC_PGA[PGALPb]=0)
— 420 644 μA 2
IDC_PGA Input DC current A 3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
— 1.54 — μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
— 0.57 — μA
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
40 Freescale Semiconductor, Inc.
Table 28. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
G Gain4• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
0.95
1.9
3.8
7.6
15.2
30.0
58.8
1
2
4
8
16
31.6
63.3
1.05
2.1
4.2
8.4
16.6
33.2
67.8
RAS < 100Ω
BW Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
4
40
kHz
kHz
PSRR Power supply
rejection ratio
Gain=1 — -84 — dB VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
CMRR Common mode
rejection ratio
• Gain=1
• Gain=64
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
VOFS Input offset
voltage
— 0.2 — mV Output offset =
VOFS*(Gain+1)
TGSW Gain switching
settling time
— — 10 µs 5
EIL Input leakage
error
All modes IIn × RAS mV IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF Maximum
differential input
signal swing where VX = VREFPGA × 0.583
V6
SNR Signal-to-noise
ratio
• Gain=1
• Gain=64
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
Average=32
THD Total harmonic
distortion
• Gain=1
• Gain=64
85
49
100
95
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
SFDR Spurious free
dynamic range
• Gain=1
• Gain=64
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=100Hz
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 41
Table 28. 16-bit ADC with PGA characteristics (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
ENOB Effective number
of bits
• Gain=1, Average=4
• Gain=64, Average=4
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
11.6
7.2
12.8
11.0
7.9
7.3
6.8
6.8
7.5
13.4
9.6
14.5
14.3
13.8
13.1
12.5
11.5
10.6
—
—
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
bits
bits
16-bit
differential
mode,fin=100Hz
SINAD Signal-to-noise
plus distortion
ratio
See ENOB 6.02 × ENOB + 1.76 dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1,
PMODE=1)
20 50 200 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
42 Freescale Semiconductor, Inc.
Table 29. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
tDLS Propagation delay, low-speed mode (EN=1,
PMODE=0)
80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.04
0.05
0.06
0.07
0.08
P Hystereris (V)
00
01
10
HYSTCTR
Setting
0
0.01
0.02
0.03
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
CM
10
11
Vin level (V)
Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 43
0 08
0.1
0.12
0.14
0.16
0.18
P Hystereris (V)
00
01
10
HYSTCTR
Setting
0
0.02
0.04
0.06
0.08
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
CMP
10
11
Vin level (V)
Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 30. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
44 Freescale Semiconductor, Inc.
6.6.3.2 12-bit DAC operating behaviors
Table 31. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 150 μA
IDDA_DACH
P
Supply current — high-speed mode — — 700 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance load = 3 kΩ — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
CT Channel to channel cross talk — — -80 dB
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 45
Figure 15. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
46 Freescale Semiconductor, Inc.
Figure 16. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 47
Table 33. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915 1.195 1.1977 V
Vout Voltage reference output — factory trim 1.1584 — 1.2376 V
Vstep Voltage reference trim step — 0.5 — mV
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range)
— — 80 mV
Ibg Bandgap only current — — 80 µA 1
Ilp Low-power buffer current — — 360 uA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation
• current = + 1.0 mA
• current = - 1.0 mA
—
—
2
5
—
—
mV 1, 2
Tstup Buffer startup time — — 100 µs
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 50 °C
Table 35. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vout Voltage reference output with factory trim 1.173 1.225 V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
48 Freescale Semiconductor, Inc.
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
6.8.2 USB DCD electrical specifications
Table 36. USB DCD electrical specifications
Symbol Description Min. Typ. Max. Unit
VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 — 0.7 V
VLGC Threshold voltage for logic high 0.8 — 2.0 V
IDP_SRC USB_DP source current 7 10 13 μA
IDM_SINK USB_DM sink current 50 100 150 μA
RDM_DWN D- pulldown resistance for data pin contact detect 14.25 — 24.8 kΩ
VDAT_REF Data detect voltage 0.25 0.33 0.4 V
6.8.3 USB VREG electrical specifications
Table 37. USB VREG electrical specifications
Symbol Description Min. Typ.1Max. Unit Notes
VREGIN Input supply voltage 2.7 — 5.5 V
IDDon Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
— 120 186 μA
IDDstby Quiescent current — Standby mode, load current
equal zero
— 1.27 30 μA
IDDoff Quiescent current — Shutdown mode
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
—
—
650
—
—
4
nA
μA
ILOADrun Maximum load current — Run mode — — 120 mA
ILOADstby Maximum load current — Standby mode — — 1 mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
• Standby mode
3
2.1
3.3
2.8
3.6
3.6
V
V
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1 — 3.6 V 2
COUT External output capacitor 1.76 2.2 8.16 μF
ESR External output capacitor equivalent series
resistance
1 — 100 mΩ
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 49
Table 37. USB VREG electrical specifications
(continued)
Symbol Description Min. Typ.1Max. Unit Notes
ILIM Short circuit current — 290 — mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 25 MHz
DS1 DSPI_SCK output cycle time 2 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
2
— ns 1
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
2
— ns 2
DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid −2 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 15 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
50 Freescale Semiconductor, Inc.
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 17. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Frequency of operation 12.5 MHz
DS9 DSPI_SCK input cycle time 4 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 18. DSPI classic SPI timing — slave mode
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 51
6.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation — 12.5 MHz
DS1 DSPI_SCK output cycle time 4 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 20.5 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 19. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation — 6.25 MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
52 Freescale Semiconductor, Inc.
Table 41. Slave mode DSPI timing (full voltage range) (continued)
Num Description Min. Max. Unit
DS9 DSPI_SCK input cycle time 8 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 20 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 19 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 19 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 20. DSPI classic SPI timing — slave mode
6.8.7 Inter-Integrated Circuit Interface (I2C) timing
Table 42. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.3 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 013.452030.91µs
Data set-up time tSU; DAT 2504— 1002, 5— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb6300 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 53
Table 42. I 2C timing (continued)
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb5300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
SDA
SCL
tHD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
Figure 21. Timing definition for fast and standard mode devices on the I2C bus
6.8.8 UART switching specifications
See General switching specifications.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
54 Freescale Semiconductor, Inc.
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 43. SDHC switching specifications
Num Symbol Description Min. Max. Unit
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
fOD Clock frequency (identification mode) 0 400 kHz
SD2 tWL Clock low time 7 — ns
SD3 tWH Clock high time 7 — ns
SD4 tTLH Clock rise time — 3 ns
SD5 tTHL Clock fall time — 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 tOD SDHC output delay (output valid) -5 8.3 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 tISU SDHC input setup time 5 — ns
SD8 tIH SDHC input hold time 0 — ns
SD2SD3 SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 22. SDHC timing
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 55
6.8.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 44. I2S master mode timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
S1 I2S_MCLK cycle time 2 x tSYS ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_BCLK cycle time 5 x tSYS — ns
S4 I2S_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_BCLK to I2S_FS output valid — 15 ns
S6 I2S_BCLK to I2S_FS output invalid -2.5 — ns
S7 I2S_BCLK to I2S_TXD valid — 15 ns
S8 I2S_BCLK to I2S_TXD invalid -3 — ns
S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 20 — ns
S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 23. I2S timing — master mode
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
56 Freescale Semiconductor, Inc.
Table 45. I2S slave mode timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_BCLK cycle time (input) 8 x tSYS — ns
S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period
S13 I2S_FS input setup before I2S_BCLK 10 — ns
S14 I2S_FS input hold after I2S_BCLK 3 — ns
S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 20 ns
S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_BCLK 10 — ns
S18 I2S_RXD hold after I2S_BCLK 2 — ns
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 24. I2S timing — slave modes
Table 46. I2S master mode timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 2 x tSYS ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_BCLK cycle time 5 x tSYS — ns
S4 I2S_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_BCLK to I2S_FS output valid — 15 ns
S6 I2S_BCLK to I2S_FS output invalid -4.3 — ns
S7 I2S_BCLK to I2S_TXD valid — 15 ns
S8 I2S_BCLK to I2S_TXD invalid -4.6 — ns
S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 23.9 — ns
S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 — ns
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 57
Table 47. I2S slave mode timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_BCLK cycle time (input) 8 x tSYS — ns
S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period
S13 I2S_FS input setup before I2S_BCLK 10 — ns
S14 I2S_FS input hold after I2S_BCLK 3.5 — ns
S15 I2S_BCLK to I2S_TXD/I2S_FS output valid — 28.6 ns
S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_BCLK 10 — ns
S18 I2S_RXD hold after I2S_BCLK 2 — ns
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 48. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDDTSI Operating voltage 1.71 — 3.6 V
CELE Target electrode capacitance range 1 20 500 pF 1
fREFmax Reference oscillator frequency — 5.5 12.7 MHz 2
fELEmax Electrode oscillator frequency — 0.5 4.0 MHz 3
CREF Internal reference capacitor 0.5 1 1.2 pF
VDELTA Oscillator delta voltage 100 600 760 mV 4
IREF Reference oscillator current source base current
• 1uA setting (REFCHRG=0)
• 32uA setting (REFCHRG=31)
—
—
1.133
36
1.5
50
μA 3 , 5
IELE Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
• 32uA setting (EXTCHRG=31)
—
—
1.133
36
1.5
50
μA 3 , 6
Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 7
Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8
Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9
MaxSens Maximum sensitivity 0.003 12.5 — fF/count 10
Res Resolution — — 16 bits
TCon20 Response time @ 20 pF 8 15 25 μs 11
ITSI_RUN Current added in run mode — 55 — μA
ITSI_LP Low power mode current adder — 1.3 2.5 μA 12
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF.
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
58 Freescale Semiconductor, Inc.
3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF.
4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF.
5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
10. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
* Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following
configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The
minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best
sensitivity but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based
on the following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5
pF
11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and
fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
6.9.2 LCD electrical characteristics
Table 49. LCD electricals
Symbol Description Min. Typ. Max. Unit Notes
fFrame LCD frame frequency 28 30 58 Hz
CLCD LCD charge pump capacitance — nominal value — 100 — nF 1
CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1
CGlass LCD glass capacitance — 2000 8000 pF 2
VIREG VIREG
• HREFSEL=0, RVTRIM=1111
• HREFSEL=0, RVTRIM=1000
• HREFSEL=0, RVTRIM=0000
• HREFSEL=1, RVTRIM=1111
• HREFSEL=1, RVTRIM=1000
• HREFSEL=1, RVTRIM=0000
—
—
—
—
—
—
1.11
1.01
0.91
1.84
1.69
1.54
—
—
—
—
—
—
V
V
V
V
V
V
3
ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG
— VIREG ripple
• HREFSEL = 0
• HREFSEL = 1
—
—
—
—
30
50
mV
mV
IVIREG VIREG current adder — RVEN = 1 — 1 — µA 4
IRBIAS RBIAS current adder
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
—
—
10
1
—
—
µA
µA
Table continues on the next page...
Peripheral operating requirements and behaviors
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 59
Table 49. LCD electricals (continued)
Symbol Description Min. Typ. Max. Unit Notes
RRBIAS RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
—
—
0.28
2.98
—
—
MΩ
MΩ
VLL2 VLL2 voltage
• HREFSEL = 0
• HREFSEL = 1
2.0 − 5%
3.3 − 5%
2.0
3.3
—
—
V
V
VLL3 VLL3 voltage
• HREFSEL = 0
• HREFSEL = 1
3.0 − 5%
5 − 5%
3.0
5
—
—
V
V
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
100-pin LQFP 98ASS23308W
8 Pinout
Dimensions
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
60 Freescale Semiconductor, Inc.
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
1 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA
2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL
3 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_b SDHC0_DCLK
4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD
5 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
6 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2
7 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_b I2S0_MCLK I2S0_CLKIN
8 VDD VDD VDD
9 VSS VSS VSS
10 USB0_DP USB0_DP USB0_DP
11 USB0_DM USB0_DM USB0_DM
12 VOUT33 VOUT33 VOUT33
13 VREGIN VREGIN VREGIN
14 ADC0_DP1 ADC0_DP1 ADC0_DP1
15 ADC0_DM1 ADC0_DM1 ADC0_DM1
16 ADC1_DP1 ADC1_DP1 ADC1_DP1
17 ADC1_DM1 ADC1_DM1 ADC1_DM1
18 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
19 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
20 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
21 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
22 VDDA VDDA VDDA
23 VREFH VREFH VREFH
24 VREFL VREFL VREFL
25 VSSA VSSA VSSA
26 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 61
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
27 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
28 XTAL32 XTAL32 XTAL32
29 EXTAL32 EXTAL32 EXTAL32
30 VBAT VBAT VBAT
31 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b
32 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN
33 PTE26 DISABLED PTE26 UART4_CTS_b RTC_CLKOUT USB_CLKIN
34 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_b FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
35 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
36 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
37 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 JTAG_TMS/
SWD_DIO
38 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
39 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_BCLK JTAG_TRST
40 VDD VDD VDD
41 VSS VSS VSS
42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_
PHA
43 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
44 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_TX_BCLK
45 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD
46 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_b I2S0_RX_FS
47 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_b I2S0_MCLK I2S0_CLKIN
48 VDD VDD VDD
49 VSS VSS VSS
50 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0
51 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN1 LPT0_ALT1
52 RESET_b RESET_b RESET_b
53 PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
LCD_P0
54 PTB1 LCD_P1/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
LCD_P1/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
LCD_P1
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
62 Freescale Semiconductor, Inc.
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
55 PTB2 LCD_P2/
ADC0_SE12/
TSI0_CH7
LCD_P2/
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_b FTM0_FLT3 LCD_P2
56 PTB3 LCD_P3/
ADC0_SE13/
TSI0_CH8
LCD_P3/
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA UART0_CTS_b FTM0_FLT0 LCD_P3
57 PTB7 LCD_P7/
ADC1_SE13
LCD_P7/
ADC1_SE13
PTB7 LCD_P7
58 PTB8 LCD_P8 LCD_P8 PTB8 UART3_RTS_b LCD_P8
59 PTB9 LCD_P9 LCD_P9 PTB9 SPI1_PCS1 UART3_CTS_b LCD_P9
60 PTB10 LCD_P10/
ADC1_SE14
LCD_P10/
ADC1_SE14
PTB10 SPI1_PCS0 UART3_RX FTM0_FLT1 LCD_P10
61 PTB11 LCD_P11/
ADC1_SE15
LCD_P11/
ADC1_SE15
PTB11 SPI1_SCK UART3_TX FTM0_FLT2 LCD_P11
62 PTB16 LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16 SPI1_SOUT UART0_RX EWM_IN LCD_P12
63 PTB17 LCD_P13/
TSI0_CH10
LCD_P13/
TSI0_CH10
PTB17 SPI1_SIN UART0_TX EWM_OUT_b LCD_P13
64 PTB18 LCD_P14/
TSI0_CH11
LCD_P14/
TSI0_CH11
PTB18 CAN0_TX FTM2_CH0 I2S0_TX_BCLK FTM2_QD_
PHA
LCD_P14
65 PTB19 LCD_P15/
TSI0_CH12
LCD_P15/
TSI0_CH12
PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FTM2_QD_
PHB
LCD_P15
66 PTB20 LCD_P16 LCD_P16 PTB20 SPI2_PCS0 CMP0_OUT LCD_P16
67 PTB21 LCD_P17 LCD_P17 PTB21 SPI2_SCK CMP1_OUT LCD_P17
68 PTB22 LCD_P18 LCD_P18 PTB22 SPI2_SOUT CMP2_OUT LCD_P18
69 PTB23 LCD_P19 LCD_P19 PTB23 SPI2_SIN SPI0_PCS5 LCD_P19
70 PTC0 LCD_P20/
ADC0_SE14/
TSI0_CH13
LCD_P20/
ADC0_SE14/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXTRG I2S0_TXD LCD_P20
71 PTC1/
LLWU_P6
LCD_P21/
ADC0_SE15/
TSI0_CH14
LCD_P21/
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RTS_b FTM0_CH0 LCD_P21
72 PTC2 LCD_P22/
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
LCD_P22/
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CTS_b FTM0_CH1 LCD_P22
73 PTC3/
LLWU_P7
LCD_P23/
CMP1_IN1
LCD_P23/
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 LCD_P23
74 VSS VSS VSS
75 VLL3 VLL3 VLL3
76 VLL2 VLL2 VLL2
77 VLL1 VLL1 VLL1
78 VCAP2 VCAP2 VCAP2
79 VCAP1 VCAP1 VCAP1
80 PTC4/
LLWU_P8
LCD_P24 LCD_P24 PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT LCD_P24
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 63
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
81 PTC5/
LLWU_P9
LCD_P25 LCD_P25 PTC5/
LLWU_P9
SPI0_SCK LPT0_ALT2 CMP0_OUT LCD_P25
82 PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXTRG LCD_P26
83 PTC7 LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7 SPI0_SIN LCD_P27
84 PTC8 LCD_P28/
ADC1_SE4b/
CMP0_IN2
LCD_P28/
ADC1_SE4b/
CMP0_IN2
PTC8 I2S0_MCLK I2S0_CLKIN LCD_P28
85 PTC9 LCD_P29/
ADC1_SE5b/
CMP0_IN3
LCD_P29/
ADC1_SE5b/
CMP0_IN3
PTC9 I2S0_RX_BCLK FTM2_FLT0 LCD_P29
86 PTC10 LCD_P30/
ADC1_SE6b/
CMP0_IN4
LCD_P30/
ADC1_SE6b/
CMP0_IN4
PTC10 I2C1_SCL I2S0_RX_FS LCD_P30
87 PTC11/
LLWU_P11
LCD_P31/
ADC1_SE7b
LCD_P31/
ADC1_SE7b
PTC11/
LLWU_P11
I2C1_SDA I2S0_RXD LCD_P31
88 VSS VSS VSS
89 VDD VDD VDD
90 PTC16 LCD_P36 LCD_P36 PTC16 CAN1_RX UART3_RX LCD_P36
91 PTC17 LCD_P37 LCD_P37 PTC17 CAN1_TX UART3_TX LCD_P37
92 PTC18 LCD_P38 LCD_P38 PTC18 UART3_RTS_b LCD_P38
93 PTD0/
LLWU_P12
LCD_P40 LCD_P40 PTD0/
LLWU_P12
SPI0_PCS0 UART2_RTS_b LCD_P40
94 PTD1 LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1 SPI0_SCK UART2_CTS_b LCD_P41
95 PTD2/
LLWU_P13
LCD_P42 LCD_P42 PTD2/
LLWU_P13
SPI0_SOUT UART2_RX LCD_P42
96 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_SIN UART2_TX LCD_P43
97 PTD4/
LLWU_P14
LCD_P44 LCD_P44 PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_b FTM0_CH4 EWM_IN LCD_P44
98 PTD5 LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5 SPI0_PCS2 UART0_CTS_b FTM0_CH5 EWM_OUT_b LCD_P45
99 PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 LCD_P46
100 PTD7 LCD_P47 LCD_P47 PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1 LCD_P47
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
64 Freescale Semiconductor, Inc.
60
59
58
57
56
55
54
53
52
51
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA0_DP/ADC0_DP0/ADC1_DP3
ADC1_DM1
ADC1_DP1
ADC0_DM1
ADC0_DP1
VREGIN
VOUT33
USB0_DM
USB0_DP
VSS
VDD
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VLL3
VSS
PTC3
PTC2
PTC1
PTC0
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
PTB11
PTB10
PTB9
PTB8
PTB7
PTB3
PTB2
PTB1
PTB0
RESET_b
PTA19
25
24
23
22
21
VSSA
VREFL
VREFH
VDDA
PGA1_DM/ADC1_DM0/ADC0_DM3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
99
79
78
77
76
PTD6
VCAP1
VCAP2
VLL1
VLL2
50
49
48
47
46
45
44
43
42
41
PTA18
VSS
VDD
PTA17
PTA16
PTA15
PTA14
PTA13
PTA12
VSS
VDD
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTE26
PTE25
PTE24
VBAT
EXTAL32
XTAL32
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/
CMP0_IN5/ADC1_SE18
98 PTD5
97 PTD4
96 PTD3
95 PTD2
94 PTD1
93 PTD0
92 PTC18
91 PTC17
90 PTC16
89 VDD
88 VSS
80 PTC4
PTC5
PTC6
81
82
83 PTC7
84 PTC8
85 PTC9
86 PTC10
87 PTC11
100 PTD7
Figure 25. K40 100 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Revision History
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 65
Table 50. Revision History
Rev. No. Date Substantial Changes
1 11/2010 Initial public revision
2 3/2011 Many updates throughout
3 3/2011 Added sections that were inadvertently removed in previous revision
4 3/2011 Reworded IIC footnote in "Voltage and Current Operating Requirements" table.
Added paragraph to "Peripheral operating requirements and behaviors" section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
5 6/2011 • Changed supported part numbers per new part number scheme
• Changed DC injection current specs in "Voltage and current operating requirements"
table
• Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage
and current operating behaviors" table
• Split Low power stop mode current specs by temperature range in "Power
consumption operating behaviors" table
• Changed typical IDD_VBAT spec in "Power consumption operating behaviors" table
• Added LPTMR clock specs to "Device clock specifications" table
• Changed Minimum external reset pulse width in "General switching specifications"
table
• Changed PLL operating current in "MCG specifications" table
• Added footnote to PLL period jitter in "MCG specifications" table
• Changed Supply current in "Oscillator DC electrical specifications" table
• Changed Crystal startup time in "Oscillator frequency specifications" table
• Changed Operating voltage in "EzPort switching specifications" table
• Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table
• Changed Gain spec in "16-bit ADC with PGA characteristics" table
• Added typical Input DC current to "16-bit ADC with PGA characteristics" table
• Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA
characteristics" table
• Changed Analog comparator initialization delay in "Comparator and 6-bit DAC
electrical specifications"
• Changed Code-to-code settling time, DAC output voltage range low, and Temperature
coefficient offset voltage in "12-bit DAC operating behaviors" table
• Changed Temperature drift and Load regulation in "VREF full-range operating
behaviors" table
• Changed Regulator output voltage in "USB VREG electrical specifications" table
• Changed ILIM description and specs in "USB VREG electrical specifications" table
• Changed DSPI_SCK cycle time specs in "DSPI timing" tables
• Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table
• Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high-
speed mode)" table
• Changed Reference oscillator current source base current spec and added Low-power
current adder footer in "TSI electrical specifications" table
• Added LCD glass capacitance footnote
Table continues on the next page...
Revision History
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
66 Freescale Semiconductor, Inc.
Table 50. Revision History (continued)
Rev. No. Date Substantial Changes
6 01/2012 • Added AC electrical specifications.
• Replaced TBDs with silicon data throughout.
• In "Power mode transition operating behaviors" table, removed entry times.
• Updated "EMC radiated emissions operating behaviors" to remove SAE level and also
added data for 144LQFP.
• Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram".
• Added "ENOB vs. ADC_CLK for 16-bit differential and 16-bit single-ended modes"
figures.
• Updated IDD_RUN numbers in 'Power consumption operating behaviors' section.
• Clarified 'Diagram: Typical IDD_RUN operating behavior' section and updated 'Run
mode supply current vs. core frequency — all peripheral clocks disabled' figure.
• In 'Voltage reference electrical specifications' section, updated CL, Vtdrift, and Vvdrift
values.
• In 'USB electrical specifications' section, updated VDP_SRC, IDDstby, and 'VReg33out
values.
• In 'LCD electrical characteristics' section, updated VIREG and ΔRTRIM values.
7 02/2013 • In "ESD handling ratings", added a note for ILAT.
• Updated "Voltage and current operating requirements".
• Updated "Voltage and current operating behaviors".
• Updated "Power mode transition operating behaviors".
• Updated "EMC radiated emissions operating behaviors" to add MAPBGA data.
• In "MCG specifications", updated the description of fints_t.
• In "16-bit ADC operating conditions", updated the max spec of VADIN.
• In "16-bit ADC electrical characteristics", updated the temp sensor slope and voltage
specs.
• Updated "I2C switching specifications".
• In "SDHC specifications", removed the operating voltage limits and updated the SD1
and SD6 specs.
• In "I2S switching specifications", added separate specification tables for the full
operating voltage range.
Revision History
K40 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 67
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Rev. 7, 02/2013
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