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P/N:PM1041 REV. 1.2, JUL. 01, 2004
MX29LV160BT/BB
16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors.
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 1.4V
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 10 years data retention
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 2,097,152 x 8/1,048,576 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
•Fully compatible with MX29LV160A device
• Fast access time: 70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase Suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
GENERAL DESCRIPTION
The MX29LV160BT/BB is a 16-mega bit Flash memo ry
organized as 2M bytes of 8 bits or 1M words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memo ry . The MX29LV160BT/BB is packaged in 44-pin
SOP, 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV160BT/BB o ff ers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29LV160BT/BB has separate chip enable
(CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and pro gramming. The
MX29LV160BT/BB uses a command register to man-
age this functionality. The command register allows f or
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and pro gram cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV160BT/BB uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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PIN CONFIGURATIONS PIN DESCRIPTION
SYMBOL PIN NAME
A0~A19 Address Input
Q0~Q14 Data Input/Output
Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)
CE Chip Enable Input
WE Write Enable Input
BYTE Word/Byte Selection input
RESET Hardware Reset Pin/Sector Protect Unlock
OE Output Enable Input
RY/BY Ready/Busy Output
VCC P ower Supply Pin (2.7V~3.6V)
GND Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
44 SOP(500 mil)
ABCDEFGH
6 A13 A12 A14 A15 A16 BYTE Q15/A-1 GND
5 A9 A8 A10 A11 Q7 Q14 Q13 Q6
4 WE RESET NC A19 Q5 Q12 VCC Q4
3 RY/BY NC A18 NC Q2 Q10 Q11 Q3
2 A7 A17 A6 A5 Q0 Q8 Q9 Q1
1A3A4A2A1A0CEOEGND
48-Ball CSP 6mm x 8mm (Ball Pitch=0.8mm) Top View, Balls Facing Down
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
WE
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
MX29LV160BT/BB
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29LV160BT/BB
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BLOCK STRUCTURE
Sector Sector Size Address range Sector Address
Byte Mode W ord Mode Byte Mode(x8) W ord Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12
SA0 64Kbytes 32Kwords 000000-00FFFF 00000-07FFF 00000XXX
SA1 64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF 00001XXX
SA2 64Kbytes 32Kwords 020000-02FFFF 10000-17FFF 00010XXX
SA3 64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF 00011XXX
SA4 64Kbytes 32Kwords 040000-04FFFF 20000-27FFF 00100XXX
SA5 64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF 00101XXX
SA6 64Kbytes 32Kwords 060000-06FFFF 30000-37FFF 00110XXX
SA7 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF 00111XXX
SA8 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF 01000XXX
SA9 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF 01001XXX
SA10 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF 01010XXX
SA11 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF 01011XXX
SA12 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF 01100XXX
SA13 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF 01101XXX
SA14 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF 01110XXX
SA15 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF 01111XXX
SA16 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF 10000XXX
SA17 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF 10001XXX
SA18 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF 10010XXX
SA19 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF 10011XXX
SA20 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF 10100XXX
SA21 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF 10101XXX
SA22 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF 10110XXX
SA23 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF 10111XXX
SA24 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF 11000XXX
SA25 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF 11001XXX
SA26 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF 11010XXX
SA27 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF 11011XXX
SA28 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF 11100XXX
SA29 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF 11101XXX
SA30 64Kbytes 32Kwords 1E0000-1EFFFF F0000-F7FFF 11110XXX
SA31 32Kbytes 16Kwords 1F0000-1F7FFF F8000-FBFFF 111110XX
SA32 8Kbytes 4Kwords 1F8000-1F9FFF FC000-FCFFF 1111110 0
SA33 8Kbytes 4Kwords 1FA000-1FBFFF FD000-FDFFF 1111110 1
SA34 16Kbytes 8Kwords 1FC000-1FFFFF FE000-FFFFF 1111111 X
Table 1: MX29LV160BT SECTOR ARCHITECTURE
Note: Byte mode: address range A19:A-1, word mode:address range A19:A0.
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Sector Sector Size Address range Sector Address
Byte Mode Word Mode Byte Mode (x8) W ord Mode (x16) A19 A 18 A17 A16 A15 A14 A1 3 A12
SA0 16Kbytes 8Kwords 000000-003FFF 00000-01FFF 0000000 X
SA1 8Kbytes 4Kwords 004000-005FFF 02000-02FFF 0000001 0
SA2 8Kbytes 4Kwords 006000-007FFF 03000-03FFF 0000001 1
SA3 32Kbytes 16Kwords 008000-00FFFF 04000-07FFF 000001XX
SA4 64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF 00001XXX
SA5 64Kbytes 32Kwords 020000-02FFFF 10000-17FFF 00010XXX
SA6 64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF 00011XXX
SA7 64Kbytes 32Kwords 040000-04FFFF 20000-27FFF 00100XXX
SA8 64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF 00101XXX
SA9 64Kbytes 32Kwords 060000-06FFFF 30000-37FFF 00110XXX
SA10 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF 00111XXX
SA11 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF 01000XXX
SA12 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF 01001XXX
SA13 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF 01010XXX
SA14 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF 01011XXX
SA15 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF 01100XXX
SA16 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF 01101XXX
SA17 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF 01110XXX
SA18 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF 01111XXX
SA19 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF 10000XXX
SA20 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF 10001XXX
SA21 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF 10010XXX
SA22 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF 10011XXX
SA23 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF 10100XXX
SA24 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF 10101XXX
SA25 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF 10110XXX
SA26 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF 10111XXX
SA27 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF 11000XXX
SA28 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF 11001XXX
SA29 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF 11010XXX
SA30 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF 11011XXX
SA31 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF 11100XXX
SA32 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF 11101XXX
SA33 64Kbytes 32Kwords 1E0000-1EFFFF F0000-FFFFF 11110XXX
SA34 64Kbytes 32Kwords 1F0000-1FFFFF F8000-FFFFF 11111XXX
Table 2: MX29LV160BB SECTOR ARCHITECTURE
Note: Byte mode:address range A19:A-1, word mode:address range A19:A0.
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BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-A19
CE
OE
WE
RESET
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AUTOMATIC PROGRAMMING
The MX29LV160BT/BB is byte/wo rd pro grammable us-
ing the Automatic Programming algorithm. The Auto-
matic Programming algorithm makes the external sys-
tem do not need to have time out sequence nor to verify
the data programmed. The typical chip programming
time at room temperature of the MX29LV160BT/BB is
less than 18 sec (byte)/12 sec (word).
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The de vice auto matically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to D ATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, table 7, for
more information on these status bits.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at ro om temperature is acco mplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verificatio n of electrical erase
are controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29LV160BT/BB is sector(s) erasable using
MXIC's Auto Sector Erase algorithm. The Automatic
Sector Erase algorithm automatically programs the
specified sector(s) prior to electrical erase. The timing
and verification of electrical erase are controlled inter-
nally within the device. An erase operation can erase
one sector, multiple sectors, or the entire device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard micro processo r write timings. The device will auto-
matically pre-progr am and verify the entire arra y. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry . During write cycles, the co mmand register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched o n the rising edge o f WE o r CE, whichev er hap-
pens first.
MXIC's Flash technology combines years of EPROM
e xperience to pro duce the highest le v els of quality, reli-
ability, and cost effectiveness. The MX29LV160BT/BB
electrically erases all bits simultaneously using Fowler-
No rdheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
thro ugh identifier co des o utput on Q7~Q0. This mo de is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9. Other address pin A6, A1 and A0 as referring to
Table 3. In additio n, to access the automatic select codes
in-system, the host can issue the automatic select com-
mand through the command register without requiring
VID, as shown in table 5.
To verify whether or not secto r being pro tected, the sec-
tor address must appear on the appropriate highest or-
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A19 A11 A9 A8 A6 A5 A1 A0
Description Mode CE O E WE RESET | | | | Q15~Q0
A12 A10 A7 A2
Read Silicon ID L L H H X X VID X L X L L C2H
Manufacture Code
Device ID Word L L H H X X VID X L X L H 22C4H
(Top Boot Block) Byte L L H H X X VID X L X L H XXC4H
Device ID Word L L H H X X VID X L X L H 2249H
(Bottom Boot Block) Byte L L H H X X VID X L X L H XX49H
XX01H
Sector Protection L L H H SA X VID X L X H L (protected)
Verification XX00H
(unprotected)
TABLE 3. MX29LV160BT/BB AUTO SELECT MODE BUS OPERATION (A9=VID)
NO TE: SA=Sector Address, X=Don't Care, L=Lo gic Lo w, H=Lo gic High
der address bit (see Table 1 and Table 2). The rest of
address bits, as sho wn in Ta ble 3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.
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QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX29LV160BT/BB is capable of operating in the CFI
mode. This mode all the host system to determine the
manufacturer of the device such as operating param-
eters and co nfigur atio n. Two commands are required in
CFI mode. Query command of CFI mode is placed first,
then the Reset command exits CFI mode. These are
described in Table 4.
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Standby mode, and Auto matic Select mo de; however , it
is ignored otherwise.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, or Automatic Se-
lect mode. The command is valid only when the de vice
is in the CFI mode.
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Query-unique ASCII string "QRY" 2 0 1 0 0051
22 11 0052
24 12 0059
Primary vendor command set and control interface ID code 2 6 1 3 0002
28 14 0000
Address for primary algorithm extended query table 2A 1 5 0040
2C 16 0000
Alternate vendor command set and control interface ID code (none) 2E 1 7 0000
30 18 0000
Address for secondary algorithm extended query table (none) 32 19 0000
34 1A 0000
Table 4-2. CFI Mode: System Interface Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
VCC supply, minimum (2.7V) 3 6 1B 0027
VCC supply, maximum (3.6V) 3 8 1 C 0036
VPP supply, minimum (none) 3A 1 D 0000
VPP supply, maximum (none) 3 C 1E 0000
Typical timeout for single word/byte write (2N us) 3E 1F 0004
Typical timeout for Minimum size buffer write (2N us) (not supported) 4 0 2 0 0000
Typical timeout for individual sector erase (2N ms) 4 2 2 1 000A
Typical timeout for full chip erase (2N ms) 4 4 22 0000
Maximum timeout for single word/byte write times (2N X Typ) 46 23 0005
Maximum timeout for buffer write times (2N X Typ) 48 24 0000
Maximum timeout for individual sector erase times (2N X Typ) 4A 2 5 0004
Maximum timeout for full chip erase times (not supported) 4 C 2 6 0000
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Table 4-3. CFI Mode: Device Geometry Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Device size (2N bytes) 4E 27 0015
Flash device interface code (x8/x16 async.) 50 28 0002
52 29 0000
Maximum number of bytes in multi-byte write (not supported) 5 4 2A 0000
56 2B 0000
Number of erase sector regions 5 8 2C 0004
Erase sector region 1 information (refer to the CFI publication 100) 5A 2 D 0000
5C 2E 0000
5E 2F 0040
60 30 0000
Erase sector region 2 information 6 2 31 0001
64 32 0000
66 33 0020
68 34 0000
Erase sector region 3 information 6A 3 5 0000
6C 36 0000
6E 37 0080
70 38 0000
Erase sector region 4 information 7 2 39 001E
74 3A 0000
76 3B 0000
78 3C 0001
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
(All values in these tables are in hexadecimal)
Description Address Address Data
(Byte Mode) (Word Mode)
Query-unique ASCII string "PRI" 8 0 4 0 0050
82 41 0052
84 42 0049
Major version number, ASCII 8 6 43 0031
Minor version number, ASCII 8 8 44 0030
Address sensitive unlock (0=required, 1= not required) 8A 4 5 0000
Erase suspend (2= to read and write) 8 C 4 6 0002
Sector protect (N= # of sectors/group) 8E 4 7 0001
Temporary sector unprotect (1=supported) 90 48 0001
Sector protect/chip unprotect scheme 9 2 4 9 0004
Simultaneous R/W operation (0=not supported) 94 4A 0000
Burst mode type (0=not supported) 9 6 4B 0000
Page mode type (0=not supported) 98 4 C 0000
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in the improper sequence will reset the device to the
read mo de. Table 5 defines the v alid register co mmand
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Command Bus Cycle Cycle Cycle Cycle Cycle Cycle
Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXXH F0H
Read 1 RA RD
Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI
Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI
Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H
Verify x02H XX01H
Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H
x04H 01H
Program Word 4 555H AAH 2AAH 55H 555H A0H PA PD
Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD
Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H
Sector Erase Suspend 1 XXXH B0H
Sector Erase Resume 1 XXXH 30 H
CFI Query Word 1 55H 98
Byte AAH
TABLE 5. MX29LV160BT/BB COMMAND DEFINITIONS
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code.
X = X can be VIL o r VIH
RA=Address of memory location to be read. RD=Data to be read at location RA.
2.PA = Address of memor y location to be programmed. PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or
555H to Address A10~A-1 in byte mode.
Address bit A11~A19=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A19 in either state.
4. For Sector Protect Ver ify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,
it means the sector is still not being protected.
5. Any number of CFI data read cycles are permitted.
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ADDRESS Q8~Q15
DESCRIPTION CE OE WE RESET A19A1 1 A9 A 8 A 6 A5 A1 A 0 Q0~Q7 BYTE BYTE
A12 A10 A7 A2 =VIH =VIL
Read L L H H AIN Dout Dout Q8~Q14
=High Z
Q15=A-1
Write L H L H AIN DIN(3) DIN
Reset X X X L X High Z High Z High Z
Temporary sector unlock X X X VID AIN DIN DIN High Z
Output Disable L H H H X High Z High Z High Z
Standby Vcc±X X Vcc±X High Z High Z High Z
0.3V 0.3V
Sector Protect L H L VID SA X X X L X H L DIN X X
Chip Unprotect L H L VID X X X X H X H L DIN X X
Sector Protection Verify L L H H SA X VID X L X H L CODE(5) X X
TABLE 6. MX29LV160BT/BB BUS OPERATION
NOTES:
1. Manufacturer and device codes may also be accessed via a command register wr ite sequence. Refer to Table 4.
2. VID is the high voltage, 11.5V to 12.5V.
3. Refer to Table 5 for valid Data-In during a wr ite operation.
4. X can be VIL or VIH.
5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
6. A19~A12=Sector address for sector protect.
7. The sector protect and chip unprotect functions may also be implemented via programming equipment.
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REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power co ntrol
and selects the device. OE is the output control and
gates arra y data to the output pins. WE sho uld remain at
VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read
access until the command register contents are altered.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of
memo ry, the system must drive WE and CE to VIL, and
OE to VIH.
An erase operatio n can er ase one sector , m ultiple sec-
to rs, or the entire device. Table 1 and Table 2 indicate the
address space that each sector occupies. A "sector ad-
dress" consists of the address bits required to uniquely
select a sector. The Writing specific address and data
commands or sequences into the command register ini-
tiates de vice o peratio ns. Table 5 defines the v alid regis-
ter co mmand sequences. Writing inco rrect address and
data values or writing them in the improper sequence
resets the device to reading array data. Section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
After the system writes the "read silicon-ID" and "sector
protect verify" command sequence, the device enters
the "read silicon-ID" and "sector protect verify" mode.
The system can then read "read silicon-ID" and "sector
protect verify" codes from the internal register (which is
separate from the memory array) on Q7-Q0. Standard
read cycle timings apply in this mode. Refer to the "read
silicon-ID" and "sector protect verify" Mode and "read
silicon-ID" and "sector protect verify" Command Se-
quence section for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
STANDBY MODE
When using both pins of CE and RESET, the device
enter CMOS Standby with both pins held at Vcc ± 0.3V.
If CE and RESET are held at VIH, but not within the
range o f VCC ± 0.3V, the device will still be in the standby
mo de, but the standby current will be larger . During Auto
Algorithm operation, Vcc active current (ICC2) is required
e ven CE = "H" until the operatio n is completed. The de-
vice can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.
OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from
the de vices are disabled. This will cause the o utput pins
to be in a high impedance state.
RESET OPERATION
The RESET pin provides a hardware method of reset-
ting the de vice to reading array data. When the RESET
pin is driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write com-
mands f o r the duration o f the RESET pulse. The device
also resets the internal state machine to reading array
data. The operation that was interrupted should be re-
initiated once the device is ready to accept another com-
mand sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS±0.3V, the standby current will be
greater.
The RESET pin ma y be tied to system reset circuitry. A
system reset would that also reset the Flash memor y,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET is asserted during a progr am o r erase o per a-
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READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.
The MX29LV160BT/BB co ntains a Silicon-ID-Read op-
eration to supple traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of C4H/22C4H for MX29LV160BT, 49H/
2249H fo r MX29LV160BB.
The system must write the reset command to exit the
"Silicon-ID Read Command" code.
AUTOMATIC CHIP ERASE COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlo c k" write cycles. These are f o llo wed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
The device does not require the system to entirely pre-
program prior to executing the Automatic Chip Erase.
Upon executing the Automatic Chip Erase, the device
will automatically program and verify the entire memory
for an all-zero data pattern . When the device is auto-
matically verified to contain an all-zero pattern, a self-
timed chip erase and v erify begin. The erase and verify
operations are completed when the data on Q7 is "1" at
which time the device retur ns to the Read mode. The
system is not required to provide any control or timing
during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1" (see Table 8), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when either the data
on Q7 is "1" at which time the device returns to the
Read mode or the data on Q6 stops toggling for two
consecutive read cycles at which time the device re-
turns to the Read mode.
tion, the RY/BY pin remains a "0" (busy) until the inter-
nal reset operation is complete, which requires a time of
tREAD Y (during Embedded Algorithms). The system can
thus mo nitor R Y/BY to determine whether the reset o p-
eration is complete. If RESET is asserted when a pro-
gram or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The sys-
tem can read data tRH after the RESET pin returns to
VIH.
Refer to the AC Characteristics tables for RESET
parameters and to Figure 22 for the timing diagram.
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READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to re-
trieve data. The device is also ready to read arra y data
after completing an Automatic Program or Automatic
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See erase Suspend/Erase
Resume Commands” for more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the "read silicon-ID" and "sector protect verify"
mode. See the "Reset Command" section, next.
RESET COMMAND
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading arra y
data. Once erasure begins, however, the device igno res
reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Sus-
pend mode). Once programming begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the se-
quence cycles in an Automatic Select command se-
quence. Once in the Automatic Select mode, the reset
command must be written to return to reading array data
(also applies to Automatic Select during Erase Suspend).
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).
Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacturer code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H
Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H
Device code Word VIH VIL 22H 1 1 0 0 0 1 0 0 22C4H
for MX29LV160BT Byte VIH VIL X 1 1 0 0 0 1 0 0 C4H
Device code Word VIH VIL 22H 0 1 0 0 1 0 0 1 2249H
for MX29LV160BB Byte VIH VIL X 0 1 0 0 1 0 0 1 49H
Sector Protection Word X VIH X 0 0 0 0 0 0 0 1 01H (Protected)
Verification Byte X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)
TABLE 7. SILICON ID CODE
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SECTOR ERASE COMMANDS
The device does not require the system to entirely pre-
program prior to executing the Automatic Sector Erase
Set-up command and Automatic Sector Erase com-
mand. Upon executing the Automatic Sector Erase com-
mand, the device will automatically program and verify
the sector(s) memory for an all-zero data pattern. The
system is not required to provide any control or timing
during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when either the data on Q7 is "1" at which time the de-
vice returns to the Read mode or the data on Q6 stops
toggling for two consecutive read cycles at which time
the device returns to the Read mo de. The system is no t
required to provide any control or timing during these
operations.
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" wr ite cycles
are then followed by the sector erase command 30H.
The secto r address is latched on the falling edge o f WE
or CE, whichever happens later, while the command
(data) is latched o n the rising edge of WE o r CE, which-
ever happens first. Sector addresses selected are
loaded into internal register on the sixth falling edge of
WE or CE, whichever happens later. Each successive
sector load cycle star ted by the falling edge of WE or
CE, whichever happens later must begin within 50us
fro m the rising edge of the preceding WE or CE, which-
ever happens first. Otherwise, the loading period ends
and internal auto secto r erase cycle starts. (Monito r Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command other
than Sector Erase (30H) or Erase Suspend (B0H) during
the time-out period resets the device to read mode.
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Secto r Erase operation. When the Erase Suspend Com-
mand is issued during the sector erase operation, the
device requires a maximum 20us to suspend the sector
erase o peration. However , when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mo de automatically after suspend is ready . At this time,
state machine only allows the command register to re-
spond to Erase Resume, program data to , or read data
from any sector not selected for erasure. The system
can use Q7 or Q6 and Q2 together, to determine if a
sector is actively erasing or is erase-suspend.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing. However ,
for MX29LV160BT/BB, a 10ms time delay must be re-
quired after the erase resume command, if the system
implements a endless erase suspend/resume loop, or
the number of erase suspend/resume is exceeded 1024
times. The erase times will be expended if the erase
behavior always be suspended. (Please refer to MXIC
Flash Application Note for details.) Please note that the
above 10ms time delay is not necessary for
MX29LV160BT/BB.
WORD/BYTE PROGRAM COMMAND SEQUENCE
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 5 shows the address
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and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, Q6, or RY/BY. See "Write Operation Status" for
information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Byte/Word Program command sequence
should be reinitiated once the device has reset to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may cause the
device to set Q5 to "1", or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY. Table 8 and the following subsections descr ibe the
functions o f these bits . Q7, RY/BY, and Q6 each o ff er a
method for determining whether a program or erase op-
eration is complete or in progress. These three bits are
discussed first.
Q7: Data Polling
The Data Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend. Data
P olling is valid after the rising edge o f the final WE pulse
in the program or erase command sequence.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. This Q7 status also applies to pro gramming dur-
ing Erase Suspend. When the Auto matic Pro gram algo-
rithm is complete, the device outputs the datum pro-
gr ammed to Q7. The system must provide the pro gram
address to read valid status information on Q7. If a pro-
gr am address falls within a protected secto r, Data Poll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.
During the Auto matic Erase algo rithm, Data Po lling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, or if the device enters the Erase Sus-
pend mode, Data Polling produces a "1" on Q7. This is
analogous to the complement/true datum output de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the de vice outputs the "co mplement,” or "0".” The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
ab le (OE) is asserted low.
RY/BY : Ready/Busy
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, in the co mmand sequence. Since R Y/BY
is an o pen-drain o utput, se veral R Y/BY pins can be tied
to gether in par allel with a pull-up resistor to Vcc.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the de-
vice is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
Table 8 shows the o utputs fo r RY/BY during write opera-
tion.
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During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con-
tro l the read cycles. When the o peratio n is co mplete, Q6
stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
If a program address f alls within a protected sector , Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.
Table 8 sho ws the outputs for To ggle Bit I on Q6.
Q2:Toggle Bit II
The "To ggle Bit II" o n Q2, when used with Q6, indicates
whether a par ticular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus , bo th status bits
are required for sectors and mode information. Refer to
Tab le 7 to co mpare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a to ggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
co mpleted the pro gram o r erase o peratio n. The system
can read array data on Q7-Q0 on the following read cycle.
How ever, if after the initial two read cycles , the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must wr ite
the reset command to return to reading array data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system m ust start at the beginning o f the
algorithm when it returns to determine the status of the
operation.
Q5 : Exceeded Timing Limits
Q5 will indicate if the program or erase time has ex-
Q6:Toggle BIT I
To ggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence (prior to the
program or erase operation), and during the sector time-
out.
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ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
no t successfully completed. Data Po lling and To ggle Bit
are the only operating functions of the device under this
condition.
If this time-out condition occurs during sector erase op-
eratio n, it specifies that a particular secto r is bad and it
may no t be reused. However , other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
Status Q7 Q6 Q5 Q3 Q2 RY/BY
(Note1) (Note2)
Byte/Word Program in Auto Program Algorithm Q7 Toggle 0 N/A No 0
Toggle
Auto Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase Suspend Read 1 No 0 N/A Toggle 1
(Erase Suspended Sector) Toggle
In Progress Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1
(Non-Erase Suspended Sector)
Erase Suspend Program Q7 Toggle 0 N/A N/A 0
Byte/Word Program in Auto Program Algorithm Q7 Toggle 1 N/A No 0
Toggle
Exceeded
Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0
Erase Suspend Program Q7 Toggle 1 N/A N/A 0
Table 8. WRITE OPERATION ST ATUS
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5: Exceeded Timing Limits " for more infor mation.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
If this time-out condition occurs during the byte/word
programming operation, it specifies that the entire sec-
tor containing that byte/word is bad and this sector may
not be reused, (other sectors are still functional and can
be reused).
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
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POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND .
POWER-UP SEQUENCE
The MX29L V160BT/BB powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
pro tected secto r to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET pin to VID (11.5V -12.5V). During this mo de, fo r-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin. All the previously protected sectors are pro-
tected again.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and T o ggle Bit are valid after the initial secto r erase co m-
mand sequence.
If Data P o lling o r the To ggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the co m-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
DATA PROTECTION
The MX29LV160BT/BB is designed to of fer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down tran-
sition or system noise.
WRITE PULSE "GLITCH" PROTECTION
No ise pulses of less than 5ns (typical) on OE, CE or WE
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH o r WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
SECTOR PROTECTION
The MX29LV160BT/BB features hardware sector pro-
tectio n. This f eature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and OE (suggest VID = 12V). Program-
ming of the protection circuitry begins on the falling edge
of the WE pulse and is ter minated on the r ising edge.
Please refer to sector protect algorithm and waveform.
To verify programming o f the pro tection circuitry , the pro-
gramming equipment must force VID on address pin A9
( with CE and OE at VIL and WE at VIH). When A1=VIH,
A0=VIL, A6=VIL, it will produce a logical "1" code at
de vice output Q0 for a pro tected sector. Otherwise the
device will produce 00H for the unprotected sector. In
this mode, the addresses, except for A1, are don't care.
Address locations with A1 = VIL are reser ved to read
manufacturer and device codes. (Read Silicon ID)
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
P erfo rming a read operatio n with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
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CHIP UNPROTECT
The MX29LV160BT/BB also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
code. It is recommended to protect all sectors before
activating chip unprotect mode.
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.
Refer to chip unprotect algorithm and waveform for the
chip unprotect algorithm. The unprotection mechanism
begins on the falling edge of the WE pulse and is
terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
The system must write the reset command to exit the
"Silicon-ID Read Command" code.
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ABSOLUTE MAXIMUM RATINGS
Storage T emperature
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Vo ltage with Respect to Gro und
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE, and
RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (No te 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-
mum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may over-
shoot to VCC +2.0 V for periods up to 20 ns.
2. Minimum DC input voltage on pins A9, OE, and
RESET is -0.5 V. During voltage transitions, A9, OE,
and RESET may overshoot VSS to -2.0 V f o r perio ds
of up to 20 ns. Maximum DC input voltage on pin A9
is +12.5 V which ma y oversho ot to 14.0 V fo r perio ds
up to 20 ns.
3. No mo re than one output ma y be shorted to gro und at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
OPERATING RATINGS
Commercial (C) Devices
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA ). . . . . . . . . . - 40°C to +85°C
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
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CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS
CIN1 Input Capacitance 6 7.5 pF VIN = 0V
CIN2 Control Pin Capacitance 7.5 9 pF VIN = 0V
COUT Output Capacitance 8.5 12 pF VOUT = 0V
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3.Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.
Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS
ILI Input Leakage Current ± 1 uA VIN = VSS to VCC, VCC=VCC max
ILIT A9 Input Leakage Current 3 5 u A VCC=VCC max; A9=12.5V
ILO Output Leakage Current ± 1 uA VOUT = VSS to VCC, VCC=VCC max
ICC1 VCC Active Read Current 9 1 6 mA CE=VIL, OE=VIH @5MHz
2 4 mA (Byte Mode) @1MHz
9 16 mA CE=VIL, OE=VIH @5MHz
2 4 mA (Word Mode) @1MHz
ICC2 VCC Active write Current 2 0 3 0 mA CE=VIL, OE=VIH, WE=VIL
ICC3 VCC Standby Current 0.2 5 uA CE; RESET=VCC ± 0.3V
ICC4 VCC Standby Current 0.2 5 uA RESET=VSS ± 0.3V
During Reset (See Conditions)
ICC5 Automatic sleep mode 0.2 5 uA VIH=VCC ± 0.3V;VIL=VSS ± 0.3V
VIL Input Low Voltage (Note 1) -0.5 0.8 V
VIH Input High Voltage 0.7xVCC VCC+ 0.3 V
VID Voltage for Automatic
Select and Temporary 11.5 12.5 V VCC=3.3V
Sector Unprotect
VOL Output Low Voltage 0.45 V IOL = 4.0mA, VCC= VCC min
VOH1 Output High Voltage (TTL) 0.85xVCC IOH = -2mA, VCC=VCC min
VOH2 Output High Voltage VCC-0.4 IOH = -100uA, VCC min
(CMOS)
VLKO Low VCC Lock-out 1.4 2.1 V
Voltage
Table 9. DC CHARACTERISTICS TA = -40oC T O 85oC, VCC = 2.7V~3.6V
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29LV160BT/BB-70 29LV160BT/BB-90
Symbol PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS
tRC Read Cycle Time (Note 1) 7 0 9 0 n s
tACC Address to Output Delay 7 0 9 0 ns CE=OE=VIL
tCE CE to Output Delay 70 90 ns OE=VIL
tOE OE to Output Delay 30 30 ns CE=VIL
tDF OE High to Output Float (Note2) 0 25 0 25 n s CE=VIL
tOEH Output Enable Read 0 0 ns
Hold Time Toggle and Data Polling 10 10 ns
tOH Address to Output hold 0 0 ns CE=OE=VIL
NOTE:
1. Not 100% tested.
2. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
TEST CONDITIONS:
•Input pulse levels: 0V/3.0V.
•Input rise and fall times is equal to or less than 5ns.
•Output load: 1 TTL gate + 100pF (Including scope and
jig) for 29LV160BT/BB-90, 1 TTL gate + 30pF (Includ-
ing scope and jig) for 29LV160BT/BB-70.
•Reference levels for measuring timing: 1.5V.
AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 10. READ OPERATIONS
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SWITCHING TEST CIRCUITS
SWITCHING TEST WAVEFORMS
TEST POINTS
3.0V
0V
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
OUTPUT
INPUT
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm +3.3V
CL=100pF Including jig capacitance for MX29LV160BT/BB-90
CL=30pF Including jig capacitance for MX29LV160BT/BB-70
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Figure 1. READ TIMING WAVEFORMS
Addresses
CE
OE
tACC
WE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
HIGH Z HIGH Z
D ATA V alid
tOE
tOEH tDF
tCE
tACC
tRC
Outputs
RESET
tOH
ADD V alid
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29LV160BT/BB-70 29LV160BT/BB-90
SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT
tWC Write Cycle Time (Note 1) 7 0 9 0 ns
tAS Address Setup Time 0 0 ns
tAH Address Hold Time 4 5 4 5 ns
tDS Data Setup Time 3 5 45 ns
tDH Data Hold Time 0 0 ns
tOES Output Enable Setup Time 0 0 ns
tGHWL Read Recovery Time Before Write 0 0 ns
(OE High to WE Low)
tCS CE Setup Time 0 0 ns
tCH CE Hold Time 0 0 ns
tWP Write Pulse Width 3 5 3 5 ns
tWPH Write Pulse Width High 3 0 30 ns
tWHWH1 Programming Operation (Note 2) 9/11(typ.) 9/11(typ.) us
(Byte/Word program time)
tWHWH2 Sector Erase Operation (Note 2) 0.7(typ.) 0.7(typ.) sec
tVCS VCC Setup Time (Note 1) 5 0 5 0 us
tRB Recovery Time from RY/BY 0 0 n s
tBUSY Sector Erase Valid to RY/BY Delay 90 90 ns
Chip Erase Valid to RY/BY Delay 90 9 0 ns
Program Valid to RY/BY Delay 9 0 9 0 ns
tWPP1 Write pulse width for sector 100ns 10us(typ.) 100ns 10us(typ.)
protect (A9, OE Control)
tWPP2 Write pulse width for sector 100ns 12ms(typ.) 100ns 12ms(typ.)
unprotect (A9, OE Control)
tVLHT Voltage transition time 4 4 us
tOESP OE setup time to WE active 4 4 us
NOTES:
1. Not 100% tested.
2. See the "Erase and Programming P erf ormance" sectio n f or mo re info rmation.
Table 11. Erase/Program Operations
AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V
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29LV160BT/BB-70 29LV160BT/BB-90
SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT
t WC Write Cycle Time (No te 1) 7 0 9 0 ns
tAS Address Setup Time 0 0 ns
tAH Address Ho ld Time 4 5 4 5 ns
tDS Data Setup Time 3 5 4 5 ns
tDH Data Ho ld Time 0 0 ns
tOES Output Enable Setup Time 0 0 ns
tGHEL Read Reco very Time Befo re Write 0 0 ns
tWS WE Setup Time 0 0 ns
t WH WE Ho ld Time 0 0 ns
tCP CE Pulse Width 3 5 3 5 ns
tCPH CE Pulse Width High 3 0 3 0 ns
tWHWH1 Programming Byte 9(Typ.) 9(Typ.) us
Operation(note2) Word 11(Typ.) 11(Typ.) us
tWHWH2 Sector Erase Operation (note2) 0.7(Typ.) 0.7(Typ.) sec
NOTE:
1. Not 100% tested.
2. See the "Erase and Programming P erf ormance" sectio n f or mo re info rmation.
AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 12. Alternate CE Controlled Erase/Program Operations
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Figure 2. COMMAND WRITE TIMING WAVEFORM
Addresses
CE
OE
WE
DIN
tDS
tAH
Data
tDH
tCS tCH
tCWC
tWPH
tWP
tOES
tAS
VCC
3V
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ADD V alid
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AUTOMATIC PROGRAMMING TIMING WAVEFORM
Figure 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tion can be verified by DATA polling o r toggle bit check-
ing after auto matic programming starts. Device o utputs
DAT A during pro gramming and DATA after programming
on Q7.(Q6 is f or toggle bit; see to ggle bit, DATA polling,
timing waveform)
tWC
Address
OE
CE
A0h
555h PA
PD Status DOUT
PA PA
NOTES:
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH1
Read Status Data (last two cycle)Program Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE
Data
RY/BY
VCC
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Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH
Write Data 55H
Write Program Data/Address
Write Data A0H
YES
Verify Data Ok ?
YES
Auto Program Completed
Data Poll
from system
Increment
Address
Last Address ?
No
No
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Figure 5. CE CONTROLLED WRITE TIMING WAVEFORM
tWC
tWH
tGHEL
tWHWH1 or 2
tCP
Address
WE
OE
CE
Data Q7
PA
Data Polling
DOUT
RESET
RY/BY
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
tAH
tAS
PA for program
SA for sector erase
555 for chip erase
tRH
tDH
tDS
tWS
A0 for program
55 for erase
tCPH
tBUSY
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
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All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA polling or toggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle
bit, D ATA po lling, timing wa v eform)
Figure 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM
AUTOMATIC CHIP ERASE TIMING WAVEFORM
tWC
Address
OE
CE
55h
2AAh 555h
10h In
Progress Complete
VA VA
NOTES:
VA=Valid Address for reading status data(see "Write Operation Status").
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE
Data
RY/BY
VCC
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Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data Poll from System
Auto Chip Erase Completed
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Figure 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A12 to A19 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tio n can be v erified by D ATA po lling o r to ggle bit chec k-
ing after automatic erase starts. De vice outputs 0 dur-
ing erasure and 1 after erasure on Q7. (Q6 is for toggle
bit; see toggle bit, DATA polling, timing wav ef orm)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
tWC
Address
OE
CE
55h
2AAh SA
30h
In
Progress Complete
VA VA
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
tAS
tAH
tGHWL
tCH
tWP
tDS tDH
tWHWH2
Read Status Data Erase Command Sequence(last two cycle)
tBUSY tRB
tCS tWPH
tVCS
WE
Data
RY/BY
VCC
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Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data Poll from System
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
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Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Delay 10ms (note)
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
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Figure 11. IN-SYSTEM SECTOR PROTECT/CHIP UNPROTECT TIMING WAVEFORM (RESET Control)
Sector Protect =150us
chip Unprotect =15ms
1us
VID
VIH
Data
SA, A6
A1, A0
CE
WE
OE
Valid* Valid*
Status
Valid*
Sector Protect or Sector Unprotect
40h60h60h
Verify
RESET
Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0.
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Figure 12. SECTOR PROTECT TIMING W AVEFORM (A9, OE Contr ol)
tOE
Data
OE
WE
12V
5V
12V
5V
CE
A9
A1
A6
tOESP
tWPP 1
tVLHT
tVLHT
tVLHT
Verify
01H F0H
A19-A12 Sector Address
Notes: tVLHT (Vo ltage transitio n time)=4us min.
tOESP (OE setup time to WE active)=4us min.
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Figure 13. SECTOR PROTECTION ALGORITHM (A9, OE Control)
START
Set Up Sector Addr
PLSCNT=1
Sector Protection
Complete
Data=01H?
Yes
.
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 150us
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1, A6=0, A0=0
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=32?
Yes
No
No
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Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET=VID
START
PLSCNT=1
First Write
Cycle=60H
Yes
No
RESET=VID
Wait 1us
Set up sector address
Write 60H to sector address
with A6=0, A1=1, A0=0
Verify sector protect :
write 40H with A6=0,
A1=1, A0=0
Wait 150us
Increment PLSCNT
Read from sector address
Remove VID from RESET
Temporary Sector
Unprotect Mode
Reset PLSCNT=1
Data=01H
Yes
Yes
Yes
No
No
No
?
PLSCNT=25?
Protect another
sector?
Write reset command
Sector protect complete
Device failed
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Figure 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET=VID
START
PLSCNT=1
First Write
Cycle=60H ?
Yes
No
RESET=VID
Wait 1us
Set up first sector address
Sector unprotect :
write 60H with
A6=1, A1=1, A0=0
Verify sector unprotect
write 40H to sector address
with A6=1, A1=1, A0=0
Wait 50ms
Increment PLSCNT
Read from sector address
with A6=1, A1=1, A0=0
Remove VID from RESET
Temporary Sector
Unprotect Mode
Set up next sector address
All sector
protected?
Yes
Data=00H
Yes
Yes
Yes
No
No
No
No Protect all sectors
?
PLSCNT=1000?
Last sector
verified?
Write reset command
Sector unprotect complete
Device failed
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Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE Control)
tOE
Data
OE
WE
12V
Vcc 3V
12V
Vcc 3V
CE
A9
A1
tOESP
tWPP 2
tVLHT
tVLHT
tVLHT
Verify
00H
A6
Sector Address
A19-A12
F0H
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Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE Control)
START
Protect All Sectors
PLSCNT=1
Chip Unprotect
Complete
Data=00H?
Yes
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 50ms
Set OE=CE=VIL
A9=VID, A1=1, A6=0, A0=0
Set Up First Sector Addr
All sectors have
been verified?
Remove VID from A9
Write Reset Command
Device Failed
PLSCNT=1000?
No
Increment
PLSCNT
No
Read Data from Device
Yes
Yes
No
Increment
Sector Addr
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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Figure 18. DATA POLLING ALGORITHM
WRITE OPERATION STATUS
Read Q7~Q0
Add.=VA(1)
Read Q7~Q0
Add.=VA
Start
Q7 = Data ?
Q5 = 1 ?
Q7 = Data ?
FAIL Pass
No
No
(2)
No
Yes
Yes
Yes
NOTE : 1.VA=Valid address for programming or erasure.
2.Q7 should be re-checked even Q5="1" because Q7 may change
simultaneously with Q5.
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Figure 19. TOGGLE BIT ALGORITHM
Read Q7-Q0
Read Q7-Q0
Q5= 1?
Read Q7~Q0 Twice
Program/Erase Operation
Not Complete,Write
Reset Command
Program/Erase
operation Complete
Toggle bit Q6=
Toggle?
Toggle Bit Q6 =
Toggle ? NO
(Note 1)
(Note 1,2)
YES
NO
NO
YES
YES
Note:1.Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".
Start
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Figure 20. Data Polling Timings (During Automatic Algorithms)
RY/BY
NOTES:
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
tDF
tCE
tACC
tRC
tCH tOE
tOEH
tOH
tBUSY
Address
CE
OE
WE
DQ7
Q0-Q6 Status Data Status Data
Complement Complement Valid DataTrue
VAVAVA
High Z
High Z
Valid DataTrue
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NOTES:
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
tDF
tCE
tACC
tRC
tCH
tOE
tOEH
tBUSY
High Z
tOH
Address
CE
OE
WE
Q6/Q2
RY/BY
Valid Status
(first raed)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA
Valid Data
Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
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Figure 22. RESET TIMING WAVEFORM
Table 13. AC CHARACTERISTICS
Parameter Std Description T est Setup All Speed Options Unit
tREADY1 RESET PIN Low (During Automatic Algorithms) MAX 2 0 us
to Read o r Write (See No te)
tREADY2 RESET PIN Low (NO T During Auto matic MAX 5 00 ns
Algo rithms) to Read o r Write (See No te)
tRP RESET Pulse Width (During Auto matic Algo rithms) M IN 5 0 0 ns
t RH RESET High Time Befo re Read (See No te) MIN 7 0 ns
tRB R Y/BY Recov ery Time (to CE, OE go lo w) MI N 70 ns
Note:Not 100% tested
tRH
tRB
tReady1
tRP
tRP
tReady2
RY/BY
CE, OE
RESET
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY
CE, OE
RESET
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Figure 23. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from byte
mode to word mode)
tFHQV
tELFH
DOUT
(Q0-Q7) DOUT
(Q0-Q14)
VA DOUT
(Q15)
CE
OE
BYTE
Q0~Q14
Q15/A-1
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE)
Parameter Description Speed Options Unit
JEDEC Std -70 -90
tELFL/tELFH CE to BYTE Switching Low or High Max 5 ns
tFLQZ BYTE Switching Low to Output HIGH Z Ma x 2 5 30 n s
tFHQV BYTE Switching High to Output Active Mi n 70 90 ns
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Figure 24. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from word
mode to byte mode)
Figure 25. BYTE TIMING WAVEFORM FOR PROGRAM OPERATIONS
tAS tAH
The falling edge of the last WE signal
CE
WE
BYTE
tFLQZ
tELFH
DOUT
(Q0-Q7)
DOUT
(Q0-Q14)
VA
DOUT
(Q15)
CE
OE
BYTE
Q0~Q14
Q15/A-1
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Table 14. TEMPORARY SECTOR UNPROTECT
Parameter Std. Description Test Setup All Speed Options Unit
tVI DR VID Rise and F all Time (See No te) Mi n 5 0 0 ns
tRSP RESET Setup Time fo r T empo rary Sector Unprotect Min 4 us
Note:
Not 100% tested
Figure 26. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM
RESET
CE
WE
RY/BY
tVIDR tVIDR
Program or Erase Command Sequence
12V
0 or Vcc 0 or Vcc
tRSP
Figure 27. Q6 vs Q2 for Erase and Erase Suspend Operations
NOTES:
The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
WE
Enter Embedded
Erasing Erase
Suspend Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase Suspend
Read Erase
Erase
Resume
Erase
Complete
Erase
Q6
Q2
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Figure 28. TEMPORARY SECTOR UNPROTECT ALGORITHM
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Operation Completed
2. All previously protected sectors are protected again.
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
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Figure 29. ID CODE READ TIMING WAVEFORM
tACC
tCE
tACC
tOE
tOH tOH
tDF
DATA OUT
C2H/00C2H C4H/49H (Byte)
22C4H/2249H (Word)
VID
VIH
VIL
ADD
A9
ADD
A2-A8
A10-A19
CE
OE
WE
ADD
A0
DATA OUT
DATA
Q0-Q15
VCC
A1
3V
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
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MIN. MAX.
Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V
Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V
VCC Current -100mA +100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
LIMITS
PARAMETER MIN. TYP.(2) MAX.(3) UNITS
Sector Erase Time 0. 7 1 5 sec
Chip Erase Time 1 5 30 sec
Byte Programming Time 9 300 us
Word Programming Time 1 1 3 60 us
Chip Programming Time Byte Mode 1 8 5 4 sec
Word Mode 12 36 sec
Erase/Program Cycles 100,000 Cycles
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE (1)
Note: 1. Not 100% Tested, Excludes e xternal system le v el ov er head.
2. Typical values measured at 25°C, 3V .
3. Maximum values measured at 85°C , 2.7V, 100,000 cycles.
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P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark
TIME (ns) Current MAX. (mA) Current MAX. (uA)
MX29LV160BTMC-70 70 30 5 44 Pin SOP
MX29LV160BBMC-70 70 30 5 44 Pin SOP
MX29LV160BTMC-90 90 30 5 44 Pin SOP
MX29LV160BBMC-90 90 30 5 44 Pin SOP
MX29LV160BTMI-70 70 30 5 44 Pin SOP
MX29LV160BBMI-70 70 30 5 44 Pin SOP
MX29LV160BTMI-90 90 30 5 44 Pin SOP
MX29LV160BBMI-90 90 30 5 44 Pin SOP
MX29LV160BTTC-70 7 0 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BBTC-70 70 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BTTC-90 9 0 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BBTC-90 90 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BTTI-70 70 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BBTI-70 70 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BTTI-90 90 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BBTI-90 90 30 5 48 Pin TSOP
(Normal T ype)
MX29LV160BTXBC-70 70 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BBXBC-70 7 0 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BTXBC-90 90 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BBXBC-90 9 0 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BTXBI-70 70 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BBXBI-70 70 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BTXBI-90 90 30 5 48 Ball CSP
(ball size:0.3mm)
MX29LV160BBXBI-90 90 30 5 48 Ball CSP
(ball size:0.3mm)
ORDERING INFORMATION
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P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark
TIME (ns) Current MAX. (mA) Current MAX. (uA)
MX29LV160BTXEC-70 70 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BBXEC-70 7 0 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BTXEC-90 90 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BBXEC-90 9 0 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BTXEI-70 70 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BBXEI-70 70 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BTXEI-90 90 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BBXEI-90 90 30 5 48 Ball CSP
(ball size:0.4mm)
MX29LV160BTTC-70G 7 0 30 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BBTC-70G 7 0 3 0 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BTTC-90G 9 0 30 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BBTC-90G 9 0 3 0 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BTTI-70G 7 0 3 0 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BBTI-70G 70 30 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BTTI-90G 9 0 3 0 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BBTI-90G 90 30 5 48 Pin TSOP PB free
(Normal T ype)
MX29LV160BTXBC-70G 7 0 3 0 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BBXBC-70G 70 30 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BTXBC-90G 9 0 3 0 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BBXBC-90G 90 30 5 48 Ball CSP PB free
(ball size:0.3mm)
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P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark
TIME (ns) Current MAX. (mA) Current MAX. (uA)
MX29LV160BTXBI-70G 7 0 30 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BBXBI-70G 7 0 30 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BTXBI-90G 9 0 30 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BBXBI-90G 9 0 30 5 48 Ball CSP PB free
(ball size:0.3mm)
MX29LV160BTXEC-70G 7 0 3 0 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BBXEC-70G 70 30 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BTXEC-90G 9 0 3 0 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BBXEC-90G 90 30 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BTXEI-70G 7 0 30 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BBXEI-70G 7 0 30 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BTXEI-90G 9 0 30 5 48 Ball CSP PB free
(ball size:0.4mm)
MX29LV160BBXEI-90G 9 0 30 5 48 Ball CSP PB free
(ball size:0.4mm)
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PACKAGE INFORMATION
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48-Ball CSP (for MX29LV160BTXBC/BTXBI/BBXBC/BBXBI)
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48-Ball CSP (for MX29LV160BTXEC/BTXEI/BBXEC/BBXEI)
62
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REVISION HISTORY
Revision No. Description Page Date
1.0 1. Added 90ns & pb-free information All MAR/16/2004
2. Removed 55R information All
3. Removed "Advanced Information" P1
1.1 1. To added data retention information P1 MAY/28/2004
1. 2 1. To corrected CFI Query command address P10 JUL/01/2004
2. To added "PB free" remark P56,57
MX29LV160BT/BB
MACRONIX INTERNATIONAL CO., LTD .
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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