TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com High-Efficiency, 5-A Step-Down Regulator with Integrated Switcher Check for Samples: TPS53316 FEATURES LOW VOLTAGE APPLICATIONS * * * * * 1 2 * * * * * * * * * * * * * * 96% Maximum Efficiency Continuous 5-A Output Current Capability Support all MLCC Output Capacitor SmoothPWMTM Auto-Skip Eco-modeTM for Light-Load Efficiency Voltage Mode Control Single Rail Input Selectable Frequency Selectable OCP Threshold Selectable Soft-Start Time 2.9 V to 6.0 V Input Voltage Range Adjustable Output Voltage Ranging from 0.6 V up to 0.8 x VIN Soft-Stop Output Discharge During Disable Overcurrent, Overvoltage and Over-Temperature Protection Open-Drain Power Good Indication Internal Bootstrap Switch Supports Pre-Bias Start-Up Functionality Small 3 x 3, 16-Pin, QFN Package Low RDS(on), 22-m with 3.3-V input and 18-m with 5-V Input * Low-Voltage Applications for 5-V Step-Down Rail Low-Voltage Applications for 3.3-V Step-Down Rail DESCRIPTION TPS53316 provides a fully integrated 3.3-V or 5-V input, synchronous buck converter with 16 total components, in 200 mm2 of PCB area. Due to low RDS(on) and TI proprietary SmoothPWMTM skip mode of operation, it enables 96% peak efficiency and over 90% efficiency at load as light as 100 mA. It requires only two 22-F ceramic output capacitors for a power-dense, 5-A solution. TPS53316 features 750-kHz, 1.1-MHz and 2-MHz switching frequency selections, pre-bias startup, selectable internal softstart, output soft discharge, Internal VBST switch, power good, EN/Input UVLO, overcurrent, overvoltage, undervoltage and over temperature protections and all ceramic output capacitor support. It supports input voltages from 2.9 V to 6.0 V and no extra bias voltage is needed. The output voltage is adjustable from 0.6 V up to 0.8 x VIN. TPS53316 is available in the 3 mm x 3 mm ,16-pin, QFN package (Green RoHs compliant and Pb free) and is specified from -40C to 85C. TYPICAL APPLICATION CIRCUIT 2.9 V to 6 V Output All MLCCs VREG3 VIN CBST SW VIN VBST AGND TPS53316 EN EN RF/OC PS PowerPad PGD PGD FB COMP UDG-11233 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Eco-mode, SmoothPWM are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (2) TA PACKAGE Plastic QFN (RGT) -40C to 85C (1) (2) ORDERABLE DEVICE NUMBER PINS OUTPUT SUPPLY MINIMUM QUANTITY ECO PLAN TPS53316RGTR 16 Tape and reel 3000 TPS53316RGTT 16 Mini reel 250 Green (RoHS and no Pb/Br) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package ABSOLUTE MAXIMUM RATINGS (1) Over operating free air-temperature range (unless otherwise noted) VALUE Input voltage range VIN -0.3 to 7 VBST -0.3 to17 VBST(with respect to LL) -0.3 to 7 EN -0.3 to 7 Output voltage range V -0.3 to 3.7 FB, PS. RF/OC SW UNIT -1 to 7 DC Pulse < 20ns, E=5J -5 or <10 -0.3 to 7 PGD COMP, VREG3 -0.3 to 3.7 PGND -0.3 to 0.3 V Operating free-air temperature, TA -40 to 85 C Storage temperature range, Tstg -55 to 150 C Junction temperature range, TJ -40 to 150 C 300 C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS VALUE MIN VIN (main supply) Input voltage range 2.9 6 VBST -0.1 13.5 VBST(with respect to SW) -0.1 6 EN, -0.1 6 FB, PS, RF/OC -0.1 3.5 -1 6.5 SW Output voltage range UNIT MAX PGD -0.1 6 COMP, VREG3 -0.1 3.5 PGND -0.1 0.1 -40 125 Junction temperature range, TJ V V C THERMAL INFORMATION THERMAL METRIC (1) TPS53316 RGT (16) PINS JA Junction-to-ambient thermal resistance 45.9 JCtop Junction-to-case (top) thermal resistance 54.3 JB Junction-to-board thermal resistance 18.3 JT Junction-to-top characterization parameter 1.1 JB Junction-to-board characterization parameter 18.3 JCbot Junction-to-case (bottom) thermal resistance 5.3 (1) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 3 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VIN = 3.3V, PGND = GND (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY: VOLTAGE, CURRENTS, AND UVLO VVIN VIN supply voltage Nominal input voltage range IVIN(sdn) VIN shutdown current EN = LO 2.9 IVIN VIN supply current EN = HI, VFB = 0.63 V, No load VUVLO VIN UVLO threshold Ramp up; EN =HI 2.8 V VUVLO(hys) VIN UVLO hysteresis VIN UVLO hysteresis 120 mV VREG3 LDO output VVIN = 5 V, 0 IDD 5 mA 2.0 3.135 3.3 6.0 V 15 A 3.5 mA 3.465 V VOLTAGE FEEDBACK LOOP: VREF AND ERROR AMPLIFIER VVREF VREF Internal precision reference voltage 0.6 0C TA 85C 1% -1.25% 1.25% TOLVREF VREF tolerance UGBW (1) Unity gain bandwidth 14 AOL (1) Open loop gain 80 IFBINT FB input leakage current Sourced from FB pin IEA(max) (1) Outaput sinking and sourcing current CCOMP = 20 pF SR (1) -40C TA 85C V -1% MHz dB 30 Slew rate nA 5 mA 5 V/s OCP: OVERCURRENT AND ZERO CROSSING Overcurrent limit on high-side FET 4.5-A setting, when IOUT exceeds this threshold for 4 consecutive cycles, VVIN = 3.3V, VOUT = 1.5 V with 1-H inductor, fSW = 1.1 MHz, TA= 25C 4.05 4.5 4.95 A One-time overcurrent latch off on the low-side FET 4.5-A setting, immediate shut down when sensed current reach this value VVIN = 3.3 V, VOUT = 0.6 V with 1-H inductor, fSW = 1.1 MHz, TA= 25C 4.49 5.1 5.61 A IOCPL5A (2) Overcurrent limit on high-side FET 6.5-A setting, when IOUT exceeds this threshold for 4 consecutive cycles, VVIN = 3.3 V, VOUT = 1.5 V with 1-H inductor, fSW = 1.1 MHz, TA= 25C 6.1 6.8 7.5 A IOCPH5A (2) One time overcurrent latch off on the low-side FET 6.5-A setting, immediate shut down when sensed current reach this value VVIN = 3.3 V, VOUT = 0.6 V with 1-H inductor, fSW = 1.1 MHz, TA= 25C 6.75 7.50 8.30 A thiccup Hiccup time interval fSW = 1.1 MHz VZXOFF (1) Zero crossing comparator internal offset PGND - SW, SKIP mode IOCPL3A (2) IOCPH3A (2) 14.5 ms -4.5 -3.0 -1.5 mV PROTECTION: OVP, UVP, PGD, AND INTERNAL THERMAL SHUTDOWN VOVP Overvoltage protection threshold voltage Measured at the FB w/r/t VREF 114% 117% 120% VUVP Undervoltage protection Threshold voltage Measured at the FB w/r/t VREF 80% 83% 86% VPGDL PGD low threshold Measured at the FB w/r/t VREF 80% 83% 86% VPGDU PGD upper threshold Measured at the FB w/r/t .VREF 114% 117% 120% VINMINPG Minimum input voltage for valid PGD at start-up Measured at VIN with 1-mA sink current on PGD pin at start up THSD (1) THSDHYS (1) (2) Thermal shutdown (1) Thermal shutdown hysteresis 1 130 Controller start again after temperature has dropped 140 40 V 150 C C Ensured by design. Not production tested. See Figure 5 and Figure 6 on OCP level for other operating conditions. 4 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN = 3.3V, PGND = GND (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT 0.1 0.3 V 0 2 A LOGIC PINS: I/O VOLTAGE AND CURRENT VPGPD PGD pull down voltage Pull down voltage with 4mA sink current IPGLK PGD leakage current Hi-Z leakage current, Apply 3.3V in off state RENPU Enable pull-up resistor VENH EN logic high VENHYS -2 2.25 VVIN = 3.3 V 0.82 0.97 1.10 V VVIN = 5 V 0.95 1.10 1.25 V 0.16 0.24 V 0.2 0.275 V VVIN = 3.3 V EN hysteresis VVIN = 5 V Level 1 to Level 2 (3) PSTHS PS mode threshold voltage 0.12 Level 2 to Level 3 0.4 Level 3 to Level 4 0.8 Level 4 to Level 5 1.4 Level 5 to Level 6 IPS PS source RF/OC pin threshold voltage 8 (4) RF/OC source current 10 0.4 Level 3 to Level 4 0.8 Level 4 to Level 5 1.4 10-A pull-up current when enabled 12 A 0.12 Level 2 to Level 3 Level 5 to Level 6 IRF/OC V 2.2 10-A pull-up current when enabled Level 1 to Level 2 RF/OCTHS M V 2.2 8 10 12 A 1 A BOOT STRAP: VOLTAGE AND LEAKAGE CURRENT IVBSTLK VBST leakage current VVIN = 3.3 V, VVBST = 6.6 V, TA = 25C TIMERS: SS, FREQUENCY, RAMP, ON-TIME AND I/O TIMING EN = `HI' 0.2 0 V VSS 0.6 V 0.4 0 V VSS 0.6 V, 4 x SS time(option2) 1.6 VSS = 0.6 V to PGD (SSOK) going high 0.3 VSS = 0.6 V to PGD (SSOK), option 2 1.2 tSS_1 Delay after EN Asserting tSS_2 Soft start ramp_up time tPGDENDLY PGD startup delay time tOVPDLY OVP delay time Time from FB out of +20% of VREF to OVP fault tUVPDLY UVP delay time Time from FB out of -20% of VREF to UVP fault fSW Switching frequency Ramp amplitude 1.7 ms ms 2.5 0.653 0.725 0.798 All modes, fSET = 1.1 MHz 0.99 1.10 1.21 FCCM and DE mode, fSET = 2 MHz 1.71 1.90 2.09 1.566 1.800 2.034 2.9 V VVIN 6.0 V s s 10 All modes, fSET = 0.75 MHz HEF mode, fSET = 2 MHz (5) 1.0 ms VVIN/4 MHz V Minimum OFF time, FCCM and DE All frequencies 90 130 ns Minimum OFF time, HEF fSW = 1.1 MHz 160 240 ns DMAX Maximum duty cycle, FCCM and DE fSW = 1.1 MHz 84% 89% DMAX Maximum duty cycle, HEF All frequencies 75% 81% RSFTSTP Soft-discharge transistor resistance EN = LO, VVIN = 3.3 V, VOUT = 0.5 V tMIN(off) (3) (4) (5) 60 See PS pin description for levels. See RF/OC pin description for levels. Ensured by design. Not production tested. 5 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com DEVICE INFORMATION EN 1 RF/OC 2 PGND PGND VIN VIN QFN PACKAGE 16 PINS (TOP VIEW) 16 15 14 13 12 VREG3 11 AGND TPS53316 VBST 4 9 COMP 5 6 7 8 PS FB SW 10 SW 3 SW PGD PIN DESCRIPTIONS PIN I/O (1) DESCRIPTION NAME NO. AGND 11 G Device analog ground terminal COMP 9 O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability. EN 1 I Enable pin. Internally pulled-up to the VIN pin through a 2-M resistor. The EN voltage needs to be less than (VIN+ 0.5 V) FB 10 I Voltage feedback pin. Use for OVP, UVP and PGD determination PGD 3 O Power good output flag. Open drain output. Pull up to an external rail via a resistor P Device power ground terminal I Mode configuration pin (with10 A current): Connecting to ground: Forced CCM with 4 x soft-start time Pulled high or floating (internal pulled high): Forced CCM master Connect with 24.3 k to GND: HEF mode with 4 x soft-start time, Connect with 57.6 k to GND: HEFF mode Connect with 105 k to GND : DE mode Connect with 174 k to GND: DE Mode with 4 x soft-start time I Switching frequency and OC level configuration pin: Connecting to ground: 1.1 MHz, 6.5 A OCP Pulled high or floating (internal pulled high): 1.1 MHz, 4.5 A OCP Connect with 24.3 k to GND: 750 kHz, 4.5 A OCP Connect with 57.6 k to GND: 750 kHz, 6.5 A OCP Connect with 105 k to GND : 2 MHz, 4.5 A OCP Connect with 174 k to GND: 2MHz, 6. 5A OCP B Output inductor connection to integrated power devices PGND PS 15 16 8 RF/OC 2 5 SW 6 7 VBST 4 P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal VREG3 12 O 3.3V LDO output, serves as supply voltage for internal analog circuitry. The EN pin controls the turn-on function of the LDO. P Gate driver supply and power conversion input voltage. The input range is from 2.9 V to 6 V. - Thermal pad of the device. use 4 or 5 vias to connect to GND plane for heat dissipation. 13 VIN 14 PowerPad (1) - I - Input; B - Bidirectional; O - Output; G - Ground; P - Supply (or Ground) 6 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN 0.6 V UV/OV Threshold Generation 0.6 V-20% FB VBST + UV VIN UVLO UV 0.6 V+20% + OV OV Control Logic HDRV PWM + COMP E/A + 0.6 V Ramp SW + XCON PWM LL One-Shot Overtemp VOUT Discharge SS LDRV PGND Enable Control Mode Scanner Frequency and OCP Setting OCP Logic UVLO VREG3 VIN LDO TPS53316 EN PS RF/OC AGND PGD UDG-11234 7 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Inductor used: PCMC065T-1R0, 1 H, 5.6 m 3.0 610 2.5 606 Input Current (mA) Reference Voltage (mV) 608 604 602 600 598 596 594 2.0 1.5 1.0 VIN = 3.3 V VFB = 0.63 V EN = HI 0.5 592 590 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 0.0 -40 -25 -10 110 125 1.506 1.506 1.504 1.504 1.502 1.500 1.498 1.494 fSW = 1.1 MHz 1.492 0 1 VIN = 3.3 V, FCCM VIN = 3.3 V, DE Mode VIN = 5 V, FCCM VIN = 5 V, DE Mode 2 3 Output Current (A) 4 1.496 fSW = 1.1 MHz 1.494 2.9 5 7 OCP Threshold (A) OCP Threshold (A) 6 5 4 1.0 fSW = 750 kHz, 4.5 A OC Setting fSW = 1.1 MHz, 4.5 A OC Setting fSW = 2 MHz, 4.5 A OC Setting fSW = 750 kHz, 6.5 A OC Setting fSW = 1.1 MHz, 6.5 A OC Setting fSW = 2 MHz, 6.5 A OC Setting 1.5 Output Voltage (V) 2.0 IOUT = 0 A, FCCM IOUT = 0 A, DE Mode IOUT = 1 A, FCCM IOUT = 1 A, DE Mode 3.9 4.4 4.9 Input Voltage (V) 5.4 5.9 G020 6 5 4 3 2 FCCM Mode VIN = 5 V 1 H Inductor 1 2.5 0 0.5 G021 Figure 5. OCP Threshold vs. Output Voltage G018 Figure 4. Output Voltage vs. Input Voltage 8 0 0.5 3.4 G019 7 FCCM Mode VIN = 3.3 V 1 H Inductor 110 125 1.498 9 1 95 1.500 8 2 80 1.502 Figure 3. Output Voltage vs. Output Current 3 20 35 50 65 Temperature (C) Figure 2. Input Current vs. Temperature Output Voltage (V) Output Voltage (V) Figure 1. Regerence Voltage vs. Temperature 1.496 5 G017 1 fSW = 750 kHz, 4.5 A OC Setting fSW = 1.1 MHz, 4.5 A OC Setting fSW = 2 MHz, 4.5 A OC Setting fSW = 750 kHz, 6.5 A OC Setting fSW = 1.1 MHz, 6.5 A OC Setting fSW = 2 MHz, 6.5 A OC Setting 1.5 Output Voltage (V) 2 2.5 G022 Figure 6. OCP Threshold vs. Output Voltage 8 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 2000 2000 1500 1500 Frequency (kHz) Frequency (kHz) Inductor used: PCMC065T-1R0, 1 H, 5.6 m 1000 500 0 0 1 500 fSW=750 kHz fSW=1.1 MHz fSW=2 MHz FCCM VIN=3.3 V VOUT=1.5 V 2 3 Output Current (A) 4 0 5 1500 1500 Frequency (kHz) Frequency (kHz) 2000 1000 0 0 1 2 3 Output Current (A) 4 1500 Frequency (kHz) 1500 1000 0 1 2 3 Output Current (A) 0 1 2 3 Output Current (A) G002 5 0 HEF Mode VIN=5 V VOUT=1.5 V 0 G005 Figure 11. Frequency vs. Output Current, DE Mode 4 5 G004 1000 500 fSW=750 kHz fSW=1.1 MHz fSW=2 MHz 4 5 Figure 10. Frequency vs. Output Current, FCCM 2000 0 4 fSW=750 kHz fSW=1.1 MHz fSW=2 MHz FCCM VIN=5 V VOUT=1.5 V G003 2000 DE Mode VIN=5 V VOUT=1.5 V 2 3 Output Current (A) 1000 0 5 Figure 9. Frequency vs. Output Current, HEF Mode 500 1 500 fSW=750 kHz fSW=1.1 MHz fSW=2 MHz HEF Mode VIN=3.3 V VOUT=1.5 V 0 Figure 8. Frequency vs. Output Current, DE Mode 2000 500 fSW=750 kHz fSW=1.1 MHz fSW=2 MHz DE Mode VIN=3.3 V VOUT=1.5 V G001 Figure 7. Frequency vs. Output Current, FCCM Frequency (kHz) 1000 1 2 3 Output Current (A) fSW=750 kHz fSW=1.1 MHz fSW=2 MHz 4 5 G006 Figure 12. Frequency vs. Output Current, HEF Mode 9 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 100 100 90 90 Efficiency (%) Efficiency (%) Inductor used: PCMC065T-1R0, 1 H, 5.6 m 80 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V VOUT=1.5 V VOUT=1.8 V VOUT=2.5 V 70 60 FCCM VIN=3.3 V fSW=750 kHz 0 1 2 3 Output Current (A) 4 60 5 90 Efficiency (%) 90 80 60 0 1 VOUT=0.9 V VOU=1.0 V VOU=1.2 V VOU=1.5 V VOU=1.8 V 2 3 Output Current (A) 4 60 5 1 Efficiency (%) Efficiency (%) 90 0 VOUT=0.9V VOUT=1.0V VOUT=1.2V VOUT=1.5V VOUT=1.8V VOUT=2.5V VOUT=3.3V 2 3 Output Current (A) 4 5 G008 0 1 2 3 Output Current (A) 80 60 HEF Mode VIN=5 V fSW=750 kHz 0 G011 Figure 17. Efficiency vs. Output Current, DE Mode 5 G010 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V VOUT=1.5 V VOUT=1.8 V VOUT=2.5 V VOU=3.3 V 70 5 4 Figure 16. Efficiency vs. Output Current, FCCM 90 60 4 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V VOUT=1.5 V VOUT=1.8V VOUT=2.5 V VOUT=3.3 V FCCM VIN=5 V fSW=750 kHz G009 100 DE Mode VIN=5 V fSW=750 kHz 2 3 Output Current (A) 70 100 70 1 80 Figure 15. Efficiency vs. Output Current, HEF Mode 80 0 Figure 14. Efficiency vs. Output Current, DE Mode 100 HEF Mode VIN=3.3 V fSW=750 kHz DE Mode VIN=3.3 V fSW=750 kHz G007 100 70 VOUT=0.9 V VOU=1.0 V VOU=1.2 V VOU=1.5 V VOU=1.8 V VOU=2.5 V 70 Figure 13. Efficiency vs. Output Current, FCCM Efficiency (%) 80 1 2 3 Output Current (A) 4 5 G012 Figure 18. Efficiency vs. Output Current, HEF Mode 10 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 100 100 90 90 Efficiency (%) Efficiency (%) Inductor used: PCMC065T-1R0, 1 H, 5.6 m 80 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V VOUT=1.5 V VOUT=1.8 V VOUT=2.5 V 70 60 FCCM VIN=3.3 V fSW=1.1 MHz 0 1 2 3 Output Current (A) 4 80 70 60 5 90 90 Efficiency (%) Efficiency (%) 100 80 60 0 1 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V 2 3 Output Current (A) 0 1 5 60 FCCM VIN=5 V fSW=2 MHz 0 G015 Figure 21. Efficiency vs. Output Current, FCCM 5 G014 1 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V VOUT=1.5 V VOUT=1.8 V VOUT=2.5 V VOUT=3.3 V 2 3 Output Current (A) 4 5 G016 Figure 22. Efficiency vs. Output Current, FCCM DE Mode VIN = 5 V IOUT = 0 A DE Mode VIN = 5 V IOUT = 0 A 4 80 70 VOUT=1.5 V VOUT=1.8 V VOUT=2.5 V 4 2 3 Output Current (A) Figure 20. Efficiency vs. Output Current, FCCM 100 FCCM VIN=3.3 V fSW=2 MHz FCCM VIN=5 V fSW=1.1 MHz G013 Figure 19. Efficiency vs. Output Current, FCCM 70 VOUT=0.9 V VOUT=1.0 V VOUT=1.2 V VOUT=1.5 V VOUT=1.8 V VOUT=2.5 V VOUT=3.3 V EN (5V/div) EN (5 V/div) VOUT (1 V/div) VOUT (1 V/div) 0.5V pre-biased SW (5 V/div) SW (5 V/div) PGOOD (5 V/div) PGOOD (5 V/div) Time (1 ms/div) Time (1 ms/div) Figure 23. Normal Startup Figure 24. Pre-Biased Startup 11 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Inductor used: PCMC065T-1R0, 1 H, 5.6 m DE Mode VIN = 5 V IOUT = 5 A EN (5V/div) VOUT (1 V/div) VREG3 (2 V/div) PGOOD (5 V/div) Time (2 ms/div) Figure 25. Turn-Off Enable Figure 26. UVLO Start-Up Waveform DE Mode FCCM VIN = 5 V VIN = 5 V VOUT = 1.5 V VOUT = 1.5 V IOUT = 0 A IOUT = 0 A VOUT Ripple (10 mV/div) VOUT Ripple (10 mV/div) SW (5 V/div) SW (5 V/div) IINDUCTOR (1 A/div) IINDUCTOR (1 A/div) Time (1 s/div) Time (1 s/div) Figure 27. Output Voltage Ripple - FCCM Figure 28. Output Voltage Ripple - DE Mode 12 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Inductor used: PCMC065T-1R0, 1 H, 5.6 m DE Mode FCCM VIN = 5 V VIN = 5 V VOUT = 1.5 V VOUT = 1.5 V IOUT = 0 A to 2 A IOUT = 0 A to 2 A VOUT (50 mV/div) VOUT (50 mV/div) IOUT (1 A/div) IOUT (1 A/div) Time (100 s/div) Time (100 s/div) Figure 29. Load Transient - FCCM Figure 30. Load Transient - DE Mode DE Mode VIN = 5 V HEF Mode VIN = 5 V VOUT = 1.5 V VOUT = 1.5 V IOUT = 0 A to 1 A IOUT = 0 A to 1 A VOUT (50 mV/div) VOUT (50 mV/div) IOUT (1 A/div) IOUT (1 A/div) Time (400 s/div) Time (400 s/div) Figure 31. DE Mode DCM and CCM Transition Figure 32. HEF Mode DCM and CCM Transition 13 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Inductor used: PCMC065T-1R0, 1 H, 5.6 m FCCM Mode VOUT (1 V/div) FCCM Mode VOUT (1 V/div) VIN = 5 V VIN = 5 V VOUT = 1.5 V VOUT = 1.5 V I OUT = 5 A to short I OUT = 5 A to 8 A SW (5 V/div) SW (5 V/div) I INDUCTOR (5 A/div) I INDUCTOR (5 A/div) PGOOD (5 V/div) PGOOD (5 V/div) Time (10 ms/div) Time (10 ms/div) Figure 33. Overcurrent Protection Figure 34. Short Circuit Protection 90 Temperature (C) 80 VIN = 3.3 V @ VOUT = 0.6 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VIN = 5 V @ VOUT = 0.6 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 70 60 50 40 30 No Air Flow 20 0 Figure 35. Over Temperature Protection 14 1 2 3 Output Current (A) 4 5 G023 Figure 36. Safe Operating Area Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com APPLICATION INFORMATION APPLICATION CIRCUIT DIAGRAM L1 1 mH Output All MLCCs VIN 5V C5 22 mF C6 0.1 mF 13 14 5 6 7 VIN VIN SW SW SW 12 VREG3 C OUT 22 mF C4 0.1 mF VBST 4 PGD 3 C OUT 22 mF VOUT = 1.2 V C OUT 22 mF VIN C6 0.1 mF 11 AGND EN TPS53316 1 EN 2 RF/OC 8 PS PGD R3 4.02 kW C1 2.2 nF FB 10 R8 NI C2 2.2 nF PowerPad COMP 9 PGND PGND R5 57.6 kW 15 R1 4.02 kW R4 4.02 kW C3 100 pF 16 R2 4.02 kW UDG-11235 Figure 37. Typical 3.3V input Application Circuit Diagram OVERVIEW The TPS53316 is a high-efficiency switching regulator with two integrated N-channel MOSFETs and is capable of delivering up to 5 A of load current. The TPS53316 provides output voltage from 0.6 V up to 0.8 x VIN from 2.9V to 6.0V wide input voltage range. This device employs 3 operation modes to fit into various application needs. The skip mode operation provides reduced power loss and increases the efficiency at light load. The unique, patented PWM modulator enables smooth light load to heavy load transition while maintaining fast load transient. OVERCURRENT AND FREQUENCY SETTING The Overcurrent and frequency setting are determined by RF/OC pin connection as shown in Table 1. At start up, the RF/OC pin sources 10 A current and then sense the voltage on this pin to determine the switching frequency and OCP threshold. Table 1. Overcurrent and Frequency Setting RF/OC PIN CONNECTION FREQUENCY (kHz) OVERCURRENT THRESHOLD (A) GND 1100 6.5 24.3 k to GND 750 4.5 57.6 k to GND 750 6.5 105 k to GND 2000 4.5 174 k to GND 2000 6.5 Floating or pulled to VREG3 1100 4.5 15 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com OPERATION MODE The TPS53316 has 3 operation modes determined by PS connection as listed in Table 2. Each mode has two soft-start and power good delay options (1x and 4x). At start-up, the PS pin sources 10 A of current and then sense the voltage on this pin to determine the operation mode and soft-start time. Table 2. Operation Mode Selection PS PIN CONNECTION OPERATION MODE AUTO-SKIP AT LIGHT LOAD SOFT-START TIME GND FCCM No 4x 24.3 k to GND HEF Mode Yes 4x 57.6 k to GND HEF Mode Yes 1x 105 k to GND DE Mode Yes 1x 174 k to GND DE Mode Yes 4x Floating or pulled to VREG3 FCCM No 1x In forced continuous conduction mode (FCCM), the high-side FET is ON during the on-time and low-side FET is ON during the off-time. The switching is synchronized to the internal clock thus the switching frequency is fixed. In diode emulation mode (DE), the high-side FET is ON during the on-time and low-side FET is ON during the off-time until the inductor current reaches zero. An internal zero-crossing comparator detects the zero crossing of inductor current from positive to negative. When the inductor current reaches zero, the comparator sends a signal to the logic control and turns off the low-side FET. When the load is increased, the inductor current is always positive and the zero-crossing comparator does not send a zero-crossing signal. The converter enters into continuous conduction mode (CCM) when no zero-crossing is detected for two consecutive PWM pulses. The switching is synchronized to the internal clock and the switching frequency is fixed. In high-efficiency mode (HEF), the converter does not synchronize to internal clock during CCM. Instead, the PWM modulator determines the switching frequency. The operation in discontinuous conduction mode (DCM) is the same as DE mode. In both DE and HEF modes, the device operates under CCM with fixed SW frequency if the load current is higher than half of the inductor ripple current. When the load current is decreased and seven consecutive zero-crossing events are detected, the device enters DCM and light load control is enabled. The on-pulse in DCM is designed to be 25% higher than CCM to provide hysteresis to avoid chattering between CCM and DCM. The PS pins also set the soft-start time and power good start-up delay of the device. The nominal sort-start time is 400 s from the time VOUT= 0 V to when VOUT = 100%, and the nominal power good delay is 300 s from the time VOUT = 100% to when power good is asserted. When the PS pin is connected to GND directly or with a resistor with a value of 24.3 k or 174 k. , the soft-start time and power good delay is 4 times the nominal (1.6 ms for soft-start time and 1.2 ms for power good delay). 16 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com LIGHT LOAD OPERATION In skip modes (DE and HEF), when the load current is less than half of inductor ripple current, the inductor current reaches zero by the end of OFF-Time. The light load control scheme then turns off the low-side MOSFET when inductor current reaches zero. Since there is no negative inductor current, the energy delivered to the load per switching cycle is increased compared to the normal PWM mode operation. The controller then reduces the switching frequency to maintain the output voltage regulation. The switching loss is reduced and thus efficiency is improved. In both DE and HEF mode, when the load current decreases, the switching frequency also decreases continuously in discontinuous conduction mode (DCM). When the load current is 0 A, the minimum switching frequency is reached. It is also required that the difference between VVBST and VSW to be higher than 2.4 V to ensure the supply for high-side gate driver. IL(ripple) /2 Output Current Internal Clock PWM, FCCM Mode PWM, DE Mode PWM, HEF Mode With Zero-Crossing No Zero-Crossing No Zero-Crossing for two PWM cycles, and the device enters CCM In DE Mode, the PWM sync to internal clock after entering CCM UDG-11269 Figure 38. TPS53316 Operation Modes in Light and Heavy Load Conditions FORCED CONTINUOUS CONDUCTION MODE When the PS pin is grounded or greater than 2.2 V, the TPS53316 is operating in continuous conduction mode in both light and heavy load condition. In this mode, the switching frequency remains constant over the entire load range which is suitable for applications need tight control of switching frequency at a cost of lower efficiency at light load. SOFT-START OPERATION The soft-start operation reduces the inrush current during the start-up time. A slow rising reference is generated by the soft-start circuitry and send to the input of the error amplifier. When the soft-start ramp voltage is less than 600 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 600 mV, the error amplifier switch to a fixed 600 mV reference. The typical soft-start time is 400 s for 1 x soft-start time setting and 1.6 ms for 4x the soft-start time setting. POWER GOOD The TPS53316 monitors the voltage on the FB pin. If the FB voltage is within 117% and 83% of the reference voltage, the power good signal remains high. If FB voltage is out of this window, power good pin is pulled low by the internal open drain output. During start-up operation , the input voltage must be higher than 1 V in order to have valid power good logic, and the power good signal has 300 s(1.2 ms with 4x setting) delay after FB falling into the power good window. There is also 10-s delay during shut down after FB falling out of the power good window. 17 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com UVLO FUNCTION The TPS53316 provides UVLO protection for input voltage. If the input voltage is higher than UVLO threshold voltage, the device starts up. When the voltage becomes lower than the threshold voltage minus the hysteresis, the device shuts off. The typical UVLO rising threshold is 2.8 V and the hysteresis is 130 mV. A similar UVLO function is provided to the VREG3 pin. The typical UVLO rising threshold is 2.8V and the hysteresis is 75 mV for VREG3. OVERCURRENT PROTECTION The TPS53316 continuously monitors the current flowing through high-side and low-side MOSFETs. If the current through the high-side FET exceeds 6.8 A (or 4.5 A with 4.5 A setting), the high-side FET turns off and the low-side FET turns on. An OC counter starts to increment to count the occurrence of the overcurrent events. The converter shuts down immediately when the OC counter reaches 4. The OC counter resets if the detected current is less 6.8 A after an OC event. Another set of overcurrent circuitry monitors the current through low-side FET. If the current through the low-side FET exceeds 7.5 A (or 5.1 A with 4.5 A setting), the overcurrent protection is engaged and turns off both high-side and low-side FETs immediately. The device is fully protected against overcurrent during both on-time and off-time. After an OCP event, the device will attempt to restart after a hiccup delay (14.5 ms typcial). If the OC condition clears before restart, the device starts up normally. Otherwise the hiccup process repeats. OVERVOLTAGE PROTECTION The TPS53316 monitors the voltage divided feedback voltage to detect the overvoltage and undervoltage conditions. When the feedback voltage is greater than 117% of the reference, the high-side MOSFET turns off and the low-side MOSFET turns on. Then the output voltage drops and reaches the undervoltage threshold. At that point the low-side MOSFET turns off and the device enters high-impedance state. UNDERVOLTAGE PROTECTION When the feedback voltage is lower than 83% of the reference voltage, the undervoltage protection counter starts. If the feedback voltage remains lower than the undervoltage threshold voltage after 10 s, the device turns off both high-side and low-side MOSFETs and enters high-impedance state. After a hiccup delay (14.5 ms typical), the device attempts to restart. If the UV condition clears before restart, the device starts up normally. Otherwise the hiccup process repeats. OVERTEMPERATURE PROTECTION The TPS53316 continuously monitors the die temperature. If the die temperature exceeds the threshold value (140C typical), the device shuts off. When the device is cooled to 40C below the overtemperature threshold, it restarts and returns to normal operation. OUTPUT DISCHARGE When the EN pin is low, the TPS53316 discharges the output capacitors through an internal MOSFET switch between SW and GND while the high-side and low-side MOSFETs remain OFF. The typical discharge switch on resistance is 60 . This function is disabled when the input voltage is less than 1 V. 18 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com EXTERNAL COMPONENTS SELECTION Step One: Determine the Value of R1 and R2 The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is connected between VFB pin and the output, and R2 is connected between the VFB pin and GND. Recommended value for R1 is between 1 k and 10 k. Determine R2 using Equation 1. 0.6 R2 = R1 VOUT - 0.6 (1) Steo Two: Choose the Inductor The inductance value should be determined to give the ripple current of approximately 20% to 40% of maximum output current. The inductor ripple current is determined by Equation 2: (V - VOUT ) VOUT 1 IL(ripple) = IN L fSW VIN (2) The inductor also must have a low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. Step Three: Choose the Output Capacitor(s) The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM, the output ripple has three components. VRIPPLE(C) represents the ripple due to the output capacitance and is shown in Equation 4. VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) (3) VRIPPLE(C) = IL(ripple) 8 COUT fSW (4) VRIPPLE(ESR) = IL(ripple) ESR VRIPPLE(ESL) (5) V ESL = IN L (6) When ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in parallel. When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also varies with load current and can be expressed as shown in Equation 7. 2 VRIPPLE(DCM) = (a IL(ripple) - IOUT ) 2 fSW COUT IL(ripple) where a= * is the DCM on-time coefficient (typical value is 1.25) and can be expressed as tON(DCM) tON(CCM) (7) Figure 39 illustrates the DCM output voltage ripple. 19 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com IL VOUT a x IL(ripple) VRIPPLE IOUT T1 axT UDG-11236 Figure 39. Discontinuous Mode Output Voltage Ripple Step Four: Choose the Intput Capacitors The selection of input capacitor should be determined by the ripple current requirement. The ripple current generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS ripple current from the converter can be expressed as shown in Equation 8. IIN(ripple) = IOUT D (1 - D ) where * V D = OUT VIN D is the duty cycle and can be expressed as (8) To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be placed close to the device. The ceramic capacitor is recommended due to the low ESR and low ESL. The input voltage ripple can be calculated as below when the total input capacitance is determined: I D VIN(ripple) = OUT fSW CIN (9) Compensation Design The TPS53316 employs voltage mode control. To effectively compensation the power stage and ensures fast transient response, Type III compensation is typically used. The control to output transfer function can be described in Equation 10. 1 + s COUT ESR GCO = 4 ae o L + COUT (ESR + DCR) / + s2 L COUT 1+ s c + DCR R LOAD e o (10) The output LC filter introduces a double pole which can be calculated in Equation 11. 1 fDP = 2 p L COUT (11) The ESR zero of can be calculated in Equation 12. 1 fESR = 2 p ESR COUT (12) 20 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com Figure 40 shows the configuration of Type III compensation and typical pole and zero locations. The following equations describe the compensator transfer function and poles and zeros of the Type III network. (1 + s C1 (R1 + R3))(1 + s R4 C2 ) GEA = C2 C3 o (s R1 (C2 + C3)) (1 + s C1 R3 ) aec 1 + s R4 C2 + C3 /o e (13) 1 fZ1 = 2 p R4 C2 (14) 1 1 fZ2 = @ 2 p (R1 + R3 ) C1 2 p R1 C1 (15) C3 C1 C2 R4 R3 R2 VREF + COMP Gain (dB) R1 UGD-11238 fZ1 fZ2 fP2 fP3 Frequency UDG-11237 Figure 40. Type III Compensation Network Schematic Figure 41. Type III Compensation Network Waveform fP1 = 0 (16) 1 fP2 = 2 p R3 C1 1 1 @ fP3 = C2 C3 p C3 2 R4 ae o 2 p R4 c / e C2 + C3 o (17) (18) The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a compromise between high phase margin and fast response. A phase margin higher than 45 is required for stable operation. For DCM operation, a C3 capacitor value between 56 pF and 150 pF is recommended for output capacitance between 20 F to 200 F. 21 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 TPS53316 SLUSAP5 - DECEMBER 2011 www.ti.com LAYOUT CONSIDERATIONS Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout: * Separate the power ground and analog ground. Connect analog ground to GND plane with single via or a 0 resistor at a quiet place. * Use 4 vias to connect the thermal pad to power ground. * Place VIN and VREG3 decoupling capacitors as close to the device as possible. * Use wide traces for VIN, VOUT, PGND and SW. These nodes carry high-current and also serve as heat sinks. * Place feedback and compensation components as close to the device as possible. * Keep analog signals (FB, COMP) away from noisy signals (SW, VBST). * Refer to TPS53316 evaluation kit for a layout example. Connect to GND plane GND Shape COMP FB AGND VREG3 VIN Shape Keep SW shape away from COMP/FB traces VIN PS VIN SW PGND SW PGND SW VOUT Shape VBST PGD RF/OC EN GND Shape SW Shape Trace on inner or bottom layer UDG-11270 Figure 42. Layout Guidelines 22 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS53316 PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS53316RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS53316RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53316RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS53316RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53316RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPS53316RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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