TPS53316
VIN SW VIN
Output All MLCCs
UDG-11233
PGD
CBST
PGD
FB
COMP
VREG3
AGND
RF/OC
EN
PS
VBST
EN
PowerPad
2.9 V to 6 V
TPS53316
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SLUSAP5 –DECEMBER 2011
High-Efficiency, 5-A Step-Down Regulator with Integrated Switcher
Check for Samples: TPS53316
1FEATURES LOW VOLTAGE APPLICATIONS
2•96% Maximum Efficiency •Low-Voltage Applications for 5-V Step-Down
Rail
•Continuous 5-A Output Current Capability
•Low-Voltage Applications for 3.3-V Step-Down
•Support all MLCC Output Capacitor Rail
•SmoothPWM™Auto-Skip Eco-mode™for
Light-Load Efficiency DESCRIPTION
•Voltage Mode Control TPS53316 provides a fully integrated 3.3-V or 5-V
•Single Rail Input input, synchronous buck converter with 16 total
components, in 200 mm2of PCB area. Due to low
•Selectable Frequency RDS(on) and TI proprietary SmoothPWM™skip mode
•Selectable OCP Threshold of operation, it enables 96% peak efficiency and over
•Selectable Soft-Start Time 90% efficiency at load as light as 100 mA. It requires
•2.9 V to 6.0 V Input Voltage Range only two 22-µF ceramic output capacitors for a
power-dense, 5-A solution.
•Adjustable Output Voltage Ranging from 0.6 V
up to 0.8 ×VIN TPS53316 features 750-kHz, 1.1-MHz and 2-MHz
switching frequency selections, pre-bias startup,
•Soft-Stop Output Discharge During Disable selectable internal softstart, output soft discharge,
•Overcurrent, Overvoltage and Internal VBST switch, power good, EN/Input UVLO,
Over-Temperature Protection overcurrent, overvoltage, undervoltage and over
•Open-Drain Power Good Indication temperature protections and all ceramic output
capacitor support. It supports input voltages from 2.9
•Internal Bootstrap Switch V to 6.0 V and no extra bias voltage is needed. The
•Supports Pre-Bias Start-Up Functionality output voltage is adjustable from 0.6 V up to 0.8 ×
•Small 3 ×3, 16-Pin, QFN Package VIN.
•Low RDS(on), 22-mΩwith 3.3-V input and 18-mΩTPS53316 is available in the 3 mm ×3 mm ,16-pin,
with 5-V Input QFN package (Green RoHs compliant and Pb free)
and is specified from –40°C to 85°C.
TYPICAL APPLICATION CIRCUIT
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Eco-mode, SmoothPWM are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)(2)
ORDERABLE OUTPUT
TAPACKAGE PINS MINIMUM QUANTITY ECO PLAN
DEVICE NUMBER SUPPLY
TPS53316RGTR 16 Tape and reel 3000
Plastic QFN Green (RoHS and no
–40°C to 85°C
(RGT) Pb/Br)
TPS53316RGTT 16 Mini reel 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free air-temperature range (unless otherwise noted) VALUE UNIT
VIN –0.3 to 7
VBST –0.3 to17
Input voltage range VBST(with respect to LL) –0.3 to 7 V
EN –0.3 to 7
FB, PS. RF/OC –0.3 to 3.7
DC –1 to 7
SW Pulse <20ns, E=5μJ≥ –5 or <10
Output voltage range PGD –0.3 to 7 V
COMP, VREG3 –0.3 to 3.7
PGND –0.3 to 0.3
Operating free-air temperature, TA–40 to 85 °C
Storage temperature range, Tstg –55 to 150 °C
Junction temperature range, TJ–40 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
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SLUSAP5 –DECEMBER 2011
RECOMMENDED OPERATING CONDITIONS VALUE UNIT
MIN MAX
VIN (main supply) 2.9 6
VBST –0.1 13.5
Input voltage range VBST(with respect to SW) –0.1 6 V
EN, –0.1 6
FB, PS, RF/OC –0.1 3.5
SW –1 6.5
PGD –0.1 6
Output voltage range V
COMP, VREG3 –0.1 3.5
PGND –0.1 0.1
Junction temperature range, TJ–40 125 °C
THERMAL INFORMATION TPS53316
THERMAL METRIC(1) UNITS
RGT (16) PINS
θJA Junction-to-ambient thermal resistance 45.9
θJCtop Junction-to-case (top) thermal resistance 54.3
θJB Junction-to-board thermal resistance 18.3 °C/W
ψJT Junction-to-top characterization parameter 1.1
ψJB Junction-to-board characterization parameter 18.3
θJCbot Junction-to-case (bottom) thermal resistance 5.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright ©2011, Texas Instruments Incorporated 3
Product Folder Link(s) :TPS53316
TPS53316
SLUSAP5 –DECEMBER 2011
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 3.3V, PGND = GND (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY: VOLTAGE, CURRENTS, AND UVLO
VVIN VIN supply voltage Nominal input voltage range 2.9 6.0 V
IVIN(sdn) VIN shutdown current EN = LO 15 µA
IVIN VIN supply current EN = HI, VFB = 0.63 V, No load 2.0 3.5 mA
VUVLO VIN UVLO threshold Ramp up; EN =HI 2.8 V
VUVLO(hys) VIN UVLO hysteresis VIN UVLO hysteresis 120 mV
VREG3 LDO output VVIN = 5 V, 0 ≤IDD ≤5 mA 3.135 3.3 3.465 V
VOLTAGE FEEDBACK LOOP: VREF AND ERROR AMPLIFIER
VVREF VREF Internal precision reference voltage 0.6 V
0°C≤TA≤85°C–1% 1%
TOLVREF VREF tolerance –40°C≤TA≤85°C–1.25% 1.25%
UGBW(1) Unity gain bandwidth 14 MHz
AOL(1) Open loop gain 80 dB
IFBINT FB input leakage current Sourced from FB pin 30 nA
Outaput sinking and sourcing
IEA(max)(1) CCOMP = 20 pF 5 mA
current
SR(1) Slew rate 5 V/µs
OCP: OVERCURRENT AND ZERO CROSSING
4.5-A setting, when IOUT exceeds this threshold
for 4 consecutive cycles,
IOCPL3A(2) Overcurrent limit on high-side FET 4.05 4.5 4.95 A
VVIN = 3.3V, VOUT = 1.5 V with 1-µH inductor,
fSW = 1.1 MHz, TA= 25°C
4.5-A setting, immediate shut down when
sensed current reach this value
One-time overcurrent latch off on
IOCPH3A(2) 4.49 5.1 5.61 A
the low-side FET VVIN = 3.3 V, VOUT = 0.6 V with 1-µH inductor,
fSW = 1.1 MHz, TA= 25°C
6.5-A setting, when IOUT exceeds this threshold
for 4 consecutive cycles,
IOCPL5A(2) Overcurrent limit on high-side FET 6.1 6.8 7.5 A
VVIN = 3.3 V, VOUT = 1.5 V with 1-µH inductor,
fSW = 1.1 MHz, TA= 25°C
6.5-A setting, immediate shut down when
sensed current reach this value
One time overcurrent latch off on
IOCPH5A(2) 6.75 7.50 8.30 A
the low-side FET VVIN = 3.3 V, VOUT = 0.6 V with 1-µH inductor,
fSW = 1.1 MHz, TA= 25°C
thiccup Hiccup time interval fSW = 1.1 MHz 14.5 ms
Zero crossing comparator internal
VZXOFF(1) PGND –SW, SKIP mode –4.5 –3.0 –1.5 mV
offset
PROTECTION: OVP, UVP, PGD, AND INTERNAL THERMAL SHUTDOWN
Overvoltage protection threshold
VOVP Measured at the FB w/r/t VREF 114% 117% 120%
voltage
Undervoltage protection Threshold
VUVP Measured at the FB w/r/t VREF 80% 83% 86%
voltage
VPGDL PGD low threshold Measured at the FB w/r/t VREF 80% 83% 86%
VPGDU PGD upper threshold Measured at the FB w/r/t .VREF 114% 117% 120%
Minimum input voltage for valid Measured at VIN with 1-mA sink current on PGD
VINMINPG 1 V
PGD at start-up pin at start up
THSD(1) Thermal shutdown 130 140 150 °C
Controller start again after temperature has
THSDHYS(1) Thermal shutdown hysteresis 40 °C
dropped
(1) Ensured by design. Not production tested.
(2) See Figure 5 and Figure 6 on OCP level for other operating conditions.
4Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
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SLUSAP5 –DECEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 3.3V, PGND = GND (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
LOGIC PINS: I/O VOLTAGE AND CURRENT
VPGPD PGD pull down voltage Pull down voltage with 4mA sink current 0.1 0.3 V
IPGLK PGD leakage current Hi-Z leakage current, Apply 3.3V in off state –2 0 2 µA
RENPU Enable pull-up resistor 2.25 MΩ
VVIN = 3.3 V 0.82 0.97 1.10 V
VENH EN logic high VVIN = 5 V 0.95 1.10 1.25 V
VVIN = 3.3 V 0.16 0.24 V
VENHYS EN hysteresis VVIN = 5 V 0.2 0.275 V
Level 1 to Level 2(3) 0.12
Level 2 to Level 3 0.4
PSTHS PS mode threshold voltage Level 3 to Level 4 0.8 V
Level 4 to Level 5 1.4
Level 5 to Level 6 2.2
IPS PS source 10-µA pull-up current when enabled 8 10 12 µA
Level 1 to Level 2(4) 0.12
Level 2 to Level 3 0.4
RF/OCTHS RF/OC pin threshold voltage Level 3 to Level 4 0.8 V
Level 4 to Level 5 1.4
Level 5 to Level 6 2.2
IRF/OC RF/OC source current 10-µA pull-up current when enabled 8 10 12 µA
BOOT STRAP: VOLTAGE AND LEAKAGE CURRENT
IVBSTLK VBST leakage current VVIN = 3.3 V, VVBST = 6.6 V, TA= 25˚C 1 µA
TIMERS: SS, FREQUENCY, RAMP, ON-TIME AND I/O TIMING
tSS_1 Delay after EN Asserting EN = ‘HI’0.2 ms
0 V ≤VSS ≤0.6 V 0.4
tSS_2 Soft start ramp_up time ms
0 V ≤VSS ≤0.6 V, 4 x SS time(option2) 1.6
VSS = 0.6 V to PGD (SSOK) going high 0.3
tPGDENDLY PGD startup delay time ms
VSS = 0.6 V to PGD (SSOK), option 2 1.2
tOVPDLY OVP delay time Time from FB out of +20% of VREF to OVP fault 1.0 1.7 2.5 µs
tUVPDLY UVP delay time Time from FB out of –20% of VREF to UVP fault 10 µs
All modes, fSET = 0.75 MHz 0.653 0.725 0.798
All modes, fSET = 1.1 MHz 0.99 1.10 1.21 MHz
fSW Switching frequency FCCM and DE mode, fSET = 2 MHz 1.71 1.90 2.09
HEF mode, fSET = 2 MHz 1.566 1.800 2.034
Ramp amplitude(5) 2.9 V ≤VVIN ≤6.0 V VVIN/4 V
Minimum OFF time, FCCM and DE All frequencies 90 130 ns
tMIN(off) Minimum OFF time, HEF fSW = 1.1 MHz 160 240 ns
Maximum duty cycle, FCCM and
DMAX fSW = 1.1 MHz 84% 89%
DE
DMAX Maximum duty cycle, HEF All frequencies 75% 81%
RSFTSTP Soft-discharge transistor resistance EN = LO, VVIN = 3.3 V, VOUT = 0.5 V 60 Ω
(3) See PS pin description for levels.
(4) See RF/OC pin description for levels.
(5) Ensured by design. Not production tested.
Copyright ©2011, Texas Instruments Incorporated 5
Product Folder Link(s) :TPS53316
1
2
3
4
EN
SW
RF/OC
SW
PGD
SW
VBST
PS
12
11
10
9
16
VREG3
PGND
AGND
PGND
FB
VIN
COMP
VIN
15 14 13
5678
TPS53316
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
DEVICE INFORMATION
QFN PACKAGE
16 PINS
(TOP VIEW)
PIN DESCRIPTIONS
PIN I/O(1) DESCRIPTION
NAME NO.
AGND 11 G Device analog ground terminal
COMP 9 O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
Enable pin. Internally pulled-up to the VIN pin through a 2-MΩresistor. The EN voltage needs to be less
EN 1 I than (VIN+ 0.5 V)
FB 10 I Voltage feedback pin. Use for OVP, UVP and PGD determination
PGD 3 O Power good output flag. Open drain output. Pull up to an external rail via a resistor
15
PGND P Device power ground terminal
16 Mode configuration pin (with10 µA current):
Connecting to ground: Forced CCM with 4 x soft-start time
Pulled high or floating (internal pulled high): Forced CCM master
PS 8 I Connect with 24.3 kΩto GND: HEF mode with 4 x soft-start time,
Connect with 57.6 kΩto GND: HEFF mode
Connect with 105 kΩto GND : DE mode
Connect with 174 kΩto GND: DE Mode with 4 x soft-start time
Switching frequency and OC level configuration pin:
Connecting to ground: 1.1 MHz, 6.5 A OCP
Pulled high or floating (internal pulled high): 1.1 MHz, 4.5 A OCP
RF/OC 2 I Connect with 24.3 kΩto GND: 750 kHz, 4.5 A OCP
Connect with 57.6 kΩto GND: 750 kHz, 6.5 A OCP
Connect with 105 kΩto GND : 2 MHz, 4.5 A OCP
Connect with 174 kΩto GND: 2MHz, 6. 5A OCP
5
SW 6 B Output inductor connection to integrated power devices
7
VBST 4 P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal
3.3V LDO output, serves as supply voltage for internal analog circuitry. The EN pin controls the turn-on
VREG3 12 O function of the LDO.
13
VIN P Gate driver supply and power conversion input voltage. The input range is from 2.9 V to 6 V.
14
PowerPad – – Thermal pad of the device. use 4 or 5 vias to connect to GND plane for heat dissipation.
(1) I –Input; B –Bidirectional; O –Output; G –Ground; P –Supply (or Ground)
6Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
FB
COMP
VBST
SW
VREG3
TPS53316
EN PS RF/OC AGND
VIN
PGND
UDG-11234
UV/OV
Threshold
Generation
0.6 V +
+
+
+
0.6 V
SS
Enable
Control
Mode
Scanner
E/A
UV
OV Control
Logic
PWM
LL One-Shot
Overtemp
VOUT Discharge
0.6 V–20%
+
PWM
Ramp
VIN UVLO
XCON
HDRV
LDRV
OCP Logic
UVLO
0.6 V+20%
UV
OV
LDO
PGD
VIN
Frequency
and OCP
Setting
TPS53316
www.ti.com
SLUSAP5 –DECEMBER 2011
FUNCTIONAL BLOCK DIAGRAM
Copyright ©2011, Texas Instruments Incorporated 7
Product Folder Link(s) :TPS53316
590
592
594
596
598
600
602
604
606
608
610
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Reference Voltage (mV)
G017
0.0
0.5
1.0
1.5
2.0
2.5
3.0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Input Current (mA)
VIN = 3.3 V
VFB = 0.63 V
EN = HI
G018
1.492
1.494
1.496
1.498
1.500
1.502
1.504
1.506
0 1 2 3 4 5
Output Current (A)
Output Voltage (V)
VIN = 3.3 V, FCCM
VIN = 3.3 V, DE Mode
VIN = 5 V, FCCM
VIN = 5 V, DE Mode
fSW = 1.1 MHz
G019
1.494
1.496
1.498
1.500
1.502
1.504
1.506
2.9 3.4 3.9 4.4 4.9 5.4 5.9
Input Voltage (V)
Output Voltage (V)
IOUT = 0 A, FCCM
IOUT = 0 A, DE Mode
IOUT = 1 A, FCCM
IOUT = 1 A, DE Mode
fSW = 1.1 MHz
G020
0
1
2
3
4
5
6
7
8
0.5 1.0 1.5 2.0 2.5
Output Voltage (V)
OCP Threshold (A)
fSW = 750 kHz, 4.5 A OC Setting
fSW = 1.1 MHz, 4.5 A OC Setting
fSW = 2 MHz, 4.5 A OC Setting
fSW = 750 kHz, 6.5 A OC Setting
fSW = 1.1 MHz, 6.5 A OC Setting
fSW = 2 MHz, 6.5 A OC Setting
FCCM Mode
VIN = 3.3 V
1 µH Inductor
G021
0
1
2
3
4
5
6
7
8
9
0.5 1 1.5 2 2.5
Output Voltage (V)
OCP Threshold (A)
fSW = 750 kHz, 4.5 A OC Setting
fSW = 1.1 MHz, 4.5 A OC Setting
fSW = 2 MHz, 4.5 A OC Setting
fSW = 750 kHz, 6.5 A OC Setting
fSW = 1.1 MHz, 6.5 A OC Setting
fSW = 2 MHz, 6.5 A OC Setting
FCCM Mode
VIN = 5 V
1 µH Inductor
G022
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 1. Regerence Voltage vs. Temperature Figure 2. Input Current vs. Temperature
Figure 3. Output Voltage vs. Output Current Figure 4. Output Voltage vs. Input Voltage
Figure 5. OCP Threshold vs. Output Voltage Figure 6. OCP Threshold vs. Output Voltage
8Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
0
500
1000
1500
2000
0 1 2 3 4 5
Output Current (A)
Frequency (kHz)
fSW=750 kHz
fSW=1.1 MHz
fSW=2 MHz
FCCM
VIN=3.3 V
VOUT=1.5 V
G001
0
500
1000
1500
2000
0 1 2 3 4 5
Output Current (A)
Frequency (kHz)
fSW=750 kHz
fSW=1.1 MHz
fSW=2 MHz
DE Mode
VIN=3.3 V
VOUT=1.5 V
G002
0
500
1000
1500
2000
0 1 2 3 4 5
Output Current (A)
Frequency (kHz)
fSW=750 kHz
fSW=1.1 MHz
fSW=2 MHz
HEF Mode
VIN=3.3 V
VOUT=1.5 V
G003
0
500
1000
1500
2000
0 1 2 3 4 5
Output Current (A)
Frequency (kHz)
fSW=750 kHz
fSW=1.1 MHz
fSW=2 MHz
FCCM
VIN=5 V
VOUT=1.5 V
G004
0
500
1000
1500
2000
0 1 2 3 4 5
Output Current (A)
Frequency (kHz)
fSW=750 kHz
fSW=1.1 MHz
fSW=2 MHz
DE Mode
VIN=5 V
VOUT=1.5 V
G005
0
500
1000
1500
2000
0 1 2 3 4 5
Output Current (A)
Frequency (kHz)
fSW=750 kHz
fSW=1.1 MHz
fSW=2 MHz
HEF Mode
VIN=5 V
VOUT=1.5 V
G006
TPS53316
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SLUSAP5 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 7. Frequency vs. Output Current, FCCM Figure 8. Frequency vs. Output Current, DE Mode
Figure 9. Frequency vs. Output Current, HEF Mode Figure 10. Frequency vs. Output Current, FCCM
Figure 11. Frequency vs. Output Current, DE Mode Figure 12. Frequency vs. Output Current, HEF Mode
Copyright ©2011, Texas Instruments Incorporated 9
Product Folder Link(s) :TPS53316
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8 V
VOUT=2.5 V
FCCM
VIN=3.3 V
fSW=750 kHz
G007
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOU=1.0 V
VOU=1.2 V
VOU=1.5 V
VOU=1.8 V
VOU=2.5 V
DE Mode
VIN=3.3 V
fSW=750 kHz
G008
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOU=1.0 V
VOU=1.2 V
VOU=1.5 V
VOU=1.8 V
HEF Mode
VIN=3.3 V
fSW=750 kHz
G009
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8V
VOUT=2.5 V
VOUT=3.3 V
FCCM
VIN=5 V
fSW=750 kHz
G010
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9V
VOUT=1.0V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
VOUT=2.5V
VOUT=3.3V
DE Mode
VIN=5 V
fSW=750 kHz
G011
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8 V
VOUT=2.5 V
VOU=3.3 V
HEF Mode
VIN=5 V
fSW=750 kHz
G012
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 13. Efficiency vs. Output Current, FCCM Figure 14. Efficiency vs. Output Current, DE Mode
Figure 15. Efficiency vs. Output Current, HEF Mode Figure 16. Efficiency vs. Output Current, FCCM
Figure 17. Efficiency vs. Output Current, DE Mode Figure 18. Efficiency vs. Output Current, HEF Mode
10 Copyright ©2011, Texas Instruments Incorporated
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60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8 V
VOUT=2.5 V
FCCM
VIN=3.3 V
fSW=1.1 MHz
G013
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8 V
VOUT=2.5 V
VOUT=3.3 V
FCCM
VIN=5 V
fSW=1.1 MHz
G014
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8 V
VOUT=2.5 V
FCCM
VIN=3.3 V
fSW=2 MHz
G015
60
70
80
90
100
0 1 2 3 4 5
Output Current (A)
Efficiency (%)
VOUT=0.9 V
VOUT=1.0 V
VOUT=1.2 V
VOUT=1.5 V
VOUT=1.8 V
VOUT=2.5 V
VOUT=3.3 V
FCCM
VIN=5 V
fSW=2 MHz
G016
EN (5V/div)
SW (5 V/div)
PGOOD (5 V/div)
0.5V pre-biased
DE Mode
VIN = 5 V
IOUT = 0 A
VOUT (1 V/div)
Time (1 ms/div)
Time (1 ms/div)
DE Mode
VIN = 5 V
IOUT = 0 A
EN (5 V/div)
VOUT (1 V/div)
SW (5 V/div)
PGOOD (5 V/div)
TPS53316
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SLUSAP5 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 19. Efficiency vs. Output Current, FCCM Figure 20. Efficiency vs. Output Current, FCCM
Figure 21. Efficiency vs. Output Current, FCCM Figure 22. Efficiency vs. Output Current, FCCM
Figure 23. Normal Startup Figure 24. Pre-Biased Startup
Copyright ©2011, Texas Instruments Incorporated 11
Product Folder Link(s) :TPS53316
EN (5V/div)
VREG3 (2 V/div)
PGOOD (5 V/div)
DE Mode
VIN = 5 V
IOUT = 5 A
VOUT (1 V/div)
Time (2 ms/div)
Time (1 µs/div)
DE Mode
VIN = 5 V
VOUT = 1.5 V
IOUT = 0 A VOUT Ripple (10 mV/div)
SW (5 V/div)
IINDUCTOR (1 A/div)
FCCM
VIN = 5 V
VOUT = 1.5 V
IOUT = 0 A
VOUT Ripple (10 mV/div)
SW (5 V/div)
IINDUCTOR (1 A/div)
Time (1 µs/div)
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 25. Turn-Off Enable Figure 26. UVLO Start-Up Waveform
Figure 27. Output Voltage Ripple –FCCM Figure 28. Output Voltage Ripple –DE Mode
12 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
FCCM
VIN = 5 V
VOUT = 1.5 V
IOUT = 0 A to 2 A
VOUT (50 mV/div)
IOUT (1 A/div)
Time (100 µs/div)
DE Mode
VIN = 5 V
VOUT = 1.5 V
IOUT = 0 A to 2 A
VOUT (50 mV/div)
IOUT (1 A/div)
Time (100 µs/div)
Time (400 µs/div)
DE Mode
VIN = 5 V
VOUT = 1.5 V
IOUT = 0 A to 1 A
VOUT (50 mV/div)
IOUT (1 A/div)
Time (400 µs/div)
HEF Mode
VIN = 5 V
VOUT = 1.5 V
IOUT = 0 A to 1 A
VOUT (50 mV/div)
IOUT (1 A/div)
TPS53316
www.ti.com
SLUSAP5 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 29. Load Transient –FCCM Figure 30. Load Transient –DE Mode
Figure 31. DE Mode DCM and CCM Transition Figure 32. HEF Mode DCM and CCM Transition
Copyright ©2011, Texas Instruments Incorporated 13
Product Folder Link(s) :TPS53316
SW (5 V/div)
PGOOD (5 V/div)
VOUT (1 V/div)
IINDUCTOR(5 A/div)
FCCM Mode
VIN = 5 V
VOUT = 1.5 V
IOUT = 5 A to short
Time (10 ms/div)
FCCM Mode
VIN = 5 V
VOUT = 1.5 V
IOUT = 5 A to 8 A
SW (5 V/div)
PGOOD (5 V/div)
IINDUCTOR(5 A/div)
VOUT (1 V/div)
Time (10 ms/div)
20
30
40
50
60
70
80
90
0 1 2 3 4 5
Output Current (A)
Temperature (°C)
No Air Flow
VIN = 3.3 V @
VOUT = 0.6 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VIN = 5 V @
VOUT = 0.6 V
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
G023
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
Figure 33. Overcurrent Protection Figure 34. Short Circuit Protection
Figure 35. Over Temperature Protection Figure 36. Safe Operating Area
14 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
TPS53316
L1
1mH
13
VIN
14
VIN
6 75
SW SW SW
VIN
5 V COUT
22 mF
VIN
Output All MLCCs
UDG-11235
4
3
10
9
C2
2.2 nF
R4
4.02 kW
C3
100 pF
PGD
R1
4.02 kW
R2
4.02 kW
C4
0.1 mF
PGD
FB
COMP
12
11
2
VREG3
AGND
RF/OC
1
8
EN
PS
15
PGND
16
PGND
PowerPad
VBST
EN
C1
2.2 nF
R3
4.02 kW
VOUT = 1.2 V
COUT
22 mF
COUT
22 mF
R5
57.6 kW
C5
22 mF
C6
0.1 mF
C6
0.1 mF
R8
NI
TPS53316
www.ti.com
SLUSAP5 –DECEMBER 2011
APPLICATION INFORMATION
APPLICATION CIRCUIT DIAGRAM
Figure 37. Typical 3.3V input Application Circuit Diagram
OVERVIEW
The TPS53316 is a high-efficiency switching regulator with two integrated N-channel MOSFETs and is capable
of delivering up to 5 A of load current. The TPS53316 provides output voltage from 0.6 V up to 0.8 x VIN from
2.9V to 6.0V wide input voltage range.
This device employs 3 operation modes to fit into various application needs. The skip mode operation provides
reduced power loss and increases the efficiency at light load. The unique, patented PWM modulator enables
smooth light load to heavy load transition while maintaining fast load transient.
OVERCURRENT AND FREQUENCY SETTING
The Overcurrent and frequency setting are determined by RF/OC pin connection as shown in Table 1. At start
up, the RF/OC pin sources 10 µA current and then sense the voltage on this pin to determine the switching
frequency and OCP threshold.
Table 1. Overcurrent and Frequency Setting
OVERCURRENT THRESHOLD
RF/OC PIN CONNECTION FREQUENCY (kHz) (A)
GND 1100 6.5
24.3 kΩto GND 750 4.5
57.6 kΩto GND 750 6.5
105 kΩto GND 2000 4.5
174 kΩto GND 2000 6.5
Floating or pulled to VREG3 1100 4.5
Copyright ©2011, Texas Instruments Incorporated 15
Product Folder Link(s) :TPS53316
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
OPERATION MODE
The TPS53316 has 3 operation modes determined by PS connection as listed in Table 2. Each mode has two
soft-start and power good delay options (1×and 4×). At start-up, the PS pin sources 10 µA of current and then
sense the voltage on this pin to determine the operation mode and soft-start time.
Table 2. Operation Mode Selection
PS PIN CONNECTION OPERATION MODE AUTO-SKIP AT LIGHT LOAD SOFT-START TIME
GND FCCM No 4 x
24.3 kΩto GND HEF Mode Yes 4 x
57.6 kΩto GND HEF Mode Yes 1 x
105 kΩto GND DE Mode Yes 1 x
174 kΩto GND DE Mode Yes 4 x
Floating or pulled to VREG3 FCCM No 1 x
In forced continuous conduction mode (FCCM), the high-side FET is ON during the on-time and low-side FET is
ON during the off-time. The switching is synchronized to the internal clock thus the switching frequency is fixed.
In diode emulation mode (DE), the high-side FET is ON during the on-time and low-side FET is ON during the
off-time until the inductor current reaches zero. An internal zero-crossing comparator detects the zero crossing of
inductor current from positive to negative. When the inductor current reaches zero, the comparator sends a
signal to the logic control and turns off the low-side FET.
When the load is increased, the inductor current is always positive and the zero-crossing comparator does not
send a zero-crossing signal. The converter enters into continuous conduction mode (CCM) when no
zero-crossing is detected for two consecutive PWM pulses. The switching is synchronized to the internal clock
and the switching frequency is fixed.
In high-efficiency mode (HEF), the converter does not synchronize to internal clock during CCM. Instead, the
PWM modulator determines the switching frequency. The operation in discontinuous conduction mode (DCM) is
the same as DE mode.
In both DE and HEF modes, the device operates under CCM with fixed SW frequency if the load current is
higher than half of the inductor ripple current. When the load current is decreased and seven consecutive
zero-crossing events are detected, the device enters DCM and light load control is enabled. The on-pulse in
DCM is designed to be 25% higher than CCM to provide hysteresis to avoid chattering between CCM and DCM.
The PS pins also set the soft-start time and power good start-up delay of the device. The nominal sort-start time
is 400 µs from the time VOUT= 0 V to when VOUT = 100%, and the nominal power good delay is 300 µs from the
time VOUT = 100% to when power good is asserted. When the PS pin is connected to GND directly or with a
resistor with a value of 24.3 kΩor 174 kΩ. , the soft-start time and power good delay is 4 times the nominal (1.6
ms for soft-start time and 1.2 ms for power good delay).
16 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
IL(ripple)/2
Output Current
Internal Clock
PWM, FCCM Mode
PWM, DE Mode
PWM, HEF Mode
No Zero-Crossing
With Zero-Crossing
No Zero-Crossing for two
PWM cycles, and the
device enters CCM
In DE Mode, the PWM sync to
internal clock after entering CCM
UDG-11269
TPS53316
www.ti.com
SLUSAP5 –DECEMBER 2011
LIGHT LOAD OPERATION
In skip modes (DE and HEF), when the load current is less than half of inductor ripple current, the inductor
current reaches zero by the end of OFF-Time. The light load control scheme then turns off the low-side MOSFET
when inductor current reaches zero. Since there is no negative inductor current, the energy delivered to the load
per switching cycle is increased compared to the normal PWM mode operation. The controller then reduces the
switching frequency to maintain the output voltage regulation. The switching loss is reduced and thus efficiency is
improved.
In both DE and HEF mode, when the load current decreases, the switching frequency also decreases
continuously in discontinuous conduction mode (DCM). When the load current is 0 A, the minimum switching
frequency is reached. It is also required that the difference between VVBST and VSW to be higher than 2.4 V to
ensure the supply for high-side gate driver.
Figure 38. TPS53316 Operation Modes in Light and Heavy Load Conditions
FORCED CONTINUOUS CONDUCTION MODE
When the PS pin is grounded or greater than 2.2 V, the TPS53316 is operating in continuous conduction mode in
both light and heavy load condition. In this mode, the switching frequency remains constant over the entire load
range which is suitable for applications need tight control of switching frequency at a cost of lower efficiency at
light load.
SOFT-START OPERATION
The soft-start operation reduces the inrush current during the start-up time. A slow rising reference is generated
by the soft-start circuitry and send to the input of the error amplifier. When the soft-start ramp voltage is less than
600 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 600 mV,
the error amplifier switch to a fixed 600 mV reference. The typical soft-start time is 400 μs for 1 ×soft-start time
setting and 1.6 ms for 4×the soft-start time setting.
POWER GOOD
The TPS53316 monitors the voltage on the FB pin. If the FB voltage is within 117% and 83% of the reference
voltage, the power good signal remains high. If FB voltage is out of this window, power good pin is pulled low by
the internal open drain output.
During start-up operation , the input voltage must be higher than 1 V in order to have valid power good logic, and
the power good signal has 300 μs(1.2 ms with 4x setting) delay after FB falling into the power good window.
There is also 10-μs delay during shut down after FB falling out of the power good window.
Copyright ©2011, Texas Instruments Incorporated 17
Product Folder Link(s) :TPS53316
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
UVLO FUNCTION
The TPS53316 provides UVLO protection for input voltage. If the input voltage is higher than UVLO threshold
voltage, the device starts up. When the voltage becomes lower than the threshold voltage minus the hysteresis,
the device shuts off. The typical UVLO rising threshold is 2.8 V and the hysteresis is 130 mV.
A similar UVLO function is provided to the VREG3 pin. The typical UVLO rising threshold is 2.8V and the
hysteresis is 75 mV for VREG3.
OVERCURRENT PROTECTION
The TPS53316 continuously monitors the current flowing through high-side and low-side MOSFETs. If the
current through the high-side FET exceeds 6.8 A (or 4.5 A with 4.5 A setting), the high-side FET turns off and the
low-side FET turns on. An OC counter starts to increment to count the occurrence of the overcurrent events. The
converter shuts down immediately when the OC counter reaches 4. The OC counter resets if the detected
current is less 6.8 A after an OC event.
Another set of overcurrent circuitry monitors the current through low-side FET. If the current through the low-side
FET exceeds 7.5 A (or 5.1 A with 4.5 A setting), the overcurrent protection is engaged and turns off both
high-side and low-side FETs immediately. The device is fully protected against overcurrent during both on-time
and off-time.
After an OCP event, the device will attempt to restart after a hiccup delay (14.5 ms typcial). If the OC condition
clears before restart, the device starts up normally. Otherwise the hiccup process repeats.
OVERVOLTAGE PROTECTION
The TPS53316 monitors the voltage divided feedback voltage to detect the overvoltage and undervoltage
conditions. When the feedback voltage is greater than 117% of the reference, the high-side MOSFET turns off
and the low-side MOSFET turns on. Then the output voltage drops and reaches the undervoltage threshold. At
that point the low-side MOSFET turns off and the device enters high-impedance state.
UNDERVOLTAGE PROTECTION
When the feedback voltage is lower than 83% of the reference voltage, the undervoltage protection counter
starts. If the feedback voltage remains lower than the undervoltage threshold voltage after 10 μs, the device
turns off both high-side and low-side MOSFETs and enters high-impedance state. After a hiccup delay (14.5 ms
typical), the device attempts to restart. If the UV condition clears before restart, the device starts up normally.
Otherwise the hiccup process repeats.
OVERTEMPERATURE PROTECTION
The TPS53316 continuously monitors the die temperature. If the die temperature exceeds the threshold value
(140°C typical), the device shuts off. When the device is cooled to 40°C below the overtemperature threshold, it
restarts and returns to normal operation.
OUTPUT DISCHARGE
When the EN pin is low, the TPS53316 discharges the output capacitors through an internal MOSFET switch
between SW and GND while the high-side and low-side MOSFETs remain OFF. The typical discharge switch on
resistance is 60 Ω. This function is disabled when the input voltage is less than 1 V.
18 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
OUT
0.6
R2 R1
V 0.6
= ´
-
( )
IN OUT OUT
L(ripple)
SW IN
V V V
1
IL f V
- ´
= ´
´
RIPPLE RIPPLE(C) RIPPLE(ESR) RIPPLE(ESL)
V V V V= + +
L(ripple)
RIPPLE(C)
OUT SW
I
V8 C f
=´ ´
RIPPLE(ESR) L(ripple)
V I ESR= ´
IN
RIPPLE(ESL)
V ESL
VL
´
=
( )2
L(ripple) OUT
RIPPLE(DCM)
SW OUT L(ripple)
I I
V2 f C I
a ´ -
=´ ´ ´
ON(DCM)
ON(CCM)
t
t
a =
TPS53316
www.ti.com
SLUSAP5 –DECEMBER 2011
EXTERNAL COMPONENTS SELECTION
Step One: Determine the Value of R1 and R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is
connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended value for R1 is between 1 kΩand 10 kΩ. Determine R2 using Equation 1.
(1)
Steo Two: Choose the Inductor
The inductance value should be determined to give the ripple current of approximately 20% to 40% of maximum
output current. The inductor ripple current is determined by Equation 2:
(2)
The inductor also must have a low DCR to achieve good efficiency, as well as enough room above peak inductor
current before saturation.
Step Three: Choose the Output Capacitor(s)
The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has three components. VRIPPLE(C) represents the ripple due to the output capacitance and is
shown in Equation 4.
(3)
(4)
(5)
(6)
When ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple
output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in
parallel.
When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also
varies with load current and can be expressed as shown in Equation 7.
where
• α is the DCM on-time coefficient (typical value is 1.25) and can be expressed as (7)
Figure 39 illustrates the DCM output voltage ripple.
Copyright ©2011, Texas Instruments Incorporated 19
Product Folder Link(s) :TPS53316
IL
VOUT
ax IL(ripple)
T1
VRIPPLE
ax T
IOUT
UDG-11236
( )
IN(ripple) OUT
I I D 1 D= ´ ´ -
OUT
IN
V
DV
=
OUT
IN(ripple)
SW IN
I D
Vf C
´
=´
OUT
CO
2
OUT OUT
LOAD
1 s C ESR
G 4 L
1 s C (ESR DCR) s L C
DCR R
+ ´ ´
= ´ æ ö
+ ´ + ´ + + ´ ´
ç ÷
+
è ø
DP
OUT
1
f2 L C
=´ p´ ´
ESR
OUT
1
f2 ESR C
=´ p´ ´
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
Figure 39. Discontinuous Mode Output Voltage Ripple
Step Four: Choose the Intput Capacitors
The selection of input capacitor should be determined by the ripple current requirement. The ripple current
generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS
ripple current from the converter can be expressed as shown in Equation 8.
where
•D is the duty cycle and can be expressed as (8)
To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be
placed close to the device. The ceramic capacitor is recommended due to the low ESR and low ESL. The input
voltage ripple can be calculated as below when the total input capacitance is determined:
(9)
Compensation Design
The TPS53316 employs voltage mode control. To effectively compensation the power stage and ensures fast
transient response, Type III compensation is typically used.
The control to output transfer function can be described in Equation 10.
(10)
The output LC filter introduces a double pole which can be calculated in Equation 11.
(11)
The ESR zero of can be calculated in Equation 12.
(12)
20 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
( )( )
( ) ( )
EA
1 s C1 (R1 R3) 1 s R4 C2
GC2 C3
s R1 (C2 C3) 1 s C1 R3 1 s R4 C2 C3
+ ´ ´ + + ´ ´
=´
æ ö
´ ´ + ´ + ´ ´ ´ + ´
ç ÷
+
è ø
Z1
1
f2 R4 C2
=´ p´ ´
( )
Z2
1 1
f2 R1 R3 C1 2 R1 C1
= @
´ p´ + ´ ´ p ´ ´
R3
R1
C1
R2
R4 C2
C3
+COMP
VREF
UGD-11238
UDG-11237
Frequency
fZ1 fZ2 fP2 fP3
Gain (dB)
P1
f 0=
P2
1
f2 R3 C1
=´ p´ ´
P3
1 1
fC2 C3 2 R4 C3
2 R4 C2 C3
= @
´´ p´ ´
æ ö
´ p ´ ´ ç ÷
+
è ø
TPS53316
www.ti.com
SLUSAP5 –DECEMBER 2011
Figure 40 shows the configuration of Type III compensation and typical pole and zero locations. The following
equations describe the compensator transfer function and poles and zeros of the Type III network.
(13)
(14)
(15)
Figure 40. Type III Compensation Network Figure 41. Type III Compensation Network
Schematic Waveform
(16)
(17)
(18)
The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One
pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to
attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a
compromise between high phase margin and fast response. A phase margin higher than 45°is required for
stable operation.
For DCM operation, a C3 capacitor value between 56 pF and 150 pF is recommended for output capacitance
between 20 µF to 200 µF.
Copyright ©2011, Texas Instruments Incorporated 21
Product Folder Link(s) :TPS53316
UDG-11270
VIN
VIN
PGND
PGND
PS
SW
SW
SW
COMP
FB
AGND
VREG3 EN
RF/OC
PGD
VBST
SW Shape
GND Shape
GND Shape
VOUT Shape
VIN Shape
Trace on inner
or bottom layer
Connect to
GND plane
Keep SW shape
away from
COMP/FB traces
TPS53316
SLUSAP5 –DECEMBER 2011
www.ti.com
LAYOUT CONSIDERATIONS
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout:
•Separate the power ground and analog ground. Connect analog ground to GND plane with single via or a 0 Ω
resistor at a quiet place.
•Use 4 vias to connect the thermal pad to power ground.
•Place VIN and VREG3 decoupling capacitors as close to the device as possible.
•Use wide traces for VIN, VOUT, PGND and SW. These nodes carry high-current and also serve as heat
sinks.
•Place feedback and compensation components as close to the device as possible.
•Keep analog signals (FB, COMP) away from noisy signals (SW, VBST).
•Refer to TPS53316 evaluation kit for a layout example.
Figure 42. Layout Guidelines
22 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS53316
PACKAGE OPTION ADDENDUM
www.ti.com 23-Dec-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS53316RGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS53316RGTT ACTIVE QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53316RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS53316RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53316RGTR QFN RGT 16 3000 367.0 367.0 35.0
TPS53316RGTT QFN RGT 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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