enCoRe™ USB Combination Low-Speed
USB and PS/2 Peripheral Controller
CY7C63722
CY7C63723
CY7C63743
Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600
Document #: 38-08022 Rev. *B Revised September 27, 2004
1.0 Features
• enCoRe™ USB - enhanced Component Reduc tion
—Internal oscillator eliminates the need for an external
crystal or resonator
—Interface can auto-configure to operate as PS/2 or
USB without the need for external components to
switch between modes (no General Purpose I/O
[GPIO] pins needed to manage dual mode capability)
—Internal 3.3V regulator for USB pull-up resistor
—Configurable GPIO for real-world interface without
external com ponents
• Flexible, cost-effective solution for applications that
combine PS/2 and low-speed USB, such as mice, game-
pa ds, joysticks, and many others.
• USB Specification Compliance
—Conforms to USB Specification, Version 2.0
—Conforms to USB HID Specification, Version 1.1
—Supports one low-speed USB device address and
three data endpoints
—Integrated USB transceiver
—3.3V regulated output for USB pull-up resistor
• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator or internal clock
mode
—12-MHz internal CPU clock
—Internal memory
—256 bytes of RAM
—8 Kbytes of EPROM
—Interface can auto-configure to operate as PS/2 or
USB
—No external components for switching between PS/2
and USB modes
—No GPIO pins needed to manage dual mode
capability
•I/O ports
—Up to 16 versatile GPIO pins, individually
configurable
—High current drive on any GPIO pin: 50 mA/pin
current sink
—Each GPIO pin supports high-impedance inputs,
internal pull-ups, open drain outputs or traditional
CMOS outputs
—Maskable interrupts on all I/O pins
•SPI serial communication block
—Master or slave operation
—2 Mbit/s transfers
•Four 8-bit Input Capture registers
—Two registers each for two input pins
—Capture timer setting with five prescaler settings
—Separate registers for rising and falling edge capture
—Simplifies interface to RF inputs for wireless
applications
•Internal low-power wake-up timer during suspend
mode
—Periodic wake-up with no external components
•Optional 6-MHz internal oscillator mode
—Allows fast start-up from suspend mode
•Watchdog Reset (WDR)
•Low-voltage Reset at 3.75V
•Internal brown-out reset for suspend mode
•Improved output drivers to reduce EMI
•Operating voltage from 4.0V to 5.5VDC
•Operatin g temperat ure fr om 0°C to 70°C
•CY7C63723 available in 18-pin SOIC, 18-pin PDIP
•CY7C63743 available in 24-pin SOIC, 24-pin PDIP , 24-pin
QSOP
•CY7C63722 available in DIE form
•Industry standard programmer support
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Document #: 38-08022 Rev. *B Page 2 of 49
2.0 Logic Block Diagram
3.0 Functional Overview
3.1 enCoRe USB—The New USB Standard
Cypress has reinvented its leadership position in the
low-speed USB market with a new family of innovative
microcontrollers. Introducing...enCoRe USB—“enhanced
Component Reduction.” Cypress has leveraged its design
expertise in USB solutions to create a new family of low-speed
USB microcontrollers that enables peripheral developers to
design new product s with a minimum nu mb er of components.
At the heart of the enCoRe USB technology is the break-
through design of a crystalless oscillator. By integrating the
oscillator into our chip, an external crystal or resonator is no
longer needed. We have also integrated other external compo-
nent s commonly found in low-speed USB applications such as
pull-up r esist ors, wake-up circuitry, and a 3. 3V regulator. All of
this adds up to a lower system cost.
The CY7C637xx is an 8-bit RISC one-time-programmable
(OTP) micr ocontroll er. The instruc tion se t has bee n optim ized
specif ic all y for USB and PS/2 ope rati ons , alt hou gh the mic ro-
controll ers c an b e us ed fo r a variety o f othe r emb ed ded a ppl i-
cations.
The CY7C63 7xx features up to 16 GPIO pins to sup port USB,
PS/2 and other applicatio ns. The I/O pins are grouped into two
ports (Port 0 to 1) where each pin can be individually
configu red a s input s with internal pull-up s, o pen drai n output s,
or traditional CMOS out puts with programmable drive strength
of up to 50 mA output drive. Additionally, each I/O pin can be
used to genera te a G PIO i nterr upt to the mi croco ntrolle r. Note
the GPIO interrupts all share the same “GPIO” interrupt vector.
The CY7C637xx microcon trollers feature an internal oscillator .
With the pr esence of U SB traf fic, the int ernal os cilla tor can be
set to precisely tune to USB timing requirements (6 MHz
±1 .5%). Optionally, an external 6-MHz ceramic resonator can
be used to provide a higher precision reference for USB
operation. This clock generator reduces the clock-related
noise emissions (EMI). The clock generator provides the 6-
and 12-MH z clocks that remain internal to the micr ocontroller .
The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of
data RAM for stack space, user variables, and USB FIFOs.
These p arts i nclude low-vo ltage re set logic, a W atchd og timer ,
a vectored interrupt controll er, a 12-bit free-run ning tim er, and
capture timers. The low-voltage reset (LVR) logic detects
when power is applied to the device, resets the logic to a
known state, and begins executing instructions at EPROM
address 0x0000. LVR will also reset the part when VCC drops
below the operating voltage range. The Watchdog timer can
be used to ensure the firmware never gets stalled for more
than approx im atel y 8 ms.
The microcontroller supports 10 maskable interrupts in the
vectored interrupt controller . Interrupt sources include the USB
Bus-Reset, the 128-µs and 1.024-ms outputs from the
free-running timer, three USB endpoints, two capture timers,
an inte rnal w ake-u p timer and the GP IO p orts. The ti me rs bits
cause periodic interrupts when enabled. The USB endpoints
interrupt after USB transactions complete on the bus. The
capture timers interrupt whenever a new timer value is saved
due to a selected GPIO edge event. The GPIO ports have a
level of masking to select which GPIO inputs can cause a
GPIO interrupt. For additional flexibility, the input transition
polarity that causes an interrupt is programmable for each
GPIO pin. The interrupt polarity can be either rising or falling
edge.
The free-running 12-bit timer clocked at 1 MHz provides two
interr upt s ou rce s a s no ted above (128 µs an d 1 .024 ms ). The
timer can be used to measure the duration of an event under
firmwa re control by read ing the timer at the start and end of an
Wake-Up 12-bit
Timer
USB &
D+,D–P1.0–P1.7
Interrupt
Controller Port 0
P0.0–P0.7
GPIO
8-bit
RISC
Xtal RAM
256 Byte
EPROM
8K Byte Core
Brown-out
Reset
Xcvr
Watch
Timer
Dog
3.3V
Port 1
GPIO
Capture
Timers
USB
Engine
PS/2
Internal
Oscillator Oscillator
Low
Res et
Voltage Regulator
Timer SPI
XTALOUT XTALIN/P2 .1
VREG/P2.0
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Document #: 38-08022 Rev. *B Page 3 of 49
event, a nd subtra cting the two values . The four capture ti mers
save a programmable 8 bit range of the free-running timer
when a GPIO edge occurs on the two capture pins (P0.0,
P0.1).
The CY7C637xx includes an integrated USB serial interface
engine (SIE) that supports the integrated peripherals. The
hardware supports one USB device address with three
endp oin t s . The SIE al low s the USB hos t to c ommun ic ate with
the function integrated into the microcontroller. A 3.3V
regulated output pin provides a pull-up source for the external
USB resistor on the D– pin .
The USB D+ and D– USB pins can alternately be used as PS/2
SCLK and SDATA signals, so that products can be designed
to respond to either USB or PS/2 modes of operation. PS/2
operation is su ppo rted with i nte rnal pu ll-up resistors on SC LK
and SDATA, the abil ity to di sable the regul ator outp ut pin, an d
an interrupt to signal the start of PS/2 activity. No external
components are necessary for dual USB and PS/2 systems,
and no GPIO pins nee d to b e dedicated to switchi ng b etw ee n
modes. Slow edge rates operate in both modes to reduce EMI.
4.0 Pin Configurati ons
1
2
3
4
5
6
9
11 15
16
17
18
19
20
22
21
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
VSS
VREG/P2.0
P0.6
P1.5
P1.1
P1.3
D+/SCLK
P1.7
D–/SDATA
VCC
14
P0.7
10
VPP
XTALIN/P2.1 XTALOUT
12 13
7
8
P1.4
P1.6
24
23 P0.4
P0.5
24-pin SOIC/PDIP/QSOP
CY7C63743
1
2
3
4
6
7
810
11
12
13
15
16
18
17
P0.0
P0.1
P0.2
P0.3
VSS
VREG/P2.0
P0.4
P0.6
P0.7
D+/SCLK
D–/SDATA
VCC
18-pin SOIC/PDIP
P0.5
9
VPP
XTALIN/P2.1 XTALOUT
CY7C63723
514
P1.0 P1.1
Top View
4
5
6
7
8
9
3 P0.2
1 P0.0
2 P0.1
25 P0.4
24 P0.5
23 P0.6
22
21
20
19
18
11
12
13
14
15
16
17
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VSS
VPP
XTALIN/P2.1
VREG
XTALOUT
VCC
D-/SDATA
D+/SCLK
P0.7
P1.1
P1.3
P1.5
P1.7
CY7C63722-XC
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5.0 Pin Definitions
Name I/O CY7C63723 CY7C63743 CY7C63722 Description18-Pin 24-Pin 25-Pad
D–/SDATA,
D+/SCLK I/O 12
13 15
16 16
17 USB differential data lines (D– and D+), or PS/2 clock
and data signals (SDATA and SCLK)
P0[7:0] I/O 1, 2, 3, 4,
15, 16, 17, 18 1, 2, 3, 4,
21, 22, 23, 24 1, 2, 3, 4,
22, 23, 24, 25 GPIO Port 0 capable of sinking up to 50 mA/pin, or
sinking controlled low or high programmable current.
Can also source 2 mA current, provide a resistive
pull-up, or serve as a high-impedance input. P0.0 and
P0.1 provide inputs to Capture Timers A and B, respec-
tively.
P1[7:0] I/O 5, 14 5, 6, 7, 8,
17, 18, 19, 20 5, 6, 7, 8,
18, 19, 20, 21 IO Port 1 capable of sinking up to 50 mA/pin, or sinking
controlle d low or high prog ramma ble curren t. Can also
source 2 mA current, provide a resistive pull-up, or
serve as a high-impedance input.
XTALIN/P2.1 IN 9 12 13 6-MHz ceramic resonator or external clock input, or
P2.1 input
XT ALOUT OUT 10 13 14 6-MHz ceramic resonator return pin or internal oscillator
output
VPP 7 10 11 Programming voltage supply, ground for normal
operation
VCC 11 14 15 Voltage supply
VREG/P2.0 8 11 12 Voltage supply for 1.3-kΩ USB pull-up resistor (3.3V
nominal). Also serves as P2.0 input.
VSS 6 9 9, 10 Ground
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6.0 Programming Model
Refer to the CYASM Assembler User’s Guide for more deta ils
on firmware operation with the CY7C637xx microcontroll ers.
6.1 Program Counter (PC)
The 14-bit program counter (PC) allows access for up to 8
Kbytes of EPROM using the CY7C637xx architecture. The
program counter is cleared during reset, such that the first
instruction executed after a reset is at address 0x0000. This
instruc tion is typica lly a jump instruc tion to a reset hand ler that
init ial iz es the appli cat ion.
The lower 8 bits of the program counter are incremented as
instruc tions are load ed and exec uted. The upper six bits of the
program counter are incremented by executing an XPAGE
instruction. As a result, the last instruction executed within a
256-byte “page” of sequential code should be an XPAGE
instruction. The assembler directive “XPAGEON” will cause
the assembler to insert XPAGE instructions automatically. As
instructions can be either one or two bytes long, the assembler
may oc casionally ne ed to inser t a NOP followed by an XP AGE
for correct execution.
The program counter of the next instruction to be executed,
carry flag, and zero flag are saved as two bytes on the program
stack during an interrupt acknowledge or a CALL instruction.
The program counter, carry flag, and zero flag are restored
from the program stack only during a RETI instruction.
Please not e the program counte r cannot be accessed directl y
by the firmware. The program stack can be examined by
reading SRAM from location 0x00 and up.
6.2 8-bit Accumulator (A)
The accumulator is the general-purpose, do everything
register in the architecture where results are usually calcu-
lated.
6.3 8-bit Index Register (X)
The index register “X” is available to the firmware as an
auxiliary accumulator . The X register also allows the processor
to perform indexed operations by loading an index value
into X.
6.4 8-bit Program Stack Pointer (PSP)
During a re set, th e progra m sta ck point er (PSP) is set to zero.
This means the program “stack” starts at RAM address 0x00
and “grows” upward from there. Note that the program stack
pointer is directly addressable under firmware control, using
the MOV PSP,A instruction. The PSP supports interrupt
service under hardware control and CALL, RET, and RETI
instructions under firmware control.
During an interrupt acknowledge, interrupts are disabled and
the program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is stored in the
memory addressed by the program stack pointer, then the
PSP is incremented. The second byte is stored in memory
address ed by t he progra m stac k poi nter and the PS P is incr e-
mented again. The net effect is to store the program counter
and flags on the program “stack” and increment the program
stack pointer by two.
The return from interrupt (RETI) instruction decrements the
program stack pointer, then restores the second byte from
memory addressed by the PSP. The program stack pointer is
decreme nted again and the first byte is restored from memory
addressed by the PSP. After the program counter and flags
have been restored from stack, the interrupts are enabled. The
effect is to restore the program counter and flags from the
program stack, decrement the program stack pointer by two,
and reenable interrupts.
The call subroutine (CALL) instruction stores the program
counter and flags on the program stack and increments the
PSP by two.
The return from subroutine (RET) instruction restores the
program counter, but not the flags, from program stack and
decrements the PSP by two.
Note that there are restrictions in using the JMP, CALL, and
INDEX instructions across the 4-KByte boundary of the
program memory. Refer to the CYASM Assembler User’s
Guide for a detailed description.
6.5 8-bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP
instructions that use the data stack for temporary storage. A
PUSH instruction will pre-decrement the DSP, then write data
to the memory location addressed by the DSP. A POP
inst ruction will read dat a from the me mory lo catio n addres sed
by the DSP, then post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A
PUSH instru cti on w he n DSP equ als ze ro will wri te da t a at th e
top of the data RAM (address 0xFF). This would write data to
the m emor y a rea rese rve d fo r a FIFO for US B endp oint 0. In
non-USB applications, this works fine and is not a problem.
For USB applications, the firmware should set the DSP to an
appropriate location to avoid a memory conflict with RAM
dedicated to USB FIFOs. The memory requirements for the
USB endpoints are shown in Section 8.2. For example,
assembly instructions to set the DSP to 20h (giving 32 bytes
for program and data stack combined) are shown below.
MOV A,20h ; Move 20 hex into Accumulator (must be
D8h or less to av oid USB FIF Os)
SW AP A,DSP ; swap ac c umula tor value in to DSP reg ist er
6.6 Address Modes
The CY7C637xx microcontrollers support three addressing
modes for instructi ons that require dat a operands: dat a, direct,
and indexed.
6.6.1 Data
The “Data” address mode refers to a data operand that is
actuall y a cons tant en coded in t he instruc tion. As an exampl e,
consider the instruction that loads A with the constant 0x30:
•MOV A, 30h
This instruction will require two bytes of code where the first
byte ide nti fie s th e “MOV A” inst ruc tion with a d ata operand as
the sec ond b yte. The s econd byte of the instru ction will b e the
constant “0xE8h”. A constant may be referred to by name if a
prior “EQU” statem ent assigns the constant value to the n ame.
For example, the following code is equivalent to the example
shown above.
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Document #: 38-08022 Rev. *B Page 5 of 49
•DSPINIT: EQU 30h
•MOV A,DSPINIT
6.6.2 Direct
“Direct” address mode is used when the data operand is a
variabl e stor ed in SRAM. In that case, the one byte add ress of
the variable is encoded in the instruction. As an example,
consider an instruction that loads A with the contents of
memory address location 0x10h:
•MOV A, [10h]
In normal usage, variable names are assigned to variable
addresses using “EQU” statements to improve the readability
of the assembler source code. As an example, the following
code is equivalent to the example shown above.
•buttons: EQU 10h
•MOV A, [buttons]
6.6.3 Indexed
“Indexed” address mode allows the firmware to manipulate
arrays of data stored in SRAM. The address of the data
operand is the sum of a constant encoded in the instruction
and the contents of the “X” register. In normal usage, the
const ant will be the “base” address of an array of data and the
X registe r will c ontain an index that indi cates whi ch element of
the array is actually addressed.
•array: EQU 10h
•MOV X,3
•MOV A, [x+array]
This would have the effect of loading A with the fourth element
of the SRAM “array” that begin s at address 0x10h. The four th
element would be at address 0x13h.
7.0 Instruction Set Summary
Refer to the CYASM Assembler User’s Guide for detailed
information on these instructions. Note that conditional jump
instructions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is
taken, four cycles if no jump.
MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles
HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+exp r],A ind e x 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
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Document #: 38-08022 Rev. *B Page 6 of 49
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50 - 5F 10
JMP addr 80-8F 5 JC addr C0-CF 5 (or 4)
CALL addr 90-9F 10 JNC addr D0-DF 5 (or 4)
JZ addr A0-AF 5 (or 4) JACC addr E0-EF 7
JNZ addr B0-BF 5 (or 4) INDEX addr F0-FF 14
MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles
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8.0 Memory Organization
8.1 Program Memory Organization[1]
After reset Address
14 -bit PC 0x0000 Program execution begins he re after a reset
0x0002 USB Bus Reset interrupt vector
0x0004 128-µs timer interrupt vector
0x0006 1.024-ms timer interrupt vector
0x0008 USB endpoint 0 interrupt vector
0x000A USB endpoint 1 interrupt vector
0x000C USB endpoint 2 interrupt vector
0x000E SPI inte rrup t vector
0x0010 Capture timer A interrupt Vector
0x0012 Capture timer B interrupt vector
0x0014 GPIO interrupt vector
0x0016 Wake-up interrupt vector
0x0018 Program Memory begins here
0x1FDF 8 KB PROM ends here (8K - 32 bytes). See Note below
Figure 8-1. Program Memory Space with Interrupt Vector Table
Note:
1. The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overw r ite thi s space.
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8.2 Data Memory Organization
The CY7C637xx microcontrollers provide 256 bytes of data
RAM. In normal usage, the SRAM is partitioned into four
areas: program stack, data stack, user variables and USB
endpoint FIFOs as shown bel ow.
8.3 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O
Write (IOWR, IOWX) instructions. IORD reads the selected
port into the accum ulator. IOWR wri tes dat a from the a ccumu-
lator to the selected port. Indexed I/O Write (IOWX) adds the
contents of X to the addres s in the instru cti on to form the port
address and w rites dat a from the accumul ato r to the spec ified
port. Note that specifying address 0 with IOWX (e.g., IOWX
0h) means the I/O port is selected solely by the contents of X.
Note: All bits of all registers are cleared to all zeros on
reset, except the Processor Status and Control Register
(Figure 20-1). All register s not liste d are reserv ed, and sh ould
never be written by firmware. All bits marked as reserved
should a lw ays b e w ritte n as 0 and be tre ate d as unde fined by
reads.
After reset Address
8-bit DSP 8-bit PSP 0x00 Program Stack Growth
(User’s firmware moves DSP)
8-bit DSP User Selected Data Stack Growth
User V ariables
0xE8 USB FIFO for Address A endpoint 2
0xF0 USB FIFO for Address A endpoint 1
0xF8 USB FIFO for Address A endpoint 0
Top of RAM Memory 0xFF
Figure 8-2. Data Memory Organization
Table 8-1. I/O Register Summary
Register Name I/O Address Read/Write Function Fig.
Port 0 Data 0x00 R/W GPIO Port 0 12-2
Port 1 Data 0x01 R/W GPIO Port 1 12-3
Port 2 Data 0x02 R Auxiliary input register for D+, D–, VREG, XTALIN 12-8
Port 0 Interrupt Enable 0x04 W Interrupt enable for pins in Port 0 21-4
Port 1 Interrupt Enable 0x05 W Interrupt enable for pins in Port 1 21-5
Port 0 Interrupt Polarity 0x06 W Interrupt polarity for pins in Port 0 21-6
Port 1 Interrupt Polarity 0x07 W Interrupt polarity for pins in Port 1 21-7
Port 0 Mode0 0x0A W Controls output configuration for Port 0 12-4
Port 0 Mode1 0x0B W 12-5
Port 1 Mode0 0x0C W Controls output configuration for Port 1 12-6
Por t 1 Mode1 0x0D W 12-7
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USB Device Address 0x10 R/W USB Device Address register 14-1
EP0 Counter Register 0x11 R/W USB Endpoint 0 counter register 14-4
EP0 Mode Register 0x12 R/W USB Endpoint 0 configuration register 14-2
EP1 Counter Register 0x13 R/W USB Endpoint 1 counter register 14-4
EP1 Mode Register 0x14 R/W USB Endpoint 1 configuration register 14-3
EP2 Counter Register 0x15 R/W USB Endpoint 2 counter register 14-4
EP2 Mode Register 0x16 R/W USB Endpoint 2 configuration register 14-3
USB Status & Control 0x1F R/W USB status and control register 13-1
Global Interrupt Enable 0x20 R/W Global interrupt enable register 21-1
Endpoi nt Inte rrupt Enable 0x 21 R/W USB end poi nt inte rrup t enabl es 21-2
Ti mer (LSB) 0x24 R Lower 8 bits of free-running timer (1 MHz) 18-1
Ti mer (MSB) 0x25 R Upper 4 bits of free-running timer 18-2
WDR Clear 0x26 W Watchdog Reset clear -
Capture Timer A Rising 0x40 R Rising edge Capture Timer A data register 19-2
Capture Timer A Falling 0x41 R Falling edge Capture Timer A data register 19-3
Capture Timer B Rising 0x42 R Rising edge Capture Timer B data register 19-4
Capture Timer B Falling 0x43 R Falling edge Capture Timer B data register 19-5
Capture TImer Configuration 0x44 R/W Capture Timer configuration register 19-7
Capture Timer Status 0x45 R Capture Timer status register 19-6
SPI Data 0x60 R/W SPI read and write data register 17-2
SPI Control 0x61 R/W SPI status and control register 17-3
Clock Configuration 0xF8 R/W Internal / External Clock configuration register 9-2
Processor Status & Control 0xFF R/W Processor status and control 20-1
Table 8-1. I/O Register Summary (continued)
Register Name I/O Address Read/Write Function Fig.
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9.0 Clocking
The chi p can be clocke d from ei ther the i nternal on -chip cl ock,
or from an oscillator based on an external resonator/crystal , as
shown in Figure 9-1. No additional cap acitance is in cluded on
chip at the XTALIN/OUT pins. Operation is controlled by the
Clock Configuration Register, Figure 9-2.
Bit 7: Ext. Clock Resume Delay
External Clock Resume Delay bit selects the delay time
when switching to the external oscillator from the internal
oscillator mode, or when waking from suspend mode with
the external oscillator enabled.
1 = 4 m s delay.
0 = 128 µs delay.
The delay gives the oscillator time to start up. The shorter
time is adequate for operation with ceramic resonators,
while the long er time is pre ferred fo r sta rt-up wi th a crys ta l.
(These times do not include an initial oscillator start-up
time which depends on the resonating element. This time
is typi ca lly 50 –100 µs for ceramic reson ators a nd 1–10 ms
for crystals). Note that this bit only select s the delay time for
the external clock mode. When waking from suspend mode
with the internal oscillator (Bit 0 is LOW), the delay time is
only 8 µs in ad dition to a de lay of approxim ately 1 µs for the
oscillator to start.
Bit [6:4]: Wake-up Timer Adjust Bit [2:0]
The Wake-up Timer Adjust Bits are used to adjust the
Wake-up timer period.
If the Wake-up interrupt is enabled in the Global Interrupt
Enable R eg ister, the microc ontro ll er w i ll g en erat e wak e-u p
interrupts periodically. The frequency of these periodical
wake-up in terrupt s is adjuste d by setting the W ake-up Tim-
er Adjust Bit [2:0], as described in Section 11.2. One com-
mon use of the wake-up inte rrupt s is to generat e periodica l
wake-up events during suspend mode to check for chang-
es, such as looking for movement in a mouse, while main-
taining a low average power.
Bit 3: Low-voltage Reset Disable
When V CC drop s belo w VLVR (see Sec ti on 25.0 for the va l-
ue of VLVR) and the Low-voltage Reset circuit is enabled,
the microcontroller enters a partial suspend state for a pe-
riod of tSTART (see Section 26.0 for the value of tSTART).
Program execution begins from address 0x0000 after this
tSTART dela y peri od . This pr ovides time fo r VCC to stabilize
Figure 9-1. Clock Oscillator On-chip Circuit
XTALOUT
XTALIN
Clk2x (12 MHz) Clock
Doubler
Clk1x (6 MHz)
(to Microcontroller)
(to USB SIE)
Port 2.1
Internal Osc
Int Clk Output Disable
Ext Clk Enable
Bit # 76543210
Bit Name Ext. Cloc k
Resume
Delay
Wake-up Timer Adjust Bit [2:0] Low-voltage
Reset
Disable
Precision
USB
Clocking
Enable
Internal
Clock
Output
Disable
External
Oscillator
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 9-2. Clock Configuration Register (Address 0xF8)
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befo re the part exec ute s co de. See Se ctio n 10. 1 f or m ore
details.
1 = Disables the LVR circuit.
0 = Enable s the LVR circuit.
Bit 2: Precision USB Clocking Enable
The Precision USB Clocking Enable only affects operation
in internal oscillator mod e. In tha t mode , this bit mus t be
set to 1 to cause the internal clock to automatica lly pre-
cisely tune to USB timing require ment s (6 M Hz ± 1.5% ).
The fr eque ncy may have a l ooser init ial to leranc e at po w-
er-up, but al l USB tr ansmissio ns from the ch ip wi ll meet the
USB specification.
1 = Enabled. The internal clock accuracy is 6 MHz ±1.5%
after USB traffic is received.
0 = Disabled. The internal clock accuracy is 6 MHz ±5%.
Bit 1: Internal Clock Output Disable
The I nternal Clock Output Disabl e is used to keep the int er-
nal clock from driving out to the XTALOUT pin. This bit has
no effect in the external oscillator mode.
1 = Disable internal clock output. XTALOUT pin will drive
HIGH.
0 = Enable the internal clock output. The internal clock is
driven out to the XTALOUT pin.
Bit 0: External Oscillator Enable
At power-up, the chip operates from the internal clock by
default. Setting the Exte rnal Oscillator Enable bit HIGH di s-
ables the internal clock, and halts the part while the external
resonator/crystal oscillator is started. Clearing this bit has
no immediate effect, although the state of this bit is used
when wak ing out of su spend mod e to select be tween int er-
nal and external clock. In internal clock mode, XTALIN pin
will be configured as an input with a weak pull-down and
can be used as a GPIO input (P2.1).
1 = Enable the external oscillator. The clock is switched to
external clock mode, as described in Section 9.1.
0 = Enable the internal oscillator.
9.1 Internal /Ex ternal Os cilla tor Opera ti on
The intern al osc il lat or provides an operating c lo ck, fac tory set
to a nominal frequency of 6 MHz. This clock requires no
external componen ts. At power-up, the chip operates from the
internal clock. In this mode, the internal clock is buffered and
driven to the XTALOUT pin by default, and the state of the
XTALIN pin can be read at Po rt 2.1. Wh ile the i nterna l cloc k is
enabled, its output can be disabled at the XTALOUT pin by
setting the Internal Clock Output Disable bit of the Clock
Conf igur atio n Register.
Setting the External Oscillator Enable bit of the Clock Config-
uration Register HIGH disables the internal clock, and halts
the part while the external resonator/crystal oscillator is
started. The steps involved in switching from Internal to
External Clock mode are as follows:
1. At reset, chip begins operation using the internal clock.
2. Firmware sets Bit 0 of the Clock Configuration Register. For
example,
mov A, 1h ; Set Bit 0 HIGH (External Oscil-
lator Enable bit). Bit 7 cleared
gives faster start-up
iowr F8h ; Write to Clock Configuration
Register
3. Internal clocking is halted, the internal oscillator is disabled,
and the external clock oscillator is enabled.
4. After the external clock becomes stable, chip clocks are
re-enabled using the external clock signal. (Note that the
time for the external clock to become stable depends on the
exter nal resonating device; see next section.)
5. After an additional delay the CPU is released to run. This
delay depends on the state of the Ext. Clock Resume Delay
bit of the C lo ck Conf iguration R e gis ter. The time is 128 µs
if the bit is 0, or 4 ms if the bit is 1.
6. Once the chip has been set to external oscillator , it can only
return to internal clock when waking from suspend mode.
Clearing bit 0 of the Clock Configuration Register will not
re-enable internal clock mode until suspend mode is
entered. See Section 11.0 for more details on suspend
mode operation.
If the Internal Clock is enabled, the XTALIN pin can serve as
a general purpose input, and its state can be read at Port 2,
Bit 1 (P2.1). Re fer t o Figure 12-8 for the Port 2 Data Register .
In this mode, there is a weak pull-down at the XT ALIN pin. This
input cannot provide an interrupt source to the CPU.
9.2 External Oscillator
The user can connect a low-cost ceramic resonator or an
external oscillator to the XTALIN/XTALOUT pins to provide a
precise reference frequency for the chip clock, as shown in
Figure 9-1. The external components required are a ceramic
resonator or crystal and any associated capacitors. To run
from the external resonator, the External Oscillator Enable bit
of the Clock Configuration Register must be set to 1, as
explained in the previous section.
Start-up times for the external oscillator depend on the
resonating device. Ceramic resonator based oscillators
typically start in less than 100 µs, while crystal based oscil-
lators take longer, typically 1 to 10 ms. Board capacitance
should be minimized on the XTALIN and XTALOUT pins by
keeping t he traces as short as possi ble.
An external 6-MHz clock can be applied to the XTALIN pin if
the XTALOUT pin is left open.
10.0 Reset
The USB Controller supports three types of reset s. The effects
of the reset are listed below. The reset types are:
1. Low-vo ltage Reset (LVR)
2. Brown Ou t Reset (BOR)
3. Watchdog Reset (WDR)
The occ urre nce of a re se t is rec ord ed in the Processo r St atu s
and Control Register (Figure 20-1). Bits 4 (Low-voltage or
Brown-out Reset bit) and 6 (Watchdog Reset bit) are used to
record the occurrence of LVR/BOR and WDR respectively.
The firmware can interrogate these bits to determine the cause
of a reset.
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The microcontroller begins execution from ROM address
0x0000 after a LVR, BOR, or WDR reset. Although this looks
like interrupt vector 0, there is an important difference. Reset
processing does NOT push the program counter, carry flag,
and zero flag onto pro gram stack. Attempting to execute either
a RET or RETI in the reset handler will cause unpredictable
execution results.
The following events take place on reset. More details on the
various resets are given in the following sections.
1. All registers are reset to their default states (all bits cleared,
except in Processor Status and Control Register).
2. GPIO and USB pins are set to high-impedance state.
3. The VREG pin is set to high-impedanc e state.
4. Interrupts are disabled.
5. USB operation is disabled and must be enabled by firmware
if desired, as explained in Section 14.1.
6. For a BOR or LVR, the external oscillator is disabled and
Internal C loc k mo de is act iv ated , follo w ed by a time -out
period tSTART for VCC to st abilize. A WDR does no t change
the clo ck mod e, a nd there i s no de lay fo r VCC s tabilization
on a WD R. N ot e th at th e Ex tern al Os ci ll ator Enable (Bit 0,
Figure 9-2) will be cleared by a WDR, but it does not take
effect until suspend mode is entered.
7. The Program Stack Pointer (PSP) and Data Stack Pointer
(DSP) reset to address 0x00. Firmware should move the
DSP for USB applications, as explained in Section 6.5.
8. Program execution begins at address 0x0000 after the
appropri ate tim e-o ut period.
10.1 Low-voltage Reset (LVR)
When VCC is first applied to the chip, the internal oscillator is
started and the Low-voltage Reset is initially enabled by
default. At the point where VCC has risen above VLVR (see
Section 25.0 for the value of VLVR), an internal counter starts
counting for a period of tSTART (see Secti on 26.0 for the v alu e
of tSTART). During this tSTART time, the microcontroller enters
a partial suspend state to wait for VCC to stabilize before it
begins executing code from address 0x0000.
As long as the LVR circuit is enabled, this reset sequence
repeats whene ve r the VCC pin voltage drops be low V LVR. The
LVR can be disabled by firmware by setting the Low-voltage
Reset Disable bit in the Clock Configuration Register
(Figure 9-2). In addition, the LVR is automatically disabled in
suspend mode to save power. If the LVR was enabled before
entering suspend mode, it becomes active again once the
suspend mode ends.
When LVR is disable d during norma l operation (i.e., by writing
‘0’ to the Low-voltage Reset Disable bit in the Clock Configu-
ration Register), the chip may enter an unknown state if VCC
drops below VLVR. Therefore, LVR should be enabled at all
times during normal operation. If LVR is disabled (i.e., by
firmware or during suspend mode), a secondary low-voltage
monitor, BOR, becomes active, as described in the next
section. The LVR/BOR Reset bit of the Processor Status and
Control Register (Figure 20-1), is set to ‘1’ if either a LVR or
BOR has occurred.
10.2 Brown Out Reset (BOR)
The Brown Out Reset (BOR) circuit is always active and
behaves like the POR. BOR is asserted whenever the VCC
volt age to t he device i s below an interna lly defin ed trip vol tage
of approximately 2.5V . The BOR re-enables L VR. That is, once
VCC drops and trips BOR, the part remains in reset until VCC
rises above VLVR. At that point, th e tSTART delay o ccurs befo re
normal operation resumes, and the microcontroller starts
executing code from address 0x00 after the tSTART de lay.
In suspend mode, only the BOR detection is active, giving a
reset if VCC drops belo w approxima tely 2.5V. Since the device
is suspended and code is not executing, this lower reset
voltage is safe for retaining the state of all registers and
memory. Note that in suspend mode, LVR is disabled as
discussed in Section 10.1.
10.3 Watchdog Reset (WDR)
The Watchdog Timer Reset (WDR) occurs when the internal
Watchdog timer rolls over. Writing any value to the write-only
W a tchdog Reset R egist er at add ress 0x26 will clear t he time r.
The timer will roll over and WDR will occur if it is not cleared
within tWATCH (see Figure 10-1) of the last clear. Bit 6
(Watchdog Reset bit) of the Processor Status and Control
Register i s s et to re co rd this event (see Section 20.0 for more
details). A Watchdog Timer Reset typically lasts for 2–4 ms,
after which the microcontroller begins execution at ROM
address 0x0000.
At least 10.1 ms WDR goes HIGH Execution begins at
ROM Address 0x0000
2–4 ms
since last write to WDR for 2–4 ms
14.6 ms
(at FOSC = 6 MHz)
WDR
tWATCH = 10.1 to
Figure 10-1. Watchdog Reset (WDR, Address 0x26)
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11.0 Suspend Mode
The CY 7C 63 7xx parts support a versatile low-powe r s us pen d
mode. In suspend mode, only an enabled interrupt or a LOW
stat e o n the D–/SDA TA pin will wake the part. T wo options are
available. For lowest power, all internal circuits can be
disabled, so only an external event will resume operation.
Alternati vel y, a low- powe r in tern al wak e-up ti mer can be use d
to trigger the wake-up interrupt. This timer is described in
Section 11.2, and can be used to periodically poll the system
to check for changes, such as looking for movement in a
mouse, while maintaining a low average power.
The CY7C637xx is placed into a low-power state by setting the
Suspend bit of the Processor Status and Control Register
(Figure 20-1). All logic blocks in the device are turned off
except the GPIO interrupt logic, the D–/SDATA pin input
receiver, and (optionally) the wake-up timer. The clock oscil-
lators, as well as the free-running and Watchdog timers are
shut do wn. Only the occurr ence of an enabled GPIO int errupt,
wake-up interrupt, SPI slave interrupt, or a LOW state on the
D–/SDATA pin will wake the part from suspend (D– LOW
indicates non-idle USB activity). Once one of these resuming
conditions occurs, clocks will be restarted and the device
returns to full operation after the oscillator is stable and the
select ed delay period expires. This d elay pe riod is determine d
by selection of internal vs. external clock, and by the state of
the Ext. Clock Resume Delay as explained in Section 9.0.
In suspend mode, any enabled and pending interrupt will wake
the part up. The state of the Interrupt Enable Sense bit (Bit 2,
Figure 20-1) does not have any effect. As a result, any inter-
rupts not intended for waking from suspend should be disabled
through t he Global Interrupt Ena ble Register and the USB End
Point Interrupt Enable Register (Section 21.0).
If a resum in g c ond iti on e xi st s whe n the suspen d bi t is set, the
part will still go into suspend and then awake after the appro-
priate delay time. The Run bit in the Processor Status and
Control Register must be set for the part to resume out of
suspend.
Once the clock is stable and the delay time has expired, the
microcontroller will execute the instruction following the I/O
write that placed the device into suspend mode before
servicing any interrupt requests.
To achieve the lowest pos si ble curre nt duri ng suspend mode,
all I/O should be held at either VCC or ground. In addition, the
GPIO bit interrupts (Figure 21-4 and Figure 21-5) should be
disabled for any pins that are not being used for a wake-up
inter rupt. Th is s hould be d one e ven i f the main GPIO Interru pt
Enable (Figure 21-1) is off.
Typical code for entering suspend is shown below:
... ; All GPIO set to low-power state (no floating
pins, and bit interrupts disabled unless
using for wake-up)
... ; Enable GPIO and/or wake-up timer
interrupts if desired for wake-up
... ; Select clock mode for wake-up (see
Section 11.1)
mov a, 09h ; Set suspend and run bits
iowr FFh ; Write to Status and Control Register –
Enter suspend, wait for GPIO/wake-up
in terrupt or USB acti vity
nop ; This executes before any ISR
... ; Remaining code for exiting suspend
routine
11.1 Clocking Mode on Wake-up from Suspend
When exiting suspend on a wake-up event, the device can be
configured to run in either Internal or External Clock mode.
The mode is selected by the state of the External Oscillator
Enable bit in the Clock Configuration Register (Figure 9-2).
Usin g th e I nt e rna l Cl oc k s a ve s t he ex t er nal o sc i ll at o r s tar t- up
time and ke eps th at osc illato r of f for a dditio nal pow er sa vings .
The external oscillator mode can be activated when desired,
similar to operation at power-up.
The sequence of events for these modes is as follows:
Wake in Internal Clock Mode:
1. Before entering suspend, clear bit 0 of the Clock Configu-
ration Register. This selects Internal clock mode after sus-
pend.
2. Enter suspend mode by setting the suspend bit of the
Processor Status and Control Register.
3. After a wake-up event, the internal clock star ts immediately
(within 2 µs).
4. A time-out period of 8 µs passes, and the n firmware
execution begins.
5. At some later point, to activate External Clock mod e, set bit
0 of the Clock Configuration Register. This halts the internal
clocks while the external clock becomes stable. After an
additional time-out (128 µs or 4 ms, see Section 9.0),
firmware execution resumes.
Wake in External Clock Mode:
1. Before entering suspend, the external clock must be select-
ed by setting bit 0 of the Clock Configuration Register. Make
sure thi s bit is sti ll set when s uspend mode is entered. T his
selects External clock mode after suspend.
2. Enter suspend mode by setting the suspend bit of the
Processor Status and Control Register.
3. After a wake-up event, the external oscillator is started. The
clock is monitored for stability (this takes approximately
50–100 µs with a ceramic resonator).
4. After an additional time-out period (128 µs or 4 ms, see
Section 9.0), firmware execution resumes.
11.2 Wake-up Timer
The wake-up timer runs whenever the wake-up interrupt is
enabled, and is turned off whenever that interrupt is disabled.
Operation is independent of whether the device is in suspend
mode or if the global interrupt bit is enabled. Only the W ake-up
Timer Interrupt Enable bit (Figure 21-1) controls the wake-up
timer.
Once this timer is activated, it will give interrupts after its
time-out period (s ee below ). These in terrupts continue period-
ically until the interrupt is disabled. Whenever the interrupt is
disabled, the wake-up timer is reset, so that a subsequent
enable always results in a full wake-up time.
The wake-up timer can be adjusted by the user through the
W ake-up T imer Adjust bits in the Clock Configuration Register
(Figure 9-2). These bits clear on reset. In addition to allowing
the user to select a range for the wake-up time, a firmware
algorith m can be us ed to tune out initial pr ocess and o perating
conditi on varia tions in this wak e-up time . This ca n be done by
timing the wake-up interrupt time with the accurate 1.024-ms
timer in terrupt, and a djusting the T imer Ad just bit s acco rdingly
to approximate the desired wake-up time.
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12.0 General Purpose I/O Ports
Ports 0 and 1 provid e up to 16 vers atile GPIO pi ns that can be
read or written (the number of pin s depends on packag e type).
Figure 12-1 shows a diagram of a GPIO port pin.
Port 0 is an 8-bi t port ; Port 1 con t ai ns eith er 2 b it s , P1. 1 –P1.0
in the CY7C6 3723, or all 8 bits , P1.7–P1.0 i n the C Y7C63743
parts. Each b it c an a ls o be sel ec ted as an i nterr upt s ou r ce for
the microcontroller, as explained in Section 21.0.
The data for each GPIO pin is accessible through the Port
Data r egister. Writes to the Po rt Data re gister store ou tgoing
data state for the port pins, while reads from the Port Data
register return the actual logic value on the port pins, not the
Port Data register contents.
Each GPIO pin is configured independently. The driving state
of each GPIO pin is determined by the value written to the pin’s
Dat a Re gi ste r and by two a ss ociated pin’s Mo de0 and M ode1
bits.
The Port 0 Data Register is shown in Figure 12-2, and the Port
1 Data Register is shown in Figure 12-3. The Mode0 and
Mode1 bits for the two GPIO ports are given in Figure 12-4
through Figure 12-7.
Table 11-1. Wake-up Timer Adjust Settings
Adjust Bits [2:0]
(Bits [6:4] in Figure 9-2) Wake-up Time
000 (reset state) 1 * tWAKE
001 2 * tWAKE
010 4 * tWAKE
011 8 * tWAKE
100 16 * tWAKE
101 32 * tWAKE
110 64 * tWAKE
111 128 * tWAKE
See Section 26.0 for the value of tWAKE
GPIO
Pin
VCC
14 kΩ
GPIO
Mode
Data
Out
Register
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
Control
To Inte rr upt
Controller
Q1
Q2
Q3
To Capture Ti mers (P0.0, P0.1)
and SPI (P0.4–P0.7))
Logic
Interrupt
Polarity
2
Thresh old Sel ect
SPI Bypas s (P0.5–P0.7 only)
(=1 if SPI inactive, or for non-SPI pins)
(Data Reg must be 1
for SPI outputs)
Figure 12-1. Block Diagram of GPIO Port (one pin shown)
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Bit [7:0]: P0[7:0]
1 = Port Pin is logic HIGH
0 = Port Pin is l ogic LOW
Bit [7:0]: P1[7:0]
1 = Port Pin is logic HIGH
0 = Port Pin is l ogic LOW
Bit [7:0]: P0[7:0] Mode 0
1 = Port 0 Mode 0 is logic HIGH
0 = Port 0 Mode 0 is logic LOW
Bit [7:0]: P0[7:0] Mode 1
1 = Por t Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Bit [7:0]: P1[7:0] Mode 0
1 = Port Pin Mode 0 is logic HIGH
0 = Port Pin Mode 0 is logic LOW
Bit [7:0]: P1[7:0] Mode 1
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Each pin can be independentl y configured as hi gh-impedance
inputs, inputs with internal pull-ups, open drain outputs, or
traditiona l CMOS outputs with selectable drive strengths.
The drivi ng st ate of ea ch GPIO pin is determi ned by the valu e
written to the pin’s Dat a Register and by its ass ociated Mode 0
and Mode1 bits. Table 12-1 lists the configuration states
based on these bits. The GPIO ports default on reset to all
Data and Mode Registers cleared, so the pins are all in a
high-impedance state. The available GPIO output drive
strength are:
•Hi-Z Mode (Mode1 = 0 and Mode0 = 0)
Q1, Q2, and Q3 (Figure 12-1) are OFF. The GPIO pi n is not
driven internally . Performing a read from the Port Data Reg-
ister return the actual logic value on the port pins.
•Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 2 mA of current.
•Medium Sink Mo de (Mode1 = 0, Mode0 = 1, and the pin’s
Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 8 mA of current.
•High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data
Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 50 mA of current.
•High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s
Data Register = 1)
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of
sourcing 2 mA of current.
•Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Register = 1)
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up
with an internal 14-kΩ resistor.
Note that open drain mode can be achieved by fixing the Data
and Mod e1 Registe rs LOW , and s witching t he Mode0 regi ster .
Input th resholds are CMOS, or TTL as show n in the t able (See
Section 25.0 for the input threshold voltage in TTL or CMOS
modes). Both input modes include hysteresis to minimize
noise sensitivity. In suspend mode, if a pin is used for a
wake-up interrupt using an external R-C circuit, CMOS mode
is preferred for lowest power.
Bit # 76543210
Bit Name P0
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Reset 00000000
Figure 12-2. Port 0 Data (Address 0x00)
Bit # 76543210
Bit Name P1
Notes Pins 7:2 only in CY7C63743 Pins 1:0 in
all parts
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 12-3. Port 1 Data (Address 0x01)
Bit # 76543210
Bit Name P0[7:0] Mode0
Read/Write WWWWWWWW
Reset 00000000
Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A)
Bit # 76543210
Bit Name P0[7:0] Mode1
Read/Write WWWWWWWW
Reset 00000000
Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B)
Bit # 76543210
Bit Name P1[7:0] Mode0
Read/Write WWWWWWWW
Reset 00000000
Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C)
Bit # 76543210
Bit Name P1[7:0] Mode1
Read/Write WWWWWWWW
Reset 00000000
Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D)
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12.1 Auxiliary Input Port
Port 2 serves as an auxiliary input port as shown in
Figure 12-8. The Port 2 inputs all have TTL inp ut thres ho lds.
Bit [7:6]: Reserved
Bit [5:4]: D+ (SCLK) and D– (SDATA) States
The st ate of the D+ and D– pins can be rea d at Po rt 2 Da ta
Regist er. Performi ng a read fro m the po rt pins returns their
logic values.
1 = Port Pin is logic HIGH
0 = Port Pin is l ogic LOW
Bit [3:2]: Reserved
Bit 1: P2.1 (Internal Clock Mode Only)
In the Internal Clock mode, the XTALIN pin can serve as a
general purpose input, and its state can be read at Port 2,
Bit 1 (P2.1). See Section 9.1 for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is l ogic LOW
Bit 0: P2.0/VREG Pin State
In PS/2 mode, the VREG pin can be used as an input and
its state can be read at port P2.0. Section 15.0 for more
details.
1 = Port Pin is logic HIGH
0 = Port Pin is l ogic LOW
13.0 USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the
USB host. Th e SIE simpli fies the interfac e between the m icro-
controller and USB by incorporating hardware that handles the
following USB bus activity independently of the microcon-
troller:
•Translate the encoded received data and format the data to
be transmitted on the bus.
•CRC checking and generation. Flag the microcontroller if
errors exist during transmission.
•Address checking. Ignore the transactions not addressed
to the device.
•Send appropriate ACK/NAK/STALL handshakes.
•Token type identification (SETUP, IN, or OUT). Set the ap-
propriate token bit once a valid token is received.
•Place valid received data in the appropriate endpoint FIFOs.
•Send and update the data toggle bit (Data1/0).
•Bit stuffing/unstuffing.
Firmware is required to handle the rest of the USB interface
with the following tasks:
•Coordinate enumeration by decoding USB device requests.
•Fill and empty the FIFOs.
•Suspend/Resume coordination.
•Verify and select Data toggle values.
13.1 USB Enumeration
A typical USB enumeration sequence is shown below. In this
description, ‘Firmware’ refers to embedded firmware in the
CY7C637xx controller.
1. The host computer sends a SETUP pack et followed by a
DATA packet to USB address 0 requesting the Device de-
scriptor.
2. Firmware decodes the request and retrieves its Device
descriptor from the program memory tables.
3. The ho st c ompu t er pe rform s a co ntro l rea d se qu enc e an d
Firmwa re responds by sendin g the Device des cripto r over
the USB bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP
packet followed by a DATA packet to address 0 assigning
a new USB address to the device.
5. Firmware stores the new address in its USB Device
Address Register after the no-data control sequence
completes.
6. The host sends a request for the Device descriptor using
the new USB address.
7. Firmware decodes the request and retrieves the Device
descriptor from program memory tables.
8. The ho st p erfo rms a c ontro l re ad s equ enc e a nd Fi rmw a re
responds by se nding its Device descriptor over the USB
bus.
9. The host generates control reads from the device to request
the Configuration and Report descriptors.
10.Once the device receives a Set Configuration request, its
functions may now be used.
11.Firmware should take appropriate action for Endpoint 1
and/or 2 transactions, which may occur from this point.
Table 12-1. Ports 0 and 1 Output Control Truth Table
Data
Register Mode1 Mode0 Output Drive
Strength Input
Threshold
000 Hi-Z CMOS
1Hi-ZTTL
001Medium
(8 mA) Sink CMOS
1High DriveCMOS
010
Low (2 mA)
Sink CMOS
1ResistiveCMOS
011
High (50 mA)
Sink CMOS
1High DriveCMOS
Bit # 7 6 5 4 3 2 1 0
Bit
Name Reserved D+
(SCLK)
State
D–
(SDATA)
State
Reserved P2.1
(Internal
Clock
Mode
Only)
P2.0
VREG
Pin
State
Read/
Write -- R R -- R R
Reset 00 0 0 00 0 0
Figure 12-8. Port 2 Data Register (Address 0x02)
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13.2 USB Port Status and Control
USB status and control is regulated by the USB Status and
Cont rol Register as shown in Figure 13-1.
Bit 7: PS/2 Pull-up Enable
This bit is used to enab le the i nternal PS/2 pu ll-up resisto rs
on the SDATA and SCLK pins. Normally the output high
level on these pins is VCC, but note that the output will be
clamped to approximately 1 Volt above VREG if the VREG
Enable bit is set, or if the Device Address is enabled (bit 7
of the USB Device Address Register, Figure 14-1).
1 = Enable PS/2 Pull-up resistors. The SDATA and SCLK
pins are pulled up internally to VCC with two resistors of
approximately 5 kΩ (see Section 25.0 for the value of
RPS2).
0 = Disable PS/2 Pull-up resistors.
Bit 6: VREG Enable
A 3.3V voltage regulato r is integrated on chip to provide a
voltage source for a 1.5-kΩ pull-up resistor connected to
the D– pin as required by the USB Specification. Note that
the VREG output has an internal series resistance of ap-
proximately 200Ω, the external pull-up resistor required is
approximately 1.3-kΩ (see Figure 16-1).
1 = Enable the 3.3V output voltage on the VREG pin.
0 = Disable. The VREG pin can be configured as an input.
Bit 5: USB-PS/2 Interrupt Select
This bi t allows the user to sel ect whether an USB bus res et
inter rupt or a PS/2 a ctivi ty interru pt will be generat ed whe n
the interrupt conditions are detected.
1 = PS/2 in terrupt mode . A PS/2 acti vity i nterrupt wi ll occur
if the SDATA pin is continuously LOW for 128 to 256 µs.
0 = USB interrupt mode (d efault sta te). In this m ode, a USB
bus res et i nte rrupt will o ccur i f th e s ing le en ded ze ro (SE 0,
D– and D+ are LOW) exists for 128 to 256 µs.
See Section 21.3 for more details.
Bit 4: Reserved. Must be written as a ‘0’.
Bit 3: USB Bus Activity
The Bus Ac tivity bit is a “sticky” bit that detects any non-idle
USB event has occurred on the USB bus. Once set to HIGH
by the SIE to indicate the bus activity, this bit retains its
logical HIGH value until firm ware clears it. Writing a ‘0’ to
this bit clears it; writing a ‘1’ preserves its value. The user
firm war e sh ou ld ch ec k an d cle a r thi s bit pe r i od ic all y t o de -
tect any loss of bus activity. Firmware can clear the Bus
Activity bit, but only the SIE can set it. The 1.024-ms timer
interrupt service routine is normally used to check and clear
the Bus Activity bit.
1 = There has been bus activity since the last time this bit
was cleared. This bit is set by the SIE.
0 = No bus a ctivi ty since l ast time this bi t was clear ed (by
firmware).
Bit [2:0]: D+/D– Forcing Bit [2:0]
Forc in g bi ts allo w fir m war e t o dir e ctl y dr iv e t he D + an d D–
pins, as shown in Table 13-1. Outputs are driven with con-
trolled edge rates in these modes for low EMI. For forcing
the D+ and D– pins in USB mode, D+/D– Forcing Bit 2
should be 0. Setting D+/D– Forcing Bit 2 to ‘1’ puts both
pins in an open-drain mode, preferred for applicati ons such
as PS/2 or LED driving.
Note:
2. For PS/2 operation, the D+/D– Forcing Bit [2:0] = 111b mode must be set initially (one time only) before using the other PS/2 force modes.
Bit # 76 5 4 3 2:0
Bit
Name PS/2
Pull-up
Enable
VREG
Enable USB
Reset-
PS/2
Activity
Interrupt
Mode
Reserved USB
Bus
Activity
D+/D–
Forcing
Bit
Read/
Write R/W R/W R/W - R/W R/W
Reset 00 0 0 0000
Figure 13-1. USB Status and Control Register (Address
0x1F)
Table 13-1. Control Modes to Force D+/D– Outputs
D+/D– Forcing
Bit [2:0] Control Action Application
000 Not forcing (SIE controls driver) Any Mode
001 Force K (D+ HIGH, D– LOW) USB Mode
010 Force J (D+ LOW, D– HIGH)
011 Force SE0 (D– LOW , D+ LOW)
100 Force D– LOW, D+ LOW PS/2 Mode[2]
101 Force D– LOW, D+ HiZ
110 Force D– HiZ, D+ LOW
111 Force D– HiZ, D+ HiZ
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14.0 USB Device
The CY7C637xx supports one USB Device Address with three
endpoints: EP0, EP1, and EP2.
14.1 USB Address Register
The USB Device Address Register contains a 7-bit USB
address and one bit to enable USB communication. This
register is cleared during a reset, setting the USB device
address to zero and marking this address as disabled.
Figure 14-1 shows the format of the USB Address Register.
In either USB or PS/2 mode, this register is cleared by both
hardware res et s and the U SB bus reset. Se e Sec tion 21.3 for
more information on the USB Bus Reset – PS/2 interrupt.
Bit 7: Device Address Enable
This bit must be enabled by firmware before the serial in-
terface engine (SIE) will respond to USB traffic at the ad-
dress specified in Bit [6:0].
1 = Enable USB device address.
0 = Disable USB device address.
Bit [6:0]: Device Address Bit [6:0]
These bits must be set by firmware during the USB enumer-
ation process (i.e., SetAddress) to the non-zero address
assigned by the USB host.
14.2 USB Control Endpoint
All USB devices are required to have an endpoint number 0
(EP0) that is used to ini tialize and control the USB device. EP0
provides access to the device configuration information and
allows generic USB status and control accesses. EP0 is
bidirec tional as the devic e can bot h receive and transmit dat a.
EP0 uses an 8-byte FIFO at SRAM locations 0xF8-0xFF, as
shown in Section 8.2.
The EP0 endpoint mode register uses the format shown in
Figure 14-2.
The SIE provides a locking feature to prevent firmware from
over w rit i ng bi ts i n t he U SB Endpo i nt 0 Mode R e gis te r. Writes
to the regi ste r have no ef fec t fro m t he p oin t tha t Bit[6:0] of th e
register are updated (by the SIE) until the firmware reads this
register. The CPU can unlock this register by reading it.
Because of these hardware-locking features, firmware should
perform an read after a write to the USB Endpoint 0 Mode
Register and USB Endpoint 0 Count Register (Figure 14-4) to
verify tha t the content s have chang ed as desired , and that the
SIE has not updated thes e val ue s.
Bit [7:4] of this register are cleared by any non-locked write to
this register, regardless of the value written.
Bit 7: SETUP Received
1 = A valid SETUP packet has been received. This bit is
forced HIGH from the start of the data packet phase of the
SETUP transaction until the start of the ACK packet re-
turned b y the SIE. Th e CPU is p revente d from c learin g thi s
bit during this interval. While this bit is set to ‘1’, the CPU
cannot wri te to t he EP0 FIFO. This preven t s firmw are from
overwriting an incoming SETUP transaction before firm-
ware has a chance to read the SETUP data.
0 = No SETUP received. This bit is cleared by any
non-locked writes to the register.
Bit 6: IN Received
1 = A va lid IN packe t has been rece ived. This bi t is updated
to ‘1’ after t he last received p acket in an IN transaction. This
bit is cleared by any non-locked writes to the register.
0 = No IN received. This bit is cleared by any non-locked
writes to the register.
Bit 5: OUT Received
1 = A valid OUT packet has been received. This bit is up-
dated to ‘1’ after the last received packet in an OUT trans-
action. This bit is cleared by any non-locked writes to the
register.
0 = No OUT receiv ed. This bit is c leared by any non- locked
writes to the register.
Bit 4: ACKed Transaction
The ACKed T ransactio n bit is set whene ver the SIE engag-
es in a transaction to the register's endpoint that completes
with an ACK pa cket.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode Bit[3:0]
The endpoint modes determine how the SIE responds to
USB traffic that the host sends to the endpoint. For exam-
ple, if the end poi nt Mode Bit s [3:0] are set to 0001 which is
NAK IN/OUT mode as shown in Table 22-1, the SIE will
send NAK handshak es in response to any IN or OU T token
sent to this endpoint. In this NAK IN/OUT mode, the SIE will
send an ACK handshake when the host sends a SETUP
token to this endpoint. The mode encoding is shown in
Table 22-1. Addit ion al i nfo rma tio n on the mode b it s c an b e
found in Table 22-2 and Table 22-3. T hes e mo des g ive the
firmware total control on how to respond to different tokens
sent to the endpoints from the host.
Bit # 7 6543210
Bit Name Device
Address
Enable
Device Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0000000
Figure 14-1. USB Device Address Register (Address 0x10)
Bit # 765 4 3:0
Bit
Name SETUP
Received IN
Received OUT
Received ACKed
Transaction Mode Bit
Read/
Write R/W R/W R/W R/W R/W
Reset 000 00000
Figure 14-2. Endpoint 0 Mode Register (Address 0x12)
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In addi tion, the M ode Bits are automat ically chang ed by the
SIE in response to many USB transa ctions. For example, if
the Mode Bit [3:0] are set to 1011 which is ACK OUT-NAK
IN mode as shown in Table 22-1, the SIE will change the
endpoint Mode Bit [3:0] to NAK IN/OUT (0001) mode after
issuing an ACK handshake in response to an OUT token.
Firmware ne eds to upd ate the mode for th e SIE to respon d
appropriately.
14.3 USB Non-control Endpoints
The CY7C637xx feature two non-control endpoints, endpoint
1 (EP1) and endpoint 2 (EP2). The EP1 and EP2 Mode
Registers do not have the locking mechanism of the EP0
Mode Register. The EP1 and EP2 Mode Registers use the
format shown in Figure 14-3. EP1 uses an 8-byte FIFO at
SRAM locations 0xF0–0xF7, EP2 uses an 8-byte FIFO at
SRAM locations 0xE8–0xEF as shown in Section 8.2.
Bit 7: STALL
1 = The SIE will stall an OUT packet if the Mode Bits are set
to ACK-OUT, and the SIE will stall an IN packet if the mode
bits are set to ACK-IN. See Section 22.0 for the available
modes.
0 = This bit must be set to LOW for all other modes.
Bit [6:5]: Reserved. Must be written to zero during register
writes.
Bit 4: ACKed Transaction
The ACKed tran sacti on bit is set when ever the SIE engag-
es in a transaction to the register's endpoint that completes
with an ACK packet.
1 = The transaction completes with an ACK.
0 = The transaction does not complete with an ACK.
Bit [3:0]: Mode Bit [3:0]
The EP1 and EP2 Mode Bits operate in the same manner
as the EP0 Mode Bits (see Section 14.2).
14.4 USB Endpoint Counter Registers
There are three Endpoint Counter registers, with identical
formats for both control and non-control endpoints. These
registers cont ain by te count in formati on for USB transa ctions ,
as well as bits for data packet status. The format of these
registers is shown in Figure 14-4.
Bit 7: Data Toggle
This bit selects the DATA packet's toggle state. For IN
transactions, firmware must set this bit to the select the
transmitted Data Toggle. For OUT or SETUP transactions,
the hardware sets this bit to the state of the received Data
Toggle bit.
1 = DATA1
0 = DATA0
Bit 6: Data Valid
This bit is used for OUT and SET UP tokens only. This bit is
clear ed to ‘0’ if CRC, bitstuff, or PID errors have occurred.
This bit does not update for some endpoint mode settings.
Refer to Table 22-3 for more details.
1 = Data is vali d.
0 = Data is invalid. If enabled, the endpoint interrupt will
occur even if invalid data is received.
Bit [5:4]: Reserved
Bit [3:0]: Byte Count Bit [3:0]
Byte Count Bits indicate the number of data bytes in a
transaction: For IN transactions, firmware loads the count
with th e n umb er o f by te s to be transmitted to th e h os t from
the endpoint FIFO. Valid values are 0 to 8 inclusive. For
OUT or SETUP transac tions, th e count is updated by hard-
ware to the number of data bytes received, plus 2 for the
CRC bytes. Va lid values are 2 to 10 inclusive.
For Endpoint 0 Count Register, whenever the count up-
dates from a SETUP or OUT transaction, the count register
locks and cannot be written by the CPU. Reading the reg-
ister unlocks it. This prevents firmware from overwriting a
status update on incoming SETUP or OUT transactions be-
fore firmware has a chance to read the data.
Bit # 7 65 4 3210
Bit
Name STALL Reserved ACKed
Transaction Mode Bit
Read/
Write R/W - - R/C R/W R/W R/W R/W
Reset 0 00 0 0000
Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Ad-
dresses 0x14 and 0x1 6)
Bit # 7 6 5 4 3210
Bit Name Data
Toggle Data
Valid Reserved By te Coun t
Read/Writ
eR/W R/W - - R/
WR/
WR/
WR/
W
Reset 0 0 0 0 0000
Figure 14-4. Endpoint 0,1,2 Counter Registers
(Addresses 0x11, 0x13 and 0x15)
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15.0 USB Regulator Output
The VREG pi n prov ide s a regu lat ed out put for connecting the
pull-up r esistor requir ed for USB operat ion. For USB, a 1 .5-kΩ
resistor is connected between the D– pin and the VREG
voltage, to indicate low-speed USB operation. Since the
VREG output has an internal series resistance of approxi-
mately 200Ω, the external pull-up resistor required is RPU (see
Section 25. 0).
The regulator output is placed in a high-impedance state at
reset, and must be enabled by firmware by setting the VREG
Enable bit in the USB Status and Control Register
(Figure 13-1). This simplifies the design of a combination
PS/2-USB dev ice, since th e USB pull-up resis tor can be lef t in
place during PS/2 operation without loading the PS/2 line. In
this mode, the VREG pin can be used as an input and its state
can be read at port P2.0. Refer to Figure 12-8 for the Port 2
data register. This input has a TTL threshold.
In suspend mode, the regulator is automatically disabled. If
VREG Enable bit is set (Figure 13-1), the VREG pin is pulled
up to VCC with an internal 6.2-kΩ resistor. This holds the
proper VOH state in suspend mode
Note that enabling the device for USB (by setting the Device
Address Enable bit, Figure 14-1) activates the internal
regulator, even if the VREG Enable bit is cleared to 0. This
insures p roper USB sig naling in the case wh ere the VREG pin
is used as an input, and an external regulator is provided for
the USB pull-up resistor. This also limits the swing on the D–
and D+ pins to about 1V above the internal regulator voltage,
so the D evi ce Addre ss Enab le bit no rmally sh ou ld on ly be s et
for USB operating modes.
The regula tor output is only designed to provide current for the
USB pull-up resistor. In addition, the output voltage at the
VREG pin is effectively disconnected when the CY7C637xx
device transmits USB from the internal SIE. This means that
the VREG pin does not provide a stable voltage during
transmits, although this does not affect USB signaling.
16.0 PS/2 Operation
The CY7C637xx parts are optimized for combination USB or
PS/2 devices, through the following features:
1. USB D+ and D– lin es can also be used for PS/2 SCLK and
SDATA pins, respectively. With USB disabled, these lines
can be p laced in a high-imp edance st ate tha t will pull up to
VCC. (Disable USB by clearing the Address Enable bit of
the USB Device Address Register, Figure 14-1).
2. An interrupt is provided to indi cate a long LOW state on the
SDA T A pin. This eliminates the need to poll this pin to check
for PS/2 activity. Refer to Section 21.3 for more details.
3. Internal PS/2 pull-up resistors can be enabled on the SCLK
and SDA T A lines, so no GPIO pins are required for this task
(bit 7, USB Status and Control Register, Figure 13-1).
4. The controlled slew rate outputs from these pins apply to
both USB and PS/2 modes to minimize EMI.
5. The state of the SCLK and SDATA pins can be read, and
can be individually driven LOW in an open drain mode. The
pins are re ad at bit s [5:4 ] of Port 2, and are drive n with the
Control Bits [2:0] of the USB Status and Control Register.
6. The VREG pin can be placed into a high-impedance state,
so that a USB p ull-up resi stor on the D–/SDAT A pin will not
interfere with PS/2 operation (bit 6, USB S tatus and Control
Register).
The PS/2 on- chip support circui try is illustrated in Figure 16-1.
Figure 16-1. Diagram of USB-PS/2 System Connections
D–/SDATA
D+/SCLK
5 kΩ
3.3V
Regulator
5 kΩ
VCC
USB - PS/2
Driver
1.3 kΩ
VREG
VREG Enable
PS/2 Pull-up
Enable
Port 2.0
On-chip Off-chip
Port 2.5
Port 2.4
200Ω
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17.0 Serial Peripheral Interface (SPI )
SPI is a four-wire, full-duplex serial communication interface
betwee n a ma ster de vice a nd one or m ore sl ave de vices . The
CY7C637xx SPI circuit supports byte serial transfers in either
Master or Slave modes. The block diagram of the SPI circuit
is shown in Figure 17-1. The block contains buffers for both
transmit and receive data for maximum flexibility and
throughput. The CY7C637xx can be configured as either an
SPI Master or Slave. The external interface consists of
Master-Out/Slave-In (MOSI), Master-In/Slave-Out (MISO),
Serial Clock (SCK), and Slave Select (SS).
SPI modes are activated by setting the appropriate bits in the
SPI Control Register, as described below.
The SPI Da ta Register below serve s as a transmit a nd receive
buffer.
Bit [7:0]: Dat a I/O[7:0]
Writes to the SPI Data Register load the transmit buffer,
while reads from this register read the receive buffer con-
tents.
1 = Logic HIGH
0 = Logic LOW
17.1 Operation as an SPI Master
Only an SPI Master can initiate a byte/data transfer. This is
done by the Master writing to the SPI Data Register. The
Master sh ift s out 8 bits of data (MSB first) along with the serial
clock SCK for the Slave. The Master’s outgoing byte is
replace d with an inc oming one from a Slave d evice. When th e
last bit is received, the shift register contents are transferred
to the receive buf fer and an interrupt is generated. The receive
data must be read from the SPI Data Register before the next
byte of data is tra nsferre d to the receive buf fer, or the dat a will
be lost.
When op erating as a Master , an active LOW Slave Select (SS)
must be generated to enable a Slave for a byte transfer. This
Slave Select is generated under firmware control, and is not
part of the SPI internal hardware. Any available GPIO can be
used for the Master’s Slave Select output.
When the Master writes to the SPI Data Register, the data is
loaded into the transmit buffer. If the shift register is not busy
shifting a previous byte, the TX buffer contents will be automat-
ically transferred into the shift register and shifting will begin.
If the shi f t regist er is busy, the new by te will be loa ded into th e
shift register only after the active byte has finished and is trans-
ferred to the receive buffer. The new byte will then be shifted
out. The Transmit Buffer Full (TBF) bit will be set HIGH until
the transmit buffer’s data-byte is transferred to the shift
register . Writing to the transmit buffer while the TBF bit is HIGH
will overwrite the old byte in the transmit buffer.
The byte shifting and SCK generation are handled by the
hardware (based on firmware selection of the clock source).
Dat a is sh ifte d out on the MO SI pin (P0. 5) and the serial cloc k
is output on the SCK pin (P0.7). Data is received from the slave
on the MISO pin (P0.6). The output pins must be set to the
desired drive strength , and the GPIO dat a register m ust be set
to 1 to enable a bypass mode for these pins. The MISO pin
must be configured in the desired GPIO input mode. See
Section 12.0 for GPIO configuration details.
17.2 Master SCK Selection
The Master’s SCK is programmable to one of four clock
settings, as shown in Figure 17-1. The frequency is selected
with the Clock Select Bits of the SPI control register. The
8 bit shift register
Data Bus
Data Bus
MOSI
MISO
SCK
SS
Master
/ Slave
Control
Write
Read
4
TX Buffer
RX Buffer
Internal SCK
Figure 17-1. SPI Block Diagram
Bit # 76543210
Bit Name Data I/O
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 17-2 . SPI Data Register (Address 0x6 0)
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hardware provides 8 output clocks on the SCK pin (P0.7) for
eac h byt e trans fer. C lock ph ase and po larit y are sele cted by
the C PH A an d C POL c on t rol bi t s (s ee Figure 17-1 and 17-4).
The master SCK duty cycle is nominally 33% in the fastest (2
Mbps) mode, and 50% in all other modes.
17.3 Operation as an SPI Slave
In slav e mode, the chip receives SCK from an e xternal m aster
on pin P0.7. Dat a from the m aster is shif ted in on the MOSI pi n
(P0.5), wh ile data i s being shift ed out of the slave on the MISO
pin (P0.6). In addition, the active LOW Slave Select must be
asserted to enable the slave for transmit. The Slave Select pin
is P0.4. These pins must be configured in appropriate GPIO
modes, with the GPIO data register set to 1 to enable bypass
mode selected for the MISO pin.
In Slave mode, writes to the SPI Data Register load the
T ransmit buffer. If the Slave Select is asserted (SS LOW) and
the shift register is not busy shifting a previous byte, the
transmit buffer contents will be autom atically transferred into
the shift register. If the shift register is busy, the new byte will
be loaded into the shift register only after the active byte has
finishe d an d is trans ferre d to th e rec eiv e bu f fe r. The new byte
is then rea dy to be shi f ted out (s hi f tin g waits for SCK from the
Master). If the Slave Select is not active when the transmit
buff er is loaded, data is not transferred to the shift register until
Slave Select is asserted. The T ransmit Buf fer Full (TBF) bi t will
be s e t to ‘1’ unt il th e tran smit buffer’s data-byte is transferred
to the s hift regis ter . Writin g to the trans mit buffe r while the TBF
bit is HIGH will overwrite the old byte in the Transmit Buffer.
If the Slave Select is deasserted before a byte transfer is
complete, the transfer is aborted and no interrupt is generated.
Whenever Slave Select is asserted, the transmit buffer is
automat ic all y relo aded into the shif t regi ste r.
Clock phase and polarity must be selected to match the SPI
master, using the CPHA and CPOL control bits (see
Figure 17-3 and Figure 17-4).
The SPI slave logic continues to operate in suspend, so if the
SPI interrupt is enabled, the device can go into suspend during
a SPI slave trans action, and it will wake up at the inte rrupt that
signals the end of the byte transfer.
17.4 SPI Status and Control
The SPI Control Register is shown in Figure 17-3. The timing
diagram in Figure 17-4 shows the clock and data states for the
vario us SPI modes.
Bit 7: TCMP
1 = TCMP is set to 1 by the hardwa re when 8-bit tran sfer is
complete. The SPI interrupt is asserted at the same time
TCMP is set to 1.
0 = This bit is only cleared by firmware.
Bit 6: TBF
Transmit Buffer Full bit.
1 = Indic ates d ata in t he trans mit bu ffe r has n ot trans ferred
to the shift register.
0 = Indicates data in the transmit buffer has transferred to
the shift register.
Bit [5:4] Comm Mode[1:0]
00 = All communications functions disabled (default).
01 = SPI Master Mode.
10 = SPI Slave Mode.
11 = Reserved.
Bit 3: CPOL
SPI Clock Polarity bit.
1 = SCK idles HIGH.
0 = SCK idles LOW.
Bit 2: CPHA
SPI Clock Phase bit (see Figure 17-4)
Bit [1:0]: SCK Select
Master mode SCK frequency selection (no effect in Slave
Mode):
00 = 2 Mbit/s
01 = 1 Mbit/s
10 = 0.5 Mbit/s
11 = 0.0625 Mbit/s
Bit # 76543 210
Bit Name TCMP TBF Comm
Mode[1:0] CPOL CPHA SCK
Select
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000 000
Figure 17-3. SPI Control Register (Address 0x61)
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17.5 SPI Interrupt
For SPI, an interrupt request is generated after a byte is
received or transmitted. See Section 21.3 for details on the SPI
interrupt.
17.6 SPI Modes for GPIO Pins
The GPIO pins used for SPI outputs (P0.5–P0.7) contain a
bypass mode, as shown in the GPIO block diagram
(Figure 12-1). Whenever the SPI block is inactive (Mode[5:4]
= 00), the bypass value is 1, which enables normal GPIO
operatio n. When SPI m aster or slave mode s are activa ted, the
appropriate bypass signals are driven by the hardware for
outputs, and are held at 1 for inputs. Note that the corre-
sponding data bits in the Port 0 Dat a Register must be s et
to 1 for each pin being used for an SPI output. In addition,
the GPIO modes are not affected by operation of the SPI
block, so each pin must be programmed by firmware to the
desired drive strength mode.
For GPIO pins that are not used for SPI outputs, the SPI
bypass value in Figure 12-1 is always 1, for normal GPIO
operation.
MSB LSB
x
SS
SCK (CPOL = 1)
SCK (CPOL = 0)
MOSI/MISO
MSB LSB x
MOSI/MISO
Data Capture Strobe
Data Capture Strobe
Interrupt Iss ue d
Interrupt Iss ue d
CPHA = 1:
CPHA = 0:
Figure 17-4. SPI Data Timing
Table 17-1. SPI Pin Assignments
SPI Function GPIO Pin Comment
Slave Select ( SS) P0.4 For Master Mode, Firmware sets SS , may use any GPIO pin.
For S lave Mode, SS is an active LOW input.
Master Out, Slave In (MOSI) P0.5 Data output for master, data input for slave.
Master In, Slave Out (MISO) P0.6 Data input for master, data output for slave.
SCK P0.7 SPI Clock: Output for master, input for slave.
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18.0 12-bit Free-running Timer
The 12-bit timer operates with a 1-µs tick, provides two inter-
rupts (128-µs and 1.024-ms) and allows the firmware to
directly time events that are up to 4 ms in duration. The lower
eight bits of the timer can be read directly by the firmware.
Reading the lower eight bits latches the upper four bits into a
temporary register. When the firmware reads the upper four
bits of the timer, it is actually reading the count stored in the
temporary register. The effect of this is to ensure a stable 12-bit
timer value can be read, even when the two reads are
separated in time.
Bit [7:0]: Timer lower eight bits
Bit [7:4]: Reserved
Bit [3:0]: Timer upper four bits
Bit # 76543210
Bit Name Timer [7:0]
Read/Write RRRRRRRR
Reset 00000000
Figure 18-1. Timer LSB Register (Address 0x24)
Bit # 76543210
Bit Name Reserved Ti mer [11:8]
Read/Write ----RRRR
Reset 00000000
Figure 18-2. Timer MSB Register (Address 0x25)
Figure 18-3. Timer Block Diagram
10 9 7856432 1 MHz clock
1.024-ms interrupt
128-µs int er ru pt
To Timer Registers
8
1 011
L1 L0L2L3
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
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19.0 Timer Capture Registers
Four 8-bit capture timer registers provide both rising- and
falling-edge event timing capture on two pins. Capture Timer
A is connected to Pin 0.0, and Capture Timer B is connected
to Pin 0.1. These can be used to mark the time at which a rising
or falling event occurs at the two GPIO pins. Each timer will
capture eight bits of the free-running timer into its Capture
Timer Data Register if a rising or falling edge event that
matches the specified rising or falling edge condition at the pin.
A prescaler allows selection of the capture timer tick size.
Interrupts can be individually enabled for the four capture
registers . A block diagra m is sh own in Figure 19-1.
The f our Captu re Timer Dat a R egiste rs are r ead -only, and are
shown in Figure 19-2 through Figure 19-5.
Out of the 12-bit free running timer, the 8-bit captured in the
Capture T imer Dat a Registers are dete rmined by the Pres cale
Bit [2:0] in the Capture Timer Configuration Register
(Figure 19-7).
.
Figure 19-1. Capture Timers Block Diagram
Free-running Timer
GPIO
P0.0
11 10 9 8 7 4 3 2 1 0 1 MHz
Clock
Rising
Edge
Detect
Falling
Edge
Detect
Timer A Rising Edge Time
6 5
Ti mer A Falling Edge Time
Prescaler
GPIO
P0.1
Rising
Edge
Detect
Falling
Edge
Detect
Timer B Rising Edge Time
Ti mer B Falling Edge Time
8-bit Capture Registers
Capture Timer A Interrupt Request
Capture Timer B Interrupt Request
Capture B Falling Int Enable
Capture B Rising Int Enab le
Capture A Falling Int Enable
Capture A Rising Int Enab le
Bit 0, Reg 0x44
Bit 1, Reg 0x44
Bit 2, Reg 0x44
Bit 3, Reg 0x44
First Edge Hold
Bit 7, Reg 0x44
Mux
Bit # 76543210
Bit Name Capture A Rising Data
Read/Write RRRRRRRR
Reset 00000000
Figure 19-2. Capture Timer A-Rising, Data Register
(Address 0x4 0)
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Bit [7:4]: Reserved.
Bit [3:0]: Capture A/B, Falling/Rising Event
These bits record the occurrence of any rising or falling
edges on the capture GPIO pins. Bits in this register are
cleared by reading the corresponding data register.
1 = A rising or falling event that matches the pin’s rising/fall-
ing condition has occurred.
0 = No event that matches the pin’s rising or falling edge
condition.
Because both Capture A events (rising and falling) share
an interrupt, user’s firmware needs to check the status of
both Capture A Falling and Rising Event bits to determine
what caused the interrupt. This is also true for Capture B
events.
Bit 7: First Edge Hold
1 = The time of the first occurre nce of an edge is held in th e
Capture Timer Data Register unti l the data is read. Subs e-
quent ed ges are i gnored unt il the Capture Timer Dat a Reg-
ister is read.
0 = The time of the m ost recent edge is he ld in the C aptu re
Timer Data Register. That is, if multiple edges have oc-
curred before reading the capture timer , the time for the last
one will be read (default state).
The First Edge Hold function applies globally to all f our cap-
ture timers.
Bit [6:4]: Prescale Bit [2:0]
Three pres caler bit s allow the cap ture timer clock rate to be
selected among 5 choices, as shown in Table 19-1 below.
Bit [3:0]: Capture A/B, Rising/Falling Interrupt Enable
Each of the four Capture T imer registers can be indi vidually
enabled to provide interrupts.
Both Capture A events share a common interrupt request,
as do the two Capture B events. In addition to the event
enables , the main Capt ure Inte rrup t En abl es bi t i n th e Gl o-
bal Interrupt Enable register (Section 21.0) must be set to
activate a capture interrupt.
1 = Enable interrupt
0 = Disable interrup t
Bit # 76543210
Bit Name Capture A Falling Data
Read/Write RRRRRRRR
Reset 00000000
Figure 19-3. Capture Timer A-Falling, Data Register
(Address 0x41)
Bit # 76543210
Bit Name Capture B Rising Data
Read/Write RRRRRRRR
Reset 00000000
Figure 19-4. Capture Timer B-Rising, Data Register
(Address 0x42)
Bit # 76543210
Bit Name Capture B Falling Data
Read/Write RRRRRRRR
Reset 00000000
Figure 19-5. Capture Timer B-Falling, Data Register
(Address 0x43)
Bit # 76543210
Bit
Name Reserved Capture
B
Falling
Event
Capture
B
Rising
Event
Capture
A
Falling
Event
Capture
A
Rising
Event
Read/
Write ---- R R R R
Reset 00000000
Figure 19-6. Capture Timer Status Register (Address 0x45)
Bit # 76543210
Bit
Name First
Edge
Hold
Prescale Bit
[2:0] Capture
B
Falling
Int
Enable
Capture
B
Rising
Int
Enable
Capture
A
Falling
Int
Enable
Capture
A
Rising
Int
Enable
Read/
Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 19-7. Capture Timer Configuration Register
(Address 0x44)
Table 19-1. Capture Timer Prescalar Settings (Step size
and range for FCLK = 6 MHz)
Prescale
2:0 Captured Bits
LSB
Step
Size Range
000 Bits 7:0 of free-running timer 1 µs 256 µs
001 Bits 8:1 of free-running timer 2 µs 512 µs
010 Bits 9:2 of free-running timer 4 µs 1.024 ms
011 Bits 10:3 of free-running timer 8 µs 2.048 ms
100 Bits 11:4 of free-running timer 16 µs 4.096 ms
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20.0 Processor Status and Control Register
Bit 7: IRQ Pending
When an interrupt is generated, it is registered as a pending
inter rupt. The interrupt w ill remain pending until i ts in terrupt
enable bit is set (Figure 21-1 and Figure 21-2) and inter-
rupts are globally enabled (Bit 2, Processor Status and
Control Register). At that point the internal interrupt han-
dling sequence will clear the IRQ Pending bit until another
interrupt is detected as pending. This bit is only valid if the
Global Interrupt Enable bit is disabled.
1 = There are pending interrupts.
0 = No pending interrupts.
Bit 6: Watchdog Reset
The Watchdog Timer Reset (WDR) occurs when the inter-
nal Watchdog timer rolls over. The timer will roll over and
WDR will occur if it is not cleared within tWATCH (see Section
26.0 for the value of tWATCH). This bit is cleared by an
LVR/BOR. Note that a Watchdog reset can occur with a
POR/LVR/BOR event, as discussed at the end of this sec-
tion.
1 = A Watchdog reset occurs.
0 = No Watchdog reset
Bit 5: Bus Interrupt Event
The Bus Reset Status is set whenever the event for the
USB Bus Rese t or PS/2 Activity i nterrupt occurs . The event
type (USB or PS/2) is selected by the state of the USB-PS/2
Interrupt Mode bit in the USB Status and Control Register
(see Figure 13-1). The details on the event conditions that
set this bit are gi ven in Se ction 21.3 . In either mode, thi s bit
is set as so on as the ev ent has lasted for 128–256 µs, and
the bit w ill be set even if th e interrupt is no t enabled. The b it
is only cleared by firmware or LVR/WDR.
1 = A U SB res e t o cc u rr e d or P S/ 2 A c t iv ity is de t ec t ed , de -
pending on USB-PS/2 Interrupt Select bit.
0 = No event detected since last cleared by firmware or
LVR/WDR.
Bit 4: LVR/BOR Res et
The Low-voltage or Brown-out Reset is set to ‘1’ during a
power-on reset. Firmware can check bits 4 and 6 in the
reset handler to determine whether a reset was caused by
a L V R/BOR conditio n or a Wat chdog timeou t. This bit is not
affect ed b y W DR. N ot e t h at a LV R/ BO R ev en t ma y b e f ol-
lowed by a W atchdo g reset be fore firmw are begi ns execut-
ing, as explained at the end of this section.
1 = A P OR or LVR has occurred.
0 = No POR nor LVR since this bit last cleared.
Bit 3: Suspend
Writing a '1' to the Suspend bit will halt the processor and
cause the microcontroller to enter the suspend mode that
significantly reduces power consumption. An interrupt or
USB bus activity will cause the device to come out of sus-
pend. Afte r comi ng ou t of sus p en d, t he de vice w ill re su me
firmware execution at the instruction following the IOWR
which put th e part into suspe nd. When writing the suspen d
bit with a resume condition present (such as non-idle USB
activity), the suspend state will still be entered, followed
immediately by the wake-up process (with appropriate de-
lays for the clock start-up). See Section 11.0 for more de-
tails on suspend mode operation.
1 = Suspend the proces sor.
0 = Not in suspend mode. Cleared by the hardware when
resuming from suspend.
Bit 2: Interrupt Enable Sense
This bit shows whether interrupts are enabled or disabled.
Firmware has no direct control over this bit as writing a zero
or one to this bit position will have no effect on interrupts.
This bit is further gated with the bit settings of the Global
Interrupt Enable Register (Figure 21-1) and USB Endpoint
Interrupt Ena ble Register (Figure 21-2). Instructi ons DI, EI,
and RETI manipulate the state of this bit.
1 = Interrupts are enabled.
0 = Interrupts are masked off.
Bit 1: Reserved. Must be written as a 0.
Bit 0: Run
This bit is ma nip ula ted by th e H ALT instructi on. When Halt
is executed, the processor clears the run bit and halts at the
end of the current instruction. The processor remains halt-
ed until a reset occurs (low-voltage, brown-out, or Watch-
dog). This bit should normally be written as a ‘1’.
During power-up, or during a low-voltage reset, the Processor
Status and Control Register is set to 00010001, which
indica tes a L VR/BOR (bit 4 set) has occurred and no interrupt s
are pe nding (bit 7 cl ear). Note that during the tSTART ms partial
suspend at start-up (explained in Section 10.1), a Watchdog
Reset will also occur. When a WDR occurs during the
power-up suspend interval, firmware would read 01010001
from the S tatu s and Con trol Regis ter afte r power-up. No rmally
the LVR/BOR bit should be cleared so that a subsequent WDR
can be clearly identified. Note that if a USB bus reset (long
SE0) is received before firmware examines this register, the
Bus Interrupt Event bit would also be set.
Bit # 76543210
Bit Name IRQ
Pending Watchdog
Reset Bus
Interrupt
Event
LVR/BOR
Reset Suspend Interrupt
Enable
Sense
Reserved Run
Read/Write R R/W R/W R/W R/W R - R/W
Reset 01010001
Figure 20-1. Processor Status and Control Register (Address 0xFF)
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During a Watchdog Reset, the Processor Status and Control
Register is set to 01XX0001, which indicates a Watchdog
Reset (bit 4 set) has occurred and no interrupts are pending
(bit 7 clear).
21.0 Interrupts
Interrupts can be generated by the GPIO lines, the internal
free-running timer, the SPI block, the capture timers, on
various USB events, PS/2 ac tivity, or by the wake-up timer. All
interrupts are maskable by the Global Interrupt Enable
Register and the USB End Point Interrupt Enable Register.
Wri t in g a ‘1’ to a bit position enables the interrupt associated
with that bit position. During a reset, the contents of the
interrupt enable registers are cleared, along with the Global
Interrupt enable bit of the CPU, effectively disabling all inter-
rupts.
The interrupt controller contains a separate flip-flop for each
interrupt. See Figure 21-3 for the logic block diagram of the
interrupt controller. When an interrupt is generated it is first
registered as a pending interrupt. It will stay pending until it is
serviced or a reset occurs. A pending interrupt will only
generate an interrupt request if it is enabled by the corre-
sponding bit in the interrupt enable registers. The highest
priority interrupt request will be serviced following the
completion of the currently executing instruction.
When servicing an interrupt, the hardware will first disable all
interrupts by clearing the Global Interrupt Enable bit in the
CPU (the st a te of this bit can be read at Bit 2 of the Process or
Status and Control Register). Next, the flip-flop of the current
interrupt is cleared. This is followed by an automatic CALL
instruction to the ROM address associated with the interrupt
being serviced (i.e., the Interrupt Vector, see Section 21.1).
The instruction in the interrupt table is typically a JMP
instruction to the address of the Interrupt Service Routine
(ISR). The user can re-enable interrupts in the interrupt service
routine by executing an EI instruction. Interrupts can be nested
to a level limited only by the available stack space.
The Program Counter value as well as the Carry and Zero
flags (CF, ZF) are stored onto the Program Stack by the
automatic CALL instruction generated as part of the interrupt
acknowledge process. The user firmware is responsible for
ensuring that the processor state is preserved and restored
during an interrupt. The PUSH A instruction should typically be
used as the first comm and in th e ISR to save the ac cumu lator
value and the POP A instruction should be used just before the
RETI instruction to restore the accumulator value. The
program counter, CF and ZF are restored and interrupts are
enabled when the RETI instruction is executed.
The DI and EI instructions can be used to disable and enable
interrupts, respectively. These instructions affect only the
Global Interrupt Enable bit of the CPU. If desired, EI can be
used to re-enable interrupts while inside an ISR, instead of
waiting for the RETI that exits the ISR. While the global
interrupt enable bit is cleared, the presence of a pending
interrupt can be detected by e xam in in g th e IRQ Se ns e b it (Bit
7 in the Processor Status and Control Register).
21.1 Interrupt Vectors
The Interrupt Vectors supported by the device are listed in
Table 21-1. The hig hest priority interrupt is #1 (USB Bus Reset
/ PS/2 activity), and the lowest priority interrupt is #11
(Wake-up Timer). Although Reset is not an interrupt, the first
instruction executed after a reset is at ROM address 0x0000,
which corresponds to the first entry in the Interrupt Vector
Table. Interrupt vectors occupy two bytes to allow for a
two-byte JMP instruction to the appropriate Interrupt Service
Routine (ISR).
21.2 Interrupt Latency
Interrupt latency can be calculated from the following
equation:
Interrupt Late ncy = (Number of clock cycles rem aining in th e
current instruction)
+ (10 clock cycles for the CALL
instruction)
+ (5 clock cycles for the JMP instruction)
For exam ple , if a 5 c lo ck cy cl e i ns truc t io n s uch as JC is bein g
executed when an interrupt occurs, the first instruction of the
Interrupt Serv ice Rou tin e will ex ecute a m inimum of 16 cloc ks
(1+10+5) or a maximum of 20 clocks (5+10+5) after the
inte rrupt is issue d. With a 6-MHz e xtern al resona tor, intern al
CPU cloc k speed is 12 MHz, so 20 clocks take 20/12 MHz =
1.67 µs.
Table 21-1. Interrupt Vector Assignments
Interrupt Vec-
tor Number ROM
Address Function
not applicable 0x0000 Execution after Reset begins
here
1 0x0002 USB Bus Reset or PS/2 Activity
interrupt
2 0x0004 128-µs timer interrupt
3 0x0006 1.024-ms timer interrupt
4 0x0008 USB Endpoint 0 int errupt
5 0x000A USB Endpoint 1 interrupt
6 0x00 0C USB Endpoi nt 2 interr upt
7 0x000E SPI Interrupt
8 0x0010 Capture Timer A interrupt
9 0x0012 Capture Timer B interrupt
10 0x0014 GPIO interrupt
11 0x0016 Wake-up Timer interrupt
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21.3 Interrupt Sources
The follo wing sect ion s provi de det ail s on the dif fe rent typ es of
interrupt sources.
Bit 7: Wake-up Interrupt Enable
The internal wake-up timer is normally used to wake the
part from suspend mode, but it can also provide an interrupt
when the part is awake. The wake-up timer is cleared
whene ver the W ake-up I nterrupt Enable bit is written to a 0,
and r uns whenev er that bit is writte n to a 1. W hen the in ter-
rupt is enabled, the wake-up timer provides periodic inter-
rupts at multiples of period, as described in Section 11.2.
1 = Enable wake-up timer for periodic wake-up.
0 = Disable and power-off wake-up timer.
Bit 6: GPIO Interrupt Enable
Each GPIO pin can serve as an interrupt input. During a
reset, GPIO interrupts are disabled by clearing all GPIO
interrupt enable registers. Writing a ‘1’ to a GPIO Interrupt
Enable bit ena bles GPIO interrup ts from the correspon ding
input pin . These registers are sh own in Figure 21-4 for Port
0 and Figure 21-5 for Port 1. In addition to enabling the
desired individual pins for interrupt, the main GPIO interrupt
must be enabled, as explained in Section 21.0.
The pola rity tha t trigge rs an in terrupt i s con trolled indepe n-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers . Se ttin g a Pol ari ty bit to ‘0’ allow s an in terru pt o n
a falli ng GPIO e dge, wh ile s etting a Po larity bit to ‘1’ allo ws
an interrupt on a rising GPIO edge. The Polarity Registers
reset to 0 and are shown in Figure 21-6 for Port 0 and
Figure 21-7 for Port 1.
All of the GPIO pins share a single interrupt vector, which
means the firmware will need to read the GPIO ports with
enabled interrupts to determine which pin or pins caused
an interrupt.The GPIO interrupt structure is illustrated in
Figure 21-8.
Note that if one port pin triggered an interrupt, no other port
pins can cause a GPIO interrupt until that port pin has re-
turned to its inac tive (non-trig ger) state or its co rresponding
port interrupt enable bit is cleared. The CY7C637xx does
not assign interrupt priority to different port pins and the
Port Interrupt Enable Registers are not affected by the in-
terrupt acknowledge process.
1 = Enable
0 = Disable
Bit [5:4]: Capture Timer A and B Interrupts
There are two capture timer interrupts, one for each
assoc iated pin. Eac h of these interrupt s occu rs on an enable d
edge of the selected GPIO pin(s). For each pin, rising and/or
falling edge capture interrupts can be in selected. Refer to
Section 19.0. These interrupts are independent of the GPIO
interrupt, described in the next section.
1 = Enable
0 = Disable
Bit 3: SPI Interrupt Enable
The SPI interrupt occurs at the end of each SPI byte trans-
action, at the final clock edge, as shown in Figure 17-4. Afte r
the interrup t, the received data by te c an be read from the SPI
Data Register, and the TCMP control bit will be high
1 = Enable
0 = Disable
Bit 2: 1.024-ms Interrupt Enable
The 1.024-ms interrupts are periodic timer interrupts from
the free-running timer (based on the 6-MHz clock). The
user sh ould d isabl e this interr upt before going into t he sus -
pend mode to avoid possible conflicts between servicing
the timer interrupts (128-µs interrupt and 1.024-ms inter-
rupt) first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approxi-
mately every 1.024 ms.
0 = Disable.
Bit 1: 128-µs Interrupt Enable
The 128-µs interrupt is another source of timer interrupt
from the free-running timer. The user should disable both
timer interrupts (128-µs and 1.024-ms) before going into
the susp end mode to avoid possi ble co nflic ts b etwee n ser-
vicing the timer interrupts first or the suspend request first
when waking up.
1 = Enable. Periodic interrupts will be generated approxi-
mately every 128 µs.
0 = Disable.
Bit 0: USB Bus Reset - PS/2 Interrupt Enable
The function of this interrupt is selectable between detec-
tion of either a USB bus reset condition, or PS/2 activity.
The selection is made with the USB-PS/2 Interrupt Mode
bit in th e USB S t atus and Control R egister (Figure 13-1). In
either case, the interr upt wi ll occ ur if the se lecte d condi tion
exists for 256 µs, and may occur as early as 128 µs.
Bit # 76543210
Bit Name Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Capture
Ti mer B
Intr. Enable
Capture
Timer A
Intr. Enable
SPI
Interrupt
Enable
1.024-ms
Interrupt
Enable
128-µs
Interrupt
Enable
USB Bus
Reset /
PS/2 Activity
Intr. Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 21-1. Global Interrupt Enable Register (Address 0x20)
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A USB bus reset is ind ic ate d by a si ngl e e nde d z ero (SE0)
on the USB D+ and D– pi ns . The USB Bus R eset in terru pt
occurs when the SE0 condition ends. PS/2 activity is indi-
cated by a continuous LOW on the SDATA pin. The PS/2
interrupt occurs as soon as the long LOW state is detected.
During the entire interval of a USB Bus Res et or PS/2 inter-
rupt event, the USB Device Address register is cleared.
The Bus Reset/PS/2 interrupt may occur 128 µs after the
bus condition is removed.
1 = Enable
0 = Disable
Bit [7:3]: Reserved.
Bit [2:1]: EP2,1 Interrupt Enable
There are two non-control endpoint (EP2 and EP1) inter-
rupts . If en abl ed, a non-control end poi nt in terru pt is gen er-
ated when :
•The USB host writes valid d a ta to an endpoint FIFO.
However, if the endp oint i s in ACK OUT modes, an in-
terr upt is generated regardless of data packet validity
(i.e., good CRC). Firmware must check for data validity.
•The device SIE sends a NAK or ST ALL handshake pack-
et to the U SB host during the host attempt s to read dat a
from the end poi nt (INs).
•The device receives an ACK handshake after a success-
ful read transaction (IN) from the host.
•The device SIE sends a NAK or ST ALL handshake pack-
et to the USB host during the host attempts to write data
(OUTs) to the endpoint FIFO.
1 = Enable
0 = Disable
Refer to Table 22-1 for more information.
Bit 0: EP0 Interrupt Enable
If enabled, a control endpoint interrupt is generated when:
•The endpoint 0 m ode is set to accept a SETUP token.
•After the SIE sends a 0-byte packet in the status stage
of a control transfer.
•The USB host writes valid data to an endpoint FIFO.
However, if the endpoint is in ACK OUT modes, an in-
terrupt is generated regardless of what data is received.
Firmware mu st check for data validity.
•The device SIE sends a NAK or ST ALL handshake pack-
et to the U SB host during the host attempt s to read dat a
from the end poi nt (INs).
•The device SIE sends a NAK or ST ALL handshake pack-
et to the USB host during the host attempts to write data
(OUTs) to the endpoint FIFO.
1 = Enable EP0 interrupt
0 = Disable EP0 interrupt
Bit # 76543 2 1 0
Bit Name Reserved EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
Read/Write ----- R/W R/W R/W
Reset 00000 0 0 0
Figure 21-2. Endpoint Interrupt Enable Register
(Address 0x2 1)
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Bit [7:0]: P0 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
Bit [7:0]: P1 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers. Figure 21-6 and Figure 21-7 control the interrupt
polarity of each GPIO pin.
Bit [7:0]: P0[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Figure 21-3. Interrupt Controller Logic Block Diagram
CLR
Global
Interrupt
Interrupt
Acknowledge
IRQout
USB-PS/2 Clear Interrupt
Interrupt
Priority
Encoder
Enable [0]
DQ
1
Enable
Bit
CLR
USB-PS/2 IRQ
128-µs CLR
128-µs IRQ
1-ms CLR
1-ms IRQ
EP0 IRQ
EP0 CLR
Wake-up IRQ
Vector
Enable [7]
CLK
CLR
DQ
CLK
1
Wake-up CLR
Int
Wake-up
Int
USB-
EP1 IRQ
EP1 CLR
IRQ Pending
IRQ
Controlled by DI, EI, and
RETI Instructions
To CPU
CPU
PS/2
GPIO IR Q
GPIO C LR
EP2 IRQ
EP2 CLR
Capture A IRQ
Capture A CLR
Capture B IRQ
Capture B CLR
(Reg 0x20)
(Reg 0x20)
CLR
Enable [2]
DQ
1
CLK
Int
EP2 (Reg 0x21)
Int Ena ble
Sense
(Bit 7, Reg 0xFF)
(Bit 2, Reg 0xFF)
SPI IRQ
SPI CL R
Bit # 76543210
Bit Name P0 Interrupt Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 21-4. Port 0 Interrupt Enable Register (Address
0x04)
Bit # 76543210
Bit Name P1 Interrupt Enable
Read/Write WWWWWWWW
Reset 00000000
Figure 21-5. Port 1 Interrupt Enable Register
(Address 0x05)
Bit # 76543210
Bit Name P0 Interrupt Polarity
Read/Write WWWWWWWW
Reset 00000000
Figure 21-6. Port 0 Interrupt Polarity Register
(Address 0x0 6)
Bit # 76543210
Bit Name P1 Interrupt Polarity
Read/Write WWWWWWWW
Reset 00000000
Figure 21-7. Port 1 Interrupt Polarity Register
(Address 0x07)
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Bit [7:0]: P1[7:0] Interrupt Polarity
1 = Ri sing GPIO edge
0 = Falling GPIO edge
22.0 USB Mode Tables
The following tables give details on mode setting for the USB
Serial Interface Engine (SIE) for both the control endpoint
(EP0) and non-control endpoints (EP1 and EP2).
Note:
3. STALL bit is the bit 7 of the USB Non-Control Device Endpoint Mode registers. Refer to Section 14.3 for more explanation.
Figure 21-8. GPIO Interrupt Diagram
Port Bit Interrupt OR Gate GPIO Interru pt
Flip Flop
CLR
GPIO
Pin
1 = Enable
0 = Disable Port Bit Interrupt
Enable Register
1 = Enable
0 = Disable
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
DQ
M
U
X
1
(1 input per
GPIO pin)
Global
GPIO Interru pt
Enable
(Bit 6, Register 0x20)
IRA
Polarity Register
Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints
Mode Encoding SETUP IN OUT Comments
Disable 0000 Ignore Ignore Ignore Ignore all USB traffic to this endpoint
NAK IN/OUT 0001 Accept NAK NAK On Control end point , af ter s uccess fully s ending an AC K
handshake to a SETU P packet, the SIE forces the
endpoint mode (from modes other than 0000) to 0001.
The m ode is also changed by the SIE to 0001 f rom mode
1011 on issuance of ACK handshake to an OUT.
Status OUT Only 0010 Accept STALL Chec k For Control endpoints
STALL IN/OUT 0011 Ac cept STA LL STA LL For Control endpoints
Ignore IN/OUT 0100 Accept Igno re Igno re For Control endpoints
Reserved 0101 Ignore Ignore Always Reserved
Status IN O nly 0110 Accept TX 0 Byte STALL For Control Endpoints
Reserved 0111 Ignore TX Count Ignore Reserved
NAK OUT 1000 Ignore Ignore NAK In mode 1001, after sending an ACK handshake to an
OUT, the SIE changes the mode to 1000
ACK OUT(STALL[3]=0)
ACK OUT(STALL[3]=1) 1001
1001 Ignore
Ignore Ignore
Ignore ACK
STALL This mode is changed by the SIE to mode 1000 on
issuance of ACK handshake to an OUT
NAK OUT - S tatus IN 1010 Accept TX 0 Byte NAK
ACK OUT - NAK IN 1011 Accept NAK ACK This mode is changed by the SIE to mode 0001 on
issuance of ACK handshake to an OUT
NAK IN 1100 Ignore NAK Ignore An ACK from mode 1101 changes the mode to 1100
ACK IN(STALL[3]=0)
ACK IN(STALL[3]=1) 1101
1101 Ignore
Ignore TX Count
STALL Ignore
Ignore This mode is changed by the SIE to mode 1100 on
issuance of ACK handshake to an IN
NAK IN - S tatus OUT 1110 Accept NAK Check An ACK from mode 1111 changes the mode to 1110
ACK IN - S tatus OUT 1111 Accept TX Count Check This mode is changed by the SIE to mode 1110 on
issuance of ACK handshake to an IN
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Mode Column:
The ’Mode’ co lumn contains t he mnemonic names given to the
modes of the endpoint. The mode of the endpoint is deter-
mined by the four-bit binaries in the ’Encoding’ column as
discussed below. The Status IN and Status OUT modes
represent the status IN or OUT stage of the control transfer.
Encoding Column:
The contents of the ’Encoding’ column represent the Mode Bits
[3:0] of the Endpoint Mode Registers (Figure 14-2 and
Figure 14-3). The endpoint modes determine how the SIE
responds to different tokens that the host sends to the
endpoints. For example, if the Mode Bits [3:0] of the Endpoint
0 Mo de Regi ster (Figure 14-2) are s et t o ’0001’, whic h is N AK
IN/OUT mode as shown in Table 22-1 above, the SIE of the
part will send an ACK handshake in response to SETUP
tokens and NAK any IN or OUT tokens. For more information
on the functionality of the Serial Interface Engine (SIE), see
Section 13.0.
SETUP, IN, and OUT Columns:
Depending on the mode specified in the ’Encoding’ column,
the ’SETUP’, ’IN’, and ’OUT’ columns contain the device SIE’s
responses when the endpoint receives SETUP, IN, and OUT
tokens respectively.
A ’Check’ in the Out column means that upon receiving an
OUT token the SIE checks to see whether the OUT is of zero
length and has a Data Toggle (Data1/0) of 1. If these condi-
tions are true, the SIE responds with an ACK. If any of the
above c on dit ion s i s n ot m et , the SIE w i ll r espond with ei the r a
STALL or Ignore. Table 22-3 gives a detailed analysis of all
possible cases.
A ’TX Count’ entry in the IN column means that the SIE will
transmit the number of bytes specified in the Byte Count Bit
[3:0] of the Endpoint Count Register (Figure 14-4) in response
to any IN token.
A ’TX 0 Byte’ entry in the IN column means that the SIE will
transmit a zero byte packet in response to any IN sent to the
endpoint. Sending a 0 byte packet is to complete the status
stage of a control transfer.
An ’Ignore’ means that the device sends no handshake tokens.
An ’Accept’ means that the SIE will respond with an ACK to a
valid SETUP transaction.
Comments Column:
Some Mode Bits are automatically changed by the SIE in
response to many USB transa ctions. For example, if the Mode
Bits [3:0] are set to ’1111’ wh ich is A CK IN -Status O UT mode
as shown in Table 22-1, the SIE will change the endpoint Mode
Bits [3:0] to NAK IN-Status OUT mode (1110) after ACKing a
valid status stage OUT token. The firmware needs to update
the mode fo r the SIE to re spond appropriatel y . See Table 22-1
for more details on what modes will be changed by the SIE.
Any SET UP packet t o an enabled endpoint with mod e set to
accept SETUPs will be changed by the SIE to 0001 (NAKing).
Any mode set to accept a SETUP will send an ACK handshake
to a valid SETUP token.
A disabled endpoint will remain disabled until changed by
firmware, and all endpoints reset to the Disabled mo de (0000).
Firmware normally enables the end point mode after a SetCon-
figuration request.
The control endpoint has three status bits for identifying the
token type received (SETUP, IN, or OUT), but the endpoint
must be placed in the correct mode to function as such.
Non-control endpoints should not be placed into modes that
accept SETUPs .
Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions”
Endpoint Mode
Encoding Prope rties of incoming
packet Changes to the internal register made by the SIE as a result of
the incoming token Interrupt?
End Point
Mode
3 2 1 0 Token count buffer dval DTOG DVAL COUNT Setup In Out ACK 3 2 1 0 Response Int
Bit[3:0], Figure 14-4 SIE’s Response
Data Valid (Bit 6, Figure 14-4) Endpoint Mode changed
by the SIE.
Data 0/1 (Bit 7, Figure 14-4)
Received Token
(SETUP, IN,OUT)
The validity of the received data Acknowledge transaction completed
(Bit4,Figure 14-2/3)
The quality status of the DMA buffer PID Status Bits
(Bit[7:5], Figure 14-2)
The number of received bytes
Legend: UC: unchanged TX: transmit TX0: transmit 0-length packet
x: don’t care RX: receive
available for Cont rol endpo i nt only
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The response of the SIE can be summarized as follows:
1. The SIE will only respond to valid transactions, and will ig-
nore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction
is completed or when the FIFO is corrupted. FIFO
corrupti on occurs durin g an OUT or SETUP transaction to
a valid internal address, that ends with a non-valid CRC.
3. An incom ing Dat a pa cket is valid if the coun t is < End point
Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an O UT configured endpoi nt and
visa versa.
5. The IN and OUT PID status is updated at the end of a
transaction.
6. The SETUP PID status is updated at the beginning of the
Data packet phase.
7. The entire Endpoint 0 mode register and the Count register
are locked to CPU writes at the end of any transaction to
that endpoint in which an ACK is transferred. These
registers are only unlocked by a CPU read of these
registers, and only if that read happens after the transaction
completes. This represents about a 1-µs window in which
the CPU is locked from register writes to these USB
registers . Norm al ly the firmw are sho uld perf orm a reg is ter
read at th e beginn ing of the Endpoint ISRs to unlo c k and
get the mode register information. The interlock on the
Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might have made
during the previous transaction.
Table 22-3. Details of Modes for Differing Traffic Conditions
End Point Mode PID Set End Point Mode
3210
Rcved
Token Count Buffer Dval DTOG DVAL COUNT SETUP IN OUT ACK 3 2 1 0 Response Int
SETUP Packet (if accepting)
See22-1 SETUP <= 10 data valid updates 1 updates 1 UC UC 1 0 0 0 1 ACK yes
See22-1 SETUP > 10 junk x updates updates updates 1 UC UC UC NoChange Ignore yes
See 22-1 SETUP x junk invalid updates 0 updates 1 UC UC UC NoChange Ignore yes
Disabled
0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange Ignore no
NAK IN/OUT
0 0 0 1 OUT x UC x UC UC UC UC UC 1 UC NoChange NAK yes
0 0 0 1 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 0 0 1 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 0 0 1 IN x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Ignore IN/OUT
0 1 0 0 OUT x UC x UC UC UC UC UC UC UC NoChange Ignore no
0 1 0 0 IN x UC x UC UC UC UC UC UC UC NoChange Ignore no
STALL IN/OUT
0 0 1 1 OUT x UC x UC UC UC UC UC 1 UC NoChange STALL yes
0 0 1 1 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 0 1 1 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 0 1 1 IN x UC x UC UC UC UC 1 UC UC NoChange STALL yes
Control Write
ACK OUT/NAK IN
1 0 1 1 OUT <= 10 data valid updates 1 updates UC UC 1 1 0 0 0 1 ACK yes
1 0 1 1 OUT > 10 junk x updates updates updates UC UC 1 UC NoChange Ignore yes
1 0 1 1 OUT x junk invalid updates 0 updates UC UC 1 UC NoChange Ignore yes
1 0 1 1 IN x UC x UC UC UC UC 1 UC UC NoChange NAK yes
NAK OUT/Status IN
1 0 1 0 OUT <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 1 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
1 0 1 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
1 0 1 0 IN x UC x UC UC UC UC 1 UC 1 NoChange TX 0 Byte yes
Status IN Only
0 1 1 0 OUT <= 10 UC valid UC UC UC UC UC 1 UC 0 0 1 1 STALL yes
0 1 1 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 1 1 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 1 1 0 IN x UC x UC UC UC UC 1 UC 1 NoChange TX 0 Byte yes
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Control Read
ACK IN/Status OUT
1 1 1 1 OUT 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 1 OUT 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 STALL yes
1 1 1 1 OUT !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 STALL yes
1 1 1 1 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
1 1 1 1 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
1 1 1 1 IN x UC x UC UC UC UC 1 UC 1 1 1 1 0 ACK (back) yes
NAK IN/Status OUT
1 1 1 0 OUT 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
1 1 1 0 OUT 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 STALL yes
3 2 1 0 token count buffer dval DTOG DVAL COUNT SETUP IN OUT ACK 3 2 1 0 response int
1 1 1 0 OUT !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 STALL yes
1 1 1 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
1 1 1 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
1 1 1 0 IN x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Status OUT Only
0 0 1 0 OUT 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes
0 0 1 0 OUT 2 UC valid 0 1 updates UC UC 1 UC 0 0 1 1 STALL yes
0 0 1 0 OUT !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 STALL yes
0 0 1 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 0 1 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 0 1 0 IN x UC x UC UC UC UC 1 UC UC 0 0 1 1 STALL yes
OUT Endpoint
ACK OUT, STALL Bit = 0 (Figure 14-3)
1 0 0 1 OUT <= 10 data valid updates 1 updates UC UC 1 1 1 0 0 0 ACK yes
1 0 0 1 OUT > 10 junk x updates updates updates UC UC 1 UC NoChange Ignore yes
1 0 0 1 OUT x junk invalid updates 0 updates UC UC 1 UC NoChange Ignore yes
1 0 0 1 IN x UC x UC UC UC UC UC UC UC NoChange Ignore no
ACK OUT, STALL Bit = 1 (Figure 14-3)
1 0 0 1 OUT <= 10 UC valid UC UC UC UC UC 1 UC NoChange STALL yes
1 0 0 1 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
1 0 0 1 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
1 0 0 1 IN x UC x UC UC UC UC UC UC UC NoChange Ignore no
NAK OUT
1 0 0 0 OUT <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 0 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
1 0 0 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
1 0 0 0 IN x UC x UC UC UC UC UC UC UC NoChange Ignore no
Reserved
0 1 0 1 OUT x updates updates updates updates updates UC UC 1 1 NoChange RX yes
0 1 0 1 IN x UC x UC UC UC UC UC UC UC NoChange Ignore no
IN Endpoint
ACK IN, STALL Bit = 0 (Figure 14-3)
1 1 0 1 OUT x UC x UC UC UC UC UC UC UC NoChange Ignore no
1 1 0 1 IN x UC x UC UC UC UC 1 UC 1 1 1 0 0 ACK (back) yes
ACK IN, STALL Bit = 1 (Figure 14-3)
1 1 0 1 OUT x UC x UC UC UC UC UC UC UC NoChange Ignore no
1 1 0 1 IN x UC x UC UC UC UC 1 UC UC NoChange STALL yes
NAK IN
Table 22-3. Details of Modes for Differing Traffic Conditions (continued)
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1 1 0 0 OUT x UC x UC UC UC UC UC UC UC NoChange Ignore no
1 1 0 0 IN x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Reserved
0 1 1 1 Out x UC x UC UC UC UC UC UC UC NoChange Ignore no
0 1 1 1 IN x UC x UC UC UC UC 1 UC UC NoChange TX yes
Table 22-3. Details of Modes for Differing Traffic Conditions (continued)
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23.0 Register Summary
Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/
Both/ Default/
Reset
GPIO CONFIGURATION PORTS 0, 1 AND 2
0x00 Port 0 Data P0 BBBBBBBB 00000000
0x01 Port 1 Data P1 BBBBBBBB 00000000
0x02 Port 2 Data Reserved D+( SCL K)
State D- (SDATA )
State Reserved P2.1 (Int Clk
Mode Only VREG Pin
State --RR--RR 00000000
0x0A GPIO Port 0 Mode 0 P0[7:0] Mode0 WWWWWWWW 00000000
0x0B GPIO Port 0 Mode 1 P0[7:0] Mode1 WWWWWWWW 00000000
0x0C GPIO Port 1 Mode 0 P1[7:0] Mode0 WWWWWWWW 00000000
0x0D GPIO Port 1 Mode 1 P1[7:0] Mode1 WWWWWWWW 00000000
0x04 Port 0 Interrupt Enable P0[7:0] In terrupt Enable WWWWWWWW 00000000
0x05 Port 1 Interrupt Enable P1[7:0] In terrupt Enable WWWWWWWW 00000000
0x06 Port 0 Interrupt Polarity P0[7:0] Interrupt Polarity WWWWWWWW 00000000
0x07 Port 1 Interrupt Polarity P1[7:0] Interrupt Polarity WWWWWWWW 00000000
Clock
Config.
0xF8 Clock Configuration Ext. Clock
Resume
Delay
Wake-up Timer Adjust Bit [2:0] Low-voltage
Reset
Disable
Precision
USB
Clocking
Enable
Internal
Clock
Output
Disable
External
Oscillator
Enable
BBBBBBBB 00000000
ENDPOINT 0, I AND 2
CONFIGURATION
0x10 USB Device Address Device
Address
Enable
Device Address BBBBBBBB 00000000
0x12 EP0 Mode SETUP
Received IN
Received OUT
Received ACKed
Transaction Mode Bit BBBBBBBB 00000000
0x14,
0x16 EP1, EP2 Mode Register STALL Reserved ACKed
Transaction Mode Bit B--BBBBB 00000000
0x1 1,
0x13, and
0x15
EP0,1, and 2 Counter Data 0/1
Toggle Data Valid Reserve d Byte Count BB--BBBB 00000000
USB-
SC
0x1F USB Status and Control PS/2 Pull-up
Enable VREG
Enable USB
Reset-PS/2
Activity
Interrupt
Mode
Reserved USB Bus
Activity D+/D- Forcing Bit BBB-BBBB 00000000
INTERRUPT
0x20 Global Interrupt Enable Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Capture
Timer B Intr.
Enable
Capture
T i mer A Intr.
Enable
SPI
Interrupt
Enable
1.024 ms
Interrupt
Enable
128 µs
Interrupt
Enable
USB Bus
Reset-PS/2
Activity Intr.
Enable
BBBBBBBB 00000000
0x21 Endpoint Interrupt Enable Reserved EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
-----BBB 00000000
TIMER
0x24 Timer LSB Timer Bit [7:0] RRRRRRRR 00000000
0x25 Timer (MSB) Reserved Timer Bit [11:8] ----RRRR 00000000
SPI
0x60 SPI Data Data I/O BBBBBBBB 00000000
0x61 SPI Control TCMP TBF Comm Mode [1:0] CPOL CPHA SCK Select BBBBBBBB 00000000
CAPTURE TIMER
0x40 Capture Timer A-Rising,
Data Register Capture A Rising Data RRRRRRRR 00000000
0x41 Capture Timer A-Falling,
Data Register Capture A Falling Data RRRRRRRR 00000000
0x42 Capture Timer B-Rising,
Data Register Capture B Rising Data RRRRRRRR 00000000
0x43 Capture Timer B-Falling,
Data Register Capture B Falling Data RRRRRRRR 00000000
0x44 Capture Timer
Configuration First Edge
Hold Prescale Bit [2:0] Capture B
Falling Intr
Enable
Capture B
Rising Intr
Enable
Capture A
Falling Intr
Enable
Capture A
Rising Intr
Enable
BBBBBBBB 00000000
0x45 Capture Timer Status Reserved Capture B
Falling
Event
Capture B
Rising Event Capture A
Falling
Event
Capture A
Rising Event ----BBBB 00000000
PROC
SC.
0xFF Process Status & Control IRQ
Pending Watch Dog
Reset Bus
Interrupt
Event
LVR/BOR
Reset Suspend Interrupt
Enable
Sense
Reserved Run RBBBBR-BSee
Section
20.0
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24.0 Absolute Maximum Ratings
Storage Temperature ..........................................................................................................................................–65°C to +150°C
Ambient Temperature with Power Applied...............................................................................................................–0°C to +70°C
Supply Voltage on VCC Relative to VSS ..................................................................................................................–0.5V to +7.0V
DC Input Voltage........................................................................................................................................... –0.5V to +VCC+0.5V
DC Voltage Applied to Outputs in High Z State............................................................................................ –0.5V to + VCC+0.5V
Maximum Total Sink Output Current into Port 0 and 1 and Pins.......................................................................................... 70 mA
Maximum Total Source Output Current into Port 0 and 1 and Pins..................................................................................... 30 mA
Maximum On-chip Power Dissipation on any GPIO Pin......................................................................................................50 mW
Power Dissipation..............................................................................................................................................................300 mW
Static Discharge Voltage .................................................................................................................................................. > 2000V
Latch-up Current ........................................................................................................................................................... > 200 mA
25.0 DC Characteristics FOSC = 6 MHz; Operating Temperature = 0 to 70 °C
Parameter Conditions Min. Max. Unit
General
VCC1 Operating Voltage Note 4 VLVR 5.5 V
VCC2 Operating Voltage Note 4 4.35 5.25 V
ICC1 VCC Operating Supply Current – Internal
Oscillator Mode
Typical ICC1 = 16 mA[5]
VCC = 5.5V, no GPIO loading
VCC = 5.0V. T = Room Temperature
20 mA
ICC2 VCC Operating Supply Current – External
Oscillator Mode
Typical ICC2= 13 mA[5]
VCC = 5.5V, no GPIO loading
VCC = 5.0V. T = Room Temperature
17 mA
ISB1 Standby Current – No Wake-up Osc Oscillator off, D– > 2.7V 25 µA
ISB2 Standby Current – With Wake-up Osc Oscillator off, D– > 2.7V 75 µA
VPP Programming Voltage (disabled) –0.4 0.4 V
TRSNTR Resonator Start-up Interval VCC = 5.0V, ceramic resonator 256 µs
IIL Input Leakage Current Any I/O pin 1 µA
ISNK Max ISS GPIO Sink Current Cumulative across all ports[6] 70 mA
ISRC Max ICC GPIO Source Current Cumulative across all ports[6] 30 mA
Low-Voltage and Power-on Reset
VLVR Low-Voltage Reset Trip Voltage VCC below VLVR for >100 ns[7] 3.5 4.0 V
tVCCS VCC Power-on Slew Time linear ramp: 0 to 4V[8] 100 ms
USB Interface
VREG VREG Regulator Output Voltage Load = RPU +RPD[9, 10] 3.0 3.6 V
CREG Capacitance on VREG Pin External cap not required 300 pF
VOHU Static Output High, driven RPD to Gnd[4] 2.8 3.6 V
Notes:
4. Full functionality is guaranteed in VCC1 range, except USB transmitter specifications and GPIO output currents are guaranteed for VCC2 range.
5. Bench measurements taken under nominal operating conditions. Spec cannot be guaranteed at final test.
6. Total current cumulative across all Port pins, limited to minimize Power and Ground-Drop noise effects.
7. LVR is auto ma tic ally disab led dur i ng susp end mode .
8. LVR will re-occur whenever VCC drops below VLVR. In suspend or with LVR di sabled, BOR occurs whenever VCC drops below approximately 2.5V.
9. VREG specified for regulator enabled, idle conditions (i.e., no USB traffic), with load resistors listed. During USB transmits from the internal SIE, the VREG
output is not regulated, and should not be used as a general source of regulated voltage in that case. During receive of USB data, the VREG output drops
when D– is LOW due to internal series resistance of approximately 200Ω at the VREG pin.
10. In suspend mode, VREG is only valid if RPU is connected fro m D– to VREG pin, and RPD is connected from D– to ground.
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Note:
11. The 200Ω internal resistance at the VREG pin gives a standard USB pull-up using this value. Alternately , a 1.5 kΩ,5%pull-up from D– to an external 3.3V supply
can be used .
VOLU Static Output Low With RPU to VREG pin 0.3 V
VOHZ Static Output High, idle or suspend RPD connected D– to Gnd, RPU
connected D– to VREG pin[4] 2.7 3.6 V
VDI Differential Input Sensitivity |(D+)–(D–)| 0.2 V
VCM Differential Input Common Mode Range 0.8 2.5 V
VSE Single Ended Receiver Threshold 0.8 2.0 V
CIN Transceiver Capacitance 20 pF
ILO Hi-Z State Data Line Leakage 0 V < Vin<3.3 V (D+ or D– pins) –10 10 µA
RPU External Bus Pull-up resistance (D–) 1.3 kΩ ±2% to VREG[11] 1.274 1.326 kΩ
RPD External Bus Pull-down resistance 15 kΩ ±5 % to Gnd 14.25 15.75 kΩ
PS/2 Interface
VOLP Static Output Low Isink = 5 mA, SDATA or SCLK pins 0.4 V
RPS2 Internal PS/2 Pull-up Resistance SDATA, SCLK pins, PS/2 Enabled 3 7 kΩ
General Purpose I/O Interface
RUP Pull-up Resistance 8 24 kΩ
VICR Input Threshold Voltage, CMOS mode Low to high edge, Port 0 or 1 40% 60% VCC
VICF Input Threshold Voltage, CMOS mode High to low edge, Port 0 or 1 35% 55% VCC
VHC Input Hysteresis Voltage, CMOS mode High to low edge, Port 0 or 1 3% 10% VCC
VITTL Input Threshold Voltage, TTL mode Ports 0, 1, and 2 0.8 2.0 V
VOL1A
VOL1B Output Low Voltage, high drive mode IOL1 = 50 mA, Ports 0 or 1[4]
IOL1 = 25 mA, Ports 0 or 1[4] 0.8
0.4 V
V
VOL2 Output Low Voltage, medium drive mode IOL2 = 8 mA, Ports 0 or 1[4] 0.4 V
VOL3 Output Low Voltage, low drive mode IOL3 = 2 mA, Ports 0 or 1[4] 0.4 V
VOH Output High Voltage, strong drive mode Port 0 or 1, IOH = 2 mA[4] VCC–2V
RXIN Pull-down resistance, XTALIN pin Internal Clock Mode only 50 kΩ
25.0 DC Characteristics FOSC = 6 MHz; Operating Temperature = 0 to 70 °C (continued)
Parameter Conditions Min. Max. Unit
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Document #: 38-08022 Rev. *B Page 40 of 49
26.0 Switching Characteristics
Parameter Description Conditions Min. Max. Unit
Internal Clock Mode
FICLK Internal Clock Frequency Internal Clock Mode enabled 5.7 6.3 MHz
FICLK2 Internal Clock Frequency, USB
mode I nte rnal Cloc k Mo de e nabled, Bit 2 of regi ste r
0xF8 h is set (Precision USB Clocking)[12] 5.91 6.09 MHz
External Oscillator Mode
TCYC Input Clock Cycle Time USB Operation, with External ±1.5%
Ceramic Resonator or Crystal 164.2 169.2 ns
TCH Clock HIGH Time 0.45 tCYC ns
TCL Clock LOW Time 0.45 tCYC ns
Reset Timing
tSTART Time-out Delay after LVR/BOR 24 60 ms
tWAKE Internal Wake-up Period Enabled Wake-up Interrupt[13] 15ms
tWATCH WatchDog Timer Period FOSC = 6 MHz 10.1 14.6 ms
USB Driver Characteristics
TRTransition Rise Time CLoad = 200 pF (10% to 90%[4])75 ns
TRTransition Rise Time CLoad = 600 pF (10% to 90%[4])300ns
TFTransition Fall Time CLoad = 200 pF (10% to 90%[4])75 ns
TFTransition Fall Time CLoad = 600 pF (10% to 90%[4])300ns
TRFM Rise/Fall Time Matching tr/tf[4, 14] 80 125 %
VCRS Output Signal Crossover
Voltage[18] CLoad = 200 to 600 pF[4] 1.3 2.0 V
USB Data Timing
TDRATE Low Speed Data Rate Ave. Bit Rate (1.5 Mb/s ±1.5%) 1.4775 1.5225 Mb/s
TDJR1 Receiver Data Jitter Tolerance To Next Transition[15] –75 75 ns
TDJR2 Receiver Data Jitter Tolerance For Paire d Transitions[15] –45 45 ns
TDEOP Differential to EOP transition Sk ew Note 15 –40 100 ns
TEOPR2 EOP Width at Receiver Accepts as EOP[15] 670 ns
TEOPT Source EOP Width 1.25 1.50 µs
TUDJ1 Differential Driver Jitter To next transition, Figure 26-5 –95 95 ns
TUDJ2 Differential Driver Jitter To paired transition, Figure 26-5 –150 150 ns
TLST Wid th of SE0 during Diff . Transition 210 ns
Non-USB Mode Driver
Characteristics Note 16
TFPS2 SDATA/SCK Transition Fall Time CLoad = 150 pF to 600 pF 50 300 ns
SPI Timing See Figures 26-6 to 26-9[17]
TSMCK SPI Master Cloc k Rate FCLK/3; see Figure 17-1 2MHz
TSSCK SPI Slave Clock Rate 2.2 MHz
Notes:
12. Initially FICLK2 = FICLK until a USB packet is received.
13. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)
14. Tested at 200 pF.
15. Measured at cross-over point of differential data signals.
16. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.
17. SPI timing specified for capacitive load of 50 pF, with GPIO output mode = 01 (medium low drive, strong high drive).
18. Per the USB 2.0 Specification, Table 7.7, Note 10, the first transition from the Idle state is excluded.
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Document #: 38-08022 Rev. *B Page 41 of 49
TSCKH SPI Clock High Time High for CPOL = 0, Low for CPOL = 1 125 ns
TSCKL SPI Clock Low Time Low for CPOL = 0, High for CPOL = 1 125 ns
TMDO Master Data Output Time SCK to data valid –25 50 ns
TMDO1 Master Data Output Time,
First bit with CPHA = 1 Time before leading SCK edge 100 ns
TMSU Master Input Data Set-up time 50 ns
TMHD Master Input Data Hold time 50 ns
TSSU Slave Input Data Set-up Time 50 ns
TSHD Slav e Input Data Hold Time 50 ns
TSDO Slav e Data Ou tput Time SCK to data valid 100 ns
TSDO1 Slave Data Output Time,
First bit with CPHA = 1 Time after SS LOW to data valid 100 ns
TSSS Slave Select Set-up Time Before first SCK edge 150 ns
TSSH Slave Select Hold Time After last SCK edge 150 ns
26.0 Switching Characteristics (continued)
Parameter Description Conditions Min. Max. Unit
Figure 26-1. Clock Timing
Figure 26-2. USB Data Signal Timing
CLOCK
TCYC
TCL
TCH
90%
10%
90%
10%
D−
D+TRTF
Vcrs
Voh
Vol
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Document #: 38-08022 Rev. *B Page 42 of 49
Figure 26-3. Receiver Jitter Tolerance
Figure 26-4. Differential to EOP Transition Skew and EOP Width
Figure 26-5. Differential Data Jitter
Differential
Data Lines
Paired
Transitions
N * TPERIOD + TJR2
TPERIOD
Consecutive
Transitions
N * TPERIOD + TJR1
TJR TJR1 TJR2
TPERIOD
Differential
Data Lines
Crossover
Point
Crossover
Point E xtended
Source EOP Width: TEOPT
Receiver EOP Width: TEOPR1, TEOPR2
Diff. Data to
SE0 Skew
N * TPERIOD + TDEOP
TPERIOD
Differential
Data Lines
Crossover
Points
Paired
Transitions
N * TPERIOD + TxJR2
Consecutive
Transitions
N * TPERIOD + TxJR1
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Document #: 38-08022 Rev. *B Page 43 of 49
Figure 26-6. SPI Master Timing, CPHA = 0
MSB
TMSU
LSB
TMHD
TSCKH
TMDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
TSCKL
MSB LSB
MSB
TSSU
LSB
TSHD
TSCKH
TSDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
TSCKL
TSSS TSSH
MSB LSB
Figure 26-7. SPI Slave Timing, CPHA = 0
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Document #: 38-08022 Rev. *B Page 44 of 49
MSB
TMSU
LSB
TMHD
TSCKH
TMDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
TSCKL
TMDO
LSBMSB
Figure 26-8. SPI Master Timing, CPHA = 1
MSB
TSSU
LSB
TSHD
TSCKH
TSDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
TSCKL
TSDO
LSBMSB
TSSS TSSH
Figure 26-9. SPI Slave Timing, CPHA = 1
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Document #: 38-08022 Rev. *B Page 45 of 49
27.0 Ordering Information
Ordering Code EPROM
Size Package
Name Package Type Operating
Range
CY7C63723-PC 8 KB P3 18-Pin (300-Mil) PDIP Commercial
CY7C63723-PXC 8 KB P3 18-Pin (300-Mil) Lead-free PDIP Commercial
CY7C63723-SC 8 KB S3 18-Pin Small Outline Package Commercial
CY7C63723-SXC 8 KB S3 18-Pin Small Outline Lead-free Package Commercial
CY7C63743-QXC 8 KB Q13 24 QSOP Lead-free Package Commercial
CY7C63743-PC 8 KB P13 24-Pin (300-Mil) PDIP Commercial
CY7C63743-PXC 8 KB P13 24-Pin (300-Mil) Lead-free PDIP Commercial
CY7C63743-SC 8 KB S13 24-Pin Small Outline Package Commercial
CY7C63743-SXC 8 KB S13 24-Pin Small Outline Lead-free Package Commercial
CY7C63722-XC 8 KB –25-Pad DIE Form Commercial
CY7C63722-XWC 8 KB –25-Pad DIE Form Lead-free Commercial
28.0 Package Diagrams
51-85010-*A
18-Lead (300-Mil) Molded DIP P3
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Document #: 38-08022 Rev. *B Page 46 of 49
28.0 Package Diagrams (continued)
51-85023-A
PIN 1 ID
SEATING PLANE
0.447[11.353]
0.463[11.760]
18 Lead (300 Mil) SOIC - S3
19
10 18
*
*
*
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.291[7.391]
0.300[7.620]
0.394[10.007]
0.419[10.642]
0.050[1.270]
TYP.
0.092[2.336]
0.105[2.667]
0.004[0.101]
0.0118[0.299]
0.0091[0.231]
0.0125[0.317]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S18.3 STANDARD PKG.
SZ18.3 LEAD FREE PKG.
18-Lead (300-Mil) Molded SOIC S3
51-85023-*B
PIN 1 ID
SEATING PLANE
0.597[15.163]
0.615[15.621]
112
13 24
*
*
*
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.291[7.391]
0.300[7.620]
0.394[10.007]
0.419[10.642]
0.050[1.270]
TYP.
0.092[2.336]
0.105[2.667]
0.004[0.101]
0.0118[0.299]
0.0091[0.231]
0.0125[0.317]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S24.3 STANDARD PKG.
SZ24.3 LEAD FREE PKG.
PACKAGE WEIGHT 0.65gms
51-85025-*B
24-Lead (300-Mil) SOIC S13
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Document #: 38-08022 Rev. *B Page 47 of 49
28.0 Package Diagrams (continued)
24-Lead Quarter Size Outline Q13
51-85055-*B
51-85013-*B
24-Lead (300-Mil) PDIP P13
CY7C63722
CY7C63723
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Document #: 38-08022 Rev. *B Page 48 of 49
© Cypress Semiconducto r Corpor ati on, 2004. The informat i on cont ained her ein i s subject to change with out notice. Cy press Sem iconducto r Corporation assum es no respo nsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to res
ult in significant injury to the user. The inclusion of Cypress
Table 28-1 below shows the die pad coordinates for the
CY7C63722-XC. The center location of each bond pad is
relative to the bottom left corner of the die which has
coordinate (0,0).
enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
28.0 Package Diagrams (continued)
DIE FORM
4
5
6
7
8
9
3
24
23
22
21
20
19
18
11
12
13
14
15
16
17
10
2
1
25
(1907, 3001)
(0,0)
Y
X
Die Step: 1907 x 3011 microns
Die Size: 1830.8 x 2909 microns
Die Thickness: 14 mils = 355.6 microns
Pad Size: 80 x 80 microns
Cypress Logo
Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers)
Pad Number Pin Name X
(microns) Y
(microns)
1 P0.0 788.95 2843.15
2 P0.1 597.45 2843.15
3 P0.2 406.00 2843.15
4 P0.3 154.95 2687.95
5 P1.0 154.95 2496.45
6 P1.2 154.95 2305.05
7 P1.4 154.95 2113.60
8 P1.6 154.95 1922.05
9 Vss 154.95 1730.90
10 Vss 154.95 312.50
11 Vpp 363.90 184.85
12 VREG 531.70 184.85
13 XTALIN 1066.55 184.85
14 XTALOUT 1210.75 184.85
15 Vcc 1449.75 184.85
16 D–1662.35 184.85
17 D+ 1735.35 289.85
18 P1.7 1752.05 1832.75
19 P1.5 1752.05 2024.30
20 P1.3 1752.05 2215.75
21 P1.1 1752.05 2407.15
22 P0.7 1752.05 2598.65
23 P0.6 1393.25 2843.15
24 P0.5 1171.80 2843.15
25 P0.4 980.35 2843.15
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Document #: 38-08022 Rev. *B Page 49 of 49
Document History Page
Document Title: CY7C63722, CY7C63723, CY7C63743 enCoRe™ USB Combination Low-Speed USB
and PS/2 Peripheral Controller
Document Numbe r: 38-080 22
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 118643 10/22/02 BON Converted from Spec 38-00944 to Spec 38-08022.
Added notes 17, 18 to section 26
Removed obs ol ete p arts (6372 2-PC and 637 42)
Added di e sale
Added section 23 (Registe r Summary)
*A 243308 SEE ECN KKU Added 24 QSOP package
Added Lead-free packages to section 27
Reformatted to update format
*B 267229 See ECN ARI Corrected part number in the Ordering In formation section
