LO1
LM25119
HO1
CS1
PGND1
UVLO
VIN
VCC1
HB1
SW1
CSG1
RAMP1
FB1
COMP1
VIN
VIN
AGND SS1 RT SS2 RES
LO2
HO2
CS2
PGND2
VCC2
HB2
SW2
CSG2
RAMP2
FB2
COMP2
VOUT1 VOUT2
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Design
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25119
SNVS680I AUGUST 2010REVISED APRIL 2018
LM25119 Wide Input Range, Dual Synchronous Buck Controller
1
1 Features
1 Emulated Peak Current Mode Control
Wide Operating Range (4.5 V to 42 V)
Easily Configurable for Dual Outputs or
Interleaved Single Output
Robust 3.3-A Peak Gate Drive
Switching Frequency Programmable to 750 kHz
Optional Diode Emulation Mode
Programmable Output From 0.8 V
Precision 1.5% Voltage Reference
Programmable Current Limit
Hiccup Mode Overload Protection
Programmable Soft-Start
Programmable Line Undervoltage Lockout
Automatic Switchover to External Bias Supply
Channel2 Enable Logic Input
Thermal Shutdown
Leadless 32-Pin WQFN Package
2 Applications
Industrial DC-DC Motor Drivers
Telecom Servers and Routers
3 Description
The LM25119 device is a dual synchronous buck
controller intended for step-down regulator
applications from a high voltage or widely varying
input supply. The control method is based upon
current mode control using an emulated current ramp.
Current mode control provides inherent line
feedforward, cycle-by-cycle current limiting and ease-
of-loop compensation. The use of an emulated
control ramp reduces noise sensitivity of the pulse-
width modulation circuit, allowing reliable control of
very small duty cycles necessary in high input voltage
applications. The switching frequency is
programmable from 50 kHz to 750 kHz. The
LM25119 device drives external high-side and low-
side N-channel MOS power switches with adaptive
dead-time control. A user-selectable diode emulation
mode enables discontinuous mode operation for
improved efficiency at light load conditions. A high
voltage bias regulator with automatic switch-over to
external bias further improves efficiency. Additional
features include thermal shutdown, frequency
synchronization, cycle-by-cycle and hiccup mode
current limit and adjustable line undervoltage lockout.
The device is available in a power enhanced leadless
32-pin WQFN package featuring an exposed die
attach pad to aid thermal dissipation.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM25119 WQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 8
6.7 Typical Characteristics.............................................. 9
7 Detailed Description............................................ 11
7.1 Overview................................................................. 11
7.2 Functional Block Diagram....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 18
8 Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 35
10 Layout................................................................... 35
10.1 Layout Guidelines ................................................. 35
10.2 Layout Example .................................................... 36
11 Device and Documentation Support................. 37
11.1 Community Resources.......................................... 37
11.2 Trademarks........................................................... 37
11.3 Electrostatic Discharge Caution............................ 37
11.4 Glossary................................................................ 37
12 Mechanical, Packaging, and Orderable
Information........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (May 2016) to Revision I Page
Moved automotive grade device LM25119Q references to data sheet SLUSD97 ............................................................... 1
Changed Two-Phase Operation to Two-Phase Interleaved Operation section header....................................................... 19
Added Interleaved 4-Phase Operation section..................................................................................................................... 20
Added Two-Phase Design Example..................................................................................................................................... 32
Changes from Revision G (January 2014) to Revision H Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision F (February 2013) to Revision G Page
Changed LLP-32 to WQFN-32............................................................................................................................................. 11
1
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 1513 14 16
32 31 30 29 2628 27 25
2
SW1
HO1
HB1
VIN
HO2
UVLO
HB2
SW2
VCC1
LO1
PGND1
CSG1
CS1
RAMP1
SS1
VCCDIS
FB1
COMP1
EN2
AGND
COMP2
RT
RES
FB2
VCC2
LO2
PGND2
CSG2
CS2
RAMP2
SS2
DEMB
3
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5 Pin Configuration and Functions
RTV Package
32-Pin WQFN
Top View
(1) G = Ground, I = Input, O = Output, P = Power
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 12 G Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.
COMP1 10 O Output of the channel1 internal error amplifier. The loop compensation network must be connected
between this pin and the FB1 pin.
COMP2 15 O Output of the channel2 internal error amplifier. The loop compensation network must be connected
between this pin and the FB2 pin.
CS1 5 I Current sense amplifier input. Connect to the high side of the channel1 current sense resistor.
CS2 20 I Current sense amplifier input. Connect to the high side of the channel2 current sense resistor.
CSG1 4 I Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the
channel1 current sense resistor.
CSG2 21 I Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the
channel2 current sense resistor.
DEMB 17 I
Logic input that enables diode emulation when in the low state. In diode emulation mode, the low-side
MOSFET is latched off for the remainder of the PWM cycle when the buck inductor current reverses
direction (current flow from output to ground). When DEMB is high, diode emulation is disabled allowing
current to flow in either direction through the low-side MOSFET. A 50-kpulldown resistor internal to the
LM25119 holds DEMB pin low and enables diode emulation if the pin is left floating.
EN2 11 I If the EN2 pin is low, channel2 is disabled. Channel1 and all other functions remain active. The EN2 has
a 50-kpullup resistor to enable channel2 when the pin is left floating.
FB1 9 I Feedback input and inverting input of the channel1 internal error amplifier. A resistor divider from the
channel1 output to this pin sets the output voltage level. The regulation threshold at the FB1 pin is 0.8 V.
FB2 16 I Feedback input and inverting input of the channel2 internal error amplifier. A resistor divider from the
channel2 output to this pin sets the output voltage level. The regulation threshold at the FB2 pin is 0.8 V.
HB1 30 P High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel1 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the
high-side MOSFET gate and must be placed as close to controller as possible.
4
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Pin Functions (continued)
PIN TYPE(1) DESCRIPTION
NAME NO.
HB2 27 P High-side driver supply for bootstrap gate drive. Connect to the cathode of the channel2 external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the
high-side MOSFET gate and must be placed as close to the controller as possible.
HO1 31 O High-side MOSFET gate drive output. Connect to the gate of the channel1 high-side MOSFET through a
short, low inductance path.
HO2 26 O High-side MOSFET gate drive output. Connect to the gate of the channel2 high-side MOSFET through a
short, low inductance path.
LO1 2 O Low-side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous
MOSFET through a short, low inductance path.
LO2 23 O Low-side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous
MOSFET through a short, low inductance path.
PGND1 3 G Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the
channel1 current sense resistor.
PGND2 22 G Power ground return pin for low-side MOSFET gate driver. Connect directly to the low side of the
channel2 current sense resistor.
RAMP1 6 I PWM ramp signal. An external resistor and capacitor connected between the SW1 pin, the RAMP1 pin
and the AGND pin sets the channel1 PWM ramp slope. Proper selection of component values produces
a RAMP1 signal that emulates the current in the buck inductor.
RAMP2 19 I PWM ramp signal. An external resistor and capacitor connected between the SW2 pin, the RAMP2 pin
and the AGND pin sets the channel2 PWM ramp slope. Proper selection of component values produces
a RAMP2 signal that emulates the current in the buck inductor.
RES 14 O
The restart timer pin for an external capacitor that configures the hiccup mode current limiting. A
capacitor on the RES pin determines the time the controller remains off before automatically restarting in
hiccup mode. The two regulator channels operate independently. One channel may operate in normal
mode while the other is in hiccup mode overload protection. The hiccup mode commences when either
channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting. After this occurs, a
10-µA current source charges the RES pin capacitor to the 1.25-V threshold which restarts the
overloaded channel.
RT 13 I The internal oscillator is set with a single resistor between RT and AGND. The recommended maximum
oscillator frequency is 1.5 MHz which corresponds to a maximum switching frequency of 750 kHz for
either channel. The internal oscillator can be synchronized to an external clock by coupling a positive
pulse into RT through a small coupling capacitor.
SS1 7 I An external capacitor and an internal 10-µA current source set the ramp rate of the channel1 error amp
reference. The SS1 pin is held low when VCC1 or VCC2 < 4 V, UVLO < 1.25 V or during thermal
shutdown.
SS2 18 I An external capacitor and an internal 10-µA current source set the ramp rate of the channel2 error amp
reference. The SS2 pin is held low when VCC1 or VCC2 < 4 V, UVLO < 1.25 V or during thermal
shutdown.
SW1 32 I/O Switching node of the buck regulator. Connect to channel1 bootstrap capacitor, the source terminal of the
high-side MOSFET and the drain terminal of the low-side MOSFET.
SW2 25 I/O Switching node of the buck regulator. Connect to channel2 bootstrap capacitor, the source terminal of the
high-side MOSFET and the drain terminal of the low-side MOSFET.
UVLO 28 I
Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown
mode with all function disabled. If the UVLO pin is greater than 0.4 V and below 1.25 V, the regulator is
in standby mode with the VCC regulators operational, the SS pins grounded and no switching at the HO
and LO outputs. If the UVLO pin voltage is above 1.25 V, the SS pins are allowed to ramp and pulse
width modulated gate drive signals are delivered at the LO and HO pins. A 20-µA current source is
enabled when UVLO exceeds 1.25 V and flows through the external UVLO resistors to provide
hysteresis.
VCCDIS 8 I
Optional input that disables the internal VCC regulators when external biasing is supplied. If VCCDIS >
1.25 V, the internal VCC regulators are disabled. The externally supplied bias must be coupled to the
VCC pins through a diode. VCCDIS has a 500-kpulldown resistor to ground to enable the VCC
regulators when the pin is left floating. The pulldown resistor can be overridden by pulling VCCDIS above
1.25 V with a resistor divider connected to the external bias supply.
VIN 29 P Supply voltage input source for the VCC regulators.
Thermal Pad Thermal pad of WQFN package. No internal electrical connections. Solder to the ground plane to reduce
thermal resistance.
5
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These pins must not exceed VIN.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN to AGND –0.3 45 V
SW1, SW2 to AGND –3 45 V
HB1 to SW1, HB2 to SW2 –0.3 15 V
VCC1, VCC2 to AGND (2) –0.3 15 V
FB1, FB2, DEMB, RES, VCCDIS, UVLO to AGND –0.3 15 V
HO1 to SW1, HO2 to SW2 –0.3 VHB + 0.3 V
LO1, LO2 to AGND –0.3 VVCC + 0.3 V
SS1, SS2 to AGND –0.3 7 V
EN2, RT to AGND –0.3 7 V
CS1, CS2, CSG1, CSG2 to AGND –0.3 0.3 V
PGND to AGND –0.3 0.3 V
Junction temperature, TJ150 °C
Storage temperature, Tstg –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The human-body model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±750
(1) COMP1, COMP2, RAMP1, and RAMP2 are output pins. As such they are not specified to have an external voltage applied.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN 4.5 42 V
VCC 4.5 14 V
HB to SW 4.5 14 V
TJJunction temperature –40 125 °C
6
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1) LM25119
UNITRTV (WQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 36.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.9 °C/W
RθJB Junction-to-board thermal resistance 9 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 8.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instrument's Average Outgoing Quality
Level (AOQL).
(2) Per VCC Regulator.
6.5 Electrical Characteristics
Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range. VIN = 36 V, VCC = 8 V, VCCDIS = 0 V, EN2 = 5 V, RT= 25 k, and no load on LO or HO (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
VIN SUPPLY
IBIAS VIN operating current VSS1 = VSS2 = 0 V 6 7.3 mA
VVCCDIS = 2 V, VSS1 = VSS2 = 0 V 340 500 µA
IVCC VCC1 operating current VVCCDIS = 2 V, VSS1 = VSS2 = 0 V 3.9 4.5 mA
VCC2 operating current VVCCDIS = 2 V, VSS1 = VSS2 = 0 V 1.4 2 mA
ISHUTDOWN VIN shutdown current VUVLO = 0 V, VSS1 = VSS2 = 0 V 15 33 µA
VCC REGULATOR(2)
VCC(REG) VCC regulation 6.77 7.6 8.34 V
VIN = 4.5 V, No external load 4.4 4.46
Sourcing current limit VCC = 0 V 25 40 mA
VCCDIS switch threshold VVCCDIS rising 1.19 1.25 1.29 V
VCCDIS switch hysteresis 0.07 V
VCCDIS input current VVCCDIS = 0 V –20 nA
Undervoltage threshold Positive going VCC 3.8 4 4.2 V
Undervoltage hysteresis 0.2 V
EN2 INPUT
VIL EN2 input low threshold 2 1.5 V
VIH EN2 input high threshold 2.9 2.5 V
EN2 input pullup resistor 50 k
UVLO
Threshold UVLO rising 1.2 1.25 1.29 V
Hysterisis current VUVLO = 1.4 V 15 20 25 µA
Shutdown threshold 0.4 V
Shutdown hysteresis voltage 0.1 V
SOFT START
Current source VSS = 0 V 7 10 13 µA
Pulldown RDSON 10
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Electrical Characteristics (continued)
Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range. VIN = 36 V, VCC = 8 V, VCCDIS = 0 V, EN2 = 5 V, RT= 25 k, and no load on LO or HO (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
ERROR AMPLIFIER
VREF FB reference voltage Measured at FB pin, FB = COMP 0.788 0.8 0.812 V
FB input bias current VFB = 0.8 V 1 nA
FB disable threshold Interleaved threshold 2.5 V
COMP VOH ISOURCE = 3 mA 2.8 V
COMP VOL ISINK = 3 mA 0.31 V
AOL DC gain 80 dB
fBW Unity gain bandwidth 3 MHz
PWM COMPARATORS
tHO(OFF) Forced HO OFF-time 220 320 430 ns
tON(min) Minimum HO ON-time CRAMP = 50 pF 100 ns
OSCILLATOR
fSW1 Frequency 1 RT= 25 k180 200 220 kHz
fSW2 Frequency 2 RT= 10 k430 480 530 kHz
RT output voltage 1.25 V
RT sync positive threshold TJ= 25°C 2.5 3.2 4 V
Sync pulse minimum width 100 ns
CURRENT LIMIT
VCS(TH) Cycle-by-cycle sense voltage
threshold (CS CSG) RAMP = 0 106 120 134 mV
CS bias current VCS = 0 V –70 –95 µA
Hiccup mode fault timer 256 Cycles
RES
IRES Current source 9.7 µA
VRES Threshold CRES charging 1.2 1.25 1.3 V
DIODE EMULATION
VIL DEMB input low threshold 2 1.65 V
VIH DEMB input high threshold 2.9 2.6 V
DEMB input pulldown resistance 50 k
SW zero cross threshold –5 mV
LO GATE DRIVER
VOLL LO low-state output voltage ILO = 100 mA 0.1 0.18 V
VOHL LO high-state output voltage ILO = –100 mA, VOHL = VCC VLO 0.17 0.26 V
LO rise time CLOAD = 1000 pF 6 ns
LO fall time CLOAD = 1000 pF 5 ns
IOHL Peak LO source current VLO = 0 V 2.5 A
IOLL Peak LO sink current VLO = VCC 3.3 A
HO GATE DRIVER
VOLH HO low-state output voltage IHO = 100 mA 0.11 0.19 V
VOHH HO high-state output voltage IHO = –100 mA, VOHH = VHB VHO 0.18 0.27 V
HO rise time CLOAD = 1000 pF 6 ns
HO fall time CLOAD = 1000 pF 5 ns
IOHH Peak HO Source current VHO = 0 V, VSW = 0, VHB = 8 V 2.2 A
IOLH Peak HO sink current VHO = VHB = 8 V 3.3 A
HB to SW undervoltage 3 V
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Electrical Characteristics (continued)
Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range. VIN = 36 V, VCC = 8 V, VCCDIS = 0 V, EN2 = 5 V, RT= 25 k, and no load on LO or HO (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
HB DC bias current VHB VSW = 8 V 70 100 µA
THERMAL
TSD Thermal shutdown Rising 165 °C
Thermal shutdown hysteresis 25 °C
6.6 Switching Characteristics
Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature
range. VIN = 36 V, VCC = 8 V, VVCCDIS = 0 V, VEN2 = 5 V, RT= 25 k, and no load on LO or HO (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LO fall to HO rise delay No load 70 ns
HO fall to LO rise delay No load 60 ns
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6.7 Typical Characteristics
Figure 1. HO Peak Driver Current vs Output Voltage Figure 2. LO Peak Driver Current vs Output Voltage
Figure 3. Driver Dead Time vs VCC Figure 4. Driver Dead Time vs Temperature
Figure 5. VCC vs IVCC Figure 6. Switching Frequency vs RT
10
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Typical Characteristics (continued)
Figure 7. Error Amp Gain and Phase vs Frequency
11
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7 Detailed Description
7.1 Overview
The LM25119 high voltage switching regulator features all of the functions necessary to implement an efficient
dual-channel buck regulator that operates over a very wide input voltage range. The LM25119 may be configured
as two independent regulators or as a single high-current regulator with two interleaved channels. This easy-to-
use regulator integrates high-side and low-side MOSFET drivers capable of supplying peak currents of 2.5 A
(VCC = 8 V). The regulator control method is based on current mode control using an emulated current ramp.
Emulated peak current mode control provides inherent line feedforward, cycle-by-cycle current limiting and ease-
of-loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width
modulation circuit, allowing reliable processing of the very small duty cycles necessary in high input voltage
applications. The switching frequency is user programmable from 50 kHz to 750 kHz. An oscillator or
synchronization pin allows the operating frequency to be set by a single resistor or synchronized to an external
clock. An undervoltage lockout and channel2 enable pin allows either both regulators to be disabled or channel2
to be disabled with full operation of channel1. Fault protection features include current limiting, thermal shutdown
and remote shutdown capability. The undervoltage lockout input enables both channels when the input voltage
reaches a user selected threshold and provides a very low quiescent shutdown current when pulled low. The
32-pin WQFN package features an exposed pad to aid in thermal dissipation.
VIN
RT
RES
UVLO
VCC2
FB2
SS2
0.8V
HB2
HO2
SW2
DISABLE
LO2
VCC2
DRIVER
DRIVER
CS2
A = 10
CLK 2
RAMP2
PGND2
COMP2
CSG2
EN2
AGND
VCC DISABLE
LOGIC
CHANNEL 2
HB
UVLO
LEVEL SHIFT/
ADAPTIVE
TIMER
+
-
TRACK
SAMPLE
and
HOLD
EN2
LOGIC
S
R
Q
Q
CLK 2
+
-
+
-
-+
+
+
-
1.2V
10 PA
VCC
UVLO
7.6V
REGULATOR
VIN
1.2V
VCC1
FB1
SS1
0.8V
HB1
HO1
SW1
DISABLE
LO1
VCC1
DRIVER
DRIVER
CS1
A = 10
CLK 1
RAMP1
PGND1
COMP1
CSG1
LOGIC DECODER/
DIODE EMULATION
HB
UVLO
LEVEL SHIFT/
ADAPTIVE
TIMER
+
-
TRACK
SAMPLE
and
HOLD
S
R
Q
Q
CLK 1
+
-
+
-
-+
+
+
-
1.2V
10 PA
VCC
UVLO
7.6V
REGULATOR
VIN
1.2V
CHANNEL 1
COMMON BIAS
GENERATOR
BIAS
0.8V
UVLO
LOGIC SHUTDOWN
STANDBY
CONTROL
THERMAL
SHUTDOWN
CHANNEL 1
CHANNEL 2
50 k:
VCCDIS
DEMB
VCC DISABLE
LOGIC
VCC
REGULATORS
LOGIC
DECODER
CHANNEL 1
CHANNEL 2
500 k:
50 k:
OSCILLATOR /
SYNC DETECTOR
CLK 1
CLK 2
10 PARESTART
LOGIC
HICCUP
FAULT TIMER
256 CYCLES
CHANNEL 1
STANDBY CHANNEL 2
STANDBY
CHANNEL 1
FAULT CHANNEL 2
FAULT
COMMON
LOGIC DECODER/
DIODE EMULATION
VCC DISABLE
LOGIC
RES Current
SS1 Current
SS2 Current
Copyright © 2016, Texas Instruments Incorporated
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7.2 Functional Block Diagram
13
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7.3 Feature Description
7.3.1 High Voltage Start-Up Regulator
The LM25119 contains two internal high voltage bias regulators, VCC1 and VCC2, that provide the bias supply
for the PWM controllers and gate drive for the MOSFETs of each regulator channel. The input pin (VIN) can be
connected directly to an input voltage source as high as 42 V. The outputs of the VCC regulators are set to
7.6 V. When the input voltage is below the VCC set-point level, the VCC output tracks the VIN with a small
dropout voltage. If VCC1 is in an undervoltage condition, channel2 is disabled. This interdependence is
necessary to prevent channel2 from running open-loop in the single output interleaved mode when the channel2
error amplifier is disabled (if either VCC is in UV, both channels are disabled).
The outputs of the VCC regulators are current limited at 25-mA (minimum) output capability. Upon power up, the
regulators source current into the capacitors connected to the VCC pins. When the voltage at the VCC pins
exceed 4 V and the UVLO pin is greater than 1.25 V, both channels are enabled and a soft-start sequence
begins. Both channels remain enabled until either VCC pin falls below 3.8 V, the UVLO pin falls below 1.25 V or
the die temperature exceeds the thermal limit threshold.
When operating at higher input voltages the bias power dissipation within the controller can be excessive. An
output voltage derived bias supply can be applied to a VCC pins to reduce the IC power dissipation. The
VCCDIS input can be used to disable the internal VCC regulators when external biasing is supplied.
If VCCDIS > 1.25 V, the internal VCC regulators are disabled. The externally supplied bias must be coupled to
the VCC pins through a diode, preferably a Schottky (low forward voltage). VCCDIS has a 500-kinternal
pulldown resistance to ground for normal operation with no external bias. The internal pulldown resistance can
be overridden by pulling VCCDIS above 1.25 V through a resistor divider connected to an external bias supply.
The VCC regulator series pass transistor includes a diode between VCC and VIN that must not be forward-
biased in normal operation.
If the external bias winding can supply VCC greater than VIN, an external blocking diode is required from the
input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply
through the VCC pins. For VOUT between 5 V and 14.5 V, VOUT can be connected directly to VCC through a
diode. For VOUT < 5 V, a bias winding on the output inductor can be added as shown in Figure 8.
Figure 8. VCC Bias Supply With Additional Inductor Winding
In high voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 45 V. During line or load transients, voltage ringing on the VIN line that exceeds the absolute
maximum rating can damage the IC. Both careful PCB layout and the use of quality bypass capacitors located
close to the VIN and AGND pins are essential.
7.3.2 UVLO
The LM25119 contains a dual-level undervoltage lockout (UVLO) circuit. When the UVLO pin is less than 0.4 V,
the LM25119 is in shutdown mode. The shutdown comparator provides 100 mV of hysteresis to avoid chatter
during transitions. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in
standby mode. In the standby mode the VCC bias regulators are active but the controller outputs are disabled.
This feature allows the UVLO pin to be used as a remote enable or disable function. When the VCC outputs
exceed their respective undervoltage thresholds (4 V) and the UVLO pin voltage is greater than 1.25 V, the
outputs are enabled and normal operation begins.
9
TSW
5.2 10
R 948
f
u
14
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Feature Description (continued)
An external set-point voltage divider from the VIN to GND is used to set the minimum VIN operating voltage of
the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.25 V when
the input voltage is in the desired operating range. UVLO hysteresis is accomplished with an internal 20-μA
current source that is switched on or off into the impedance of the set-point divider. When the UVLO pin voltage
exceeds 1.25-V threshold, the current source is activated to quickly raise the voltage at the UVLO pin. When the
UVLO pin voltage falls below the 1.25-V threshold, the current source is turned off causing the voltage at the
UVLO pin to quickly fall. The UVLO pin must not be left floating.
7.3.3 Enable 2
The LM25119 contains an enable function allowing shutdown control of channel2, independent of channel1. If
the EN2 pin is pulled below 2 V, channel2 enters shutdown mode. If the EN2 input is greater than 2.5 V,
channel2 returns to normal operation. An internal 50-kpullup resistor on the EN2 pin allows this pin to be left
floating for normal operation. The EN2 input can be used in conjunction with the UVLO pin to sequence the two
regulator channels. If EN2 is held low as the UVLO pin increases to a voltage greater than the 1.25-V UVLO
threshold, channel1 begins operation while channel2 remains off. Both channels become operational when the
UVLO, EN2, VCC1, and VCC2 pins are above their respective operating thresholds. Either channel of the
LM25119 can also be disabled independently by pulling the corresponding SS pin to AGND.
7.3.4 Oscillator and Sync Capability
The LM25119 switching frequency is set by a single external resistor connected between the RT pin and the
AGND pin (RT). The resistor must be located very close to the device and connected directly to the pins of the IC
(RT and AGND). To set a desired switching frequency (fSW) of each channel, the resistor can be calculated with
Equation 1.
where
RT is in ohms (Ω)
fSW is in hertz (Hz) (1)
The frequency fSW is the output switching frequency of each channel. The internal oscillator runs at twice the
switching frequency and an internal frequency divider interleaves the two channels with 180° phase shift between
PWM pulses at the HO pins.
The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25 V and
the voltage at the RT pin must exceed 4 V to trip the internal synchronization pulse detector. A 5-V amplitude
signal and 100-pF coupling capacitor are recommended. Synchronizing at greater than twice the free-running
frequency may result in abnormal behavior of the pulse width modulator. Also, note that the output switching
frequency of each channel is one-half the applied synchronization frequency.
7.3.5 Error Amplifiers and PWM Comparators
Each of the two internal high-gain error amplifiers generates an error signal proportional to the difference
between the regulated output voltage and an internal precision reference (0.8 V). The output of each error
amplifier is connected to the COMP pin allowing the user to provide loop compensation components. Generally a
Type II network is recommended. This network creates a pole at 0 Hz, a mid-band zero, and a noise-reducing,
high-frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP
generator to the error amplifier output voltage at the COMP pin. Only one error amplifier is required when
configuring the controller as a two channel, single output interleaved regulator. For these applications, the
channel1 error amplifier (FB1, COMP1) is configured as the master error amplifier. The channel2 error amplifier
must be disabled by connecting the FB2 pin to the VCC2 pin. When configured in this manner the output of the
channel2 error amplifier (COMP2) is disabled and have a high output impedance. To complete the interleaved
configuration, the COMP1 and the COMP2 pins must be connected together to facilitate PWM control of
channel2 and current sharing between channels.
IN PERIOD
RAMP RAMP RAMP
V t
VR C
u
|
u
PERIOD
RAMP IN RAMP RAMP
t
V V 1 eR C
§ ·
u
¨ ¸
u
© ¹
IN S
RAMP 10 K V R
dVdt L
u u u
RAMP
Sample and
Hold DC Level
VIN x tON
10 x RS V/A
tON
RRAMP x CRAMP
RAMP =
15
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Feature Description (continued)
7.3.6 Ramp Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using
this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feedforward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering, blanking time, and propagation
delay limit the minimum achievable pulse width. In applications where the input voltage may be relatively large in
comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation.
The LM25119 uses a unique ramp generator which does not actually measure the buck switch current but rather
reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM
comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is
comprised of two elements; a sample-and-hold DC level and the emulated inductor current ramp as shown in
Figure 9.
Figure 9. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measurement of the recirculating current flowing through the
current sense resistor. The voltage across the sense resistor is sampled and held just prior to the onset of the
next conduction interval of the buck switch. The current sensing and sample-and-hold provide the DC level of the
reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor
connected from RAMP pin to AGND and a series resistor connected between SW and RAMP. The ramp resistor
must not be connected to VIN directly because the RAMP pin voltage rating could be exceeded under high VIN
conditions. The ramp created by the external resistor and capacitor has a slope proportional to the rising inductor
current plus some additional slope required for slope compensation. Connecting the RAMP pin resistor to SW
provides optimum slope compensation with a RAMP capacitor slope that is proportional to VIN. This adaptive
slope compensation eliminates the requirement for additional slope compensation circuitry with high output
voltage set points and frees the user from additional concerns in this area. The emulated ramp signal is
approximately linear and the ramp slope is given in Equation 2.
(2)
The factor of 10 Equation 2 corresponds to the internal current sense amplifier gain of the LM25119. The K factor
is a constant which adds additional slope for robust pulse-width modulation control at lower input voltages. In
practice this constant can be varied from 1 to 3. RSis the external sense resistor value.
The voltage on the ramp capacitor is given with Equation 3and Equation 4.
(3)
(4)
The approximation is the first order term in a Taylor Series expansion of the exponential and is valid because
tPERIOD is small relative to the RAMP pin R-C time constant.
SW
CURRENT LIMIT
COMPARATOR CS
RAMP
CLK
CSG
+
-
+
-
1.2V CURRENT SENSE
AMPLIFIER
A=10
HO
CRAMP
RRAMP
RSIL
RAMP S RAMP
L
C10 R K R
u u u
16
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Feature Description (continued)
Multiplying Equation 2 by tPERIOD to convert the slope to a peak voltage, and then equating Equation 2 with
Equation 4 allows us to solve for CRAMP using Equation 5.
(5)
Choose either CRAMP or RRAMP and use Equation 5 to calculate the other component.
The difference between the average inductor current and the DC value of the sampled inductor current can
cause instability for certain operating conditions. This instability is known as sub-harmonic oscillation, which
occurs when the inductor ripple current does not return to its initial value by the start of next switching cycle.
Sub-harmonic oscillation is normally characterized by alternating wide and narrow pulses at the switch node. The
ramp equation above contains the optimum amount of slope compensation, however extra slope compensation is
easily added by selecting a lower value for RRAMP or CRAMP.
7.3.7 Current Limit
The LM25119 contains a current limit monitoring scheme to protect the regulator from possible overcurrent
conditions. When set correctly, the emulated current signal is proportional to the buck switch current with a scale
factor determined by the current limit sense resistor, RS, and current sense amplifier gain. The emulated signal is
applied to the current limit comparator. If the emulated ramp signal exceeds 1.2 V, the present cycle is
terminated (cycle-by-cycle current limiting). Shown in Figure 10 is the current limit comparator and a simplified
current measurement schematic. In applications with small output inductance and high input voltage, the switch
current may overshoot due to the propagation delay of the current limit comparator. If an overshoot must occur,
the sample-and-hold circuit detects the excess recirculating current before the buck switch is turned on again. If
the sample-and-hold DC level exceeds the internal current limit threshold, the buck switch is disabled and skip
pulses until the current has decayed below the current limit threshold. This approach prevents current runaway
conditions due to propagation delays or inductor saturation because the inductor current is forced to decay to a
controlled level following any current overshoot.
Figure 10. Current Limit and Ramp Circuit
7.3.8 Hiccup Mode Current Limiting
To further protect the regulator during prolonged current limit conditions, an internal counter counts the PWM
clock cycles during which cycle-by-cycle current limiting occurs. When the counter detects 256 consecutive
cycles of current limiting, the regulator enters a low power dissipation hiccup mode with the HO and LO outputs
disabled. The restart timer pin, RES, and an external capacitor configure the hiccup mode current limiting. A
capacitor on the RES pin (CRES) determines the time the controller remains in low power standby mode before
automatically restarting. A 10-µA current source charges the RES pin capacitor to the 1.25-V threshold which
restarts the overloaded channel. The two regulator channels operate independently. One channel may operate
normally while the other is in the hiccup mode overload protection. The hiccup mode commences when either
channel experiences 256 consecutive PWM cycles with cycle-by-cycle current limiting. If that occurs, the
overloaded channel turns off and remains off for the duration of the RES pin timer.
The hiccup mode current-limiting function can be disabled. The RES configuration is latched during initial power
up when UVLO is above 1.25 V and VCC1 and VCC2 are above their UV thresholds, determining hiccup or non-
hiccup current limiting. If the RES pin is tied to VCC at initial power on, hiccup current limit is disabled.
MAX SW
D f 9
1 320 10-
= - ´ ´
17
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Feature Description (continued)
7.3.9 Soft Start
The soft-start feature allows the regulator to gradually reach the steady-state operating point, thus reducing start-
up stresses and surges. The LM25119 regulates the FB pin to the SS pin voltage or the internal 0.8-V reference,
whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 10-µA soft-start
current source gradually increases the voltage on an external soft-start capacitor (CSS) connected to the SS pin
resulting in a gradual rise of the FB and output voltages.
Either regulator channel of the LM25119 can be disabled by pulling the corresponding SS pin to AGND.
7.3.10 HO and LO Output Drivers
The LM25119 contains a high-current, high-side driver and associated high voltage level shift to drive the buck
switch of each regulator channel. This gate driver circuit works in conjunction with an external diode and
bootstrap capacitor. A 0.1 µF or larger ceramic capacitor, connected with short traces between the HB pin and
SW pin, is recommended. During the OFF-time of the high-side MOSFET, the SW pin voltage is approximately 0
V and the bootstrap capacitor charges from VCC through the external bootstrap diode. When operating with a
high PWM duty cycle, the buck switch is forced off each cycle for 320 ns to ensure that the bootstrap capacitor is
recharged.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs
are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time
logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay. Similarly, the
LO turnon is disabled until the HO voltage has discharged. This methodology insures adequate dead-time for any
size MOSFET.
Exercise care in selecting an output MOSFET with the appropriate threshold voltage, especially if VCC is
supplied from the regulator output. During start-up at low input voltages the MOSFET threshold must be lower
than the 4-V VCC undervoltage lockout threshold. Otherwise, there may be insufficient VCC voltage to
completely turn on the MOSFET as VCC undervoltage lockout is released during start-up. If the buck switch
MOSFET gate drive is not sufficient, the regulator may not start or it may hang up momentarily in a high power
dissipation state. This condition can be avoided by selecting a MOSFET with a lower threshold voltage or if VCC
is supplied from an external source higher than the output voltage. If the minimum input voltage programmed by
the UVLO pin resistor divider is above the VCC regulation level, this precaution is of no concern.
7.3.11 Maximum Duty Cycle
When operating with a high PWM duty cycle, the buck switch is forced off each cycle for 320 ns to ensure the
bootstrap capacitor is recharged and to allow time to sample and hold the current in the low-side MOSFET. This
forced OFF-time limits the maximum duty cycle of the controller. When designing a regulator with high switching
frequency and high duty cycle requirements, make sure to check the required maximum duty cycle (including
losses) against the graph shown in Figure 11.
The actual maximum duty cycle varies with the operating frequency in Equation 6.
(6)
Figure 11. Maximum Duty Cycle vs Switching Frequency
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Feature Description (continued)
7.3.12 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power reset state,
disabling the output driver and the VCC bias regulators. This feature is designed to prevent catastrophic failures
from overheating and destroying the device.
7.4 Device Functional Modes
7.4.1 Diode Emulation
A fully synchronous buck regulator implemented with a free-wheel MOSFET rather than a diode has the
capability to sink current from the output in certain conditions such as light load, overvoltage, or prebias start-up.
The LM25119 device provides a diode emulation feature that can be enabled to prevent reverse (drain to source)
current flow in the low-side, free-wheel MOSFET. When configured for diode emulation, the low-side MOSFET is
disabled when reverse current flow is detected. The benefit of this configuration is lower power loss at no load or
light load conditions and the ability to turn on into a prebiased output without discharging the output. The diode
emulation mode allows for start-up into prebiased loads, because it prevents reverse current flow as the soft-start
capacitor charges to the regulation level during start-up. The negative effect of diode emulation is degraded light
load transient response times. Enabling the diode emulation feature is recommended and allows discontinuous
conduction operation. The diode emulation feature is configured with the DEMB pin. To enable diode emulation,
connect the DEMB pin to ground or leave the pin floating. If continuous conduction operation is desired, the
DEMB pin must be tied to either VCC1 or VCC2.