N80C187-12 - Intel - Datasheet.Directory

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80C187

80-BIT MATH COPROCESSOR

YHigh Performance 80-Bit Internal

Architecture

YImplements ANSI/IEEE Standard 754-

1985 for Binary Floating-Point

Arithmetic

YUpward Object-Code Compatible from

8087

YFully Compatible with 387DX and 387SX

Math Coprocessors. Implements all 387

Architectural Enhancements over 8087

YDirectly Interfaces with 80C186 CPU

Y80C186/80C187 Provide a Software/

Binary Compatible Upgrade from

80186/82188/8087 Systems

YExpands 80C186’s Data Types to

Include 32-, 64-, 80-Bit Floating-Point,

32-, 64-Bit Integers and 18-Digit BCD

Operands

YDirectly Extends 80C186’s Instruction

Set to Trigonometric, Logarithmic,

Exponential, and Arithmetic

Instructions for All Data Types

YFull-Range Transcendental Operations

for SINE, COSINE, TANGENT,

ARCTANGENT, and LOGARITHM

YBuilt-In Exception Handling

YEight 80-Bit Numeric Registers, Usable

as Individually Addressable General

Registers or as a Register Stack

YAvailable in 40-Pin CERDIP and 44-Pin

PLCC Package

(See Packaging Outlines and Dimensions, Order Ý231369)

The Intel 80C187 is a high-performance math coprocessor that extends the architecture of the 80C186 with

floating-point, extended integer, and BCD data types. A computing system that includes the 80C187 fully

conforms to the IEEE Floating-Point Standard. The 80C187 adds over seventy mnemonics to the instruction

set of the 80C186, including support for arithmetic, logarithmic, exponential, and trigonometric mathematical

operations. The 80C187 is implemented with 1.5 micron, high-speed CHMOS III technology and packaged in

both a 40-pin CERDIP and a 44-pin PLCC package. The 80C187 is upward object-code compatible from the

8087 math coprocessor and will execute code written for the 80387DX and 80387SX math coprocessors.

80C187

270640–1

Figure 1. 80C187 Block Diagram

80C187

80C187 Data Registers

79 78 64 63 0

R0 SIGN EXPONENT SIGNIFICAND

15 0 15 0

CONTROL REGISTER INSTRUCTION POINTER

STATUS REGISTER DATA POINTER

TAG WORD

Figure 2. Register Set

FUNCTIONAL DESCRIPTION

The 80C187 Math Coprocessor provides arithmetic

instructions for a variety of numeric data types. It

also executes numerous built-in transcendental

functions (e.g. tangent, sine, cosine, and log func-

tions). The 80C187 effectively extends the register

and instruction set of the 80C186 CPU for existing

data types and adds several new data types as well.

Figure 2 shows the additional registers visible to pro-

grams in a system that includes the 80C187. Essen-

tially, the 80C187 can be treated as an additional

resource or an extension to the CPU. The 80C186

CPU together with an 80C187 can be used as a sin-

gle unified system.

A 80C186 system that includes the 80C187 is com-

pletely upward compatible with software for the

8086/8087.

The 80C187 interfaces only with the 80C186 CPU.

The interface hardware for the 80C187 is not imple-

mented on the 80C188.

PROGRAMMING INTERFACE

The 80C187 adds to the CPU additional data types,

registers, instructions, and interrupts specifically de-

signed to facilitate high-speed numerics processing.

All new instructions and data types are directly sup-

ported by the assembler and compilers for high-level

languages. The 80C187 also supports the full

80387DX instruction set.

All communication between the CPU and the

80C187 is transparent to applications software. The

CPU automatically controls the 80C187 whenever a

numerics instruction is executed. All physical memo-

ry and virtual memory of the CPU are available for

storage of the instructions and operands of pro-

grams that use the 80C187. All memory addressing

modes are available for addressing numerics oper-

ands.

The end of this data sheet lists by class the instruc-

tions that the 80C187 adds to the instruction set.

NOTE:

The 80C187 Math Coprocessor is also referred to

as a Numeric Processor Extension (NPX) in this

document.

Data Types

Table 1 lists the seven data types that the 80C187

supports and presents the format for each type. Op-

erands are stored in memory with the least signifi-

cant digit at the lowest memory address. Programs

retrieve these values by generating the lowest ad-

dress. For maximum system performance, all oper-

ands should start at even physical-memory address-

es; operands may begin at odd addresses, but will

require extra memory cycles to access the entire op-

erand.

Internally, the 80C187 holds all numbers in the ex-

tended-precision real format. Instructions that load

operands from memory automatically convert oper-

ands represented in memory as 16-, 32-, or 64-bit

integers, 32- or 64-bit floating-point numbers, or 18-

digit packed BCD numbers into extended-precision

real format. Instructions that store operands in mem-

ory perform the inverse type conversion.

80C187

Numeric Operands

A typical NPX instruction accepts one or two oper-

ands and produces one (or sometimes two) results.

In two-operand instructions, one operand is the con-

tents of an NPX register, while the other may be a

memory location. The operands of some instructions

are predefined; for example, FSQRT always takes

the square root of the number in the top stack ele-

ment (refer to the section on Data Registers).

Figure 2 shows the 80C187 register set. When an

80C187 is present in a system, programmers may

use these registers in addition to the registers nor-

mally available on the CPU.

DATA REGISTERS

80C187 computations use the extended-precision

real data type.

Table 1. Data Type Representation in Memory

270640–2

NOTES:

1. S eSign bit (0 ePositive, 1 eNegative)

2. dneDecimal digit (two per byte)

3. X eBits have no significance; 80C187 ignores when loading, zeros when storing

4. UePosition of implicit binary point

5. I eInteger bit of significand; stored in temporary real, implicit in single and double precision

6. Exponent Bias (normalized values):

Single: 127 (7FH)

Double: 1023 (3FFH)

Extended Real: 16383 (3FFFH)

7. Packed BCD: (b1)S(D17 ...D

)

8. Real: (b1)S(2E-BIAS)(F

1...)

80C187

The 80C187 register set can be accessed either as

a stack, with instructions operating on the top one or

two stack elements, or as individually addressable

registers. The TOP field in the status word identifies

the current top-of-stack register. A ‘‘push’’ operation

decrements TOP by one and loads a value into the

new top register. A ‘‘pop’’ operation stores the value

from the current top register and then increments

TOP by one. The 80C187 register stack grows

‘‘down’’ toward lower-addressed registers.

Instructions may address the data registers either

implicitly or explicitly. Many instructions operate on

the register at the TOP of the stack. These instruc-

tions implicitly address the register at which TOP

points. Other instructions allow the programmer to

explicitly specify which register to use. This explicit

addressing is also relative to TOP.

TAG WORD

The tag word marks the content of each numeric

data register, as Figure 3 shows. Each two-bit tag

represents one of the eight data registers. The prin-

cipal function of the tag word is to optimize the

NPX’s performance and stack handling by making it

possible to distinguish between empty and nonemp-

ty register locations. It also enables exception han-

dlers to identify special values (e.g. NaNs or denor-

mals) in the contents of a stack location without the

need to perform complex decoding of the actual

data.

STATUS WORD

The 16-bit status word (in the status register) shown

in Figure 4 reflects the overall state of the 80C187. It

may be read and inspected by programs.

Bit 15, the B-bit (busy bit) is included for 8087 com-

patibility only. It always has the same value as the

ES bit (bit 7 of the status word); it does not indicate

the status of the BUSY output of 80C187.

Bits 13– 11 (TOP) point to the 80C187 register that

is the current top-of-stack.

The four numeric condition code bits (C3–C0) are

similar to the flags in a CPU; instructions that per-

form arithmetic operations update these bits to re-

flect the outcome. The effects of these instructions

on the condition code are summarized in Tables 2

through 5.

Bit 7 is the error summary (ES) status bit. This bit is

set if any unmasked exception bit is set; it is clear

otherwise. If this bit is set, the ERROR signal is as-

serted.

Bit 6 is the stack flag (SF). This bit is used to distin-

guish invalid operations due to stack overflow or un-

derflow from other kinds of invalid operations. When

SF is set, bit 9 (C1) distinguishes between stack

overflow (C1e1) and underflow (C1e0).

Figure 4 shows the six exception flags in bits 5– 0 of

the status word. Bits 5– 0 are set to indicate that the

80C187 has detected an exception while executing

an instruction. A later section entitled ‘‘Exception

Handling’’ explains how they are set and used.

Note that when a new value is loaded into the status

word by the FLDENV or FRSTOR instruction, the

value of ES (bit 7) and its reflection in the B-bit (bit

15) are not derived from the values loaded from

memory but rather are dependent upon the values of

the exception flags (bits 5– 0) in the status word and

their corresponding masks in the control word. If ES

is set in such a case, the ERROR output of the

80C187 is activated immediately.

15 0

TAG (7) TAG (6) TAG (5) TAG (4) TAG (3) TAG (2) TAG (1) TAG (0)

NOTE:

The index i of tag(i) is not top-relative. A program typically uses the ‘‘top’’ field of Status Word to determine

which tag(i) field refers to logical top of stack.

TAG VALUES:

00 eValid

01 eZero

10 eQNaN, SNaN, Infinity, Denormal and Unsupported Formats

11 eEmpty

Figure 3. Tag Word

80C187

270640–3

ES is set if any unmasked exception bit is set; cleared otherwise.

See Table 2 for interpretation of condition code.

TOP values:

000 eRegister 0 is Top of Stack

001 eRegister 1 is Top of Stack

111 eRegister 7 is Top of Stack

For definitions of exceptions, refer to the section entitled,

‘‘Exception Handling’’

Figure 4. Status Word

80C187

CONTROL WORD

The NPX provides several processing options that are selected by loading a control word from memory into

the control register. Figure 5 shows the format and encoding of fields in the control word.

Table 2. Condition Code Interpretation

Instruction C0(S) C3(Z) C1(A) C2(C)

FPREM, FPREM1 Three Least Significant Reduction

(See Table 3) Bits of Quotient 0 eComplete

Q2 Q0 Q1 1 eIncomplete

or O/U

FCOM, FCOMP,

FCOMPP, FTST Result of Comparison Zero or Operand is not

FUCOM, FUCOMP, (See Table 4) O/U Comparable (Table 4)

FUCOMPP, FICOM,

FICOMP

FXAM Operand Class Sign Operand Class

(See Table 5) or O/U (Table 5)

FCHS, FABS, FXCH,

FINCSTP, FDECSTP,

Constant Loads, UNDEFINED Zero UNDEFINED

FXTRACT, FLD, or O/U

FILD, FBLD,

FSTP (Ext Real)

FIST, FBSTP,

FRNDINT, FST,

FSTP, FADD, FMUL, UNDEFINED Roundup UNDEFINED

FDIV, FDIVR, or O/U

FSUB, FSUBR,

FSCALE, FSQRT,

FPATAN, F2XM1,

FYL2X, FYL2XP1

FPTAN, FSIN, UNDEFINED Roundup Reduction

FCOS, FSINCOS or O/U,0

Complete

Undefined 1 eIncomplete

if C2 e1

FLDENV, FRSTOR Each Bit Loaded from Memory

FLDCW, FSTENV,

FSTCW, FSTSW, UNDEFINED

FCLEX, FINIT,

FSAVE

O/U When both IE and SF bits of status word are set, indicating a stack exception, this bit distinguishes between

stack overflow (C1 e1) and underflow (C1 e0).

Reduction If FPREM or FPREM1 produces a remainder that is less than the modulus, reduction is complete. When

reduction is incomplete the value at the top of the stack is a partial remainder, which can be used as input to

further reduction. For FPTAN, FSIN, FCOS, and FSINCOS, the reduction bit is set if the operand at the top of

the stack is too large. In this case the original operand remains at the top of the stack.

Roundup When the PE bit of the status word is set, this bit indicates whether one was added to the least significant bit of

the result during the last rounding.

UNDEFINED Do not rely on finding any specific value in these bits.

80C187

The low-order byte of this control word configures

exception masking. Bits 5–0 of the control word

contain individual masks for each of the six excep-

tions that the 80C187 recognizes.

The high-order byte of the control word configures

the 80C187 operating mode, including precision,

rounding, and infinity control.

#The ‘‘infinity control bit’’ (bit 12) is not meaningful

to the 80C187, and programs must ignore its val-

ue. To maintain compatibility with the 8087, this

bit can be programmed; however, regardless of

its value, the 80C187 always treats infinity in the

affine sense (b%ka%). This bit is initialized

to zero both after a hardware reset and after the

FINIT instruction.

#The rounding control (RC) bits (bits 11– 10) pro-

vide for directed rounding and true chop, as well

as the unbiased round to nearest even mode

specified in the IEEE standard. Rounding control

affects only those instructions that perform

rounding at the end of the operation (and thus

can generate a precision exception); namely,

FST, FSTP, FIST, all arithmetic instructions (ex-

cept FPREM, FPREM1, FXTRACT, FABS, and

FCHS), and all transcendental instructions.

#The precision control (PC) bits (bits 9– 8) can be

used to set the 80C187 internal operating preci-

sion of the significand at less than the default of

64 bits (extended precision). This can be useful in

providing compatibility with early generation arith-

metic processors of smaller precision. PC affects

only the instructions ADD, SUB, DIV, MUL, and

SQRT. For all other instructions, either the preci-

sion is determined by the opcode or extended

precision is used.

Table 3. Condition Code Interpretation after FPREM and FPREM1 Instructions

Condition Code Interpretation after

C2 C3 C1 C0 FPREM and FPREM1

Incomplete Reduction:

1 X X X Further Iteration Required

for Complete Reduction

Q1 Q0 Q2 Q MOD 8

000 0

0 1 0 1 Complete Reduction:

01 0 0 2 C0, C3, C1 Contain Three Least

1 1 0 3 Significant Bits of Quotient

001 4

011 5

101 6

111 7

Table 4. Condition Code Resulting from Comparison

Order C3 C2 C0

TOP lOperand 0 0 0

TOP kOperand 0 0 1

TOP eOperand 1 0 0

Unordered 1 1 1

80C187

Table 5. Condition Code Defining Operand Class

C3 C2 C1 C0 Value at TOP

0000

Unsupported

0001

NaN

0010

Unsupported

0011

NaN

0100

Normal

0101

Infinity

0110

Normal

0111

Infinity

1000

1001

Empty

1010

1011

Empty

1100

Denormal

1111

Denormal

INSTRUCTION AND DATA POINTERS

Because the NPX operates in parallel with the CPU,

any exceptions detected by the NPX may be report-

ed after the CPU has executed the ESC instruction

which caused it. To allow identification of the failing

numerics instruction, the 80C187 contains registers

that aid in diagnosis. These registers supply the op-

code of the failing numerics instruction, the address

of the instruction, and the address of its numerics

memory operand (if appropriate).

The instruction and data pointers are provided for

user-written exception handlers. Whenever the

80C187 executes a new ESC instruction, it saves

the address of the instruction (including any prefixes

that may be present), the address of the operand (if

present), and the opcode.

The instruction and data pointers appear in the for-

mat shown by Figure 6. The ESC instruction

FLDENV, FSTENV, FSAVE and FRSTOR are used

to transfer these values between the registers and

memory. Note that the value of the data pointer is

undefined

if the prior ESC instruction did not have a

memory operand.

Interrupt Description

CPU interrupt 16 is used to report exceptional condi-

tions while executing numeric programs. Interrupt 16

indicates that the previous numerics instruction

caused an unmasked exception. The address of the

faulty instruction and the address of its operand are

stored in the instruction pointer and data pointer reg-

isters. Only ESC instructions can cause this inter-

rupt. The CPU return address pushed onto the stack

of the exception handler points to an ESC instruction

(including prefixes). This instruction can be restarted

after clearing the exception condition in the NPX.

FNINIT, FNCLEX, FNSTSW, FNSTENV, and

FNSAVE cannot cause this interrupt.

Exception Handling

The 80C187 detects six different exception condi-

tions that can occur during instruction execution. Ta-

ble 6 lists the exception conditions in order of prece-

dence, showing for each the cause and the default

action taken by the 80C187 if the exception is

masked by its corresponding mask bit in the control

word.

Any exception that is not masked by the control

word sets the corresponding exception flag of the

status word, sets the ES bit of the status word, and

asserts the ERROR signal. When the CPU attempts

to execute another ESC instruction, interrupt 16 oc-

curs. The exception condition must be resolved via

an interrupt service routine. The return address

pushed onto the CPU stack upon entry to the serv-

ice routine does not necessarily point to the failing

instruction nor to the following instruction. The

80C187 saves the address of the floating-point in-

struction that caused the exception and the address

of any memory operand required by that instruction.

If error trapping is required at the end of a series of

numerics instructions (specifically, when the last

ESC instruction modifies memory data and that data

is used in subsequent nonnumerics instructions), it is

necessary to insert the FNOP instruction to force the

80C187 to check its ERROR input.

80C187

270640–4

Precision Control

00Ð 24 Bits (Single Precision)

01Ð (Reserved)

10Ð 53 Bits (Double Precision)

11Ð 64 Bits (Extended Precision)

Rounding Control

00Ð Round to Nearest or Even

01Ð Round Down (toward b%)

10Ð Round Up (toward a%)

11Ð Chop (Truncate toward Zero)

*The ‘‘infinity control’’ bit is not meaningful to the 80C187. To maintain compatibility with the 8087, this bit can be

programmed; however, regardless of its value, the 80C187 treats infinity in the affine sense (b%ka%).

Figure 5. Control Word

15 7 0

CONTROL WORD a0

STATUS WORD a2

TAG WORD a4

INSTRUCTION POINTER15..0 a6

IP19..16 0 OPCODE10..0 a8

OPERAND POINTER15..0 aA

OP19..16 000000000000a

Figure 6. Instruction and Data Pointer Image in Memory

80C187

Table 6. Exceptions

Exception Cause Default Action

(If Exception is Masked)

Invalid Operation on a signalling NaN, Result is a quiet NaN,

Operation unsupported format, indeterminate integer indefinite, or

form (0*%, 0/0), (a%) BCD indefinite

a(b%), etc.), or stack

overflow/underflow (SF is also set)

Denormalized At least one of the operands is The operand is normalized,

Operand denormalized, i.e. it has the smallest and normal processing

exponent but a nonzero significand continues

Zero Divisor The divisor is zero while the dividend Result is %

is a noninfinite, nonzero number

Overflow The result is too large in magnitude Result is largest finite

to fit in the specified format value or %

Underflow The true result is nonzero but too small Result is denormalized

to be represented in the specified format, and, or zero

if underflow exception is masked, denormalization

causes loss of accuracy

Inexact The true result is not exactly representable Normal processing

Result in the specified format (e.g. 1/3); continues

(Precision) the result is rounded according to the

rounding mode

Initialization

After FNINIT or RESET, the control word contains

the value 037FH (all exceptions masked, precision

control 64 bits, rounding to nearest) the same values

as in an 8087 after RESET. For compatibility with the

8087, the bit that used to indicate infinity control (bit

12) is set to zero; however, regardless of its setting,

infinity is treated in the affine sense. After FNINIT or

RESET, the status word is initialized as follows:

#All exceptions are set to zero.

#Stack TOP is zero, so that after the first push the

stack top will be register seven (111B).

#The condition code C3–C0is undefined.

#The B-bit is zero.

The tag word contains FFFFH (all stack locations

are empty).

80C186/80C187 initialization software should exe-

cute an FNINIT instruction (i.e. an FINIT without a

preceding WAIT) after RESET. The FNINIT is not

strictly required for 80C187 software, but Intel

recommends its use to help ensure upward compati-

bility with other processors.

8087 Compatibility

This section summarizes the differences between

the 80C187 and the 8087. Many changes have been

designed into the 80C187 to directly support the

IEEE standard in hardware. These changes result in

increased performance by elminating the need for

software that supports the standard.

GENERAL DIFFERENCES

The 8087 instructions FENI/FNENI and FDISI/

FNDISI perform no useful function in the 80C187

Numeric Processor Extension. They do not alter the

state of the 80C187 Numeric Processor Extension.

(They are treated similarly to FNOP, except that

ERROR is not checked.) While 8086/8087 code

containing these instructions can be executed on

the 80C186/80C187, it is unlikely that the exception-

handling routines containing these instructions will

be completely portable to the 80C187 Numeric Proc-

essor Extension.

The 80C187 differs from the 8087 with respect to

instruction, data, and exception synchronization. Ex-

cept for the processor control instructions, all of the

80C187 numeric instructions are automatically syn-

chronized by the 80C186 CPU. When necessary, the

80C187

80C186 automatically tests the BUSY line from the

80C187 Numeric Processor Extension to ensure that

the 80C187 Numeric Processor Extension has com-

pleted its previous instruction before executing the

next ESC instruction. No explicit WAIT instructions

are required to assure this synchronization. For the

8087 used with 8086 and 8088 CPUs, explicit WAITs

are required before each numeric instruction to en-

sure synchronization. Although 8086/8087 pro-

grams having explicit WAIT instructions will execute

on the 80C186/80C187, these WAIT instructions

are unnecessary.

The 80C187 supports only affine closure for infinity

arithmetic, not projective closure.

Operands for FSCALE and FPATAN are no longer

restricted in range (except for g%); F2XM1 and

FPTAN accept a wider range of operands.

Rounding control is in effect for FLD

constant

Software cannot change entries of the tag word to

values (other than empty) that differ from actual reg-

ister contents.

After reset, FINIT, and incomplete FPREM, the

80C187 resets to zero the condition code bits C3–

C0of the status word.

In conformance with the IEEE standard, the 80C187

does not support the special data formats

pseudozero, pseudo-NaN, pseudoinfinity, and un-

normal.

The denormal exception has a different purpose on

the 80C187. A system that uses the denormal-ex-

ception handler solely to normalize the denormal op-

erands, would better mask the denormal exception

on the 80C187. The 80C187 automatically normal-

izes denormal operands when the denormal excep-

tion is masked.

EXCEPTIONS

A number of differences exist due to changes in the

IEEE standard and to functional improvements to

the architecture of the 80C186/80C187:

1. The 80C186/80C187 traps exceptions only on

the next ESC instruction; i.e. the 80C186 does not

notice unmasked 80C187 exceptions on the

80C186 ERROR input line until a later numerics

instruction is executed. Because the 80C186

does not sample ERROR on WAIT and FWAIT

instructions, programmers should place an FNOP

instruction at the end of a sequence of numerics

instructions to force the 80C186 to sample its

ERROR input.

2. The 80C187 Numeric Processor Extension sig-

nals exceptions through a dedicated ERROR line

to the CPU. The 80C187 error signal does not

pass through an interrupt controller (the 8087 INT

signal does). Therefore, any interrupt-controller-

oriented instructions in numerics exception han-

dlers for the 8086/8087 should be deleted.

3. Interrupt vector 16 must point to the numerics ex-

ception handling routine.

4. The ESC instruction address saved in the 80C187

Numeric Processor Extension includes any lead-

ing prefixes before the ESC opcode. The corre-

sponding address saved in the 8087 does not

include leading prefixes.

5. When the overflow or underflow exception is

masked, the 80C187 differs from the 8087 in

rounding when overflow or underflow occurs. The

80C187 produces results that are consistent with

the rounding mode.

6. When the underflow exception is masked, the

80C187 sets its underflow flag only if there is also

a loss of accuracy during denormalization.

7. Fewer invalid-operation exceptions due to denor-

mal operands, because the instructions FSQRT,

FDIV, FPREM, and conversions to BCD or to inte-

ger normalize denormal operands before pro-

ceeding.

8. The FSQRT, FBSTP, and FPREM instructions

may cause underflow, because they support de-

normal operands.

9. The denormal exception can occur during the

transcendental instructions and the FXTRACT in-

struction.

10. The denormal exception no longer takes prece-

dence over all other exceptions.

11. When the denormal exception is masked, the

80C187 automatically normalizes denormal op-

erands. The 8087 performs unnormal arithmetic,

which might produce an unnormal result.

12. When the operand is zero, the FXTRACT in-

struction reports a zero-divide exception and

leaves b%in ST(1).

13. The status word has a new bit (SF) that signals

when invalid-operation exceptions are due to

stack underflow or overflow.

14. FLD

extended precision

no longer reports denor-

mal exceptions, because the instruction is not

numeric.

15. FLD

single/double precision

when the operand

is denormal converts the number to extended

precision and signals the denormalized oper-

80C187

and exception. When loading a signalling NaN,

FLD

single/double precision

signals an invalid-

operand exception.

16. The 80C187 only generates quiet NaNs (as on

the 8087); however, the 80C187 distinguishes

between quiet NaNs and signalling NaNs. Sig-

nalling NaNs trigger exceptions when they are

used as operands; quiet NaNs do not (except for

FCOM, FIST, and FBSTP which also raise IE for

quiet NaNs).

17. When stack overflow occurs during FPTAN and

overflow is masked, both ST(0) and ST(1) con-

tain quiet NaNs. The 8087 leaves the original

operand in ST(1) intact.

18. When the scaling factor is g%, the FSCALE

(ST(0), ST(1) instruction behaves as follows

(ST(0) and ST(1) contain the scaled and scaling

operands respectively):

#FSCALE (0, %) generates the invalid opera-

tion exception.

#FSCALE (finite, b%) generates zero with the

same sign as the scaled operand.

#FSCALE (finite, a%) generates %with the

same sign as the scaled operand.

The 8087 returns zero in the first case and rais-

es the invalid-operation exception in the other

cases.

19. The 80C187 returns signed infinity/zero as the

unmasked response to massive overflow/under-

flow. The 8087 supports a limited range for the

scaling factor; within this range either massive

overflow/underflow do not occur or undefined

results are produced.

Table 7. Pin Summary

Pin Function Active Input/

Name State Output

CLK CLocK I

CKM ClocKing Mode I

RESET System reset High I

PEREQ Processor Extension High O

REQuest

BUSY Busy status High O

ERROR Error status Low O

D15–D0Data pins High I/O

NPRD Numeric Processor ReaD Low I

NPWR Numeric Processor WRite Low I

NPS1 NPX select Ý1 Low I

NPS2 NPX select Ý2 High I

CMD0 CoMmanD 0 High I

CMD1 CoMmanD 1 High I

VCC System power I

VSS System ground I

80C187

HARDWARE INTERFACE

In the following description of hardware interface, an

overbar above a signal name indicates that the ac-

tive or asserted state occurs when the signal is at a

low voltage. When no overbar is present above the

signal name, the signal is asserted when at the high

voltage level.

Signal Description

In the following signal descriptions, the 80C187 pins

are grouped by function as follows:

1. Execution ControlÐ CLK, CKM, RESET

2. NPX HandshakeÐ PEREQ, BUSY, ERROR

3. Bus Interface PinsÐ D15–D0, NPWR, NPRD

4. Chip/Port SelectÐ NPS1, NPS2, CMD0, CMD1

5. Power SuppliesÐ VCC,V

Table 7 lists every pin by its identifier, gives a brief

description of its function, and lists some of its char-

acteristics. Figure 7 shows the locations of pins on

the CERDIP package, while Figure 8 shows the loca-

tions of pins on the PLCC package. Table 8 helps to

locate pin identifiers in Figures 7 and 8.

Clock (CLK)

This input provides the basic timing for internal oper-

ation. This pin does not require MOS-level input; it

will operate at either TTL or MOS levels up to the

maximum allowed frequency. A minimum frequency

must be provided to keep the internal logic properly

functioning. Depending on the signal on CKM, the

signal on CLK can be divided by two to produce the

internal clock signal (in which case CLK may be up

to 32 MHz in frequency), or can be used directly (in

which case CLK may be up to 12.5 MHz).

Clocking Mode (CKM)

This pin is a strapping option. When it is strapped to

VCC (HIGH), the CLK input is used directly; when

strapped to VSS (LOW), the CLK input is divided by

two to produce the internal clock signal. During the

RESET sequence, this input must be stable at least

four internal clock cycles (i.e. CLK clocks when CKM

is HIGH; 2 cCLK clocks when CKM is LOW) before

RESET goes LOW.

270640–5

*N.C. ePin Not Connected

Figure 7. CERDIP Pin Configuration

270640–6

*N.C. ePin Not Connected

**‘‘Top View’’ means as the package is seen from the

component side of the board.

Figure 8. PLCC Pin Configuration

80C187

Table 8. PLCC Pin Cross-Reference

Pin Name CERDIP Package PLCC Package

BUSY 25 28

CKM 39 44

CLK 32 36

CMD0 29 32

CMD1 31 35

D023 26

D122 25

D221 24

D320 22

D419 21

D518 20

D617 19

D716 18

D815 17

D914 16

D10 12 14

D11 11 13

D12 89

13 78

14 67

15 55

ERROR 26 29

No Connect 2 6, 11, 23, 33, 40

NPRD 27 30

NPS1 34 38

NPS2 33 37

NPWR 28 31

PEREQ 24 27

RESET 35 39

VCC 3, 9, 13, 37, 40 1, 3, 10, 15, 42

VSS 1, 4, 10, 30, 36, 38 2, 4, 12, 34, 41, 43

System Reset (RESET)

A LOW to HIGH transition on this pin causes the

80C187 to terminate its present activity and to enter

a dormant state. RESET must remain active (HIGH)

for at least four internal clock periods. (The relation

of the internal clock period to CLK depends on

CLKM; the internal clock may be different from that

of the CPU.) Note that the 80C187 is active internal-

ly for 25 clock periods after the termination of the

RESET signal (the HIGH to LOW transition of RE-

SET); therefore, the first instruction should not be

written to the 80C187 until 25 internal clocks after

the falling edge of RESET. Table 9 shows the status

of the output pins during the reset sequence. After a

reset, all output pins return to their inactive states.

Table 9. Output Pin Status during Reset

Output Value

Pin Name during Reset

BUSY HIGH

ERROR HIGH

PEREQ LOW

D15–D0TRI-STATE OFF

Processor Extension Request (PEREQ)

When active, this pin signals to the CPU that the

80C187 is ready for data transfer to/from its data

FIFO. When there are more than five data transfers,

80C187

PEREQ is deactivated after the first three transfers

and subsequently after every four transfers. This sig-

nal always goes inactive before BUSY goes inactive.

Busy Status (BUSY)

When active, this pin signals to the CPU that the

80C187 is currently executing an instruction. This

pin is active HIGH. It should be connected to the

80C186’s TEST/BUSY pin. During the RESET se-

quence this pin is HIGH. The 80C186 uses this

HIGH state to detect the presence of an 80C187.

Error Status (ERROR)

This pin reflects the ES bit of the status register.

When active, it indicates that an unmasked excep-

tion has occurred. This signal can be changed to

inactive state only by the following instructions (with-

out a preceding WAIT): FNINIT, FNCLEX,

FNSTENV, FNSAVE, FLDCW, FLDENV, and

FRSTOR. This pin should be connected to the

ERROR pin of the CPU. ERROR can change state

only when BUSY is active.

Data Pins (D15–D0)

These bidirectional pins are used to transfer data

and opcodes between the CPU and 80C187. They

are normally connected directly to the correspond-

ing CPU data pins. Other buffers/drivers driving the

local data bus must be disabled when the CPU

reads from the NPX. High state indicates a value of

one. D0is the least significant data bit.

Numeric Processor Write (NPWR)

A signal on this pin enables transfers of data from

the CPU to the NPX. This input is valid only when

NPS1 and NPS2 are both active.

Numeric Processor Read (NPRD)

A signal on this pin enables transfers of data from

the NPX to the CPU. This input is valid only when

NPS1 and NPS2 are both active.

Numeric Processor Selects (NPS1 and NPS2)

Concurrent assertion of these signals indicates that

the CPU is performing an escape instruction and en-

ables the 80C187 to execute that instruction. No

data transfer involving the 80C187 occurs unless the

device is selected by these lines.

Command Selects (CMD0 and CMD1)

These pins along with the select pins allow the CPU

to direct the operation of the 80C187.

System Power (VCC)

System power provides the a5V g10% DC supply

input. All VCC pins should be tied together on the

circuit board and local decoupling capacitors should

be used between VCC and VSS.

System Ground (VSS)

All VSS pins should be tied together on the circuit

board and local decoupling capacitors should be

used between VCC and VSS.

Processor Architecture

As shown by the block diagram (Figure 1), the

80C187 NPX is internally divided into three sections:

the bus control logic (BCL), the data interface and

control unit, and the floating-point unit (FPU). The

FPU (with the support of the control unit which con-

tains the sequencer and other support units) exe-

cutes all numerics instructions. The data interface

and control unit is responsible for the data flow to

and from the FPU and the control registers, for re-

ceiving the instructions, decoding them, and se-

quencing the microinstructions, and for handling

some of the administrative instructions. The BCL is

responsible for CPU bus tracking and interface.

BUS CONTROL LOGIC

The BCL communicates solely with the CPU using

I/O bus cycles. The BCL appears to the CPU as a

special peripheral device. It is special in two re-

spects: the CPU initiates I/O automatically when it

encounters ESC instructions, and the CPU uses re-

served I/O addresses to communicate with the BCL.

The BCL does not communicate directly with memo-

ry. The CPU performs all memory access, transfer-

ring input operands from memory to the 80C187 and

transferring outputs from the 80C187 to memory. A

dedicated communication protocol makes possible

high-speed transfer of opcodes and operands be-

tween the CPU and 80C187.

80C187

Table 10. Bus Cycles Definition

NPS1 NPS2 CMD0 CMD1 NPRD NPWR Bus Cycle Type

x 0 x x x x 80C187 Not Selected

1 x x x x x 80C187 Not Selected

0 1 0 0 1 0 Opcode Write to 80C187

0 1 0 0 0 1 CW or SW Read from 80C187

0 1 1 0 0 1 Read Data from 80C187

0 1 1 0 1 0 Write Data to 80C187

0 1 0 1 1 0 Write Exception Pointers

0 1 0 1 0 1 Reserved

0 1 1 1 0 1 Read Opcode Status

0 1 1 1 1 0 Reserved

DATA INTERFACE AND CONTROL UNIT

The data interface and control unit latches the data

and, subject to BCL control, directs the data to the

FIFO or the instruction decoder. The instruction de-

coder decodes the ESC instructions sent to it by the

CPU and generates controls that direct the data flow

in the FIFO. It also triggers the microinstruction se-

quencer that controls execution of each instruction.

If the ESC instruction is FINIT, FCLEX, FSTSW,

FSTSW AX, FSTCW, FSETPM, or FRSTPM, the

control executes it independently of the FPU and the

sequencer. The data interface and control unit is the

one that generates the BUSY, PEREQ, and ERROR

signals that synchronize 80C187 activities with the

CPU.

FLOATING-POINT UNIT

The FPU executes all instructions that involve the

dental, constant, and data transfer instructions. The

data path in the FPU is 84 bits wide (68 significant

bits, 15 exponent bits, and a sign bit) which allows

internal operand transfers to be performed at very

high speeds.

Bus Cycles

The pins NPS1, NPS2, CMD0, CMD1, NPRD and

NPWR identify bus cycles for the NPX. Table 10 de-

fines the types of 80C187 bus cycles.

80C187 ADDRESSING

The NPS1, NPS2, CMD0, and CMD1 signals allow

the NPX to identify which bus cycles are intended for

the NPX. The NPX responds to I/O cycles when the

I/O address is 00F8H, 00FAH, 00FCH, or 00FEH.

The correspondence betwen I/O addresses and

control signals is defined by Table 11. To guarantee

correct operation of the NPX, programs must not

perform any I/O operations to these reserved port

addresses.

Table 11. I/O Address Decoding

I/O Address 80C187 Select and Command Inputs

(Hexadecimal) NPS2 NPS1 CMD1 CMD0

00F8 1 0 0 0

00FA 1 0 0 1

00FC 1 0 1 0

00FE 1 0 1 1

80C187

CPU/NPX SYNCHRONIZATION

The pins BUSY, PEREQ, and ERROR are used for

various aspects of synchronization between the

CPU and the NPX.

BUSY is used to synchronize instruction transfer

from the CPU to the 80C187. When the 80C187 rec-

ognizes an ESC instruction, it asserts BUSY. For

most ESC instructions, the CPU waits for the

80C187 to deassert BUSY before sending the new

opcode.

The NPX uses the PEREQ pin of the CPU to signal

that the NPX is ready for data transfer to or from its

data FIFO. The NPX does not directly access mem-

ory; rather, the CPU provides memory access serv-

ices for the NPX.

Once the CPU initiates an 80C187 instruction that

has operands, the CPU waits for PEREQ signals that

indicate when the 80C187 is ready for operand

transfer. Once all operands have been transferred

(or if the instruction has no operands) the CPU con-

tinues program execution while the 80C187 exe-

cutes the ESC instruction.

In 8086/8087 systems, WAIT instructions are re-

quired to achieve synchronization of both com-

mands and operands. The 80C187, however, does

not require WAIT instructions. The WAIT or FWAIT

instruction commonly inserted by high-level compil-

ers and assembly-language programmers for excep-

tion synchronization is not treated as an instruction

by the 80C186 and does not provide exception trap-

ping. (Refer to the section ‘‘System Configuration for

8087-Compatible Exception Trapping’’.)

Once it has started to execute a numerics instruction

and has transferred the operands from the CPU, the

80C187 can process the instruction in parallel with

and independent of the host CPU. When the NPX

detects an exception, it asserts the ERROR signal,

which causes a CPU interrupt.

OPCODE INTERPRETATION

The CPU and the NPX use a bus protocol that

adapts to the numerics opcode being executed.

Only the NPX directly interprets the opcode. Some

of the results of this interpretation are relevant to the

CPU. The NPX records these results (opcode status

information) in an internal 16-bit register. The

80C186 accesses this register only via reads from

NPX port 00FEH. Tables 10 and 11 define the signal

combinations that correspond to each of the follow-

ing steps.

1. The CPU writes the opcode to NPX port 00F8H.

This write can occur even when the NPX is busy

or is signalling an exception. The NPX does not

necessarily begin executing the opcode immedi-

ately.

2. The CPU reads the opcode status information

from NPX port 00FEH.

3. The CPU initiates subsequent bus cycles accord-

ing to the opcode status information. The opcode

status information specifies whether to wait until

the NPX is not busy, when to transfer exception

pointers to port 00FCH, when to read or write op-

erands and results at port 00FAH, etc.

For most instructions, the NPX does not start exe-

cuting the previously transferred opcode until the

CPU (guided by the opcode status information) first

writes exception pointer information to port 00FCH

of the NPX. This protocol is completely transparent

to programmers.

Bus Operation

With respect to bus interface, the 80C187 is fully

asynchronous with the CPU, even when it operates

from the same clock source as the CPU. The CPU

initiates a bus cycle for the NPX by activating both

NPS1 and NPS2, the NPX select signals. During the

CLK period in which NPS1 and NPS2 are activated,

the 80C187 also examines the NPRD and NPRW

80C187

input signals to determine whether the cycle is a

read or a write cycle and examines the CMD0 and

CMD1 inputs to determine whether an opcode, oper-

and, or control/status register transfer is to occur.

The 80C187 activates its BUSY output some time

after the leading edge of the NPRD or NPRW signal.

Input and ouput data are referenced to the trailing

edges of the NPRD and NPRW signals.

The 80C187 activates the PEREQ signal when it is

ready for data transfer. The 80C187 deactivates

PEREQ automatically.

System Configuration

The 80C187 can be connected to the 80C186 CPU

as shown by Figure 9. (Refer to the 80C186 Data

Sheet for an explanation of the 80C186’s signals.)

This interface has the following characteristics:

#The 80C187’s NPS1, ERROR, PEREQ, and

BUSY pins are connected directly to the corre-

sponding pins of the 80C186.

#The 80C186 pin MCS3/NPS is connected to

NPS1; NPS2 is connected to VCC. Note that if the

80C186 CPU’s DEN signal is used to gate exter-

nal data buffers, it must be combined with the

NPS signal to insure numeric accesses will not

activate these buffers.

#The NPRD and NPRW pins are connected to the

RD and WR pins of the 80C186.

#CMD1 and CMD0 come from the latched A2and

A1of the 80C186, respectively.

#The 80C187 BUSY output connects to the

80C186 TEST/BUSY input. During RESET, the

signal at the 80C187 BUSY output automatically

programs the 80C186 to use the 80C187.

#The 80C187 can use the CLKOUT signal of the

80C186 to conserve board space when operating

at 12.5 MHz or less. In this case, the 80C187

CKM input must be pulled HIGH. For operation in

excess of 12.5 MHz, a double-frequency external

oscillator for CLK input is needed. In this case,

CKM must be pulled LOW.

270640–7

Figure 9. 80C186/80C187 System Configuration

80C187

System Configuration for 80186/

80187-Compatible Exception Trapping

When the 80C187 ERROR output signal is connect-

ed directly to the 80C186 ERROR input, floating-

point exceptions cause interrupt Ý16. However, ex-

isting software may be programmed to expect float-

ing-point exceptions to be signalled over an external

interrupt pin via an interrupt controller.

For exception handling compatible with the 80186/

82188/8087, the 80C186 can be wired to recognize

exceptions through an external interrupt pin, as Fig-

ure 10 shows. (Refer to the 80C186 Data Sheet for

an explanation of the 80C186’s signals.) With this

arrangement, a flip-flop is needed to latch BUSY

upon assertion of ERROR. The latch can then be

cleared during the exception-handler routine by forc-

ing a PCS pin active. The latch must also be cleared

at RESET in order for the 80C186 to work with the

80C187.

270640–8

*For input clocking options, refer to Figure 9.

Figure 10. System Configuration for 8087-Compatible Exception Trapping

80C187

ELECTRICAL DATA

Absolute Maximum Ratings*

Case Temperature Under Bias (TC)ÀÀÀ0§Ctoa

85§C

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Voltage on Any Pin

with Respect to GroundÀÀÀÀb0.5V to VCC a0.5V

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

Power and Frequency Requirements

The typical relationship between ICC and the fre-

quency of operation F is as follows:

ICCtyp e55a5*F mA where F is in MHz.

When the frequency is reduced below the minimum

operating frequency specified in the AC Characteris-

tics table, the internal states of the 80C187 may be-

come indeterminate. The 80C187 clock cannot be

stopped; otherwise, ICC would increase significantly

beyond what the equation above indicates.

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

DC Characteristics TCe0§Ctoa

85§C, VCC ea

5V g10%

Symbol Parameter Min Max Units Test Conditions

VIL Input LOW Voltage b0.5 a0.8 V

VIH Input HIGH Voltage 2.0 VCC a0.5 V

VICL Clock Input LOW Voltage b0.5 a0.8 V

VICH Clock Input HIGH Voltage 2.0 VCC a0.5 V

VOL Output LOW Voltage 0.45 V IOL e3.0 mA

VOH Output HIGH Voltage 2.4 V IOH eb

0.4 mA

ICC Power Supply Current 156 mA 16 MHz

135 mA 12.5 MHz

ILI Input Leakage Current g10 mA0V

IN sVCC

ILO I/O Leakage Current g10 mA 0.45V sVOUT sVCC b0.45V

CIN Input Capacitance 10 pF FCe1 MHz

COI/O or Output Capacitance 12 pF FCe1 MHz

CCLK Clock Capacitance 20 pF FCe1 MHz

80C187

AC Characteristics

TCe0§Ctoa

85§C, VCC e5V g10%

All timings are measured at 1.5V unless otherwise specified

12.5 MHz 16 MHz Test

Symbol Parameter Min Max Min Max Conditions

(ns) (ns) (ns) (ns)

Tdvwh (t6) Data Setup to NPWR 43 33

Twhdx (t7) Data Hold from NPWR 14 14

Trlrh (t8) NPRD Active Time 59 54

Twlwh (t9) NPWR Active Time 59 54

Tavwl (t10) Command Valid to NPWR 00

avrl (t11) Command Valid to NPRD 00

mhrl (t12) Min Delay from PEREQ Active 40 30

to NPRD Active

Twhax (t18) Command Hold from NPWR 12 8

Trhax (t19) Command Hold from NPRD 12 8

Tivcl (t20) NPRD, NPWR, RESET to 46 38 Note 1

CLK Setup Time

Tclih (t21) NPRD, NPWR, RESET from 26 18 Note 1

CLK Hold Time

Trscl (t24) RESET to CLK Setup 21 19 Note 1

Tclrs (t25) RESET from CLK Hold 14 9 Note 1

Tcmdi (t26) Command Inactive Time

Write to Write 69 59

Read to Read 69 59

Read to Write 69 59

Write to Read 69 59

NOTE:

1. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK

edge.

80C187

Timing Responses

All timings are measured at 1.5V unless otherwise specified

12.5 MHz 16 MHz Test

Symbol Parameter Min Max Min Max Conditions

(ns) (ns) (ns) (ns)

Trhqz (t27) NPRD Inactive to Data Float*18 18 Note 2

Trlqv (t28) NPRD Active to Data Valid 50 45 Note 3

Tilbh (t29) ERROR Active to Busy Inactive 104 104 Note 4

Twlbv (t30) NPWR Active to Busy Active 80 60 Note 4

Tklml (t31) NPRD or NPWR Active 80 60 Note 5

to PEREQ Inactive

Trhqh (t32) Data Hold from NPRD Inactive 2 2 Note 3

Trlbh (t33) RESET Inactive to BUSY Inactive 80 60

NOTES:

*The data float delay is not tested.

2. The float condition occurs when the measured output current is less than IOL on D15 –D0.

3. D15–D0loading: CLe100 pF.

4. BUSY loading: CLe100 pF.

5. On last data transfer of numeric instruction.

Clock Timings

12.5 MHz 16 MHz*Test

Symbol Parameter Min Max Min Max Conditions

(ns) (ns) (ns) (ns)

Tclcl (t1a) CLK Period CKM e1 80 250 N/A N/A Note 6

(t1B) CKM e0 40 125 31.25 125 Note 6

Tclch (t2a) CLK Low Time CKM e1 35 N/A Note 6

(t2b) CKM e0 9 7 Note 7

Tchcl (t3a) CLK High Time CKM e1 35 N/A Note 6

(t3b) CKM e0 13 9 Note 8

Tch2ch1(t4) 10 8 Note 9

Tch1ch2(t5) 10 8 Note 10

NOTES:

*16 MHz operation is available only in divide-by-2 mode (CKM strapped LOW).

6. At 1.5V

7. At 0.8V

8. At 2.0V

9. CKM e1: 3.7V to 0.8V at 16 MHz, 3.5V to 1.0V at 12.5 MHz

10. CKM e1: 0.8V to 3.7V at 16 MHz, 1.0V to 3.5V at 12.5 MHz

80C187

AC DRIVE AND MEASUREMENT

POINTSÐCLK INPUT

270640–9

AC SETUP, HOLD, AND DELAY TIME

MEASUREMENTSÐGENERAL

270640–10

AC TEST LOADING ON OUTPUTS

270640–11

DATA TRANSFER TIMING (INITIATED BY CPU)

270640–12

80C187

DATA CHANNEL TIMING (INITIATED BY 80C187)

270640–13

ERROR OUTPUT TIMING

270640–14

CLK, RESET TIMING (CKM e1)

270640–15

80C187

CLK, NPRD, NPWR TIMING (CKM e1)

270640–16

CLK, RESET TIMING (CKM e0)

270640–17

RESET must meet timing shown to guarantee known phase of internal divide by 2 circuits.

NOTE:

RESET, NPWR, NPRD inputs are asynchronous to CLK. Timing requirements are given for testing purposes only, to assure

recognition at a specific CLK edge.

CLK, NPRD, NPWR TIMING (CKM e0)

270640–18

RESET, BUSY TIMING

270640–19

80C187

80C187 EXTENSIONS TO THE CPU’s

INSTRUCTION SET

Instructions for the 80C187 assume one of the five

forms shown in Table 12. In all cases, instructions

are at least two bytes long and begin with the bit

pattern 11011B, which identifies the ESCAPE class

of instruction. Instructions that refer to memory oper-

ands specify addresses using the CPU’s addressing

modes.

MOD (Mode field) and R/M (Register/Memory spec-

ifier) have the same interpretation as the corre-

sponding fields of CPU instructions (refer to Pro-

grammer’s Reference Manual for the CPU). The

DISP (displacement) is optionally present in instruc-

tions that have MOD and R/M fields. Its presence

depends on the values of MOD and R/M, as for in-

structions of the CPU.

The instruction summaries that follow assume that

the instruction has been prefetched, decoded, and is

ready for execution; that bus cycles do not require

wait states; that there are no local bus HOLD re-

quests delaying processor access to the bus; and

that no exceptions are detected during instruction

execution. Timings are given in internal 80C187

clocks and include the time for opcode and data

transfer between the CPU and the NPX. If the in-

struction has MOD and R/M fields that call for both

base and index registers, add one clock.

Table 12. Instruction Formats

Instruction Optional

First Byte Second Byte Field

1 11011 OPA 1 MOD 1 OPB R/M DISP

2 11011 MF OPA MOD OPB *R/M DISP

3 11011 d P OPA 1 1 OPB *ST (i)

4 11011 0 0 1 1 1 1 OP

5 11011 0 1 1 1 1 1 OP

15–11 10 9 8 7 6 5 4 3 2 1 0

NOTES:

OP eInstruction opcode, possibly split into two fields OPA and OPB

MF eMemory Format

00Ð 32-Bit Real

01Ð 32-Bit Integer

10Ð 64-Bit Real

11Ð 16-Bit Integer

deDestination

0Ð Destination is ST(0)

0Ð Destination is ST(i)

R XOR d e0Ð Destination (op) Source

R XOR d e1Ð Source (op) Destination

*In FSUB and FDIV, the low-order bit of OPB is the R (reversed) bit

PePop

0Ð Do not pop stack

1Ð Pop stack after operation

ESC e11011

ST(i) eRegister Stack Element

000 eStack Top

001 eSecond Stack Element

111 eEighth Stack Element

80C187

80C187 Extensions to the 80C186 Instruction Set

Encoding Clock Count Range

Instruction Byte Byte Optional 32-Bit 32-Bit 64-Bit 16-Bit

0 1 Bytes 2–3 Real Integer Real Integer

DATA TRANSFER

FLD eLoada

Integer/real memory to ST(0) ESC MF 1 MOD 000 R/M DISP 40 65–72 59 67–71

Long integer memory to ST(0) ESC 111 MOD 101 R/M DISP 90–101

Extended real memory to ST(0) ESC 011 MOD 101 R/M DISP 74

BCD memory to ST(0) ESC 111 MOD 100 R/M DISP 296–305

ST(i) to ST(0) ESC 001 11000 ST(i) 16

FST eStore

ST(0) to integer/real memory ESC MF 1 MOD 010 R/M DISP 58 93 – 107 73 80–93

ST(0) to ST(i) ESC 101 11010 ST(i) 13

FSTP eStore and Pop

ST(0) to integer/real memory ESC MF 1 MOD 011 R/M DISP 58 93 – 107 73 80–93

ST(0) to long integer memory ESC 111 MOD 111 R/M DISP 116 – 133

ST(0) to extended real ESC 011 MOD 111 R/M DISP 83

ST(0) to BCD memory ESC 111 MOD 110 R/M DISP 542–564

ST(0) to ST(i) ESC 101 11001 ST (i) 14

FXCH eExchange

ST(i) and ST(0) ESC 001 11001 ST(i) 20

COMPARISON

FCOM eCompare

Integer/real memory to ST(0) ESC MF 0 MOD 010 R/M DISP 48 78–85 67 77 – 81

ST(i) to ST(0) ESC 000 11010 ST(i) 26

FCOMP eCompare and pop

Integer/real memory to ST ESC MF 0 MOD 011 R/M DISP 48 78–85 67 77–81

ST(i) to ST(0) ESC 000 11011 ST(i) 28

FCOMPP eCompare and pop twice

ST(1) to ST(0) ESC 110 1101 1001 28

FTST eTest ST(0) ESC 001 1110 0100 30

FUCOM eUnordered compare ESC 101 11100 ST(i) 26

FUCOMP eUnordered compare

and pop ESC 101 11101 ST(i) 28

FUCOMPP eUnordered compare

and pop twice ESC 010 1110 1001 28

FXAM eExamine ST(0) ESC 001 11100101 32-40

CONSTANTS

FLDZ eLoad a0.0 into ST(0) ESC 001 1110 1110 22

FLD1 eLoad a1.0 into ST(0) ESC 001 1110 1000 26

FLDPI eLoad pi into ST(0) ESC 001 1110 1011 42

FLDL2T eLoad log2(10) into ST(0) ESC 001 1110 1001 42

Shaded areas indicate instructions not available in 8087.

NOTE:

a. When loading single- or double-precision zero from memory, add 5 clocks.

80C187

80C187 Extensions to the 80C186 Instruction Set (Continued)

Encoding Clock Count Range

Instruction Byte Byte Optional 32-Bit 32-Bit 64-Bit 16-Bit

0 1 Bytes 2–3 Real Integer Real Integer

CONSTANTS (Continued)

FLDL2E eLoad log2(e) into ST(0) ESC 001 1110 1010 42

FLDLG2 eLoad log10(2) into ST(0) ESC 001 1110 1100 43

FLDLN2 eLoad loge(2) into ST(0) ESC 001 1110 1101 43

ARITHMETIC

FADD eAdd

Integer/real memory with ST(0) ESC MF 0 MOD 000 R/M DISP 44–52 77–92 65–73 77–91

ST(i) and ST(0) ESCdP0 11000 ST(i) 25–33b

FSUB eSubtract

Integer/real memory with ST(0) ESC MF 0 MOD 10 R R/M DISP 44 – 52 77 – 92 65 – 73 77–91c

ST(i) and ST(0) ESCdP0 1110 R R/M 28–36d

FMUL eMultiply

Integer/real memory with ST(0) ESC MF 0 MOD 001 R/M DISP 47–57 81–102 68–93 82–93

ST(i) and ST(0) ESCdP0 1100 1 R/M 31– 59e

FDIV eDivide

Integer/real memory with ST(0) ESC MF 0 MOD 11 R R/M DISP 108 140–147f128 142–146g

ST(i) and ST(0) ESCdP0 1111 R R/M 90h

FSQRTieSquare root ESC 001 1111 1010 124–131

FSCALE eScale ST(0) by ST(1) ESC 001 1111 1101 69–88

FPREM ePartial remainder of

ST(0) dST(1) ESC 001 1111 1000 76– 157

FPREM1 ePartial remainder

(IEEE) ESC 001 1111 0101 97– 187

FRNDINT eRound ST(0)

to integer ESC 001 1111 1100 68–82

FXTRACT eExtract components

of ST(0) ESC 001 1111 0100 72–78

FABS eAbsolute value of ST(0) ESC 001 1110 0001 24

FCHS eChange sign of ST(0) ESC 001 1110 0000 26–27

Shaded areas indicate instructions not available in 8087.

NOTES:

b. Add 3 clocks to the range when d e1.

c. Add 1 clock to each range when R e1.

d. Add 3 clocks to the range when d e0.

e. typical e54 (When d e0, 48–56, typical e51).

f. Add 1 clock to the range when R e1.

g. 153–159 when R e1.

h. Add 3 clocks to the range when d e1.

i. b0sST(0) sa%.

80C187

80C187 Extensions to the 80C186 Instruction Set (Continued)

Encoding

Instruction Byte Byte Optional Clock Count Range

0 1 Bytes 2–3

TRANSCENDENTAL

FCOS eCosine of ST(0) ESC 001 1111 1111 125–774j

FPTANkePartial tangent of ST(0) ESC 001 1111 0010 193–499j

FPATAN ePartial arctangent ESC 001 1111 0011 316–489

FSIN eSine of ST(0) ESC 001 1111 1110 124–773j

FSINCOS eSine and cosine of ST(0) ESC 001 1111 1011 196–811j

F2XM1le2ST(0) b1 ESC 001 1111 0000 213– 478

FYL2XmeST(1) *log2(ST(0)) ESC 001 1111 0001 122– 540

FYL2XP1neST(1) *log2(ST(0) a1.0) ESC 001 1111 1001 259– 549

PROCESSOR CONTROL

FINIT eInitialize NPX ESC 011 1110 0011 35

FSTSW AX eStore status word ESC 111 1110 0000 17

FLDCW eLoad control word ESC 001 MOD 101 R/M DISP 23

FSTCW eStore control word ESC 001 MOD 111 R/M DISP 21

FSTSW eStore status word ESC 101 MOD 111 R/M DISP 21

FCLEX eClear exceptions ESC 011 1110 0010 13

FSTENV eStore environment ESC 001 MOD 110 R/M DISP 146

FLDENV eLoad environment ESC 001 MOD 100 R/M DISP 113

FSAVE eSave state ESC 101 MOD 110 R/M DISP 550

FRSTOR eRestore state ESC 101 MOD 100 R/M DISP 482

FINCSTP eIncrement stack pointer ESC 001 1111 0111 23

FDECSTP eDecrement stack pointer ESC 001 1111 0110 24

FFREE eFree ST(i) ESC 101 1100 0 ST(i) 20

FNOP eNo operations ESC 001 1101 0000 14

Shaded areas indicate instructions not available in 8087.

NOTES:

j. These timings hold for operands in the range

kq/4. For operands not in this range, up to 78 clocks may be needed to

reduce the operand.

k. 0 s

ST(0)

k263.

l. b1.0 sST(0) s1.0.

m. 0 sST(0) k%,b%kST(1) ka%.

n. 0 s

ST(0)

k(2 b

(2))/2, b%kST(1) ka%.

DATA SHEET REVISION REVIEW

The following list represents the key differences between the -002 and the -001 version of the 80C187 data

sheet. Please review this summary carefully.

1. Figure 10, titled ‘‘System Configuration for 8087ÐCompatible Exception Trapping’’, was replaced with a

revised schematic. The previous configuration was faulty. Updated timing diagrams on Data Transfer Tim-

ing, Error Output, and RESET/BUSY.