LT3782
1
3782fg
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
2-Phase Step-UP
DC/DC Controller
The LT
®
3782 is a current mode two phase step-up DC/DC
converter controller. Its high switching frequency (up to
500kHz) and 2-phase operation reduce system fi ltering
capacitance and inductance requirements.
With 10V gate drive (VCC ≥13V) and 4A peak drive current,
the LT3782 can drive most industrial grade high power
MOSFETs with high effi ciency. For synchronous applica-
tions, the LT3782 provides synchronous gate signals with
programmable falling edge delay to avoid cross conduc-
tion when using external MOSFET drivers. Other features
include programmable undervoltage lockout, soft-start,
current limit, duty cycle clamp (50% or higher) and slope
compensation.
The LT3782 is available in thermally enhanced 28-lead
TSSOP and 4mm × 5mm QFN packages.
For new designs use the LT3782A which has improved
phase matching
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6144194.
n Industrial Equipment
n Telecom Infrastructure
n Interleaved Isolated Power Supply
n 2-Phase Operation Reduces Required Input and
Output Capacitance
n Programmable Switching Frequency:
150kHz to 500kHz
n 6V to 40V Input Range
n 10V Gate Drive with VCC ≥13V
n High Current Gate Drive (4A)
n Programmable Soft-Start and Current Limit
n Programmable Slope Compensation for
High Noise Immunity
n MOSFET Gate Signals with Programmable
Falling Edge Delay for External Synchronous
Drivers
n Programmable Undervoltage Lockout
n Programmable Duty Cycle Clamp (50% or Higher)
n Thermally Enhanced 28-Lead TSSOP and 4mm × 5mm
QFN Packages
50V 4A Boost Converter
3782 TA01
6.8nF
13k
0.1μF
10nF
CIN
10μF
50V
2x
RFREQ
80k
RSLOPE
59k
RS1
0.004Ω
M1
Si7852dp
2x
1μF
R8
274k
R6
825k COUT2
220μF
VOUT
50V, 4A
VIN
10V TO 36V
+
C3
2μF
+
RS2
0.004Ω
LT3782
VCC
RUN
SLOPE
DELAY
DCL
RSET
SS
VC
GBIAS2
GBIAS
BGATE1
VEE1
BGATE2
VEE2
SENSE1+
SENSE1–
SENSE2+
SENSE2–
FB
GND
M2
Si7852dp
2x
GBIAS1
10Ω
10nF
10Ω
RF1
475k
L1 D1
30BQ060
D2
30BQ060
L2
100pF
RF2
24.9k
COUT1
10μF
50V
2x
L1, L2: PB2020.223
CIN, COUT1: X7R, TDK
Effi ciency and Power Loss
vs Load Current
IOUT (A)
0
EFFICIENCY (%)
4
3782 TA01b
POWER LOSS (W)
18
15
12
9
6
3
0
1235
VIN = 12V
VIN = 12V
VIN = 24V
VIN = 24V
EFFICIENCY
POWER LOSS
97
93
95
91
89
87
85
NOT RECOMMENDED FOR NEW DESIGNS
Contact Linear Technology for Potential Replacement
LT3782
2
3782fg
TJMAX = 125°C, θJA = 38°C/ W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
VCC Supply Voltage ...................................................40V
GBIAS, GBIAS1, GBIAS2 Pin
(Externally Forced) ....................................................14V
SYNC, RUN Pin .........................................................30V
Operating Junction Temperature
Range (Notes 2, 3) ................................. –40°C to 125°C
(Note 1)
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
SS ................................................................ –0.3V to 6V
SENSE1+, SENSE2+,
SENSE1–, SENSE2– ..................................... –0.3V to 2V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SGATE2
SGATE1
NC
GND
SYNC
DELAY
DCL
SENSE1
+
SENSE1
–
SLOPE
R
SET
SENSE2
–
SENSE2
+
SS
GBIAS
V
CC
NC
NC
V
EE1
BGATE1
GBIAS1
GBIAS2
BGATE2
V
EE2
NC
RUN
FB
V
C
29
9 10
TOP VIEW
29
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
SYNC
DELAY
DCL
SENSE1
+
SENSE1
–
SLOPE
R
SET
SENSE2
–
BGATE1
GBIAS1
NC
NC
GBIAS2
BGATE2
V
EE2
NC
GND
SGATE1
SGATE2
GBIAS
V
CC
V
EE1
NC
SENSE2
+
SS
V
C
FB
RUN
7
17
18
19
20
21
22
16
815
TJMAX = 125°C, θJA = 37°C/ W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3782EFE#PBF LT3782EFE#TRPBF LT3782EFE 28-Lead Plastic TSSOP –40°C to 85°C
LT3782IFE#PBF LT3782IFE#TRPBF LT3782IFE 28-Lead Plastic TSSOP –40°C to 125°C
LT3782EUFD#PBF LT3782EUFD#TRPBF 3782 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3782EFE LT3782EFE#TR LT3782EFE 28-Lead Plastic SSOP –40°C to 85°C
LT3782IFE LT3782IFE#TR LT3782IFE 28-Lead Plastic SSOP –40°C to 125°C
LT3782EUFD LT3782EUFD#TR 3782 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LT3782
3
3782fg
The ● denotes the specifi cations which apply over the full operating junction
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 13V, RSET = 80k, no load on any outputs, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Overall
Supply Voltage (VCC)l640V
Supply Current (IVCC)V
C ≤ 0.5V (Switching Off), VCC ≤ 40V 11 16 mA
Shutdown
RUN Threshold l2.3 2.45 2.6 V
RUN Threshold Hysteresis 80 mV
Supply Current in Shutdown 1V ≤ RUN ≤ VREF, VCC ≤ 30V
RUN ≤ 0.3V, VCC ≤ 30V
0.4
40
0.65
90
mA
μA
RUN Pin Input Current VRUN = 2.3V l–0.5 –2 μA
Voltage Amplifi er gm
Reference Voltage (VREF)
l
2.42
2.4
2.44 2.464
2.488
V
V
Transconductance VVC = 1V, ΔIVC = ±2μA l200 260 370 μmho
Input Current IFB VFB = VREF l0.2 0.6 μA
VC High IVC = 0 1.5 V
VC Low IVC = 0 0.35 0.4 V
Source Current IVC VVC = 0.7V – 1V, VFB = VREF – 100mV 8 11 14 μA
Sink Current IVC VVC = 0.7V – 1V, VFB = VREF + 100mV 13 20 28 μA
VC Threshold for Switching Off (BGATE1, BGATE2 Low) l0.3 V
Soft-Start Current ISS VSS = 0.1V – 2.8V 6 10 15 μA
Current Amplifi er CA1, CA2
Voltage Gain ΔVC/ΔVSENSE 4
Current Limit (VSENSE1+ – VSENSE1–) (VSENSE2+ – VSENSE2–) 506280 mV
Input Current (ISENSE1+, ISENSE1–, ISENSE2+, ISENSE2–)ΔV
SENSE = 0V 60 μA
Oscillator
Switching Frequency RSET = 130k
RSET = 80k
RSET = 40k
l
l
l
130
212
386
154
250
465
177
288
533
kHz
kHz
kHz
Synchronization Pulse Threshold on SYNC Pin Rising Edge VSYNC 0.8 1.2 2 V
Synchronization Frequency Range
(Note: Operation Switching Frequency Equals
Half of the Synchronization Frequency)
RSET = 130k
RSET = 80k
RSET = 40k
180
290
550
240
392
715
kHz
kHz
kHz
VRSET RSET = 80k 2.3 V
Maximum Duty Cycle VFB = VREF – 25mV, RSET > 80k
RSET = 40k
l
l
90
83
94
90
%
%
Duty Cycle Limit RSET = 80k, VDCL ≤ 0.3V
VDCL = 1.2V
VDCL = VRSET
50
75
Max Duty Cycle
%
%
DCL Pin Input Current VDCL ≤ 0.3V l–0.1 –0.3 μA
ELECTRICAL CHARACTERISTICS
LT3782
4
3782fg
The ● denotes the specifi cations which apply over the full operating junction
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 13V, RSET = 80k, no load on any outputs, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3782E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT3782I is guaranteed to
meet performance specifi cations over the full –40°C to 125°C operating
junction temperature range.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specifi ed maximum operating junction
temperature may impair device reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Driver
VGBIAS IGBIAS < 70mA l10.2 11 11.7 V
BGATE1, BGATE2 High Voltage 13V ≤ VCC ≤ 24V, IBGATE = –100mA
VCC = 8V, IBGATE = –100mA
l
l
7.8
3.8
9.2
5
10.5 V
V
BGATE1, BGATE2 Source Current (Peak) Capacitive Load >22μF
Capacitive Load >50μF
3
4
A
A
BGATE1, BGATE2 Low Voltage 8V ≤ VCC ≤ 24V, IBGATE = 100mA l0.5 0.7 V
BGATE1, BGATE2 Sink Current (Peak) Capacitive Load >22μF
Capacitive Load >50μF
3
4
A
A
SGATE1, SGATE2 High Voltage 8V ≤ VCC ≤ 24V, ISGATE = –20mA l4.5 5.5 6.7 V
SGATE1, SGATE2 Low Voltage 8V ≤ VCC ≤ 24V, ISGATE = 20mA 0.5 0.7 V
SGATE1, SGATE2 Peak Current 500pF Load 100 mA
Delay of BGATE High DELAY Pin and RSET Pin Shorted
VDELAY = 1V
VDELAY = 0.5V
VDELAY = 0.25V
100
150
250
500
ns
ns
ns
ns
Delay Pin Input Current VDELAY = 0.25V l–0.1 –0.3 μA
LT3782
5
3782fg
JUNCTION TEMPERATURE (°C)
0
REFERENCE VOLTAGE (V)
2.446
2.444
2.442
2.440
2.438
2.436
2.434
50 100 12575
3782 G05
25 150
VCC (V)
6
ICC (mA)
20
18
16
12
14
10
8
6
4
2
022
3782 G02
108 121620 26
14 18 30
24 28
V
CC
(V)
6
ΔV
REF
(mV)
30
3782 G03
12 18 24 27
915 21
3
2
1
0
–1
–2
–3
–4
–5
ΔFREQUENCY (kHz)
12
10
8
6
4
2
0
–2
–4
ΔFrequency
ΔV
REF
RFREQ (kΩ)
0
FREQUENCY (kHz)
600
500
400
300
200
100 160
3782 G04
4020 60 100 140
80 120 200
180
TIME (s)
0
V
GBIAS
(V)
14
10
6
2
12
8
4
0
–2
I
GBIAS
(mA)
800
600
400
200
700
500
300
100
0
750μ
3782 G06
250μ 500μ 1m
V
GBIAS
I
GBIAS
VDELAY (V)
0
DELAY (ns)
1000
900
800
600
700
500
400
300
200
100
02.0
3782 G07
0.5 1.0 1.5 2.5
SWITCHING FREQUENCY (kHz)
100
DUTY CYCLE (%)
105
100
95
90
85
80 500
3782 G08
200 300 400 600
V
DCL
(V)
0
MAXIMUM DUTY CYCLE (%)
2.4
3782 G09
0.6 1.2 1.8 2.1
0.3 0.9 1.5
120
110
100
90
80
70
60
50
40
IGBIAS (mA)
0
VGBIAS (V)
10.5
100
3782 G01
10.0
10.6
10.1
10.7
10.2
10.8
10.3
10.9
10.4
50
11.0
VGBIAS vs IGBIAS ICC vs VCC
ΔVREF vs VCC, ΔFrequency vs VCC
(RSET = 80k)
Switching Frequency vs RFREQ
Reference Voltage
vs Temperature
VGBIAS vs IGBIAS at Start-Up
(Charging 2μF)
SGATE (Low) to BGATE (High)
Delay vs VDELAY (RSET = 80k)
Switching Frequency
vs Duty Cycle
Maximum Duty Cycle Limit vs
VDCL (RSET = 80k)
TA = 25°C unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
LT3782
6
3782fg
SGATE2 (Pin 1/Pin 26): Second Phase Synchronous Drive
Signal. An external driver buffer is needed to drive the top
synchronous power FET.
SGATE1 (Pin 2/Pin 27): First Phase Synchronous Drive
Signal. An external driver buffer is needed to drive the top
synchronous power FET.
GND (Pin 4/Pin 28): Chip Ground.
SYNC (Pin 5/Pin 1): Synchronization Input. The pulse
width can range from 10% to 70%. Note that the operating
frequency is half of the sync frequency.
DELAY (Pin 6/Pin 2): When synchronous drivers are used,
the programmable delay that delays BGATE turns on after
SGATE turns off.
DCL (Pin 7/Pin 3): This pin programs the limit of the maxi-
mum duty cycle. When connected to VRSET
, it operates at
natural maximum duty cycle, approximately 90%.
SENSE1+ (Pin 8/Pin 4): First Phase Current Sense Amplifi er
Positive Input. An RC fi lter is required across the current
sense resistor. Current limit threshold is set at 60mV.
SENSE1– (Pin 9/Pin 5): First Phase Current Sense Amplifi er
Negative Input. An RC fi lter is required across the current
sense resistor.
SLOPE (Pin 10/Pin 6): A resistor from SLOPE to GND
increases the internal current mode PWM slope com-
pensation.
RSET (Pin 11/Pin 7): A resistor from RSET to GND sets the
oscillator charging current and the operating frequency.
SENSE2– (Pin 12/Pin 8): Second Phase Current Sense
Amplifi er Negative Input. An RC fi lter is required across
the current sense resistor.
SENSE2+ (Pin 13/Pin 10): Second Phase Current Sense
Amplifi er Positive Input. An RC fi lter is required across
the current sense resistor. Current limit threshold is set
at 60mV.
SS (Pin 14/Pin 11): Soft-Start. A capacitor on this pin sets
the output ramp up rate. The typical time for SS to reach
the programmed level is (C • 2.44V)/10μA.
VC (Pin 15/Pin 12): The output of the gm error amplifi er and
the control signal of the current loop of the current-mode
PWM. Switching starts at 0.7V, and higher VC voltages
corresponds to higher inductor current.
FB (Pin 16/Pin 13): Error Amplifi er Inverting Input. A
resistor divider to this pin sets the output voltage.
RUN (Pin 17/Pin 14): LT3782 goes into shutdown mode
when VRUN is below 2.2V and goes to low bias current
shutdown mode when VRUN is below 0.3V.
VEE2 (Pin 19/Pin 16): Gate Driver BGATE2 Ground. This
pin should be connected to the ground side of the second
current sense resistor.
BGATE2 (Pin 20/Pin 17): Second Phase MOSFET Driver.
GBIAS2 (Pin 21/Pin 18): Bias for Gate Driver BGATE2.
Should be connected to GBIAS or an external power supply
between 12V to 14V. A bypass low ESR capacitor of 2μF
or larger is needed and should be connected directly to
the pin to minimize parasitic impedance.
GBIAS1 (Pin 22/Pin 21): Bias for Gate Driver BGATE1.
Should be connected to GBIAS2.
BGATE1 (Pin 23/Pin 22): First Phase MOSFET Driver.
VEE1 (Pin 24/Pin 23): Gate Driver BGATE1 Ground. This
pin should be connected to the ground side of the second
current sense resistor.
VCC (Pin 27/Pin 24): Chip Power Supply. Good supply
bypassing is required.
GBIAS (Pin 28/Pin 25): Internal 11V regulator output for
biasing internal circuitry. Should be connected to GBIAS1
and GBIAS2.
Exposed Pad (Pin 29/Pin 29): The exposed package pad
is fused to internal ground and is for heat sinking. Solder
the bottom metal plate onto expanded ground plane for
optimum thermal performance.
NC (Pins 3, 18, 25, 26/Pins 9, 15, 19, 20): Not Connected.
Can be connected to GND.
(FE/UFD)
PIN FUNCTIONS
LT3782
7
3782fg
GBIAS2
R2
50k
A18
ONE SHOT
A19 A2
60mV
CH1
CL1
PWM1
A3
R3
3782 BD
C2
2nF
CIN
20μF
RFREQ
RS1
M1
R8
R6
COUT
100μF
VOUT
VIN
+
C3
2μF
RS2
VCC
RUN
SYNC
DELAY
DELAY
DELAY
SLOPE
RSET
DCL
RSET
GND
C1
2000pF
R5
2k C7
10nF
GBIAS2
GBIAS
GBIAS1
BGATE1
BGATE1
BGATE1
SGATE1
BGATE2
VEE1
VEE2
VREF
SENSE1+
SENSE1–
SENSE2+
SENSE2–
FB
M2
GBIAS1
R7
10Ω
C4
2nF
R9
10Ω
RF2
RF1
R1
50k
L1
15μ D1
D2
L2
15μ
–
+
–
+
6
5
17
27
10
7VC15 SS 14
11
4
SGATE1
SGATE2
1
2
22
21
28
23
8
9
24
20
13
12
19
16
REGULATOR
SLOPE
COMP
OSC
LOGIC
QCK
QD
CH1
SET
RS
7V
+
–
+
0.5V
+
–
+
2.44V
+
–
+
2.5V
+
VCC – 2.5V
A6
A11
A12
A5
A7
A8
LOW POWER
SHUTDOWN
VGBIAS = VCC – 1V AND CLAMPED AT 11V
NOTE:
PACKAGE BOTTOM METAL PLATE (PIN 29)
IS FUSED TO CHIP DIE AGND
A20
A1A4
A17A15
A13
C5
20pF
+
ONE SHOT
BLANKING
A14 A9
–
+
–
+
SLOPE COMP
60mV
A10
R4
BLANKING
–
+
+
–
–
+
CH2
RS
SLOPE COMP
4V
BGATE2 –
+
2.5V
+
+
+
GM
D6
D7
D4 I1
10μA
CH2
CL2
PWM2
A16
SET
BLOCK DIAGRAM
LT3782
8
3782fg
Operation
The LT3782 is a two phase constant frequency current mode
boost controller. Switching frequency can be programmed
up to 500kHz. During normal switching cycles, the two
channels are controlled by internal fl ip-fl ops and are 180
degrees out-of-phase.
Referring to the Block Diagram, the LT3782’s basic func-
tions include a transconductance amplifer (gm) to regulate
the output voltage and to control the current mode PWM
current loop. It also includes the necessary logic and fl ip-
fl op to control the PWM switching cycles, two high speed
gate drivers to drive high power N-Channel MOSFETs, and
2-phase control signals to drive external gate drivers for
optional synchronous operation.
In normal operation, each switching cycle starts with a
switch turn-on. The inductor current of each channel is
sampled through the current sense resistor and amplifi ed
then compared to the error amplifi er output VC to turn
the switch off. The phase delay of the second channel is
controlled by the divide-by-two D fl ip-fl op and is exactly
180 degrees out-of-phase of the fi rst channel. With a re-
sistor divider connected to the FB pin, the output voltage
is programmed to the desired value. The 10V gate drivers
are suffi cient to drive most high power N-channel MOSFET
in many industrial applications.
Additional important features include shutdown, cur-
rent limit, soft-start, synchronization and programmable
maximum duty cycle. Additional slope compensation can
be added also.
Output Voltage Programming
With a 2.44V feedback reference voltage VREF
, the output
VOUT is programmed by a resistor divider as shown in
the Block Diagram.
VOUT =2.44 1+RF1
RF2
Soft-Start and Shutdown
During soft-start, the voltage on the SS pin (VSS) controls
the output voltage. The output voltage thus ramps up fol-
lowing VSS. The effective range of VSS is from 0V to 2.44V.
The typical time for the output to reach the programmed
level is
t=C • 2.44V
10μA
C is the capacitor connected from the SS pin to Gnd.
Undervoltage Lockout and Shutdown
Only when VRUN is higher than 2.45V VGBIAS will be ac-
tive and the switching enabled. The LT3782 goes into low
current shutdown when VRUN is below 0.3V. A resistor
divider can be used on RUN pin to set the desired VCC
undervoltage lockout voltage. 80mV of hysteresis is built
in on RUN pin thresholds.
Oscillation Frequency Setting and Synchronization
The switching frequency of LT3782 can be set up to 500kHz
by a resistor RFREQ from pin RSET to ground.
For fSET = 250kHz, RFREQ = 80k
Once the switching frequency fSET is chosen, RFREQ can be
found from the Switching Frequency vs RFREQ graph found
under the Typical Performance Characteristics section.
Note that because of the 2-phase operation, the internal
oscillator is running at twice the switching frequency. To
synchronize the LT3782 to the system frequency fSYSTEM,
the synchronizing frequency fSYNC should be two times
fSYSTEM, and the LT3782 switching frequency fSET should
be set below 80% of fSYSTEM.
f
SYNC = 2fSYSTEM and fSET < (fSYSTEM • 0.8)
For example, to synchronize the LT3782 to 200kHz system
frequency fSYSTEM, fSYNC needs to be set at 400kHz and fSET
needs to be set at 160kHz. From the Switching Frequency
vs RFREQ graph found under the Typical Performance
Characteristics section, RFREQ = 130k.
APPLICATIONS INFORMATION
LT3782
9
3782fg
With a 200ns one-shot timer on chip, the LT3782 provides
fl exibility on the external sync pulse width. The sync pulse
threshold is about 1.2V (Figure 1).
Current Limit
Current limit is set by the 60mV threshold across SEN1P,
SEN1N for channel one and SEN2P, SEN2N for channel
two. By connecting an external resistor RS (see Block
Diagram), the current limit is set for 60mV/RS. RS should
be placed very close to the power switch with very short
traces. A low pass RC fi lter is needed across RS to fi lter out
the switching spikes. Good Kelvin sensing is required for
accurate current limit. The input bypass capacitor ground
should be at the same ground point of the current sense
resistor to minimize the ground current path.
Synchronous Rectifi er Switches
For high output voltage applications, the power loss of
the catch diodes are relatively small because of high duty
cycle. If diodes power loss or heat is a concern, the LT3782
provides PWM signals through SGATE1 and SGATE2 pins
to drive external MOSFET drivers for synchronous recti-
fi er operation. Note that SGATE drives the top switch and
BGATE drives the bottom switch. To avoid cross conduction
between top and bottom switches, the BGATE turn-on is
delayed 100ns (when DELAY pin is tied to RSET pin) from
SGATE turn-off (see Figure 2). If a longer delay is needed
to compensate for the propagation delay of external gate
driver, a resistor divider can be used from RSET to ground to
program VDELAY for the longer delay needed. For example,
for a switching frequency of 250kHz and delay of 150ns,
Figure 1. Synchronizing with External Clock
Figure 2. Delay Timing
3782 F02
DELAY
BGATE1
SGATE1
SET
APPLICATIONS INFORMATION
LT3782
10
3782fg
then RFREQ1 + RFREQ2 should be 80k and VDELAY should
be 1V, with VRSET = 2.3V then RFREQ1 = 47.5k and RFREQ2
= 32.5k (see Figure 3).
Duty Cycle Limit
When DCL pin is shorted to RSET pin and switching fre-
quency is less than 250kHz (RFREQ > 80k), the maximum
duty cycle of LT3782 will be at least 90%. The maximum
duty cycle can be clamped to 50% by grounding the DCL
pin or to 75% by forcing the VDCL voltage to 1.2V with a
resistor divider from RSET pin to ground. The typical DCL
pin input current is 0.2μA.
Slope Compensation
The LT3782 is designed for high voltage and/or high
current applications, and very often these applications
generate noise spikes that can be picked up by the cur-
rent sensing amplifi er and cause switching jitter. To avoid
switching jitter, careful layout is absolutely necessary to
minimize the current sensing noise pickup. Sometimes
increasing slope compensation to overcome the noise
can help to reduce jitter. The built-in slope compensa-
tion can be increased by adding a resistor RSLOPE from
SLOPE pin to ground. Note that smaller RSLOPE increases
slope compensation and the minimum RSLOPE allowed is
RFREQ/2.
Layout Considerations
To prevent EMI, the power MOSFETs and input bypass
capacitor leads should be kept as short as possible. A
ground plane should be used under the switching circuitry
to prevent interplane coupling and to act as a thermal
spreading path. Note that the bottom pad of the package
is the heat sink, as well as the IC signal ground, and must
be soldered to the ground plane.
In a boost converter, the conversion gain (assuming 100%
effi ciency) is calculated as (ignoring the forward voltage
drop of the boost diode):
VOUT
VIN
=1
1−D
where D is the duty ratio of the main switch. D can then
be estimated from the input and output voltages:
D=1−VIN
VOUT
;D
MAX =1−VIN(MIN)
VOUT
Figure 3. Increase Delay Time
R
SET
DELAY
LT3782
R
FREQ2
32.5k
R
FREQ1
47.5k
3782 F03
APPLICATIONS INFORMATION
LT3782
11
3782fg
The Peak and Average Input Currents
The control circuit in the LT3782 measures the input current
by using a sense resistor in each MOSFET source, so the
output current needs to be refl ected back to the input in
order to dimension the power MOSFET properly. Based
on the fact that, ideally, the output power is equal to the
input power, the maximum average input current is:
IIN(MAX) =IO(MAX)
1–DMAX
The peak current is:
IIN(PEAK) =1.2 • IO(MAX)
1–DMAX
The maximum duty cycle, DMAX, should be calculated at
minimum VIN.
Power Inductor Selection
In a boost circuit, a power inductor should be designed
to carry the maximum input DC current. The inductance
should be small enough to generate enough ripple current
to provide adequate signal to noise ratio to the LT3782.
An empirical starting of the inductor ripple current (per
phase) is about 40% of maximum DC current, which is
half of the input DC current in a 2-phase circuit:
ΔIL≅40% • IOUT(MAX) •V
OUT
2V
IN
=20% • IOUT(MAX) •V
OUT
VIN
where VIN, VOUT and IOUT are the DC input voltage, output
voltage and output current, respectively.
And the inductance is estimated to be:
L=VIN •D
fs•ΔIL
where fs is the switching frequency per phase.
The saturation current level of inductor is estimated to
be:
ISAT ≥ΔIL
2+IIN
2≅70% • IOUT(MAX) •V
OUT
VIN(MIN)
Sense Resistor Selection
During the switch on-time, the control circuit limits the
maximum voltage drop across the sense resistor to about
60mV. The peak inductor current is therefore limited to
60mV/R. The relationship between the maximum load
current, duty cycle and the sense resistor RSENSE is:
R≤VSENSE(MAX) •1–DMAX
1.2 • IO(MAX)
2
Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-source breakdown voltage (BVDSS), the threshold
voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-
to-source voltage, the gate-to-source and gate-to-drain
charges (QGS and QGD, respectively), the maximum drain
current (ID(MAX)) and the MOSFET’s thermal resistances
(RTH(JC) and RTH(JA)).
APPLICATIONS INFORMATION
LT3782
12
3782fg
The gate drive voltage is set by the 10V GBIAS regulator.
Consequently, 10V rated MOSFETs are required in most
high voltage LT3782 applications.
Pay close attention to the BVDSS specifi cations for the
MOSFETs relative to the maximum actual switch voltage
in the application. The switch node can ring during the
turn-off of the MOSFET due to layout parasitics. Check the
switching waveforms of the MOSFET directly across the
drain and source terminals using the actual PC board layout
(not just on a lab breadboard!) for excessive ringing.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be known.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
the positive temperature coeffi cient of its RDS(ON)). As a
result, some iterative calculation is normally required to
determine a reasonably accurate value. Care should be
taken to ensure that the converter is capable of delivering
the required load current over all operating conditions (line
voltage and temperature), and for the worst-case speci-
fi cations for VSENSE(MAX) and the RDS(ON) of the MOSFET
listed in the manufacturer’s data sheet.
The power dissipated by the MOSFET in a 2-phase boost
converter is:
PFET =
IO(MAX)
2
1–D
( )
2
•RDS(ON) •D•T
+k•V
O2•
IO(MAX)
2
1–D
( )
•C
RSS •f
The fi rst term in the equation above represents the I2R
losses in the device, and the second term, the switching
losses. The constant, k = 1.7, is an empirical factor inversely
related to the gate drive current and has the dimension
of 1/current. The ρT term accounts for the temperature
coeffi cient of the RDS(ON) of the MOSFET, which is typically
0.4%/°C. Figure 4 illustrates the variation of normalized
RDS(ON) over temperature for a typical power MOSFET.
JUNCTION TEMPERATURE (°C)
–50
ρT
NORMALIZED ON RESISTANCE
1.0
1.5
150
3782 F06
0.5
0050 100
2.0
Figure 4. Normalized RDS(ON) vs Temperature
APPLICATIONS INFORMATION
LT3782
13
3782fg
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T
J = TA + PFET • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
Input Capacitor Choice
The input capacitor must have high enough voltage and
ripple current ratings to handle the maximum input voltage
and RMS ripple current rating. The input ripple current in
a boost circuit is very small because the input current is
continuous. With 2-phase operation, the ripple cancellation
will further reduce the input capacitor ripple current rating.
The ripple current is plotted in Figure 5. Please note that
the ripple current is normalized against
Inorm =VIN
L•f
s
Output Capacitor Selection
The voltage rating of the output capacitor must be greater
than the maximum output voltage with suffi cient derat-
ing. Because the ripple current in output capacitor is a
pulsating square wave in a boost circuit, it is important
that the ripple current rating of the output capacitor be
high enough to deal with this large ripple current. Figure
6 shows the output ripple current in the 1- and 2-phase
designs. As we can see, the output ripple current of a
2-phase boost circuit reaches almost zero when the duty
cycle equals 50% or the output voltage is twice as much as
the input voltage. Thus the 2-phase technique signifi cantly
reduces the output capacitor size.
Figure 6. Normalized Output RMS Ripple Currents in Boost
Converter: 1-Phase and 2-Phase. IOUT Is the DC Output Current.
0.1
I
ORIPPLE
/I
OUT
0.9
3782 F05
0.3 0.5 0.7 0.8
0.2 0.4 0.6
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
DUTY CYCLE OR (1-V
IN
/V
OUT
)
1-PHASE
2-PHASE
Figure 5. Normalized Input Peak-to-Peak Ripple Current
DUTY CYCLE
0
ΔIIN/INORM
1.00
0.90
0.80
0.60
0.70
0.50
0.40
0.30
0.20
0.10
00.8
3782 F04
0.2 0.4 0.6 1.0
1-PHASE
2-PHASE
APPLICATIONS INFORMATION
Inorm =VIN
L•f
s
The RMS Ripple Current is About 29% of
the Peak-to-Peak Ripple Current.
LT3782
14
3782fg
For a given VIN and VOUT
, we can calculate the duty cycle D
and then derive the output RMS ripple current from Figure
6. After choosing output capacitors with suffi cient RMS
ripple current rating, we also need to consider the ESR
requirement if electrolytic caps, tantulum caps, POSCAPs
or SP CAPs are selected. Given the required output ripple
voltage spec ΔVOUT (in RMS value) and the calculated RMS
ripple current ΔIOUT
, one can estimate the ESR value of
the output capacitor to be
ESR≤ΔVOUT
ΔIOUT
External Regulator to Bias Gate Drivers
For applications with VIN higher than 24V, the IC temperature
may get too high. To reduce heat, an external regulator
between 12V to 14V should be used to override the internal
VGBIAS regulator to supply the current needed for BGATE1
and BGATE2 (see Figure 7).
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the out-
put power divided by the input power (¥100%). Percent
effi ciency can be expressed as:
% Effi ciency = 100% – (L1 + L2 + L3 + …),
where L1, L2, etc. are the individual loss components
as a percentage of the input power. It is often useful to
analyze individual losses to determine what is limiting
the effi ciency and which change would produce the most
improvement. Although all dissipative elements in the
circuit produce losses, four main sources usually ac-
count for the majority of the losses in LT3782 application
circuits:
1. The supply current into VIN. The VIN current is the sum
of the DC supply current IQ (given in the Electrical Char-
acteristics) and the MOSFET driver and control currents.
The DC supply current into the VIN pin is typically about
7mA and represents a small power loss (much less
than 1%) that increases with VIN. The driver current
results from switching the gate capacitance of the power
MOSFET; this current is typically much larger than the
DC current. Each time the MOSFET is switched on and
then off, a packet of gate charge QG is transferred from
GBIAS to ground. The resulting dQ/dt is a current that
must be supplied to the GBIAS capacitor through the
VIN pin by an external supply. In normal operation:
I
Q(TOT) ≈ IQ = f • QG
P
IC = VIN • (IQ + f • QG)
Figure 7
3782 F07 2μF
12V
+
GBIAS
GBIAS1
GBIAS2
LT3782
APPLICATIONS INFORMATION
LT3782
15
3782fg
2. Power MOSFET switching and conduction losses:
P
FET =
IO(MAX)
2
1–DMAX
2
•RDS(ON) •D
MAX •T
+k•V
O2•
IO(MAX)
2
1–DMAX
•C
RSS •f
3. The I2R losses in the sense resistor can be calculated
almost by inspection.
P
R(SENSE) =
IO(MAX)
2
1–DMAX
2
•R•D
MAX
4. The losses in the inductor are simply the DC input cur-
rent squared times the winding resistance. Expressing
this loss as a function of the output current yields:
P
R(WINDING) =
IO(MAX)
2
1–DMAX
2
•RW
5. Losses in the boost diode. The power dissipation in the
boost diode is:
P
DIODE =IO(MAX)
2•V
D
The boost diode can be a major source of power loss
in a boost converter. For 13.2V input, 42V output at 3A,
a Schottky diode with a 0.4V forward voltage would
dissipate 600mW, which represents about 1% of the
input power. Diode losses can become signifi cant at
low output voltages where the forward voltage is a
signifi cant percentage of the output voltage.
6. Other losses, including CIN and CO ESR dissipation and
inductor core losses, generally account for less than
2% of the total losses.
PCB Layout Considerations
To achieve best performance from an LT3782 circuit, the
PC board layout must be carefully done. For lower power
applications, a two-layer PC board is suffi cient. However,
at higher power levels, a multiplayer PC board is recom-
mended. Using a solid ground plane under the circuit is
the easiest way to ensure that switching noise does not
affect the operation.
In order to help dissipate the power from MOSFETs and
diodes, keep the ground plane on the layers closest to the
layers where power components are mounted. Use power
planes for MOSFETs and diodes in order to improve the
spreading of the heat from these components into the
PCB.
APPLICATIONS INFORMATION
LT3782
16
3782fg
For best electrical performance, the LT3782 circuit should
be laid out as follows:
Place all power components in a tight area. This will
minimize the size of high current loops. Orient the input
and output capacitors and current sense resistors in a way
that minimizes the distance between the pads connected
to ground plane.
Place the LT3782 and associated components tightly to-
gether and next to the section with power components.
Use a local via to ground plane for all pads that connect to
ground. Use multiple vias for power components.
Connect the current sense inputs of LT3782 directly to the
current sense resistor pads. Connect the current sense
traces on the opposite sides of pads from the traces
carrying the MOSFETs source currents to ground. This
technique is referred to as Kelvin sensing.
APPLICATIONS INFORMATION
LT3782
17
3782fg
IOUT (A)
0
EFFICIENCY (%)
100
96
98
94
92
90
88
86 7
3782 TA02b
12 4 6
358
12VIN
15VIN
Effi ciency
10Ω
CS2
C
OUT2
330μF, 35V, 2x
+
27
26
25
24
23
22
21
20
19
18
17
16
15
28
2
3
4
5
6
7
8
9
10
11
12
13
14
1
10Ω
CS1
59k
82k
274k
825k
2R2
24.9k
221k
R
C1
13.3k
10nF
4.7nF
C
C2
100pF
C
C1
6.8nF
2.2μF C
IN
22μF
25V
C
OUT1
22μF, 25V, 4x
10nF
1μF
3782 TA02
10V TO 24V INPUT
Q1
PH3330
Q2
PH3330
OUTPUT
24V
8A
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
*OUTPUT CURRENT WITH BOTH INPUTS PRESENT
L1
PB2020-103 D1
UPS840
L2
PB2020-103 D2
UPS840
CS1
CS2
0.004Ω
0.004Ω
• •
LT3782
V
CC
NC
NC
V
EE1
BGATE1
GBIAS1
GBIAS2
BGATE2
V
EE2
NC
RUN
FB
V
C
GBIAS
SGATE1
NC
GND
SYNC
DELAY
DCL
SENSE1
+
SENSE1
–
SLOPE
R
SET
SENSE2
–
SENSE2
+
SS
SGATE2
10V to 24V Input to 24V, 8A Output Boost Converter
TYPICAL APPLICATIONS
LT3782
18
3782fg
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
FE28 (EB) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678910
11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
2.74
(.108)
28 2726 25 24 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.75
(.187)
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
PACKAGE DESCRIPTION
LT3782
19
3782fg
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
4.00 ± 0.10
(2 SIDES)
2.50 REF
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
2.65 ± 0.10
3.65 ± 0.10
3.65 ± 0.05
PACKAGE DESCRIPTION
LT3782
20
3782fg
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0109 REV G • PRINTED IN USA
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10Ω
CS2
C
OUT2
330μF, 35V, 2x
+
BAS516
27
26
25
24
23
22
21
20
19
18
17
16
15
28
2
3
4
5
6
7
8
9
10
11
12
13
14
1
10Ω
CS1
59k
82k
274k
825k
2R2
24.9k
261k
R
C1
15k
10nF
C
INA
22μF
C
INB
22μF
4.7nF
C
C2
100pF
C
C1
4.7nF
2.2μF C
OUT1
10μF, 50V, 4x
10nF
BAS516
1μF
3782 TA03
V
INB
0V TO 28V*
V
INA
0V TO 28V*
Q1
PH4840S
Q2
PH4840S
OUTPUT
28V
4A (8A**)
NOTE:
*INPUT VOLTAGE RANGE FOR VINA AND VINB IS 0V TO 28V.
AT LEAST ONE OF THE INPUTS MUST BE 12V OR HIGHER.
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
**OUTPUT CURRENT WITH BOTH INPUTS 12V OR HIGHER
L1
10μH D1
UPS840
L2
10μH D2
UPS840
CS1
CS2
0.004Ω
0.004Ω
• •
LT3782
V
CC
NC
NC
V
EE1
BGATE1
GBIAS1
GBIAS2
BGATE2
V
EE2
NC
RUN
FB
V
C
GBIAS
SGATE1
NC
GND
SYNC
DELAY
DCL
SENSE1
+
SENSE1
–
SLOPE
R
SET
SENSE2
–
SENSE2
+
SS
SGATE2
28V Output Base Station Power Converter with Redundant Input
PolyPhase is a registered trademark of Linear Technology Corporation. ThinSOT and No RSENSE are trademarks of Linear Technology Corporation.
TYPICAL APPLICATIONS