1:10 Clock Fanout Buffer
COMLINK™ SERIES
CY2CC810
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07056 Rev. *C Revised December 14, 2002
Features
•Low-voltage operation
•VDD range from 2.5V to 3.3V
•1:10 fanout
•Over voltage tolerant input hot swappable
•Drives either a 50-Ohm or 75-Ohm transmission line
•Low-input capacitance
•Low-output skew
•Low-propagation delay
•Typical (tpd < 4 ns)
•High-speed operation > 500 MHz
•Industrial versions availa ble
•A v aila ble packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cy pres s CY2 C C810 fano ut buffer feature s on e in put a nd
ten outputs. Designed for data communications clock
manag ement app lications , the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance matching and eliminate the need for series
damping resistors; they also reduce noise overall.
Pin Description
Pin Number Pin Name Description
1 IN Input LVCMOS
2, 6, 10, 13, 17 GND Ground Power
4, 8, 15, 20 VDD Power Supply Power
3, 5, 7, 9, 11, 12, 14, 16, 18, 19 Q1... Q10 Output AVCMOS
Block Diagram Pin Configuration
OUTPUT
(AVCMOS)
IN
Q1
Q5
Q7
Q6
Q4
Q3
Q2
Q8
Q9
Q10
GND
VDD
INPUT
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CY2CC810
20 pin SOIC/SSOP
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
COMLINK™ SERI ES
CY2CC810
Document #: 38-07056 Rev. *C Page 2 of 7
Maximum Ratings[1][2]
Storage Temperature: ................................–65°C to + 150°C
Ambient Temperature:...................................–40°C to +85°C
Supply Voltage to Ground Potential
VCC .................................................................. –0.5V to 4.6V
Input.................................................................–0.5V to 5.8V
Supply Voltage to Ground Potential
(Outputs only)...........................................–0.5V to VDD + 1V
DC Output Voltage....................................–0.5V to VDD + 1V
Power Dissipation........................................................0.75 W
Notes:
1. S tresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Characteristics @ 3.3V (see Figure 5)
Parameter Description Conditions Min. Typ. Max. Unit
VOH Output Hi gh Voltage VDD = Min., VIN = V IH or VIL IOH = –12 mA 2.3 3.3 V
VOL Output Low Voltage VDD = Min., VIN = VIH or VIL IOL = 12 mA 0.2 0.5 V
VIH Input High Voltage Guaranteed Logic High Level 2 5.8 V
VIL Input Low Vol tage Guaranteed Logic Low Level 0.8 V
IIH Input High Current VDD = Max. VIN = 2.7V 1 uA
IIL Input Low Current VDD = Max. VIN = 0.5V –1uA
IIInput High Current VDD = Max., VIN = VDD(Max.) 20 uA
VIK Clamp Diod e Volt a ge VDD = Min., IIN = –18 mA –0.7 –1.2 V
IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA
OOFF Power-down Disable VDD = GND, VOUT = < 4.5V 100 uA
VHInput Hysteresis VDD = Min., VIN = VIH or VIL 80 mV
DC Electrical Characteristics @ 2.5V (see Figure 1)
Parameter Description Conditions Min. Typ. Max. Unit
VOH Output High Voltage VDD = M i n., V IN = VIH or VIL IOH = –7 mA 1.8 V
IOH = 12 mA 1.6 V
VOL Output Low Voltage VDD = Min., VIN = VIH or VIL IOL = 12 mA 0.65 V
VIH Input High Voltage Guaranteed Logic High Level 1.6 5.0 V
VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V
IIH Input High Current VDD = M a x. VIN = 2. 4V 1 uA
IIL Input Low Current VDD = Max. VIN = 0.5V –1uA
IIInput High Current VDD = Max., VIN = VDD(Max.) 20 uA
VIK Clamp Diode Voltage VDD = Mi n., IIN = –18 mA –0.7 –1.2 V
IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA
OOFF Power-down Disable VDD = GND, VOUT = < 4.5V 100 uA
VHInput Hysteresis 80 mV
Capacitance
Parameter Description Test Conditions Min. Typ. Max. Unit
Cin Input Capacitance VIN = 0V 2.5 pF
Cout Output Capacitance VOUT = 0V 6.5 pF
COMLINK™ SERI ES
CY2CC810
Document #: 38-07056 Rev. *C Page 3 of 7
Power Supply Characteristics (see Figure 5)
Parameter Description Test Conditions Min. Typ. Max. Unit
∆ICC Delta ICC Quiescent Power
Supply Curren t (IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD
= Max. and VIN = VDD – 0.6V) 50 uA
ICCD Dynamic Power Supply Current VDD = Max.
Input toggling 50% Duty Cycle, Outputs Open 0.63 mA/
MHz
ICTotal Power Supply Current VDD = Max.
Input toggling 50% Duty Cycle, Outputs Open
fL = 40 MHZ
25 mA
High-frequency Parametrics
Parameter Description Test Conditions Min. Typ. Max. Unit
DJJitter, Deterministic 50% duty cyc le tW(50–50)
The “point to point load circuit”
Output Jitter – Input Jitter
See Figure 5 20 ps
Fmax Maximum frequ ency
VDD = 3.3V 50% duty cycle tW(50–50)
Standard Load Circuit. 160 MHz
50% duty cycle tW(50–50)
The “point to point load circuit” See Figure 7 650
Fmax
2.5V Maximum f requency
VDD = 2.5 V The “point to point load circuit”
VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 7 200 MHz
Fmax(20) Maximum frequency
VDD = 3.3 V 20% duty cycle tW(20-80)
The “point to point load circuit”
VIN = 3.0V/0.0V VOUT = 2.3V/0.4V
See Figure 7 250 MHz
Maximum frequency
VDD = 2.5 V The “point to point load circuit”
VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 3 200 MHz
tWMinimum pulse
VDD = 3.3 V The “point to point load circuit”
VIN = 3.0V/0.0V F = 100 MHz
VOUT = 2.0V/0.8V
See Figure 7 1ns
Minimum pulse
VDD = 2.5 V The “point to point load circuit”
VIN = 2.4V/0.0V F = 100 MHz
VOUT = 1.7V/0.7V
See Figure 3 1
AC Switching Characteristics @ 3.3V VDD = 3.3V ±5%, Temperature = –40°C to +85°C
Parameter Description Min. Typ. Max. Unit
tPLH Propagation Delay – Low to High See Figure 4 1.5 2.7 3.5 nS
tPHL Propagation Delay – High to Low 1.5 2.7 3.5 nS
tROutput Rise Time 0.8 V/nS
tFOutput Fall Time 0.8 V/nS
tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.2 nS
tSK(p) Pulse Skew : Skew betw een op posite transit ions of the same output
(tPHL – tPLH). See Figure 9 0.2 nS
tSK(t) Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type. See Figure 11 0.4 nS
COMLINK™ SERI ES
CY2CC810
Document #: 38-07056 Rev. *C Page 4 of 7
Parameter Measurement Information:
VDD @2.5V Parameter Measurement Information:
VDD @3.3V
Notes:
3. CL includes probe and jig capacitance.
4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50W, tR < 2.5 nS, tF < 2.5 nS.
5. The outputs are measured one at a time with one transition per measurement.
6. TPLH and TPHL are the same as tpd.
AC Switching Characteristics @ 2.5V VDD = 2.5V ±5%, Temperature = –40°C to +85°C
Parameter Description Min. Typ. Max. Unit
tPLH Propagation Delay – Lo w to High See Figure 4 1.5 2.0 3.5 nS
tPHL Propagation Delay – High to Low 1.5 2.0 3.5 nS
tROutput Rise Time 0.8 V/nS
tFOutput Fall Time 0.8 V/nS
tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.2 nS
tSK(p) Pulse Skew: Skew between opposite transitions of the same output
(tPHL – tPLH). See Figure 9 0.2 nS
tSK(t) Package Skew: Skew between outputs of diffe rent packages at the
same power supply voltage, temperature and package type. See Figure 11 0.65 nS
From Output
Under Test
CL = 50 pF 500 ohm
Figure 1. Load Circuit [3,4,5]
2.0 V
0 V
Input tw(20-80)
2.0 V
0 V
1.25 V 1.25 V
Input tw(50-50)
1.25 V
Figure 2. Voltage Waveforms–Pulse Duration[6]
From Output
Under Test
CL = 3 pF 500 ohm
Figure 3. Point to Point Load Circuit[3,4,5]
1.0 V
1.25 V 1.25 V
1.0 V
tPLH tPHL
2.0 V
VOH
VOL
0 VInput
Output
Figure 4. Voltage Waveforms–
Propagation Delay Times[4]
From Output
Under Test
CL = 50 pF 500 ohm
Figure 5. Load Circuit [3,4,5]
2.7V
0 V
Input tw(20-80)
2.7V
0 V
1.5V 1.5V
Input tw(50-50)
1.5V
Figure 6. Voltage Waveforms–Pulse Duration[6]
From Output
Under Test
CL = 3 pF 500 ohm
Figure 7. Point to Point Load Circuit[3,4,5]
1.5V
1.5V 1.5V
1.5V
tPLH tPHL
2.7V
VOH
VOL
0 VInput
Output Figure 8. Voltage Waveforms–
Propagation Delay Times[4]
COMLINK™ SERI ES
CY2CC810
Document #: 38-07056 Rev. *C Page 5 of 7
INPUT
OUTPUT
tPLH tPHL
tsk(P) = l tPHL - tPLH l
3V
1.5V
0V
VOH
1.5V
VOL
Figure 9. Pulse Skew–tsk(p)
INPUT
OUTPUT 1
tPLH1 tPHL1
tsk(P) = l tPLH2 - tPLH1 l or tPHL2 - tPH L1 l
3V
1.5V
0V
VOH
1.5V
VOL
OUTPUT 2
VOH
1.5V
VOL
tsk(O) tsk(O)
tPLH 2 tPLH 2
Figure 10. Output Skew–tsk(0)
INPUT
PACKAGE 1 OUTPUT
tPLH1 tPHL1
tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l
3V
1.5V
0V
VOH
1.5V
VOL
PACKAGE 2 OUTPUT
VOH
1.5V
VOL
tsk(t) tsk(t)
tPLH 2 tPLH 2
Figure 11. Package Skew–tsk(t)
Ordering Information
Part Number Package Type Product Flow
CY2 CC810 SI 20-pin SOIC Industrial, –40°C to 85°C
CY2CC810SIT 20-pin SOIC–Tape and Reel Industrial, –40°C to 85°C
CY2CC810OI 20-pin SSOP Industrial, –40°C to 85°C
CY2CC810OIT 20-pin SSOP–Tape and Reel Industrial, –40°C to 85°C
CY2CC810SC 20-pin SOIC Commercial, 0°C to 70°C
CY2CC810SCT 20-pin SOIC–Tape and Reel Commercial, 0°C to 70°C
CY2CC810OC 20-pin SSOP Commercial, 0°C to 70°C
CY2CC810OCT 20-pin SSOP–Tape and Reel Commercial, 0°C to 70°C
COMLINK™ SERIES
CY2CC810
Document #: 38-07056 Rev. *C Page 6 of 7
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assume s no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so inde mnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
All product and company names mentioned in this document are the trademarks of their respective holders.
20-lead (300-mil)Molded SOIC S5
51-85024-A
20-lead (5.3-mm) Shrunk Small Outline Package O20
51-85077-*C
COMLINK™ SERI ES
CY2CC810
Document #: 38-07056 Rev. *C Page 7 of 7
Document Histor y Page
Document Title: CY2CC810 1:10 Clock Fanout Buffer
Document #: 38-07056
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107081 06/07/01 IKA Convert from IMI to Cypress
*A 114315 05/09/02 TSM ∆ IDD Validation
*B 119117 10/07/02 RGL Added 5.8 as the Max. value of VIH in the DC Electrical Characteristics
@3.3V table.
Change d the Max . value of VIH from 1.8 to 5.0 in the DC Elec trical Chara c-
teristics @2.5V table.
*C 122743 12/14/02 RBI Added power up requirements to maximum ratings information.
