SGUS041A - MAY 2003 - REVISED JANUARY 2004 D Controlled Baseline D D D D D D D D 1M-Bit On-Chip SRAM - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -40C to 105C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree High-Performance Fixed-Point Digital Signal Processor (DSP) SM320C6201 - 5-ns Instruction Cycle Time - 200-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - 1600 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C62x DSP CPU Core - Eight Independent Functional Units: - Six Arithmetic Logic Units (ALUs) (32-/40-Bit) - Two 16-Bit Multipliers (32-Bit Results) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-, 16-, 32-Bit Data) - 32-Bit Address Range - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization D D D D D D D D D D - 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) - 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency 32-Bit External Memory Interface (EMIF) - Glueless Interface to Asynchronous Memories: SRAM and EPROM - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel 16-Bit Host-Port Interface (HPI) - Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial Peripheral Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan Compatible 352-Pin BGA Package (GJC Suffix) CMOS Technology - 0.18-m/5-Level Metal Process 3.3-V I/Os, 1.8-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI and TMS320C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 SGUS041A - MAY 2003 - REVISED JANUARY 2004 GJC/GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGES (BOTTOM VIEW) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 Table of Contents GJC BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional and CPU (DSP core) block diagram . . . . . . . . . . . 4 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 absolute maximum ratings over operating case temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 recommended operating conditions . . . . . . . . . . . . . . . . . . . 26 electrical characteristics over recommended ranges of supply voltage and operating case temperature . . . . 26 parameter measurement information . . . . . . . . . . . . . . . input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing . . . . . . . . . . . . . . . . . synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing . . . . . . . . . . . . . DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 30 32 36 40 41 43 44 47 56 57 58 description The TMS320C62x DSPs (including the SM320C6201-EP) are the fixed-point DSP family in the TMS320C6000 DSP platform. The C6201 device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1600 MIPS at a clock rate of 200 MHz, the C6201 offers cost-effective solutions to high-performance DSP programming challenges. The C6201 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201 can produce two multiply-accumulates (MACs) per cycle--for a total of 466 million MACs per second (MMACS). The C62x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. TMS320C6000, C6000, and C62x are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. The SM320C6201-EP device shall be referred to as C6201 throughout the remainder of this document. 2 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 description (continued) The C6201 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the C6201 consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The C62x DSP has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the C6201 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the C6201 Processor HARDWARE FEATURES Peripherals On-Chip Memory C6201 (FIXED-POINT DSP) EMIF 1 DMA 1 HPI 1 McBSPs 2 32-Bit Timers 2 Size (Bytes) 72K Organization 512-Kbit Program Memory 512-Kbit Data Memory (organized as two blocks) CPU ID+Rev ID Control Status Register (CSR.[31:16]) Frequency MHz Cycle Time ns Voltage PLL Options BGA Packages 0x0002 200 5 ns (C6201-200) Core (V) 1.8 I/O (V) 3.3 CLKIN frequency multiplier Bypass (x1), x4 27 x 27 mm 352-Pin BGA (GJL) 35 x 35 mm 352-Pin BGA (GJC) Process Technology m Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) 0.18 m Device Part Numbers (For more details on the C6000 DSP part numbering, see Figure 4) PD SM320C6201GJCA20EP C6000 is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 SGUS041A - MAY 2003 - REVISED JANUARY 2004 functional and CPU (DSP core) block diagram C6201 Digital Signal Processors SDRAM SBSRAM Program Access/Cache Controller 32 SRAM External Memory Interface (EMIF) ROM/FLASH Internal Program Memory (64K Bytes) I/O Devices C62x CPU (DSP Core) Timer 0 Instruction Fetch Timer 1 Instruction Dispatch Control Logic Instruction Decode Multichannel Buffered Serial Port 0 Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Control Registers Data Path A Data Path B A Register File Multichannel Buffered Serial Port 1 .S1 .M1 .D1 .D2 .M2 .S2 In-Circuit Emulation .L2 DMA Bus .L1 Test B Register File Interrupt Selector Synchronous FIFOs I/O Devices HOST CONNECTION Master /Slave TI PCI2040 Power PC 683xx 960 4 32 Host Port Interface (HPI) Interrupt Control Peripheral Control Bus Direct Memory Access Controller (DMA) (4 Channels) PLL (x1, x4) POST OFFICE BOX 1443 Data Access Controller Internal Data Memory (64K Bytes) PowerDown Logic Boot Configuration * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see functional and CPU (DSP core) block diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 SGUS041A - MAY 2003 - REVISED JANUARY 2004 CPU (DSP core) description (continued) AAAAAA AAAA A AAAAAAA AAAA AAAAAA AAAAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAAAA AAAA A AAAAAA AA AA AAAA AAAA AAAAAA AA AA AAAA AAAA AAAAAAA AAAAAAA AAAAAA AAAAAAA AAAAAAA AAAA AAAAAA AAAAAAAA AAAAAA AAAA A AAAAAAA AAAAAAA AAAAAAA src1 .L1 src2 dst long dst long src ST1 Data Path A long src long dst dst .S1 src1 8 8 32 8 Register File A (A0-A15) src2 .M1 dst src1 src2 LD1 DA1 DA2 .D1 .D2 dst src1 src2 2X 1X src2 src1 dst LD2 src2 .M2 src1 dst src2 Data Path B src1 .S2 dst long dst long src ST2 long src long dst dst .L2 src2 Register File B (B0-B15) 8 32 8 src1 AAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAA AAAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAAA AAAAAA AAAAAA AAAAAAA AAAAAA AAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAA AAAAAA A 8 Figure 1. TMS320C62x CPU (DSP Core) Data Paths 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 Control Register File SGUS041A - MAY 2003 - REVISED JANUARY 2004 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF Boot Mode BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0 Reset and Interrupts RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 Little ENDIAN Big ENDIAN LENDIAN Clock/PLL TMS TDO TDI TCK TRST EMU1 EMU0 JTAG Emulation RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status HD[15:0] HCNTL0 HCNTL1 16 Data HPI (Host-Port Interface) Register Select Control HHWIL HBE1 HBE0 Half-Word/Byte Select HAS HR/W HCS HDS1 HDS2 HRDY HINT Figure 2. CPU (DSP Core) and Peripheral Signals POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 SGUS041A - MAY 2003 - REVISED JANUARY 2004 signal groups description (continued) 32 ED[31:0] Data Asynchronous Memory Control CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 HOLD HOLDA ARE AOE AWE ARDY Memory Map Space Select 20 Word Address SBSRAM Control SSADS SSOE SSWE SSCLK SDRAM Control SDA10 SDRAS SDCAS SDWE SDCLK Byte Enables HOLD/ HOLDA EMIF (External Memory Interface) TOUT1 Timer 1 Timer 0 TOUT0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Receive Receive CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 3. Peripheral Signals 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION CLOCK/PLL CLKIN C10 I Clock Input CLKOUT1 AF22 O Clock output at full device speed CLKOUT2 AF20 O Clock output at half of device speed I Clock mode selects * Selects whether the CPU clock frequency = input clock frequency x4 or x1 For more details on the GJC and GJL CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. I PLL frequency range (3, 2, and 1) * The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. CLKMODE1 C6 CLKMODE0 C5 PLLFREQ3 A9 PLLFREQ2 D11 PLLFREQ1 PLLV B10 D12 PLLG PLL analog VCC connection for the low-pass filter C12 A A PLLF A11 A PLL low-pass filter connection to external components and a bypass capacitor TMS L3 I TDO W2 O/Z TDI R4 I JTAG test port data in (features an internal pullup) TCK R3 I JTAG test port clock TRST T1 I JTAG test port reset (features an internal pulldown) EMU1 Y1 I/O/Z EMU0 W3 I/O/Z PLL analog GND connection for the low-pass filter JTAG EMULATION JTAG test port mode select (features an internal pullup) JTAG test port data out Emulation pin 1, pullup with a dedicated 20-k resistor Emulation pin 0, pullup with a dedicated 20-k resistor RESET AND INTERRUPTS RESET K2 I Device reset NMI L2 I Nonmaskable interrupt * Edge-driven (rising edge) EXT_INT7 U3 EXT_INT6 V2 EXT_INT5 W1 I EXT_INT4 U4 External interrupts * Edge-driven * Polarity independently selected via the external interrupt polarity register bits (EXTPOL.[3:0]) IACK Y2 O Interrupt acknowledge for all active interrupts serviced by the CPU O Active interrupt identification number * Valid during IACK for all active interrupts (not just external) * Encoding order follows the interrupt-service fetch-packet ordering INUM3 AA1 INUM2 W4 INUM1 AA2 INUM0 AB1 LITTLE ENDIAN/BIG ENDIAN LENDIAN H3 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing POWER-DOWN STATUS PD D3 O Power-down mode 2 or 3 (active if high) I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. A = Analog Signal (PLL Filter) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-k resistor. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION HOST-PORT INTERFACE (HPI) HINT H26 O Host interrupt (from DSP to host) HCNTL1 F23 I Host control - selects between control, address, or data registers HCNTL0 D25 I Host control - selects between control, address, or data registers HHWIL C26 I Host half-word select - first or second half-word (not necessarily high or low order) HBE1 E23 I Host byte select within word or half-word HBE0 D24 I Host byte select within word or half-word HR/W C23 I Host read or write select HD15 B13 HD14 B14 HD13 C14 HD12 B15 HD11 D15 HD10 B16 HD9 A17 HD8 B17 HD7 D16 HD6 B18 HD5 A19 HD4 C18 HD3 B19 HD2 C19 HD1 B20 I/O/Z Host-port data (used for transfer of data, address, and control) HD0 B21 HAS C22 I Host address strobe HCS B23 I Host chip select HDS1 D22 I Host data strobe 1 HDS2 A24 I Host data strobe 2 HRDY J24 O Host ready (from DSP to host) BOOTMODE4 D8 BOOTMODE3 B4 BOOT MODE BOOTMODE2 A3 BOOTMODE1 D5 I Boot mode BOOTMODE0 C4 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 10 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AE22 CE2 AD26 CE1 AB24 CE0 AC26 BE3 AB25 BE2 AA24 BE1 Y23 BE0 AA26 O/Z Memory space enables * Enabled by bits 24 and 25 of the word address * Only one asserted during any external data access O/Z Byte-enable control * Decoded from the two lowest bits of the internal address * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF - ADDRESS EA21 J26 EA20 K25 EA19 L24 EA18 K26 EA17 M26 EA16 M25 EA15 P25 EA14 P24 EA13 R25 EA12 T26 EA11 R23 EA10 U26 EA9 U25 EA8 T23 EA7 V26 EA6 V25 EA5 W26 EA4 V24 EA3 W25 O/Z External address (word address) EA2 Y26 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION EMIF - DATA ED31 AB2 ED30 AC1 ED29 AA4 ED28 AD1 ED27 AC3 ED26 AD4 ED25 AF3 ED24 AE4 ED23 AD5 ED22 AF4 ED21 AE5 ED20 AD6 ED19 AE6 ED18 AD7 ED17 AC8 ED16 AF7 ED15 AD9 ED14 AD10 ED13 AF9 ED12 AC11 ED11 AE10 ED10 AE11 ED9 AF11 ED8 AE14 ED7 AF15 ED6 AE15 ED5 AF16 ED4 AC15 ED3 AE17 ED2 AF18 ED1 AF19 ED0 AC17 I/O/Z External data EMIF - ASYNCHRONOUS MEMORY CONTROL ARE Y24 O/Z Asynchronous memory read enable AOE AC24 O/Z Asynchronous memory output enable AWE AD23 O/Z Asynchronous memory write enable ARDY W23 I Asynchronous memory ready input I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION EMIF - SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SSADS AC20 O/Z SBSRAM address strobe SSOE AF21 O/Z SBSRAM output enable SSWE AD19 O/Z SBSRAM write enable SSCLK AD17 O SBSRAM clock EMIF - SYNCHRONOUS DRAM (SDRAM) CONTROL SDA10 AD21 O/Z SDRAM address 10 (separate for deactivate command) SDRAS AF24 O/Z SDRAM row-address strobe SDCAS AD22 O/Z SDRAM column-address strobe SDWE AF23 O/Z SDRAM write enable SDCLK AE20 O SDRAM clock EMIF - BUS ARBITRATION HOLD AA25 I Hold request from the host HOLDA A7 O Hold-request acknowledge to the host TOUT1 H24 O Timer 1 or general-purpose output TINP1 K24 I Timer 1 or general-purpose input TOUT0 M4 O Timer 0 or general-purpose output TINP0 K4 I Timer 0 or general-purpose input DMAC3 D2 TIMER1 TIMER0 DMA ACTION COMPLETE STATUS DMAC2 F4 DMAC1 D1 DMAC0 E2 CLKS1 E25 I CLKR1 H23 I/O/Z Receive clock CLKX1 F26 I/O/Z Transmit clock DR1 D26 I Receive data DX1 G23 O/Z Transmit data FSR1 E26 I/O/Z Receive frame sync O DMA action complete MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) External clock source (as opposed to internal) FSX1 F25 I/O/Z Transmit frame sync I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 L4 I CLKR0 M2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX0 L1 I/O/Z Transmit clock DR0 J1 I Receive data DX0 R1 O/Z Transmit data FSR0 P4 I/O/Z Receive frame sync FSX0 P3 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 T2 I Reserved for testing, pullup with a dedicated 20-k resistor RSV1 G2 I Reserved for testing, pullup with a dedicated 20-k resistor RSV2 C11 I Reserved for testing, pullup with a dedicated 20-k resistor RSV3 B9 I Reserved for testing, pullup with a dedicated 20-k resistor RSV4 A6 I Reserved for testing, pulldown with a dedicated 20-k resistor RSV5 C8 O Reserved (leave unconnected, do not connect to power or ground) RSV6 C21 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV7 B22 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV8 A23 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV9 E4 O Reserved (leave unconnected, do not connect to power or ground) UNCONNECTED PINS A8 B8 C9 D10 D21 NC G1 Unconnected pins H1 H2 J2 K3 R2 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION 3.3-V SUPPLY VOLTAGE PINS A10 A15 A18 A21 A22 B7 C1 D17 F3 G24 G25 H25 J25 L25 M3 N3 N23 R26 T24 U24 DVDD W24 S 3.3-V supply voltage Y4 AB3 AB4 AB26 AC6 AC10 AC19 AC21 AC22 AC25 AD11 AD13 AD15 AD18 AE18 AE21 AF5 AF6 AF17 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION 1.8-V SUPPLY VOLTAGE PINS A5 A12 A16 A20 B2 B6 B11 B12 B25 C3 C15 C20 C24 D4 D6 D7 D9 D14 D18 CVDD D20 S 1.8-V supply voltage D23 E1 F1 H4 J4 J23 K1 K23 M1 M24 N4 N25 P2 P23 T3 T4 U1 V4 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION 1.8-V SUPPLY VOLTAGE PINS (CONTINUED) V23 AC4 AC9 AC12 AC13 AC18 AC23 AD3 AD8 CVDD AD14 S 1.8-V supply voltage AD24 AE2 AE8 AE12 AE25 AF12 - - GROUND PINS A1 A2 A4 A13 A14 A25 A26 B1 B3 VSS B5 GND Ground pins B24 B26 C2 C7 C13 C16 C17 C25 D13 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION GROUND PINS (CONTINUED) D19 E3 E24 F2 F24 G3 G4 G26 J3 L23 L26 M23 N1 N2 N24 N26 P1 P26 R24 VSS T25 GND Ground pins U2 U23 V1 V3 Y3 Y25 AA3 AA23 AB23 AC2 AC5 AC7 AC14 AC16 AD2 AD12 AD16 AD20 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJC TYPE DESCRIPTION GROUND PINS (CONTINUED) AD25 AE1 AE3 AE7 AE9 AE13 AE16 AE19 AE23 VSS AE24 GND Ground pins AE26 AF1 AF2 AF8 AF10 AF13 AF14 AF25 AF26 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 SGUS041A - MAY 2003 - REVISED JANUARY 2004 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 DSP family member devices, including documentation. See this document for further information on TMS320 DSP documentation or any TMS320 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies in the industry. To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under "Development Tools", select "Digital Signal Processors". For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 device and development support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP family devices and support tools. Each TMS320 DSP member has one of three prefixes: TMX, TMP, or TMS, and each SMJ320 DSP member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/ TMDX) through fully qualified production devices/tools (TMS / TMDS). This development flow is defined below. Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification SM/SMJ Fully-qualified production device Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS as well as SM/SMJ devices and TMDS development support tools have been characterized fully, and the quality and reliability of the device has been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GNM) and temperature range (for example, M). Figure 4 provides a legend for reading the complete device name for many TMS320 DSP family members. TMS320 is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 SGUS041A - MAY 2003 - REVISED JANUARY 2004 device and development-support tool nomenclature (continued) SM 320 C PREFIX SMX = TMP = TMS = SMJ = SMQ= SM = 6201 GJC A 20 EP experimental device prototype device qualified device MIL-PRF-38535 (QML) QML Plastic device commercial processing ENHANCED PLASTIC SPEED 20 = 200 MHz DEVICE FAMILY 320 = TMS320 Family TEMPERATURE RANGE A = Extended temperature (-40C to 105C) M = Military TECHNOLOGY C = CMOS LC = Low-Voltage CMOS (3.3 V) VC = Low-Voltage CMOS [3.3 V (2.5 V or 1.8 V core)] PACKAGE TYPE GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GFN = 256-pin plastic BGA DEVICE 6000 DSP: 6201 6203 6701 6711 NOTE: Not all speed, package, process, and temperature combinations are available. BGA = Ball Grid Array Figure 4. TMS320C6000 Device Nomenclature (Including SM320C6201-EP) MicroStar BGA is a trademark of Texas Instruments. 22 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 documentation support Extensive documentation supports all TMS320 DSP family devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The tools support documentation is electronically available within the Code Composer Studio IDE. For a complete listing of the latest C6000 DSP documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). C67x is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 23 SGUS041A - MAY 2003 - REVISED JANUARY 2004 clock PLL All of the C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. To use the PLL to generate the CPU clock, the filter circuit shown in Figure 5 must be properly designed. Note that for C6201, the EMI filter must be powered by the I/O voltage (3.3 V). To configure the C62x PLL clock for proper operation, see Figure 5 and Table 2. To minimize the clock jitter, a single clean power supply should power both the C62x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input clock timing requirements. EMI Filter PLLV 1 IN PLLF C3 10 F C4 0.1 F R1 CLKOUT1 Frequency Range 65 -200 MHz 0 0 0 CLKOUT1 Frequency Range 5 0-140 MHz PLLFREQ3 PLLFREQ2 PLLFREQ1 3 OUT CLKOUT1 Frequency Range 130 -233 MHz 0 0 1 C6201 EMIF CLKOUT1 CLKOUT 2 PLLG (Bypass) C1 C2 GND CLKIN CLKMODE0 CLKMODE1 3.3 V 0 1 0 1 1 - MULT x 4 CLKOUT2 SSCLK SDCLK f(CLKOUT) = f(CLKIN) x 4 0 1 - Reserved 1 0 - Reserved 0 0 - MULT x 1 f(CLKOUT) = f(CLKIN) NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown. For CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT. B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean supply and the PLLG and PLLF terminals should be tied together. C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a PLLFREQ value of 000b should be used. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved. D. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. E. EMI filter manufacturer TDK part number ACF451832-153-T Figure 5. PLL Block Diagram 24 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 clock PLL (continued) Table 2. PLL Component Selection Table CLKMODE CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 () C1 (nF) C2 (pF) TYPICAL LOCK TIME (s) x4 12.5-50 50-200 25-100 60.4 27 560 75 Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 25 SGUS041A - MAY 2003 - REVISED JANUARY 2004 absolute maximum ratings over operating case temperature ranges (unless otherwise noted) Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating case temperature ranges TC: (A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40_C to 105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT CVDD Supply voltage 1.71 1.8 1.89 V DVDD Supply voltage 3.14 3.30 3.46 V VSS VIH Supply ground 0 0 0 V High-level input voltage 2 VIL IOH Low-level input voltage 0.8 V High-level output current -12 mA IOL TC Low-level output current 12 mA 105 _C Operating case temperature A version V -40 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage DVDD = MIN, IOH = MAX VOL Low-level output voltage DVDD = MIN, IOL = MAX II IOZ Input current MIN TYP 2.4 UNIT V VI = VSS to DVDD VO = DVDD or 0 V Off-state output current MAX 0.6 V 10 uA 10 uA IDD2V Supply current, CPU + CPU memory access CVDD = NOM, CPU clock = 167 MHz IDD2V Supply current, peripherals CVDD = NOM, CPU clock = 167 MHz 240 mA IDD3V Supply current, I/O pins DVDD = NOM, CPU clock = 167 MHz 90 mA Ci Input capacitance 380 mA 10 pF Co Output capacitance 10 pF TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Vcomm Output Under Test CT IOH Where: Typical distributed load circuit capacitance IOL IOH Vcomm CT = = = = 2 mA 2 mA 0.8 V 15-30-pF typical load-circuit capacitance Figure 6. TTL-Level Outputs signal transition levels All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels. Vref = 1.5 V Figure 7. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 8. Rise and Fall Transition Time Voltage Reference Levels POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 SGUS041A - MAY 2003 - REVISED JANUARY 2004 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 9) -200 CLKMODE = x4 NO. MIN 1 2 3 4 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN tw(CLKINL) tt(CLKIN) MAX CLKMODE = x1 MIN UNIT MAX 20 5 ns Pulse duration, CLKIN high 0.4C 0.45C ns Pulse duration, CLKIN low 0.4C 0.45C Transition time, CLKIN ns 5 0.6 ns The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 1 4 2 CLKIN 3 4 Figure 9. CLKIN Timing Diagram switching characteristics over recommended operating conditions for CLKOUT1# (see Figure 10) -200 NO. CLKMODE = x4 PARAMETER MIN 1 2 3 4 tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) CLKMODE = x1 MAX MIN P - 0.7 P + 0.7 P - 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) - 0.5 (P/2 ) + 0.5 PH - 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) - 0.5 (P/2 ) + 0.5 PL - 0.5 PL + 0.5 ns 0.6 ns Transition time, CLKOUT1 0.6 P = 1/CPU clock frequency in ns. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. # PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. 1 4 2 CLKOUT1 3 4 Figure 10. CLKOUT1 Timing Diagram 28 UNIT MAX POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 11) -200 NO. 1 2 3 4 PARAMETER UNIT MIN MAX 2P - 0.7 2P + 0.7 ns tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high P - 0.7 P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low P - 0.7 P + 0.7 ns 0.6 ns Transition time, CLKOUT2 P = 1/CPU clock frequency in ns. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. 1 4 2 CLKOUT2 3 4 Figure 11. CLKOUT2 Timings SDCLK, SSCLK timing parameters SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. switching characteristics over recommended operating conditions for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 12) -200 NO. 1 PARAMETER UNIT MIN MAX (P/2) + 0.2 (P/2) + 4.2 ns Delay time, CLKOUT1 edge to SSCLK edge 2 td(CKO1-SSCLK) td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) (P/2) - 1 (P/2) + 2.4 ns 3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge (P/2) - 1 (P/2) + 2.4 ns (P/2) - 1 (P/2) + 2.4 ns 4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge P = 1/CPU clock frequency in ns. CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 SGUS041A - MAY 2003 - REVISED JANUARY 2004 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 13 and Figure 14) -200 NO. 6 7 10 11 MIN tsu(EDV-CKO1H) th(CKO1H-EDV) Setup time, read EDx valid before CLKOUT1 high tsu(ARDY-CKO1H) th(CKO1H-ARDY) MAX UNIT 4 ns Hold time, read EDx valid after CLKOUT1 high 0.8 ns Setup time, ARDY valid before CLKOUT1 high 3 ns Hold time, ARDY valid after CLKOUT1 high 1.8 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics over recommended operating conditions for asynchronous memory cycles (see Figure 13 and Figure 14) -200 NO. 1 2 3 4 5 8 9 12 13 14 PARAMETER MAX -0.2 4 ns 4 ns td(CKO1H-CEV) td(CKO1H-BEV) Delay time, CLKOUT1 high to CEx valid td(CKO1H-BEIV) td(CKO1H-EAV) Delay time, CLKOUT1 high to BEx invalid td(CKO1H-EAIV) td(CKO1H-AOEV) Delay time, CLKOUT1 high to EAx invalid -0.2 Delay time, CLKOUT1 high to AOE valid -0.2 4 ns td(CKO1H-AREV) td(CKO1H-EDV) Delay time, CLKOUT1 high to ARE valid -0.2 4 ns 4 ns td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to EDx invalid -0.2 Delay time, CLKOUT1 high to AWE valid -0.2 Delay time, CLKOUT1 high to BEx valid -0.2 Delay time, CLKOUT1 high to EAx valid POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 ns 4 Delay time, CLKOUT1 high to EDx valid The minimum delay is also the minimum output hold after CLKOUT1 high. 30 UNIT MIN ns ns ns 4 ns SGUS041A - MAY 2003 - REVISED JANUARY 2004 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 13. Asynchronous Memory Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 10 11 10 ARDY Figure 14. Asynchronous Memory Write Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15) -200 NO. 7 8 MIN tsu(EDV-SSCLKH) th(SSCLKH-EDV) MAX UNIT Setup time, read EDx valid before SSCLK high 1.5 ns Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15 and Figure 16) -200 NO. 1 PARAMETER MIN MAX UNIT tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high 0.5P - 1.3 ns Output hold time, CEx valid after SSCLK high 0.5P - 2.3 ns tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high 0.5P - 1.3 ns Output hold time, BEx invalid after SSCLK high 0.5P - 2.3 ns tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high 0.5P - 1.3 ns Output hold time, EAx invalid after SSCLK high 0.5P - 2.3 ns tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high 0.5P - 1.3 ns Output hold time, SSADS valid after SSCLK high 0.5P - 2.3 ns tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high 0.5P - 1.3 ns Output hold time, SSOE valid after SSCLK high 0.5P - 2.3 ns tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 0.5P - 1.3 ns 14 Output hold time, EDx invalid after SSCLK high 0.5P - 2.3 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P - 1.3 ns 2 3 4 5 6 9 10 11 12 13 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P - 2.3 ns When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times. 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 5 EA[21:2] 8 7 Q1 ED[31:0] 9 Q2 Q3 Q4 10 SSADS 11 12 SSOE SSWE Figure 15. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 Q3 14 Q4 5 EA[21:2] 13 ED[31:0] Q1 Q2 9 10 15 16 SSADS SSOE SSWE Figure 16. SBSRAM Write Timing (Full-Rate SSCLK) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17) -200 NO. 7 8 MIN tsu(EDV-SSCLKH) th(SSCLKH-EDV) MAX UNIT Setup time, read EDx valid before SSCLK high 2.5 ns Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17 and Figure 18) -200 NO. 1 PARAMETER MIN tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 14 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 2 3 4 5 6 9 10 11 12 13 Output hold time, CEx valid after SSCLK high Output hold time, BEx invalid after SSCLK high Output hold time, EAx invalid after SSCLK high Output hold time, SSADS valid after SSCLK high Output hold time, SSOE valid after SSCLK high Output hold time, EDx invalid after SSCLK high MAX UNIT 1.5P - 3 ns 0.5P - 1.5 ns 1.5P - 3 ns 0.5P - 1.5 ns 1.5P - 3 ns 0.5P - 1.5 ns 1.5P - 3 ns 0.5P - 1.5 ns 1.5P - 3 ns 0.5P - 1.5 ns 1.5P - 3 ns 0.5P - 1.5 ns 1.5P - 3 ns 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P - 1.5 ns When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. 34 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 Q3 9 Q4 10 SSADS 11 12 SSOE SSWE Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 Q1 Q2 Q3 Q4 6 13 14 ED[31:0] 9 10 15 16 SSADS SSOE SSWE Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 19) -200 NO. 7 8 MIN tsu(EDV-SDCLKH) th(SDCLKH-EDV) Setup time, read EDx valid before SDCLK high Hold time, read EDx valid after SDCLK high MAX UNIT 0.5 ns 3 ns switching characteristics over recommended operating conditions for synchronous DRAM cycles (see Figure 19-Figure 24) -200 NO. 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 18 PARAMETER MIN tosu(CEV-SDCLKH) toh(SDCLKH-CEV) Output setup time, CEx valid before SDCLK high tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) Output setup time, BEx valid before SDCLK high tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) Output setup time, EAx valid before SDCLK high tosu(SDCAS-SDCLKH) toh(SDCLKH-SDCAS) Output setup time, SDCAS valid before SDCLK high Output hold time, CEx valid after SDCLK high Output hold time, BEx invalid after SDCLK high Output hold time, EAx invalid after SDCLK high MAX UNIT 1.5P - 3.5 ns 0.5P - 1 ns 1.5P - 3.5 ns 0.5P - 1 ns 1.5P - 3.5 ns 0.5P - 1 ns 1.5P - 3.5 ns Output hold time, SDCAS valid after SDCLK high 0.5P - 1 ns tosu(EDV-SDCLKH) toh(SDCLKH-EDIV) Output setup time, EDx valid before SDCLK high 1.5P - 3.5 ns 0.5P - 1 ns tosu(SDWE-SDCLKH) toh(SDCLKH-SDWE) Output setup time, SDWE valid before SDCLK high 1.5P - 3.5 ns 0.5P - 1 ns tosu(SDA10V-SDCLKH) toh(SDCLKH-SDA10IV) Output setup time, SDA10 valid before SDCLK high 1.5P - 3.5 ns tosu(SDRAS-SDCLKH) toh(SDCLKH-SDRAS) Output setup time, SDRAS valid before SDCLK high Output hold time, EDx invalid after SDCLK high Output hold time, SDWE valid after SDCLK high Output hold time, SDA10 invalid after SDCLK high Output hold time, SDRAS valid after SDCLK high 0.5P - 1 ns 1.5P - 3.5 ns 0.5P - 1 ns When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ SDCLK 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 SDA10 SDRAS SDCAS SDWE Figure 19. Three SDRAM Read Commands WRITE WRITE WRITE SDCLK 1 2 CEx 3 BE[3:0] 4 BE1 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS SDCAS SDWE Figure 20. Three SDRAM WRT Commands POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 18 SDRAS SDCAS SDWE Figure 21. SDRAM ACTV Command DCAB SDCLK 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS 13 SDWE Figure 22. SDRAM DCAB Command 38 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 14 SGUS041A - MAY 2003 - REVISED JANUARY 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS 9 10 SDCAS SDWE Figure 23. SDRAM REFR Command MRS SDCLK 1 2 5 6 CEx BE[3:0] EA[15:2] MRS Value ED[31:0] SDA10 17 18 9 10 13 14 SDRAS SDCAS SDWE Figure 24. SDRAM MRS Command POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 39 SGUS041A - MAY 2003 - REVISED JANUARY 2004 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 25) -200 NO. 1 MIN tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) Setup time, HOLD high before CLKOUT1 high MAX 1 UNIT ns 2 Hold time, HOLD low after CLKOUT1 high 4 ns HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles (see Figure 25) -200 NO. 3 4 5 6 7 8 PARAMETER MIN td(HOLDL-BHZ) td(BHZ-HOLDAL) Delay time, HOLD low to EMIF Bus high impedance td(HOLDH-HOLDAH) td(CKO1H-HOLDAL) Delay time, HOLD high to HOLDA high td(CKO1H-BHZ) td(CKO1H-BLZ) Delay time, EMIF Bus high impedance to HOLDA low 4P MAX UNIT ns P 2P ns 4P 7P ns Delay time, CLKOUT1 high to HOLDA valid 1 8 ns Delay time, CLKOUT1 high to EMIF Bus high impedance Delay time, CLKOUT1 high to EMIF Bus low impedance 3 11 ns 3 11 ns 9 td(HOLDH-BLZ) Delay time, HOLD high to EMIF Bus low impedance 3P 6P ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. DSP Owns Bus External Requester DSP Owns Bus 5 9 4 3 CLKOUT1 2 2 1 1 HOLD 6 6 HOLDA 7 8 EMIF Bus C62x Ext Req C62x EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 25. HOLD/HOLDA Timing 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 RESET TIMING timing requirements for reset (see Figure 26) -200 NO. 1 MIN tw(RST) Width of the RESET pulse (PLL stable) MAX UNIT CLKOUT1 cycles 10 Width of the RESET pulse (PLL needs to sync up) 250 s This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the Clock PLL section for PLL lock times. switching characteristics over recommended operating conditions during reset (see Figure 26) -200 NO. PARAMETER MIN 2 tR(RST) Response time to change of value in RESET signal 3 td(CKO1H-CKO2IV) td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 invalid td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK invalid td(CKO1H-SSCKIV) td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK invalid td(CKO1H-LOWIV) td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group invalid td(CKO1H-HIGHIV) td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group invalid td(CKO1H-ZHZ) td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group high impedance 4 5 6 7 8 9 10 11 12 13 14 Low group consists of: High group consists of: Z group consists of: -1 ns 10 -1 Delay time, CLKOUT1 high to SDCLK valid -1 10 ns ns 10 -1 Delay time, CLKOUT1 high to high group valid ns ns -1 Delay time, CLKOUT1 high to low group valid ns ns 10 Delay time, CLKOUT1 high to SSCLK valid UNIT CLKOUT1 cycles 2 Delay time, CLKOUT1 high to CLKOUT2 valid Delay time, CLKOUT1 high to Z group valid MAX ns ns 10 -1 ns ns 10 ns IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 HINT EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 SGUS041A - MAY 2003 - REVISED JANUARY 2004 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 CLKOUT2 SDCLK SSCLK LOW GROUP HIGH GROUP Z GROUP Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 HINT EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. Figure 26. Reset Timing 42 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles (see Figure 27) -200 NO. 2 MIN tw(ILOW) tw(IHIGH) Width of the interrupt pulse low MAX 2P UNIT ns 3 Width of the interrupt pulse high 2P ns Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. switching characteristics over recommended operating conditions during interrupt response cycles (see Figure 27) -200 NO. 1 PARAMETER MIN td(EINTH-IACKH) td(CKO2L-IACKV) Delay time, EXT_INTx high to IACK high 9P 4 Delay time, CLKOUT2 low to IACK valid -4 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 x CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. MAX UNIT ns -4 6 ns 6 ns ns 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 Interrupt Number INUMx Figure 27. Interrupt Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 SGUS041A - MAY 2003 - REVISED JANUARY 2004 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles (see Figure 28, Figure 29, Figure 30, and Figure 31) -200 NO. 1 2 3 4 10 11 12 13 MIN tsu(SEL-HSTBL) th(HSTBL-SEL) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low tw(HSTBL) tw(HSTBH) tsu(SEL-HASL) th(HASL-SEL) tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) 19 MAX UNIT 4 ns 2 ns Pulse duration, HSTROBE low 2P ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low 2P ns 4 ns Hold time, select signals valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 3 ns Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 1 ns Setup time, HAS low before HSTROBE low 2 ns Hold time, HAS low after HSTROBE low 2 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics over recommended operating conditions during host-port interface cycles (see Figure 28, Figure 29, Figure 30, and Figure 31) -200 NO. PARAMETER MIN MAX UNIT Delay time, HCS to HRDY 1 9 ns 6 td(HCS-HRDY) td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 12 ns 7 toh(HSTBL-HDLZ) Output hold time, HD low impedance after HSTROBE low for an HPI read 8 Delay time, HD valid to HRDY low 9 td(HDV-HRDYL) toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 16 td(HSTBL-HDV) 17 td(HSTBH-HRDYH) td(HASL-HRDYH) 5 4 P-3 ns P+3 ns 2 12 ns 3 12 ns Delay time, HSTROBE low to HD valid 2 12 ns Delay time, HSTROBE high to HRDY high|| 3 12 ns 20 Delay time, HAS low to HRDY high 3 12 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st Half-Word 5 2nd Half-Word 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 28. HPI Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 20 8 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Read Timing (HAS Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 SGUS041A - MAY 2003 - REVISED JANUARY 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 12 12 13 13 HBE[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 14 HSTROBE HCS 12 12 13 13 HD[15:0] (input) 1st Half-Word 5 17 2nd Half-Word 5 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Write Timing (HAS Not Used, Tied High) HAS 12 19 13 12 19 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 31. HPI Write Timing (HAS Used) 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP(see Figure 32) -200 NO. 2 3 tc(CKRX) tw(CKRX) Cycle time, CLKR/X CLKR/X ext MIN 2P Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKR int 9 CLKR ext 2 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0 CLKR int 3 CLKR ext 4 CLKX int 9 CLKX ext 2 CLKX int 6 CLKX ext 3 MAX UNIT ns ns ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. The minimum CLKR/X pulse duration is either (P -1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use 4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P -1) = 9 ns as the minimum CLKR/X pulse duration. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 32) -200 NO. PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input MAX 3 10 2P C - 1.3# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -2 3 CLKX int -2 3 CLKX ext 3 9 CLKR/X int 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 td(FXH-DXV) UNIT MIN ns ns CLKX int -1 4 CLKX ext 3 9 CLKX int -1 4 CLKX ext 3 9 Delay time, FSX high to DX valid FSX int -1 3 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz (P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 32. McBSP Timing Diagram POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 33) -200 NO. 1 2 MIN tsu(FRH-CKSH) th(CKSH-FRH) MAX UNIT Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR External CLKR/X (no need to resync) CLKR/X (needs resync) Figure 33. FSR Timing When GSYNC = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 34) -200 MASTER NO. MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low MAX 12 5 Hold time, DR valid after CLKX low 4 P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. 50 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SLAVE MIN UNIT MAX 2 - 3P ns 5 + 6P ns SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 34) -200 NO. MASTER PARAMETER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 SLAVE MIN MAX T-2 T+3 L-2 L+3 -2 4 L-2 L+3 MIN UNIT MAX ns ns 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 35) -200 MASTER NO. MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN UNIT MAX 2 - 3P ns 5 + 6P ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 35) -200 NO. MASTER PARAMETER MIN 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) 6 tdis(CKXL-DXHZ) 1 SLAVE MAX MIN UNIT MAX L-2 L+3 T-2 T+3 ns Delay time, CLKX low to DX valid -2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from CLKX low -2 4 3P + 3 5P + 17 ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+4 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 52 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 36) -200 MASTER NO. MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high SLAVE MAX MIN UNIT MAX 12 2 - 3P ns 4 5 + 6P ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 36) -200 NO. MASTER PARAMETER 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 SLAVE MIN MAX T-2 T+3 H-2 H+3 -2 4 H-2 H+3 MIN UNIT MAX ns ns 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 8 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 37) -200 MASTER NO. MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low SLAVE MAX MIN UNIT MAX 12 2 - 3P ns 4 5 + 6P ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 37) -200 NO. MASTER PARAMETER SLAVE MIN MAX H-2 H+3 MIN UNIT MAX 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# T-2 T+1 3 td(CKXH-DXV) Delay time, CLKX high to DX valid -2 4 3P + 4 5P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high -2 4 3P + 3 5P + 17 ns 1 ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+4 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SGUS041A - MAY 2003 - REVISED JANUARY 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 55 SGUS041A - MAY 2003 - REVISED JANUARY 2004 DMAC, TIMER, POWER-DOWN TIMING switching characteristics over recommended operating conditions for DMAC outputs (see Figure 38) -200 NO. 1 PARAMETER td(CKO1H-DMACV) Delay time, CLKOUT1 high to DMAC valid MIN MAX 2 10 UNIT ns CLKOUT1 1 1 DMAC[0:3] Figure 38. DMAC Timing Diagram timing requirements for timer inputs (see Figure 39) -200 NO. MIN 1 tw(TINP) Pulse duration, TINP high or low P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns. MAX UNIT 2P ns switching characteristics over recommended operating conditions for timer outputs (see Figure 39) -200 NO. 2 PARAMETER td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid MIN MAX 2 9 UNIT ns CLKOUT1 1 TINP 2 2 TOUT Figure 39. Timer Timing Diagram switching characteristics over recommended operating conditions for power-down outputs (see Figure 40) -200 NO. 1 PARAMETER td(CKO1H-PDV) Delay time, CLKOUT1 high to PD valid CLKOUT1 1 1 PD Figure 40. Power-Down Timing 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 MIN MAX 2 9 UNIT ns SGUS041A - MAY 2003 - REVISED JANUARY 2004 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 41) -200 NO. 1 MIN MAX UNIT Cycle time, TCK 35 ns 3 tc(TCK) tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 41) -200 NO. 2 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid MIN MAX -3 12 UNIT ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 41. JTAG Test-Port Timing Diagram POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 57 PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SM320C6201GJCA20EP ACTIVE FC/CSP GJC 352 21 TBD Call TI Level-4-220C-72 HR V62/04606-01XA ACTIVE FC/CSP GJC 352 21 TBD Call TI Level-4-220C-72 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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