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DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−40°C to 105°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree†
DHigh-Performance Fixed-Point Digital
Signal Processor (DSP) SM320C6201
− 5-ns Instruction Cycle Time
− 200-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 1600 MIPS
DVelociTI Advanced Very Long Instruction
Word (VLIW) TMS320C62x DSP CPU Core
− Eight Independent Functional Units:
− Six Arithmetic Logic Units (ALUs)
(32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Results)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 32-Bit Address Range
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D1M-Bit On-Chip SRAM
− 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
− 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
DFour-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
D16-Bit Host-Port Interface (HPI)
− Access to Entire Memory Map
DTwo Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
DTwo 32-Bit General-Purpose Timers
DFlexible Phase-Locked Loop (PLL) Clock
Generator
DIEEE-1149.1 (JTAG‡) Boundary-Scan
Compatible
D352-Pin BGA Package (GJC Suffix)
DCMOS Technology
− 0.18-µm/5-Level Metal Process
D3.3-V I/Os, 1.8-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI and TMS320C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2003, Texas Instruments Incorporated
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GJC/GJL
352-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
AF
AD
AB
AA
AC
W
Y
U
V
AE
R
N
P
L
H
J
K
M
F
G
D
E
B
A
C
T
25262223
20
19 2117151612
1314 1810
9
8
75 64
3
2
111 24
Table of Contents
parameter measurement information 27. . . . . . . . . . . . . . .
input and output clocks 28. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 30. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 32. . . . . . . . . . . . . . . . .
synchronous DRAM timing 36. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 40. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 43. . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing 44. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 47. . . . . . . . . . . . .
DMAC, timer, power-down timing 56. . . . . . . . . . . . . . . . . .
JTAG test-port timing 57. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GJC BGA package (bottom view) 2. . . . . . . . . . . . . . . . . . . . . .
description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional and CPU (DSP core) block diagram 4. . . . . . . . . . .
CPU (DSP core) description 5. . . . . . . . . . . . . . . . . . . . . . . . . .
signal groups description 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing 25. . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature ranges 26. . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 26. . . . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 26. . . .
description
The TMS320C62x DSPs (including the SM320C6201-EP†) are the fixed-point DSP family in the
TMS320C6000DSP platform. The C6201 device is based on the high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an
excellent choice for multichannel and multifunction applications. With performance of up to 1600 MIPS at a
clock rate of 200 MHz, the C6201 offers cost-effective solutions to high-performance DSP programming
challenges. The C6201 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high
degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201 can produce two
multiply-accumulates (MACs) per cycle—for a total of 466 million MACs per second (MMACS). The C62x
DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
TMS320C6000, C6000, and C62x are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
†The SM320C6201-EP device shall be referred to as C6201 throughout the remainder of this document.
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description (continued)
The C6201 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory of the C6201 consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral
set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface
(HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and
asynchronous peripherals.
The C62x DSP has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
device characteristics
Table 1 provides an overview of the C6201 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the C6201 Processor
HARDWARE FEATURES C6201 (FIXED-POINT DSP)
EMIF 1
DMA 1
Peripherals HPI 1
Peripherals
McBSPs 2
32-Bit Timers 2
Size (Bytes) 72K
On-Chip Memory Organization 512-Kbit Program Memory
512-Kbit Data Memory (organized as two blocks)
CPU ID+Rev ID Control Status Register (CSR.[31:16]) 0x0002
Frequency MHz 200
Cycle Time ns 5 ns (C6201-200)
Voltage
Core (V) 1.8
Voltage I/O (V) 3.3
PLL Options CLKIN frequency multiplier Bypass (x1), x4
BGA Packages
27 x 27 mm 352-Pin BGA (GJL)
BGA Packages 35 x 35 mm 352-Pin BGA (GJC)
Process Technology µm0.18 µm
Product Status Product Preview (PP)
Advance Information (AI)
Production Data (PD) PD
Device Part Numbers (For more details on the C6000 DSP part
numbering, see Figure 4) SM320C6201GJCA20EP
C6000 is a trademark of Texas Instruments.
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functional and CPU (DSP core) block diagram
Multichannel
Buffered Serial
Port 1
32
Direct Memory
Access Controller
(DMA)
(4 Channels)
Test
C62x CPU (DSP Core)
Data Path B
B Register File
Program
Access/Cache
Controller
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
PLL
(x1, x4)
Data
Access
Controller
Power-
Down
Logic
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
ROM/FLASH
SRAM
I/O Devices
32
Synchronous
FIFOs
I/O Devices
Timer 0
Timer 1
External Memory
Interface (EMIF)
Multichannel
Buffered Serial
Port 0
Host Port
Interface
(HPI)
Internal Program Memory
(64K Bytes)
Control
Registers
Control
Logic
Internal Data
Memory
(64K Bytes)
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
C6201 Digital Signal Processors
Peripheral Control Bus
DMA Bus
Boot Configuration
Interrupt
Selector
SBSRAM
SDRAM
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CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see functional and CPU (DSP core) block diagram
and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally, each side features a single data bus connected to all the registers on the other side, by
which the two sets of functional units can access data from the register files on the opposite side. While register
access by functional units on the same side of the CPU as the register file can service all the units in a single
clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- o r 15-bit of fsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch
packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the
current fe tch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
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CPU (DSP core) description (continued)
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2X
1X
.L2
.S2
.M2
.D2
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.M1
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.S1
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.L1
long src
dst
src2
src1
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src1
src1
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src1
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src1
8
8
8
8
88
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
Á
DA1
DA2
ST1
LD1
LD2
ST2
32
32
Register
File A
(A0−A15)
long src
long dst
long dst
long src
Data Path B
Data Path A
Register
File B
(B0−B15)
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
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signal groups description
HHWIL
HBE0
HBE1
HCNTL0
HCNTL1
TRST
EXT_INT7
Clock/PLL
JTAG
Emulation
Reserved
Data
Register Select
Half-Word/Byte
Select
Boot Mode
Reset and
Interrupts
Little ENDIAN
Big ENDIAN
DMA Status
Power-Down
Status
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
EMU1
EMU0
RSV3
RSV2
RSV1
RSV0
HD[15:0]
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
NMI
IACK
INUM3
INUM2
INUM1
INUM0
LENDIAN
DMAC3
DMAC2
DMAC1
DMAC0
PD
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
RSV7
RSV6
RSV5
RSV4
RSV8
EXT_INT6
EXT_INT5
EXT_INT4
RESET
RSV9
Figure 2. CPU (DSP Core) and Peripheral Signals
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8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
signal groups description (continued)
CE3
ARE
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE
AWE
ARDY
SSADS
SSOE
SSWE
SSCLK
SDA10
SDRAS
SDCAS
SDWE
SDCLK
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Word Address
Byte Enables
HOLD/
HOLDA
32
20
Asynchronous
Memory
Control
SBSRAM
Control
SDRAM
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
Figure 3. Peripheral Signals
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Signal Descriptions
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
CLOCK/PLL
CLKIN C10 I Clock Input
CLKOUT1 AF22 O Clock output at full device speed
CLKOUT2 AF20 O Clock output at half of device speed
CLKMODE1 C6
I
Clock mode selects
•
Selects whether the CPU clock frequency = input clock frequency x4 or x1
CLKMODE0 C5 I
•Selects whether the CPU clock frequency = input clock frequency x4 or x1
For more details on the GJC and GJL CLKMODE pins and the PLL multiply factors,
see the Clock PLL section of this data sheet.
PLLFREQ3 A9
PLL frequency range (3, 2, and 1)
PLLFREQ2 D11 I
PLL frequency range (3, 2, and 1)
•The target range for CLKOUT1 frequency is determined by the 3-bit value of the
PLLFREQ pins.
PLLFREQ1 B10
I
The target range for CLKOUT1 frequency is determined by the 3-bit value of the
PLLFREQ pins.
PLLV‡D12 A§PLL analog VCC connection for the low-pass filter
PLLG‡C12 A§PLL analog GND connection for the low-pass filter
PLLF A11 A§PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS L3 I JTAG test port mode select (features an internal pullup)
TDO W2 O/Z JTAG test port data out
TDI R4 I JTAG test port data in (features an internal pullup)
TCK R3 I JTAG test port clock
TRST T1 I JTAG test port reset (features an internal pulldown)
EMU1 Y1 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶
EMU0 W3 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶
RESET AND INTERRUPTS
RESET K2 I Device reset
NMI L2 I Nonmaskable interrupt
•Edge-driven (rising edge)
EXT_INT7 U3
External interrupts
EXT_INT6 V2
I
External interrupts
•
Edge-driven
EXT_INT5 W1 I
•Edge-driven
•Polarity independently selected via the external interrupt polarity register bits
(EXTPOL.[3:0])
EXT_INT4 U4
Polarity independently selected via the external interrupt polarity register bits
(EXTPOL.[3:0])
IACK Y2 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 AA1
Active interrupt identification number
INUM2 W4
O
Active interrupt identification number
•Valid during IACK for all active interrupts (not just external)
INUM1 AA2 O•
Valid during IACK for all active interrupts (not just external)
•
Encoding order follows the interrupt-service fetch-packet ordering
INUM0 AB1
•Encoding order follows the interrupt-service fetch-packet ordering
LITTLE ENDIAN/BIG ENDIAN
LENDIAN H3 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word
If low, LENDIAN selects big-endian addressing
POWER-DOWN STATUS
PD D3 O Power-down mode 2 or 3 (active if high)
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§A = Analog Signal (PLL Filter)
¶For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor . For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
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10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
HOST-PORT INTERFACE (HPI)
HINT H26 O Host interrupt (from DSP to host)
HCNTL1 F23 I Host control − selects between control, address, or data registers
HCNTL0 D25 I Host control − selects between control, address, or data registers
HHWIL C26 I Host half-word select − first or second half-word (not necessarily high or low order)
HBE1 E23 I Host byte select within word or half-word
HBE0 D24 I Host byte select within word or half-word
HR/W C23 I Host read or write select
HD15 B13
HD14 B14
HD13 C14
HD12 B15
HD11 D15
HD10 B16
HD9 A17
HD8 B17
I/O/Z
Host-port data (used for transfer of data, address, and control)
HD7 D16 I/O/Z Host-port data (used for transfer of data, address, and control)
HD6 B18
HD5 A19
HD4 C18
HD3 B19
HD2 C19
HD1 B20
HD0 B21
HAS C22 I Host address strobe
HCS B23 I Host chip select
HDS1 D22 I Host data strobe 1
HDS2 A24 I Host data strobe 2
HRDY J24 O Host ready (from DSP to host)
BOOT MODE
BOOTMODE4 D8
BOOTMODE3 B4
BOOTMODE2 A3 IBoot mode
BOOTMODE1 D5
I
Boot mode
BOOTMODE0 C4
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 AE22
Memory space enables
CE2 AD26
O/Z
Memory space enables
•Enabled by bits 24 and 25 of the word address
CE1 AB24 O/Z •
Enabled by bits 24 and 25 of the word address
•
Only one asserted during any external data access
CE0 AC26
•Only one asserted during any external data access
BE3 AB25
Byte-enable control
BE2 AA24
O/Z
Byte-enable control
•
Decoded from the two lowest bits of the internal address
BE1 Y23 O/Z
•Decoded from the two lowest bits of the internal address
•Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BE0 AA26
Byte-write enables for most types of memory
•Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF − ADDRESS
EA21 J26
EA20 K25
EA19 L24
EA18 K26
EA17 M26
EA16 M25
EA15 P25
EA14 P24
EA13 R25
EA12 T26
O/Z
External address (word address)
EA11 R23 O/Z External address (word address)
EA10 U26
EA9 U25
EA8 T23
EA7 V26
EA6 V25
EA5 W26
EA4 V24
EA3 W25
EA2 Y26
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
EMIF − DATA
ED31 AB2
ED30 AC1
ED29 AA4
ED28 AD1
ED27 AC3
ED26 AD4
ED25 AF3
ED24 AE4
ED23 AD5
ED22 AF4
ED21 AE5
ED20 AD6
ED19 AE6
ED18 AD7
ED17 AC8
ED16 AF7
I/O/Z
External data
ED15 AD9 I/O/Z External data
ED14 AD10
ED13 AF9
ED12 AC11
ED11 AE10
ED10 AE11
ED9 AF11
ED8 AE14
ED7 AF15
ED6 AE15
ED5 AF16
ED4 AC15
ED3 AE17
ED2 AF18
ED1 AF19
ED0 AC17
EMIF − ASYNCHRONOUS MEMORY CONTROL
ARE Y24 O/Z Asynchronous memory read enable
AOE AC24 O/Z Asynchronous memory output enable
AWE AD23 O/Z Asynchronous memory write enable
ARDY W23 I Asynchronous memory ready input
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
EMIF − SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SSADS AC20 O/Z SBSRAM address strobe
SSOE AF21 O/Z SBSRAM output enable
SSWE AD19 O/Z SBSRAM write enable
SSCLK AD17 O SBSRAM clock
EMIF − SYNCHRONOUS DRAM (SDRAM) CONTROL
SDA10 AD21 O/Z SDRAM address 10 (separate for deactivate command)
SDRAS AF24 O/Z SDRAM row-address strobe
SDCAS AD22 O/Z SDRAM column-address strobe
SDWE AF23 O/Z SDRAM write enable
SDCLK AE20 O SDRAM clock
EMIF − BUS ARBITRATION
HOLD AA25 I Hold request from the host
HOLDA A7 O Hold-request acknowledge to the host
TIMER1
TOUT1 H24 O Timer 1 or general-purpose output
TINP1 K24 I Timer 1 or general-purpose input
TIMER0
TOUT0 M4 O T imer 0 or general-purpose output
TINP0 K4 I Timer 0 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3 D2
DMAC2 F4
O
DMA action complete
DMAC1 D1 ODMA action complete
DMAC0 E2
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 E25 I External clock source (as opposed to internal)
CLKR1 H23 I/O/Z Receive clock
CLKX1 F26 I/O/Z Transmit clock
DR1 D26 I Receive data
DX1 G23 O/Z Transmit data
FSR1 E26 I/O/Z Receive frame sync
FSX1 F25 I/O/Z Transmit frame sync
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 L4 I External clock source (as opposed to internal)
CLKR0 M2 I/O/Z Receive clock
CLKX0 L1 I/O/Z Transmit clock
DR0 J1 I Receive data
DX0 R1 O/Z Transmit data
FSR0 P4 I/O/Z Receive frame sync
FSX0 P3 I/O/Z Transmit frame sync
RESERVED FOR TEST
RSV0 T2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1 G2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2 C11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3 B9 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV4 A6 I Reserved for testing, pulldown with a dedicated 20-kΩ resistor
RSV5 C8 O Reserved (leave unconnected, do not connect to power or ground)
RSV6 C21 I Reserved for testing, pullup with a dedicated 20-kW resistor
RSV7 B22 I Reserved for testing, pullup with a dedicated 20-kW resistor
RSV8 A23 I Reserved for testing, pullup with a dedicated 20-kW resistor
RSV9 E4 O Reserved (leave unconnected, do not connect to power or ground)
UNCONNECTED PINS
A8
B8
C9
D10
D21
NC G1 Unconnected pins
NC
H1
Unconnected pins
H2
J2
K3
R2
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
3.3-V SUPPLY VOLTAGE PINS
A10
A15
A18
A21
A22
B7
C1
D17
F3
G24
G25
H25
J25
L25
M3
N3
N23
R26
T24
DVDD
U24
S
3.3-V supply voltage
DVDD W24 S3.3-V supply voltage
Y4
AB3
AB4
AB26
AC6
AC10
AC19
AC21
AC22
AC25
AD11
AD13
AD15
AD18
AE18
AE21
AF5
AF6
AF17
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
1.8-V SUPPLY VOLTAGE PINS
A5
A12
A16
A20
B2
B6
B11
B12
B25
C3
C15
C20
C24
D4
D6
D7
D9
D14
CVDD
D18
S
1.8-V supply voltage
CVDD D20 S1.8-V supply voltage
D23
E1
F1
H4
J4
J23
K1
K23
M1
M24
N4
N25
P2
P23
T3
T4
U1
V4
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
1.8-V SUPPLY VOLTAGE PINS (CONTINUED)
V23
AC4
AC9
AC12
AC13
AC18
AC23
AD3
CVDD
AD8
S
1.8-V supply voltage
CVDD AD14 S1.8-V supply voltage
AD24
AE2
AE8
AE12
AE25
AF12
−
−
GROUND PINS
A1
A2
A4
A13
A14
A25
A26
B1
B3
V
SS
B5 GND Ground pins
VSS
B24
GND
Ground pins
B26
C2
C7
C13
C16
C17
C25
D13
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
GROUND PINS (CONTINUED)
D19
E3
E24
F2
F24
G3
G4
G26
J3
L23
L26
M23
N1
N2
N24
N26
P1
P26
VSS
R24
GND
Ground pins
VSS T25 GND Ground pins
U2
U23
V1
V3
Y3
Y25
AA3
AA23
AB23
AC2
AC5
AC7
AC14
AC16
AD2
AD12
AD16
AD20
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
PIN NO.
TYPE†
DESCRIPTION
SIGNAL
NAME GJC
TYPE†
DESCRIPTION
GROUND PINS (CONTINUED)
AD25
AE1
AE3
AE7
AE9
AE13
AE16
AE19
AE23
V
SS
AE24 GND Ground pins
VSS
AE26
GND
Ground pins
AF1
AF2
AF8
AF10
AF13
AF14
AF25
AF26
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 DSP family member devices, including documentation. See
this document for further information on TMS320 DSP documentation or any TMS320 DSP support products
from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide
(SPRU052), contains information about TMS320 DSP-related products from other companies in the industry.
To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924.
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under
“Development Tools”, select “Digital Signal Processors”. For information on pricing and availability, contact the
nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
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device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP family devices and support tools. Each TMS320 DSP member has one of three prefixes: TMX,
TMP, or TMS, and each SMJ320 DSP member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments
recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes
represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS). This development flow is defined below.
Device development evolutionary flow:
SMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
SM/SMJ Fully-qualified production device
Support tool development evolutionary flow:
TMDX Development support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS as well as SM/SMJ devices and TMDS development support tools have been characterized fully, and the
quality and reliability of the device has been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GNM) and temperature range (for example, M). Figure 4 provides a legend for reading the
complete device name for many TMS320 DSP family members.
TMS320 is a trademark of Texas Instruments.
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device and development-support tool nomenclature (continued)
PREFIX
SM 320 C 6201 GJC
SMX= experimental device
TMP = prototype device
TMS = qualified device
SMJ = MIL-PRF-38535 (QML)
SMQ= QML Plastic device
SM = commercial processing
DEVICE FAMILY
320 = TMS320 Family
TECHNOLOGY
TEMPERATURE RANGE
A = Extended temperature (−40°C to 105°C)
M = Military
C = CMOS
LC = Low-Voltage CMOS (3.3 V)
VC= Low-Voltage CMOS [3.3 V (2.5 V
or 1.8 V core)]
DEVICE
6000 DSP:
6201 6203
6701 6711
†BGA = Ball Grid Array
PACKAGE TYPE†
A
SPEED
20 = 200 MHz
20 EP
ENHANCED PLASTIC
NOTE: Not all speed, package, process, and temperature combinations are available.
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GFN = 256-pin plastic BGA
Figure 4. TMS320C6000 Device Nomenclature (Including SM320C6201-EP)
MicroStar BGA is a trademark of Texas Instruments.
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documentation support
Extensive documentation supports all TMS320 DSP family devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices and tools; technical briefs;
development-support tools; on-line help; and hardware and software applications. The following is a brief,
descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory
interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct
memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), peripheral
component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also
includes information on internal data and program memories.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x
devices, associated development tools, and third-party support.
The tools support documentation is electronically available within the Code Composer Studio IDE. For a
complete listing of the latest C6000 DSP documentation, visit the Texas Instruments web site on the
Worldwide Web at http://www.ti.com uniform resource locator (URL).
C67x is a trademark of Texas Instruments.
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clock PLL
All of the C62x clocks are generated from a single source through the CLKIN pin. This source clock either
drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 5 must be properly designed. Note
that for C6201, the EMI filter must be powered by the I/O voltage (3.3 V).
To configure the C62x PLL clock for proper operation, see Figure 5 and Table 2. To minimize the clock jitter,
a single clean power supply should power both the C62xDSP device and the external clock oscillator circuit.
The minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for
input clock timing requirements.
CLKIN
PLLV
PLLF
PLLG
010
001
000
PLLFREQ3
CLKOUT1 Frequency Range 130−233 MHz
CLKOUT1 Frequency Range 65−200 MHz
CLKOUT1 Frequency Range 50−140 MHz
PLLFREQ2
PLLFREQ1
CLKOUT
11
01
10
00
− MULT×4
− Reserved
− Reserved
− MULT×1
f(CLKOUT)=f(CLKIN)×4
f(CLKOUT)=f(CLKIN)
(Bypass) C1 C2
R1
CLKMODE0
CLKMODE1
CLKOUT1
CLKOUT2
SSCLK
SDCLK
EMIF
C6201
3.3 V
GND
2
1 IN
3 OUT
EMI Filter
C3
10 µFC4
0.1 µF
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown. For
CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.
B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLL V terminal has
to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.
C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a
PLLFREQ value of 000b should be used. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 001b. PLLFREQ values other than
000b, 001b, and 010b are reserved.
D. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
E. EMI filter manufacturer TDK part number ACF451832-153-T
Figure 5. PLL Block Diagram
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clock PLL (continued)
Table 2. PLL Component Selection Table
CLKMODE CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)C1
(nF) C2
(pF)
TYPICAL
LOCK TIME
(µs)†
x4 12.5−50 50−200 25−100 60.4 27 560 75
†Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state
returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time
between the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used
to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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absolute maximum ratings over operating case temperature ranges (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) −0.3 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, DVDD (see Note 1) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature ranges TC: (A version) −40_C to 105_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
CVDD Supply voltage 1.71 1.8 1.89 V
DVDD Supply voltage 3.14 3.30 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −12 mA
IOL Low-level output current 12 mA
TCOperating case temperature A version −40 105 _C
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage DVDD = MIN,
IOH = MAX 2.4 V
VOL Low-level output voltage DVDD = MIN,
IOL = MAX 0.6 V
IIInput current‡VI = VSS to DVDD ±10 uA
IOZ Off-state output current VO = DVDD or 0 V ±10 uA
IDD2V Supply current, CPU + CPU memory access§CVDD = NOM,
CPU clock = 167 MHz 380 mA
IDD2V Supply current, peripherals§CVDD = NOM,
CPU clock = 167 MHz 240 mA
IDD3V Supply current, I/O pins§DVDD = NOM,
CPU clock = 167 MHz 90 mA
CiInput capacitance 10 pF
CoOutput capacitance 10 pF
‡TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
§Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power
Consumption Summary application report (literature number SPRA486).
SGUS041A − MAY 2003 − REVISED JANUARY 2004
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
Vcomm
IOL
CT†
IOH
Output
Under
Test
50 Ω
Where: IOL = 2 mA
IOH = 2 mA
Vcomm = 0.8 V
CT= 15−30-pF typical load-circuit capacitance
†Typical distributed load circuit capacitance
Figure 6. TTL-Level Outputs
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 7. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and
VOL MAX and VOH MIN for output clocks.
Vref = VIL MAX (or VOL MAX)
Vref = VIH MIN (or VOH MIN)
Figure 8. Rise and Fall Transition Time Voltage Reference Levels
SGUS041A − MAY 2003 − REVISED JANUARY 2004
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN†‡ (see Figure 9)
−200
NO
.
CLKMODE
= x4 CLKMODE
= x1 UNIT
MIN MAX MIN MAX
1 tc(CLKIN) Cycle time, CLKIN 20 5 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.45C ns
4 tt(CLKIN) Transition time, CLKIN 5 0.6 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
1
2
3
4
4
Figure 9. CLKIN Timing Diagram
switching characteristics over recommended operating conditions for CLKOUT1§¶#
(see Figure 10)
−200
NO. PARAMETER CLKMODE = x4 CLKMODE = x1 UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 tc(CKO1) Cycle time, CLKOUT1 P − 0.7 P + 0.7 P − 0.7 P + 0.7 ns
2 tw(CKO1H) Pulse duration, CLKOUT1 high (P/2) − 0.5 (P/2 ) + 0.5 PH − 0.5 PH + 0.5 ns
3 tw(CKO1L) Pulse duration, CLKOUT1 low (P/2) − 0.5 (P/2 ) + 0.5 PL − 0.5 PL + 0.5 ns
4 tt(CKO1) Transition time, CLKOUT1 0.6 0.6 ns
§P = 1/CPU clock frequency in ns.
¶The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
#PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
CLKOUT1
1
3
4
4
2
Figure 10. CLKOUT1 Timing Diagram
SGUS041A − MAY 2003 − REVISED JANUARY 2004
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2†‡ (see Figure 11)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tc(CKO2) Cycle time, CLKOUT2 2P − 0.7 2P + 0.7 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high P − 0.7 P + 0.7 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low P − 0.7 P + 0.7 ns
4 tt(CKO2) Transition time, CLKOUT2 0.6 ns
†P = 1/CPU clock frequency in ns.
‡The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
CLKOUT2
1
2
3
4
4
Figure 11. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics over recommended operating conditions for the relation of SSCLK,
SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 12)†
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKO1-SSCLK) Delay time, CLKOUT1 edge to SSCLK edge (P/2) + 0.2 (P/2) + 4.2 ns
2 td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) (P/2) − 1 (P/2) + 2.4 ns
3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge (P/2) − 1 (P/2) + 2.4 ns
4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge (P/2) − 1 (P/2) + 2.4 ns
†P = 1/CPU clock frequency in ns.
4
3
2
1
CLKOUT1
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
SGUS041A − MAY 2003 − REVISED JANUARY 2004
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles† (see Figure 13 and Figure 14)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
6 tsu(EDV-CKO1H) Setup time, read EDx valid before CLKOUT1 high 4 ns
7 th(CKO1H-EDV) Hold time, read EDx valid after CLKOUT1 high 0.8 ns
10 tsu(ARDY-CKO1H) Setup time, ARDY valid before CLKOUT1 high 3 ns
11 th(CKO1H-ARDY) Hold time, ARDY valid after CLKOUT1 high 1.8 ns
†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
switching characteristics over recommended operating conditions for asynchronous memory
cycles‡ (see Figure 13 and Figure 14)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKO1H-CEV) Delay time, CLKOUT1 high to CEx valid −0.2 4 ns
2 td(CKO1H-BEV) Delay time, CLKOUT1 high to BEx valid 4 ns
3 td(CKO1H-BEIV) Delay time, CLKOUT1 high to BEx invalid −0.2 ns
4 td(CKO1H-EAV) Delay time, CLKOUT1 high to EAx valid 4 ns
5 td(CKO1H-EAIV) Delay time, CLKOUT1 high to EAx invalid −0.2 ns
8 td(CKO1H-AOEV) Delay time, CLKOUT1 high to AOE valid −0.2 4 ns
9 td(CKO1H-AREV) Delay time, CLKOUT1 high to ARE valid −0.2 4 ns
12 td(CKO1H-EDV) Delay time, CLKOUT1 high to EDx valid 4 ns
13 td(CKO1H-EDIV) Delay time, CLKOUT1 high to EDx invalid −0.2 ns
14 td(CKO1H-AWEV) Delay time, CLKOUT1 high to AWE valid −0.2 4 ns
‡The minimum delay is also the minimum output hold after CLKOUT1 high.
SGUS041A − MAY 2003 − REVISED JANUARY 2004
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
1111
10 10
99
88
7
6
54
32
11
CLKOUT1
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
Setup = 2 Strobe = 5 Not ready = 2 HOLD = 1
Figure 13. Asynchronous Memory Read Timing
11
10
11
10
1414
13
12
54
32
11
CLKOUT1
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
Setup = 2 Strobe = 5 Not ready = 2 HOLD = 1
Figure 14. Asynchronous Memory Write Timing
SGUS041A − MAY 2003 − REVISED JANUARY 2004
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 1.5 ns
8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles† (full-rate SSCLK) (see Figure 15 and Figure 16)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 0.5P − 1.3 ns
2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P − 2.3 ns
3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 0.5P − 1.3 ns
4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P − 2.3 ns
5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high 0.5P − 1.3 ns
6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P − 2.3 ns
9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 0.5P − 1.3 ns
10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P − 2.3 ns
11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 0.5P − 1.3 ns
12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P − 2.3 ns
13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high 0.5P − 1.3 ns
14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P − 2.3 ns
15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P − 1.3 ns
16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P − 2.3 ns
†When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
SGUS041A − MAY 2003 − REVISED JANUARY 2004
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
8
7
65
43
21
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
Figure 15. SBSRAM Read Timing (Full-Rate SSCLK)
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1615
109
14
13
65
43
21
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
Figure 16. SBSRAM Write Timing (Full-Rate SSCLK)
SGUS041A − MAY 2003 − REVISED JANUARY 2004
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 17)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
7 tsu(EDV-SSCLKH) Setup time, read EDx valid before SSCLK high 2.5 ns
8 th(SSCLKH-EDV) Hold time, read EDx valid after SSCLK high 1.5 ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles† (half-rate SSCLK) (see Figure 17 and Figure 18)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tosu(CEV-SSCLKH) Output setup time, CEx valid before SSCLK high 1.5P − 3 ns
2 toh(SSCLKH-CEV) Output hold time, CEx valid after SSCLK high 0.5P − 1.5 ns
3 tosu(BEV-SSCLKH) Output setup time, BEx valid before SSCLK high 1.5P − 3 ns
4 toh(SSCLKH-BEIV) Output hold time, BEx invalid after SSCLK high 0.5P − 1.5 ns
5 tosu(EAV-SSCLKH) Output setup time, EAx valid before SSCLK high 1.5P − 3 ns
6 toh(SSCLKH-EAIV) Output hold time, EAx invalid after SSCLK high 0.5P − 1.5 ns
9 tosu(ADSV-SSCLKH) Output setup time, SSADS valid before SSCLK high 1.5P − 3 ns
10 toh(SSCLKH-ADSV) Output hold time, SSADS valid after SSCLK high 0.5P − 1.5 ns
11 tosu(OEV-SSCLKH) Output setup time, SSOE valid before SSCLK high 1.5P − 3 ns
12 toh(SSCLKH-OEV) Output hold time, SSOE valid after SSCLK high 0.5P − 1.5 ns
13 tosu(EDV-SSCLKH) Output setup time, EDx valid before SSCLK high 1.5P − 3 ns
14 toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P − 1.5 ns
15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P − 3 ns
16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P − 1.5 ns
†When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
SGUS041A − MAY 2003 − REVISED JANUARY 2004
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
65
43
21
8
7
Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK)
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSOE
SSWE
SSADS
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1615
109
1413
65
43
21
Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK)
SGUS041A − MAY 2003 − REVISED JANUARY 2004
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
7 tsu(EDV-SDCLKH) Setup time, read EDx valid before SDCLK high 0.5 ns
8 th(SDCLKH-EDV) Hold time, read EDx valid after SDCLK high 3 ns
switching characteristics over recommended operating conditions for synchronous DRAM
cycles† (see Figure 19−Figure 24)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 tosu(CEV-SDCLKH) Output setup time, CEx valid before SDCLK high 1.5P − 3.5 ns
2 toh(SDCLKH-CEV) Output hold time, CEx valid after SDCLK high 0.5P − 1 ns
3 tosu(BEV-SDCLKH) Output setup time, BEx valid before SDCLK high 1.5P − 3.5 ns
4 toh(SDCLKH-BEIV) Output hold time, BEx invalid after SDCLK high 0.5P − 1 ns
5 tosu(EAV-SDCLKH) Output setup time, EAx valid before SDCLK high 1.5P − 3.5 ns
6 toh(SDCLKH-EAIV) Output hold time, EAx invalid after SDCLK high 0.5P − 1 ns
9 tosu(SDCAS-SDCLKH) Output setup time, SDCAS valid before SDCLK high 1.5P − 3.5 ns
10 toh(SDCLKH-SDCAS) Output hold time, SDCAS valid after SDCLK high 0.5P − 1 ns
11 tosu(EDV-SDCLKH) Output setup time, EDx valid before SDCLK high 1.5P − 3.5 ns
12 toh(SDCLKH-EDIV) Output hold time, EDx invalid after SDCLK high 0.5P − 1 ns
13 tosu(SDWE-SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P − 3.5 ns
14 toh(SDCLKH-SDWE) Output hold time, SDWE valid after SDCLK high 0.5P − 1 ns
15 tosu(SDA10V-SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P − 3.5 ns
16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P − 1 ns
17 tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P − 3.5 ns
18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P − 1 ns
†When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
SGUS041A − MAY 2003 − REVISED JANUARY 2004
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
109
1615
6
5
4
3
21
8
7
READ
READ
READ
Figure 19. Three SDRAM Read Commands
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
1413
109
1615
12
11
6
5
4
3
2
1
WRITE
WRITE
WRITE
Figure 20. Three SDRAM WRT Commands
SGUS041A − MAY 2003 − REVISED JANUARY 2004
38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
Bank Activate/Row Address
Row Address
18
17
15
5
2
1
ACTV
Figure 21. SDRAM ACTV Command
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE 14
18
16
2
15
1
17
13
DCAB
Figure 22. SDRAM DCAB Command
SGUS041A − MAY 2003 − REVISED JANUARY 2004
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
10
9
18
17
2
1
REFR
Figure 23. SDRAM REFR Command
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
MRS Value
14
10
18
6
2
1
5
17
9
13
MRS
Figure 24. SDRAM MRS Command
SGUS041A − MAY 2003 − REVISED JANUARY 2004
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 25)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
1 tsu(HOLDH-CKO1H) Setup time, HOLD high before CLKOUT1 high 1 ns
2 th(CKO1H-HOLDL) Hold time, HOLD low after CLKOUT1 high 4 ns
†HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles‡
(see Figure 25)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
3 td(HOLDL-BHZ) Delay time, HOLD low to EMIF Bus high impedance 4P §ns
4 td(BHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low P 2P ns
5 td(HOLDH-HOLDAH) Delay time, HOLD high to HOLDA high 4P 7P ns
6 td(CKO1H-HOLDAL) Delay time, CLKOUT1 high to HOLDA valid 1 8 ns
7 td(CKO1H-BHZ) Delay time, CLKOUT1 high to EMIF Bus high impedance¶311 ns
8 td(CKO1H-BLZ) Delay time, CLKOUT1 high to EMIF Bus low impedance¶311 ns
9 td(HOLDH-BLZ) Delay time, HOLD high to EMIF Bus low impedance 3P 6P ns
‡P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus External Requester DSP Owns Bus
C62x Ext Req C62x
8
7
34
6
6
12
CLKOUT1
HOLD
HOLDA
EMIF Bus†
1
5
9
2
†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 25. HOLD/HOLDA Timing
SGUS041A − MAY 2003 − REVISED JANUARY 2004
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING
timing requirements for reset (see Figure 26)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
1
tw(RST)
Width of the RESET pulse (PLL stable)†10 CLKOUT1
cycles
1
tw(RST)
Width of the RESET pulse (PLL needs to sync up)‡250 µs
†This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
‡This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need u p t o 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the Clock PLL section for PLL lock times.
switching characteristics over recommended operating conditions during reset§¶ (see Figure 26)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 tR(RST) Response time to change of value in RESET signal 2CLKOUT1
cycles
3 td(CKO1H-CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid −1 ns
4 td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid 10 ns
5 td(CKO1H-SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid −1 ns
6 td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK valid 10 ns
7 td(CKO1H-SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid −1 ns
8 td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK valid 10 ns
9 td(CKO1H-LOWIV) Delay time, CLKOUT1 high to low group invalid −1 ns
10 td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group valid 10 ns
11 td(CKO1H-HIGHIV) Delay time, CLKOUT1 high to high group invalid −1 ns
12 td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group valid 10 ns
13 td(CKO1H-ZHZ) Delay time, CLKOUT1 high to Z group high impedance −1 ns
14 td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group valid 10 ns
§Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
High group consists of: HINT
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
¶HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
SGUS041A − MAY 2003 − REVISED JANUARY 2004
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
RESET TIMING (CONTINUED)
122
1413
1211
109
87
65
43
CLKOUT1
RESET
CLKOUT2
SDCLK
SSCLK
LOW GROUP†‡
HIGH GROUP†‡
Z GROUP†‡
†Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
High group consists of: HINT
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
‡HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
Figure 26. Reset Timing
SGUS041A − MAY 2003 − REVISED JANUARY 2004
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles†‡ (see Figure 27)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
2 tw(ILOW) Width of the interrupt pulse low 2P ns
3 tw(IHIGH) Width of the interrupt pulse high 2P ns
†Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions during interrupt response
cycles§ (see Figure 27)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(EINTH-IACKH) Delay time, EXT_INTx high to IACK high 9P ns
4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid −4 6 ns
5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 6 ns
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid −4 ns
§P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
Interrupt Number
6
5
4
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
Figure 27. Interrupt Timing
SGUS041A − MAY 2003 − REVISED JANUARY 2004
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30, and
Figure 31)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
1 tsu(SEL-HSTBL) Setup time, select signals§ valid before HSTROBE low 4 ns
2 th(HSTBL-SEL) Hold time, select signals§ valid after HSTROBE low 2 ns
3 tw(HSTBL) Pulse duration, HSTROBE low 2P ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 2P ns
10 tsu(SEL-HASL) Setup time, select signals§ valid before HAS low 4 ns
11 th(HASL-SEL) Hold time, select signals§ valid after HAS low 2 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 3 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 2 ns
14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly. 1 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡The e ffects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
switching characteristics over recommended operating conditions during host-port interface
cycles†‡ (see Figure 28, Figure 29, Figure 30, and Figure 31)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
5 td(HCS-HRDY) Delay time, HCS to HRDY¶1 9 ns
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#3 12 ns
7 toh(HSTBL-HDLZ) Output hold time, HD low impedance after HSTROBE low for an HPI read 4 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low P − 3 P + 3 ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 2 12 ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 2 12 ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 12 ns
20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 12 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡The e ffects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
SGUS041A − MAY 2003 − REVISED JANUARY 2004
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st Half-Word 2nd Half-Word
5
17
86
5
17
85
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 28. HPI Read Timing (HAS Not Used, Tied High)
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word 2nd half-word
517820
51785
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10 19 19
18
18
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Read Timing (HAS Used)
SGUS041A − MAY 2003 − REVISED JANUARY 2004
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st Half-Word 2nd Half-Word 5
17
5
13
12
13
12
4
14
3
2
1
2
1
2
1
2
1
13
12
13
12
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
HBE[1:0]
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Not Used, Tied High)
1st half-word 2nd half-word 5
17
5
13
12
13
12
4
14
3
11
10
11
10
11
10
11
10
11
10
11
10
13
12
13
12
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
HBE[1:0]
19
19
18 18
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 31. HPI Write Timing (HAS Used)
SGUS041A − M AY 2003 − REVISED JANUARY 2004
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡(see Figure 32)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P − 1¶ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 9
ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 8
ns
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 9
ns
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶The minimum CLKR/X pulse duration is either (P−1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P−1) = 9 ns as the minimum CLKR/X pulse
duration.
SGUS041A − M AY 2003 − REVISED JANUARY 2004
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡§ (see Figure 32)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input 3 10 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P¶ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1.3#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int −2 3
ns
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 9 ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX int −1 4
ns
12 tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high CLKX ext 3 9 ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −1 4
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 9 ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid FSX int −1 3
ns
14 td(FXH-DXV) ONLY applies when in data
delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶The maximum bit rate for the C6202/02B/03 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
#C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
SGUS041A − M AY 2003 − REVISED JANUARY 2004
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
Figure 32. McBSP Timing Diagram
SGUS041A − M AY 2003 − REVISED JANUARY 2004
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 33)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR External
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 33. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡
(see Figure 34)
−200
NO. MASTER SLAVE UNIT
NO.
MIN MAX MIN MAX
UNIT
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SGUS041A − M AY 2003 − REVISED JANUARY 2004
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34)
−200
NO. PARAMETER MASTER§SLAVE UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T − 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L − 2 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −2 4 3P + 4 5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low L − 2 L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high P + 3 3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SGUS041A − M AY 2003 − REVISED JANUARY 2004
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35)
−200
NO. MASTER SLAVE UNIT
NO.
MIN MAX MIN MAX
UNIT
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35)
−200
NO. PARAMETER MASTER§SLAVE UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L − 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T − 2 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −2 4 3P + 4 5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low −2 4 3P + 3 5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 4 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SGUS041A − M AY 2003 − REVISED JANUARY 2004
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 36)
−200
NO. MASTER SLAVE UNIT
NO.
MIN MAX MIN MAX
UNIT
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36)
−200
NO. PARAMETER MASTER§SLAVE UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T − 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H − 2 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −2 4 3P + 4 5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high H − 2 H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high P + 3 3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SGUS041A − M AY 2003 − REVISED JANUARY 2004
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37)
−200
NO. MASTER SLAVE UNIT
NO.
MIN MAX MIN MAX
UNIT
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37)
−200
NO. PARAMETER MASTER§SLAVE UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H − 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T − 2 T + 1 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −2 4 3P + 4 5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high −2 4 3P + 3 5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 4 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SGUS041A − M AY 2003 − REVISED JANUARY 2004
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
SGUS041A − M AY 2003 − REVISED JANUARY 2004
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics over recommended operating conditions for DMAC outputs
(see Figure 38)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKO1H-DMACV) Delay time, CLKOUT1 high to DMAC valid 2 10 ns
11
CLKOUT1
DMAC[0:3]
Figure 38. DMAC Timing Diagram
timing requirements for timer inputs† (see Figure 39)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
1 tw(TINP) Pulse duration, TINP high or low 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for timer outputs
(see Figure 39)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid 2 9 ns
2
1
CLKOUT1
TINP
TOUT 2
Figure 39. Timer Timing Diagram
switching characteristics over recommended operating conditions for power-down outputs
(see Figure 40)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 td(CKO1H-PDV) Delay time, CLKOUT1 high to PD valid 2 9 ns
11
CLKOUT1
PD
Figure 40. Power-Down Timing
SGUS041A − M AY 2003 − REVISED JANUARY 2004
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 41)
NO.
−200
UNIT
NO.
MIN MAX
UNIT
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 41)
NO.
PARAMETER
−200
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid −3 12 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 41. JTAG Test-Port Timing Diagram
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SM320C6201GJCA20EP ACTIVE FC/CSP GJC 352 21 TBD Call TI Level-4-220C-72 HR
V62/04606-01XA ACTIVE FC/CSP GJC 352 21 TBD Call TI Level-4-220C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Feb-2006
Addendum-Page 1
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