Page 1 of 13
Document No. 70-0378-01 │www.psemi.com ©2012 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Product Description
The PE64101 is a DuNE™-enhanced Digitally Tunable
Capacitor (DTC) based on Peregrine’s UltraCMOS®
technology. DTC products provide a monolithically
integrated impedance tuning solution for demanding RF
applications. They also offer a cost-effective tunable
capacitor with excellent linearity and ESD performance.
This highly versatile product can be mounted in series or
shunt configuration and is controlled by a 3-wire (SPI
compatible) serial interface. High ESD rating of 2 kV
HBM on all ports making this the ultimate in integration
and ruggedness. The DTC is offered in a standard 12-
lead 2.0 x 2.0 x 0.55 mm QFN package.
Peregrine’s DuNE™ technology enhancements deliver
high linearity and exceptional harmonics performance. It
is an innovative feature of the UltraCMOS® process,
providing performance superior to GaAs with the
economy and integration of conventional CMOS.
CMOS Control
Driver and ESD
RF+ RF-
Serial
Interface
ESD ESD
Figure 1. Functional Block Diagram
71-0066-01
Figure 2. Package Type
12-lead 2 x 2 x 0.55 mm QFN
Features
3-wire (SPI compatible) 8-bit serial interface
with built-in bias voltage generation and
stand-by mode for reduced power
consumption
DuNE™-enhanced UltraCMOS® device
5-bit 32-state Digitally Tunable Capacitor
C = 1.38 – 5.90 pF (4.3:1 tuning ratio) in
discrete 146 fF steps
RF power handling (up to 26 dBm, 6 VPK RF)
and high linearity
High quality factor
Wide power supply range (2.3 to 3.6V) and
low current consumption
(typ. IDD = 30 µA @ 2.8V)
Optimized for shunt configuration, but can
also be used in series configuration
Excellent 2 kV HBM ESD tolerance on all
pins
Applications include:
Antenna tuning
Tunable filters
Phase shifters
Impedance matching
Product Specification
UltraCMOS® Digitally Tunable Capacitor
(DTC) 100 - 3000 MHz
PE64101
END OF LIFE
Product Specification
PE64101
Page 2 of 13
©2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 │ UltraCMOS® RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Table 1. Electrical Specifications @ 25°C, VDD = 2.8V
Parameter Configuration Condition Min Typ Max Units
Operating Frequency Range 7 Both 100 3000 MHz
Minimum Capacitance Shunt 6 State = 00000, 100 MHz (RF+ to Grounded RF-) -10% 1.38 +10% pF
Maximum Capacitance Shunt 6 State = 11111, 100 MHz (RF+ to Grounded RF-) -10% 5.90 +10% pF
Tuning Ratio Shunt 6 Cmax/Cmin, 100 MHz 4.3:1
Step Size Shunt 6 5 bits (32 states), constant step size (100 MHz) 0.146 pF
Quality Factor (Cmin) 1 Shunt 6 470 - 582 MHz with Ls removed
698 - 960 MHz, with Ls removed
1710 - 2170 MHz, with Ls removed 50
50
30
Quality Factor (Cmax) 1 Shunt 6 470 - 582 MHz with Ls removed
698 - 960 MHz, with Ls removed
1710 - 2170 MHz, with Ls removed 50
25
10
Self Resonant Frequency Shunt 7 State 00000
State 11111 5.5
2.5 GHz
Harmonics (2fo and 3fo) 4
Shunt 6 470 to 582 MHz, Pin +26 dBm, 50Ω
698 to 915 MHz, Pin +26 dBm, 50Ω
1710 to 1910 MHz, Pin +26 dBm, 50Ω -36
-36
-36
dBm
dBm
dBm
Series 5 470 to 582 MHz, Pin +20 dBm, 50Ω
698 to 915 MHz, Pin +20 dBm, 50Ω
1710 to 1910 MHz, Pin +20 dBm, 50Ω -36
-36
-36
dBm
dBm
dBm
3rd Order Intercept Point Shunt 6 IIP3 = (Pblocker + 2*Ptx - [IMD3]) / 2, where IMD3 = -95 dBm,
Ptx = +20 dBm and Pblocker = -15 dBm 60 dBm
Switching Time 2, 3 Shunt 6 State change to 10/90% delta capacitance between any two
states 2 10 µs
Start-up Time 2 Shunt 6 Time from VDD within specification to all performances within
specification 5 20 µs
Wake-up Time 2, 3 Shunt 6 State change from standby mode to RF state to all
performances within specification 5 20 µs
Note: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit
Q = XC / R = (X-XL)/R, where X = XL + XC , XL = 2*pi*f*L, XC = -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance LS
2. DC path to ground at RF+ and RF– must be provided to achieve specified performance
3. State change activated on falling edge of SEN following data word
4. Between 50Ω ports in series or shunt configuration using a pulsed RF input with 4620 vs period, 50% duty cycle, measured per 3GPPTS45.005
5. In series configuration the greater RF power or higher RF voltage should be applied to RF+
6. RF- should be connected to ground
7. DTC operation above SRF is possible
END OF LIFE
Product Specification
PE64101
Page 3 of 13
Document No. 70-0378-01 │www.psemi.com ©2012 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Table 3. Operating Ranges1
Parameter Symbol Min Typ Max Units
VDD Supply Voltage VDD 2.3 2.8 3.6 V
IDD Power Supply Current
(Normal mode) 6 IDD 30 75 µA
IDD Power Supply Current
(Standby mode) 6 IDD 20 45 µA
Control Voltage High VIH 1.2 3.1 V
Control Voltage Low VIL 0 0.2 V
Peak Operating RF Voltage 5
VP to VM
VP to RFGND
VM to RFGND
6
6
6
VPK
VPK
VPK
RF Input Power (50Ω ) 3, 4, 5
shunt
series
+26
+20
dBm
dBm
Input Control Current ICTL 1 10 µA
Operating Temperature Range TOP -40 +85 °C
Storage Temperature Range TST -65 +150 °C
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any DC input -0.3 4.0 V
VESD ESD Voltage (HBM, MIL_STD
883 Method 3015.7) 2000 V
VESD ESD Voltage (MM, JEDEC
JESD22-A115-A) 100 V
Notes: 1. Operation should be restricted to the limits in the Operating Ranges table
2. The DTC is active when STBY is low (set to 0) and in low-current
stand-by mode when high (set to 1)
3. Maximum CW power available from a 50Ω source in shunt configuration
4. Maximum CW power available from a 50Ω source in series configuration
5. RF+ to RF- and RF+ and/or RF- to ground. Cannot exceed 6 VPK or max
RF input power (whichever occurs first)
6. IDD current typical value is based on VDD = 2.8V. Max IDD is based on
VDD = 3.6V
Exceeding absolute maximum ratings may cause
permanent damage. Operation between operating
range maximum and absolute maximum for
extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Figure 3. Pin Configuration (Top View)
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE64101 in the 12-lead 2 x 2 QFN package is
MSL1.
Table 2. Pin Descriptions
Pin # Pin Name Description
1 SEN Serial Enable
2 GND Digital and RF Ground
3 SCLK Serial Interface Clock Input
4 VDD Power Voltage
5 GND Digital and RF Ground
6 RF- Negative RF Port 1
7 RF- Negative RF Port 1
8 GND Digital and RF Ground 3
9 RF+ Positive RF Port 2
10 RF+ Positive RF Port 2
11 GND Digital and RF Ground
12 SDAT Serial Interface Data Input
13 GND Digital and RF Ground 3
Notes: 1. Pins 6 and 7 must be tied together on PCB board to reduce
inductance
2. Pins 9 and 10 must be tied together on PCB board to reduce
inductance
3. Pin 2, 5, 8, 11 and 13 must be connected together on PCB
SEN
6
7
81
2
3
GND
SCLK
RF+
GND
RF-
SDAT
GND
RF+
VDD
GND
RF-
13
GND
12 11 10
9
456
8
7
1
2
3
Pin 1
END OF LIFE
Product Specification
PE64101
Page 4 of 13
©2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 │ UltraCMOS® RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Figure 6. Measured Step Size vs State
(frequency)
Figure 5. Measured Shunt S11 (major states)
Performance Plots @ 25°C and 2.8V unless otherwise specified
Figure 8. Measured Shunt C vs
Frequency (major states) Figure 9. Measured Series S21 vs Frequency
(major states)
Figure 4. Measured Shunt C (@ 100 MHz) vs
State (temperature)
0 0.5 1 1.5 2 2.5 3
-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (GHz)
dB(S21)
Measured Series S21 vs. Frequency (major states)
C0
C1
C2
C4
C8
C16
C31
Figure 7. Measured Series S11/S22 (major states)
0 5 10 15 20 25 30
0
1
2
3
4
5
6
7
8
State
Capacitance(pF)
Measured Shunt C (@ 100 MHz) vs. State
510 15 20 25 30
50
100
150
200
State
Step size (fF)
Measured Step Size vs. State (frequency)
100 MHz
470 MHz
582 MHz
862 MHz
Measured Series S11/S22 (major states)
Frequency(.3 - 3000 MHz)
S11 C0
S22 C0
S11 C1
S22 C1
S11 C2
S22 C2
S11 C4
S22 C4
S11 C8
S22 C8
S11 C16
S22 C16
S11 C31
S22 C31
END OF LIFE
Product Specification
PE64101
Page 5 of 13
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Figure 11. Measured 2-Port Shunt S21 vs
Frequency (major states)
Figure 10. Measured Shunt Q vs
Frequency (major states)
Figure 12. Measured Self Resonance
Frequency vs State
0 2 4 6 8
-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (GHz)
dB(S21)
Measured 2-Port Shunt S21 vs. Frequency (major states)
C0
C1
C2
C4
C8
C16
C31
Figure 13. Measured Shunt Q vs State
510 15 20 25 30
0
20
40
60
80
100
120
140
160
State
Q
Measured Q vs. State
100 MHz
470 MHz
698 MHz
1710 MHz
END OF LIFE
Product Specification
PE64101
Page 6 of 13
©2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 │ UltraCMOS® RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Serial Interface Operation and Sharing
The PE64101 is controlled by a three wire SPI-
compatible interface. As shown in Figure 14, the
serial master initiates the start of a telegram by
driving the SEN (Serial Enable) line high. Each bit
of the 8-bit telegram is clocked in on the rising
edge of the SCL (Serial Clock) line. SDA bits are
clocked by most significant bit (MSB) first, as
shown in Table 5 and Figure 14. Transactions on
SDA (Serial Data) are allowed on the falling edge
of SCL. The DTC activates the data on the falling
edge of SEN. The DTC does not count how many
bits are clocked and only maintains the last 8 bits it
received.
More than 1 DTC can be controlled by one
interface by utilizing a dedicated enable (SEN) line
for each DTC. SDA, SCL, and VDD lines may be
shared as shown in Figure 15. Dedicated SEN
lines act as a chip select such that each DTC will
only respond to serial transactions intended for
them. This makes each DTC change states
sequentially as they are programmed.
Alternatively, a dedicated SDA line with common
SEN can be used. This allows all DTCs to change
states simultaneously, but requires all DTCs to be
programmed even if the state is not changed.
Figure 14. Serial Interface Timing Diagram (oscilloscope view)
b5b6
tR
tDHD
tDSU 1/fCLK
b7 b0b4 b3 b2 b1
Dm-1<7:0> Dm<7:0>
b0
Dm-2<7:0>
tEPW tF
tESU tEHD
SEN
SCL
SDA
DTC Data
END OF LIFE
Product Specification
PE64101
Page 7 of 13
Document No. 70-0378-01 │www.psemi.com ©2012 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Table 5. 6-Bit Serial Programming Register Map
Table 6. Serial Interface AC Characteristics
2.3V < VDD < 3.6V, -40 °C < TA < +85 °C, unless otherwise specified
Symbol Parameter Min Max Unit
fCLK Serial Clock Frequency 26 MHz
tR SCL, SDA, SEN Rise Time 6.5 ns
tF SCL, SDA, SEN Fall Time 6.5 ns
tESU SEN rising edge to SCL rising edge 19.2 ns
tEHD SCL rising edge to SEN falling edge 19.2 ns
tDSU SDA valid to SCL rising edge 13.2 ns
tDHD SDA valid after SCL rising edge 13.2 ns
tEOW SEN falling edge to SEN rising edge 38.4 ns
b4 b3 b2 b1 b0 b5 b7 b6
d4 d3 d2 d1 d0 STB1 0 0
MSB (first in) LSB (last in)
Note: 1. The DTC is active when low (set to 0) and in low-current stand-by
mode when high (set to 1)
Figure 15. Recommended Bus sharing
SCL
SDA
VDD
GND
DGND RF-
RF+
SCL
SDA
VDD
SEN
GND
DGND RF-
RF+
SCL
SDA
VDD
DTC 1
SEN
SEN2
SEN1
DTC 2
END OF LIFE
Product Specification
PE64101
Page 8 of 13
©2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 │ UltraCMOS® RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Equivalent Circuit Model Description
The DTC Equivalent Circuit Model includes all
parasitic elements and is accurate in both Series
and Shunt configurations, reflecting physical circuit
behavior accurately and providing very close
correlation to measured data. It can easily be used
in circuit simulation programs. Simple equations
are provided for the state dependent parameters.
The Tuning Core capacitance CS represents
capacitance between RF+ and RF- ports. It is
linearly proportional to state (0 to 31 in decimal) in
a discrete fashion. The Series Tuning Ratio is
defined as CSmax/CSmin.
CP1 and CP2 represent the circuit and package
parasitics from RF ports to GND. In shunt
configuration the total capacitance of the DTC is
higher due to parallel combination of CP and CS. In
Series configuration, CS and CP do not add in
parallel and the DTC appears as an impedance
transformation network.
Parasitic inductance due to circuit and package is
modeled as LS and causes the apparent
capacitance of the DTC to increase with frequency
until it reaches Self Resonant Frequency (SRF).
The value of SRF depends on state and is
approximately inversely proportional to the square
root of capacitance.
The overall dissipative losses of the DTC are
modeled by RS, RP1 and RP2 resistors. The
parameter RS represents the Equivalent Series
Resistance (ESR) of the tuning core and is
dependent on state. RP1 and RP2 represent losses
due to the parasitic and biasing networks.
Figure 16. Equivalent Circuit Model Schematic
Table 7. Equivalent Circuit Model Parameters
Variable Equation (state = 0, 1, 2…31) Unit
CS 0.148*state + 0.97 pF
RS 30/(state+30/(state+0.4)) + 0.4 Ω
CP1 -0.0022*state + 0.4005 pF
CP2 0.0026*state + 0.5092 pF
RP1 4 Ω
RP2 22000 + 6*(state)^3 Ω
LS 0.4 nH
Table 8. Maximum Operating RF Voltage
Condition Limit
VP to VM 6 VPK
VP to RFGND 6 VPK
VM to RFGND 6 VPK
RF+ LsVP
CP1
RP1
RP2
RF-
RsCsLs
VM
CP2
RP1
RP2
RFGND
END OF LIFE
Product Specification
PE64101
Page 9 of 13
Document No. 70-0378-01 │www.psemi.com ©2012 Peregrine Semiconductor Corp. All rights reserved.
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Table 9. Equivalent Circuit Data
State DTC Core Parasitic Elements
Binary Decimal Cs [pF] Rs [Ω] Cp1 [pF] Cp2 [pF] Rp2 [kΩ] Ls [nH] Rp1 [Ω]
00000 0 0.97 0.80 0.40 0.51 22.0
0.40 4.0
00001 1 1.12 1.73 0.40 0.51 22.0
00010 2 1.27 2.41 0.40 0.51 22.0
00011 3 1.41 2.81 0.39 0.52 22.2
00100 4 1.56 2.98 0.39 0.52 22.4
00101 5 1.71 3.00 0.39 0.52 22.8
00110 6 1.86 2.92 0.39 0.52 23.3
00111 7 2.01 2.81 0.39 0.53 24.1
01000 8 2.15 2.68 0.38 0.53 25.1
01001 9 2.30 2.54 0.38 0.53 26.4
01010 10 2.45 2.42 0.38 0.54 28.0
01011 11 2.60 2.29 0.38 0.54 30.0
01100 12 2.75 2.18 0.37 0.54 32.4
01101 13 2.89 2.08 0.37 0.54 35.2
01110 14 3.04 1.99 0.37 0.55 38.5
01111 15 3.19 1.90 0.37 0.55 42.3
10000 16 3.34 1.83 0.37 0.55 46.6
10001 17 3.49 1.76 0.36 0.55 51.5
10010 18 3.63 1.69 0.36 0.56 57.0
10011 19 3.78 1.63 0.36 0.56 63.2
10100 20 3.93 1.58 0.36 0.56 70.0
10101 21 4.08 1.53 0.35 0.56 77.6
10110 22 4.23 1.48 0.35 0.57 85.9
10111 23 4.37 1.44 0.35 0.57 95.0
11000 24 4.52 1.40 0.35 0.57 104.9
11001 25 4.67 1.36 0.35 0.57 115.8
11010 26 4.82 1.33 0.34 0.58 127.4
11011 27 4.97 1.30 0.34 0.58 140.1
11100 28 5.11 1.27 0.34 0.58 153.7
11101 29 5.26 1.24 0.34 0.58 168.3
11110 30 5.41 1.21 0.33 0.59 184.0
11111 31 5.56 1.19 0.33 0.59 200.7
END OF LIFE
Product Specification
PE64101
Page 10 of 13
©2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 │ UltraCMOS® RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Figure 17. Evaluation Board Layout
101-0700
Evaluation Board
The 101-0700 Evaluation Board (EVB) was
designed for accurate measurement of the DTC
impedance and loss. Two configurations are
available: 1 Port Shunt (J3) and 2 Port Shunt (J4,
J5). Three calibration standards are provided. The
open (J2) and short (J1) standards (104 ps delay)
are used for performing port extensions and
accounting for electrical length and transmission
line loss. The Thru (J9, J10) standard can be used
to estimate PCB transmission line losses for scalar
de-embedding of the 2 Port Shunt configuration (J4,
J5).
The board consists of a 4 layer stack with 2 outer
layers made of Rogers 4350B (εr = 3.48) and 2
inner layers of FR4 (εr = 4.80). The total thickness
of this board is 62 mils (1.57 mm). The inner layers
provide a ground plane for the transmission lines.
Each transmission line is designed using a coplanar
waveguide with ground plane (CPWG) model using
a trace width of 32 mils (0.813 mm), gap of 15 mils
(0.381 mm), and a metal thickness of 1.4 mils
(0.036 mm).
END OF LIFE
Product Specification
PE64101
Page 11 of 13
Document No. 70-0378-01 │www.psemi.com ©2012 Peregrine Semiconductor Corp. All rights reserved.
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Figure 18. Evaluation Board Schematic
102-0833
SHORT
1 PORT SHUNT
2 PORT SHUNT
J2
SMA CONN
TP4
J9
SMA CONN J10
SMA CONN
J1
SMA CONN
TP5
J3
SMA CONN
C3
100pF
1
13
35
57
7
22
44
66
88
10 10
12 12
14 14 13
13
9
911
11
J8
14 PIN HEADER
J5
SMA CONN
C7
100pF
1
13
35
57
7
22
44
66
88
10 10
12 12
14 14 13
13
9
911
11
J11
14 PIN HEADER
R3 DNI
R1 DNI
R2 DNI
R4 DNI
C9
100pF
C10
100pF
C11
100pF
R5 DNI
R6 DNI
R7 DNI
R8 DNI
C12
100pF
C13
100pF
C14
100pF
R9 DNI
R10 DNI
R11 DNI
R12 DNI
R13 DNI
R14 DNI
J4
SMA CONN
6RF-
7RF-
2GND
4VDD
1
SEN 12
SDAT 10
RF+ 9
RF+
11 GND
3SCLK
5GND
8GND
13 PADDLE
U1
PE6410X_QFN_12L_2X2
6RF-
7RF-
2GND
4VDD
1
SEN 12
SDAT 10
RF+ 9
RF+
11 GND
3SCLK
5GND
8GND
13 PADDLE
U2
PE6410X_QFN_12L_2X2
OPEN
THRU
SCL
SEN
SDA
VDD
VDD_1
SCL_1
SEN_1
SDA_1
END OF LIFE
Product Specification
PE64101
Page 12 of 13
©2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0378-01 │ UltraCMOS® RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Figure 19. Package Drawing
12-lead 2 x 2 x 0.55 mm QFN
Figure 20. Top Marking Specifications
PPZZ
YWW
Marking Spec
Symbol Package
Marking Definition
PP CR Part number marking for PE64101
ZZ 00-99 Last two digits of lot code
Y 0-9 Last digit of year, starting from 2009
(0 for 2010, 1 for 2011, etc)
WW 01-53 Work week
17-0112
END OF LIFE
Product Specification
PE64101
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Document No. 70-0378-01 │www.psemi.com ©2012 Peregrine Semiconductor Corp. All rights reserved.
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Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Table 10. Ordering Information
Order Code Package Description Shipping Method
PE64101MLAA-Z 12-lead 2 x 2 x 0.55 mm QFN Package Part in Tape and Reel 3000 units/T&R
EK64101-11 Evaluation Kit Evaluation Kit 1 Set/Box
Figure 21. Tape and Reel Specifications
12-lead 2 x 2 x 0.55 mm QFN
Tape Feed Direction
Top of
Device
Pin 1
Device Orientation in Tape
END OF LIFE