Order this document by MTP7N20E/D SEMICONDUCTOR TECHNICAL DATA Motorola Preferred Device N-Channel Enhancement-Mode Silicon Gate This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature TMOS POWER FET 7.0 AMPERES 200 VOLTS RDS(on) = 0.70 OHMS D G S CASE 221A-06, Style 5 TO-220AB MAXIMUM RATINGS (TC = 25C unless otherwise noted) Symbol Value Unit Drain-to-Source Voltage VDSS 200 Vdc Drain-to-Gate Voltage (RGS = 1.0 M) VDGR 200 Vdc Gate-to-Source Voltage -- Continuous -- Non-Repetitive (tp 10 ms) VGS VGSM 20 40 Vdc Vpk Drain Current -- Continuous -- Continuous @ 100C -- Single Pulse (tp 10 s) ID ID IDM 7.0 3.8 21 Adc Total Power Dissipation @ TC = 25C Derate above 25C PD 50 0.4 Watts W/C TJ, Tstg - 55 to 150 C Rating Operating and Storage Temperature Range Apk Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Adc, L = 10 mH, RG = 25 ) EAS Thermal Resistance -- Junction to Case -- Junction to Ambient RJC RJA 2.5 62.5 C/W TL 260 C Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds mJ 74 Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design. E-FET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. TMOS Motorola Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1 MTP7N20E ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 200 -- -- 689 -- -- Vdc mV/C -- -- -- -- 10 100 -- -- 100 nAdc 2.0 -- 3.1 7.1 4.0 -- Vdc mV/C -- 0.46 0.7 Ohm -- -- 3.4 -- 5.9 5.1 gFS 1.5 -- -- mhos Ciss Coss -- 342 480 pF -- 92 130 Crss -- 27 55 td(on) tr -- 8.8 17.6 -- 29 58 td(off) tf -- 22 44 -- 20 40.8 QT -- 13.7 21 Q1 -- 3.3 Q2 -- 6.6 -- Q3 -- 5.9 -- -- -- 1.02 0.9 1.2 -- trr ta -- 138 -- -- 93 -- tb QRR -- 45 -- -- 0.74 -- -- -- 3.5 4.5 -- -- -- 7.5 -- OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) IDSS Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) IGSS Adc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (negative) VGS(th) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 3.5 Adc) RDS(on) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 10 Vdc, ID = 3.5 Adc, TJ = 125C) VDS(on) Forward Transconductance (VDS = 14 Vdc, ID = 3.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time (VDD = 100 Vdc, ID = 7.0 Adc, VGS = 10 Vdc, Rg = 9.1 ) Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 7.0 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) (IS = 7.0 Adc, VGS = 0 Vdc) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (See Figure 14) (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge VSD Vdc ns C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Ld Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad.) Ls nH (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data MTP7N20E TYPICAL ELECTRICAL CHARACTERISTICS TJ = 25C VGS = 10 V 14 9V 12 ID , DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 14 8V 10 8 7V 6 4 6V 2 5V 0 0 2 4 6 8 12 TJ = 100C 10 25C 8 6 4 0 2 3 4 6 8 5 7 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.2 VGS = 10 V 1.0 100C 0.6 TJ = 25C 0.4 -55C 0.2 0 0 2 4 6 8 10 12 14 0.7 TJ = 25C 0.65 0.6 VGS = 10 V 0.55 0.5 15 V 0.45 0.4 0 2 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance versus Drain Current and Temperature 4 6 8 10 ID, DRAIN CURRENT (AMPS) 12 14 Figure 4. On-Resistance versus Drain Current and Gate Voltage 2.5 100 VGS = 0 V VGS = 10 V ID = 3.5 A TJ = 125C 2 I DSS , LEAKAGE (nA) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 10 Figure 2. Transfer Characteristics RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) Figure 1. On-Region Characteristics 0.8 -55C 2 12 10 VDS 10 V 1.5 1 100C 10 25C 0.5 0 - 50 - 25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 Figure 5. On-Resistance Variation with Temperature Motorola TMOS Power MOSFET Transistor Device Data 1 0 50 100 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 200 Figure 6. Drain-To-Source Leakage Current versus Voltage 3 MTP7N20E POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) 900 C, CAPACITANCE (pF) 750 VGS = 0 V TJ = 25C Ciss 600 Crss 450 Ciss 300 Coss 150 VDS = 0 V 0 10 Crss 5 5 0 10 15 20 25 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data QT 10 150 VGS 8 120 Q2 Q1 6 90 60 4 TJ = 25C ID = 7 A 2 Q3 0 0 2 30 VDS 4 6 8 10 14 12 0 1000 TJ = 25C ID = 7 A VDS = 100 V VGS = 10 V 100 t, TIME (ns) 180 12 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) MTP7N20E tr td(off) 10 1 tf td(on) 1 10 RG, GATE RESISTANCE (OHMS) QG, TOTAL GATE CHARGE (nC) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS I S , SOURCE CURRENT (AMPS) 7 VGS = 0 V TJ = 25C 6 5 4 3 2 1 0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reli- Motorola TMOS Power MOSFET Transistor Device Data able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 5 MTP7N20E SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25C 10 10 s 100 s 1 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 dc 100 80 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 100 ID = 7 A 70 60 50 40 30 20 10 0 1000 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 11. Maximum Rated Forward Biased Safe Operating Area 150 Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 0.01 0.00001 0.0001 0.001 0.01 0.1 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10 t, TIME (SECONDS) Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTP7N20E PACKAGE DIMENSIONS -T- B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. SEATING PLANE C F T S 4 A Q 1 2 3 U STYLE 5: PIN 1. 2. 3. 4. H K Z L R V J GATE DRAIN SOURCE DRAIN G D N CASE 221A-06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04 7 MTP7N20E Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 8 *MTP7N20E/D* Motorola TMOS Power MOSFET Transistor Device Data MTP7N20E/D