ZiLOG Totally Logical PRELIMINARY PRODUCT SPECIFICATION 289321/371 16-BiT DIGITAL SIGNAL PROCESSORS FEATURES Device DSP ROM OTP DSP RAM MIPS {[KW] [KW] [Words] 289321 4 512 20 289371 4 512 20 @ 0C to 70C Standard Temperature Range 40C to +85C Extended Temperature Range 4.5 to 5.5 Volt Operating Range DSP Core 16-Bit Fixed Point DSP with 24-Bit ALU and Accumulator Single-Cycle Multiply and ALU Operations @ Six-Level Hardware Stack @ Six Data RAM Pointers and Sixteen Program Memory Pointers RISC Processor with 30 Instruction Types Device 44-Pin 40-Pin DIP 44-PinPLCC PQFP 289321 Xx X X 289371 Xx X X Internal Peripherals @ 13-Bit General-Purpose Timer Dual Channel 8/16/64-Bit CODEC Interface with op- tional Hardware p-Law Compression External Peripheral Interface @ 16-Bit Tri-Stated External Data Bus 3-Bit Latched External Address Bus Wait-State Generator e Three Vectored Interrupts GENERAL DESCRIPTION The Z893x1 products are high-performance Digital Signal Processors (DSPs) with a modified Harvard architecture featuring separate program and dual data memory banks. The design has been optimized for processing power with a minimum of silicon area. The Z893x1 16/24-Bit architecture accommodates ad- vanced signal processing algorithms. The operating perfor- mance and efficient architecture provide deterministic in- struction execution. Compression, filtering, frequency detection, audio, voice detection/synthesis, and other vital algorithms can all be implemented. Six data RAM pointers provide circular buffer capabilities and simultaneous dual operand fetching. Three vectored in- terrupts are complemented by a six-level stack. A 13-bit Timer is available for general-purpose use. A CODEC In- terface allows high-speed transfer rates to accommodate digital audio and voice data. A dedicated Counter/Timer provides the necessary timing signals for the CODEC In- terface. The Z893x1 CODEC Interface is compatible with 8-bit PCM and 16/64-bit CODECs used in digital audio applica- tions, and serial A/D and D/A converters. A Wait-State Gen- erator is provided to accommodate slow external peripher- als. For prototypes, low volume, or special production runs, the Z89371 is a one-time programmable (OTP) device. DS000300-DSP0199Z89321/371 16-Bit Digital Signal Processors ZiLOG GENERAL DESCRIPTION (Continued) Note: All signals with an overline are active Low. For example in RD/WR, RD is active High and WR is active Low. The power connections follow the convention described be- low: Connection Circuit Device Power Vec Vop Ground GND Vss Program Data RAMO Data RAM1 ROM/OTP 256x16 pe) 256x16 4096x16 D0:0--3:0 D0:1-3:1 As As < 9 < ze L EA2-EA0 4 5 4 a External > ED15-EDO 16 a < a Ss mae) Peripheral }-> DS 16 Interface |q. WAIT _ Addr P0:0 Addr PO: 1 | RD/WR Gen P1:0 Gen P1:1 Program UnitO P2-0 Unitt P2-4 Control Unit INTO~2 } 8 16 8 HALT ~ DATA v RESET ~ 16 CLK ~ 4 16 16 MSB 16 Xx Y Stack Multiplier +> =TXD 8/16/64-Bit -** RXD p eee CODEC er SCLK Interface r FSO 24 16 MSB <r FSi mp} 13-Bit Timer UI, U1 map) User I/O -* UO0, U01 24 Cc 24 Figure 1. Z893x1 Functional Block Diagram PRELIMINARY DS000300-DSP0199ZiLOG PIN FUNCTIONS External Bus and External Registers. The following is made to clarify naming conventions used in this specifica- tion. The external bus and external registers are external Z893x1 DSP Core 3 q [External Register| [External Register| Internal Peripheral Internat Peripheral 289321/371 16-Bit Digital Signal Processors to the DSP core, and are used to access internal and external peripherals. 4 cl External Bus ~{\ = [External Register| [External Register| External Peripheral External Peripheral Figure 2. External Bus EA2-EA0. External Address Bus (output). These pins con- trol the user-defined register address output (latched). This bus is driven during both internal and external accesses. One of seven user-defined external registers is selected by the processor for reads or writes. External registers EXT0-EXT3 are always available to the user. External reg- isters EXT4EXT6 are used internally by the processor, or optionally by the user, if the pertinent internal peripherals are disabled. EXT7 is always reserved for use by the pro- cessor. ED15-ED0. External Data Bus (input/output). These pins are the data bus for the user-defined external registers. The pins are normally tri-stated, except when these registers are specified as destination registers in a write instruction to an external peripheral. This bus uses the control signals RD/WR, DS, WAIT and the address pins EA2-EA0. Note: The ED Bus was known as the EXT Bus in earlier ver- sions of this document, and may be referred to as the EXT Bus, pins EXT15EXTO, in other older related doc- uments. DS.Data Strobe (output). This pin provides the data strobe signal for the ED Bus. DS is active for transfers to/from ex- ternal peripherals only. RD/WR. Read/Write Select (output). This pin controls the data direction signal for the ED Bus. Data is available from the processor on ED15ED0 when this signal and DS are both Low. WAIT. WAIT State (input). The wait signal is sampled at the rising edge of the clock with appropriate setup and hold times. A single wait-state can be generated internally by set- ting the appropriate bits in the wait state register. The user must drive this line if multiple wait states are required. This pin has an internal pull-down. HALT. Halt State (input). This pin stops program execution. The processor continuously executes NOPs and the pro- gram counter remains at the same value when this pin is held High. This pin has an internal pull-down. INTO-INT2. Interrupts (input, positive edge triggered). These pins control interrupt requests 0-2. Interrupts are generated on the rising edge of the input signal. The DSP DS000300-DSP0199 PRELIMINARY 3289321/371 16-Bit Digital Signal Processors PIN FUNCTIONS (Continued) fetches the interrupt service routine starting addresses from the following program memory locations: Device INTO INT1 INT2 289321/371 OFFFH OFFEH OFFDH 289391 FFFFH FFFEH FFFDH The interrupt priority is INTO = highest, INT2 = lowest. These pins have internal pull-downs. Note: INTI and INT2 pins are not available on the 40-pin DIP package. CLK Clock (input). This pin is the clock circuit input. RESET. Reset (input, active Low). This pin resets the pro- cessor. It pushes the contents of the Program Counter (PC) onto the stack and then fetches a new PC value from pro- gram memory address OFFCH (or FFFCH for the Z89391) after the RESET signal is released. The Status register is set to all zeros. At power-up, RAM and other registers are un- defined; however, they are left unchanged with subsequent ZiLOG resets. RESET can be asserted asynchronously. If the rising edge of RESET meets prescribed setup conditions relative to the falling edge of the clock, the processor commences execution with a fixed number of clock cycles later. See the Timing Diagrams definitions for details. UIO, UI1. User Input (input). These general-purpose input pins are directly tested by the conditional branch instruc- tions. The pins can also be read as bits in the status register. These are asynchronous input signals that have no special clock synchronization requirements. UOO, UO1. User Output (output). These general-purpose output pins reflect the value of two bits in the status register. These bits may be used to output data by writing to the status register. Note: The value at the output pin is inverted from the value in the register. The pins SCLK, FSO, FS1, RXD and TXD are described in the CODEC Interface section. 4 PRELIMINARY DS000300-DSP0199ZiLOG PIN DESCRIPTION 289321/371 16-Bit Digital Signal Processors ED12 1 ED13 ED14 Vss Co ED15 & ED3 5 ED4 & vss & ED54 7289321/371 ED64 40-Pin DIP ED7 q TXD o ED8 c ED9 c Vss CC ED10 ED11 4 uN UlO & SCLK 20 406) RXD VSS ED2 ED1 m EDO =) Vss I FS1 AH UO1 FI UOO0 I INTO 1 FSO FI CLK DS a] Vop FI EA2 EA1 -) EAO B RESET eS RD/AWR 21 Vpp Figure 3. Z89321/371 40-Pin DIP Pin Assignments Table 1. Z289321/371 40-Pin DIP Pin Identification No. Symbol Function Direction No. Symbol Function Direction ED12 External Data Bus In/Out 21 Vpp Power Supply Input 2 ED13 External Data Bus In/Out 22 RD/WR_ Read/Write select for ED bus Output 3 ED14 External Data Bus In/Out 23 RESET Reset Input 4 Vgg Ground 24 EAO External Address Bus Output 5 ED15 External Data Bus In/Out 25 EA1 External Address Bus Output 6 ED3 External Data Bus In/Out 26 EA2 External Address Bus Output 7 ED4 External Data Bus In/Out 27 Vpp Power Supply Input 8 Vss Ground 28 DS Data Strobe for ED Bus Output 9 ED5 External Data Bus In/Out 29 CLK Clock Input 10 ED6 External Data Bus In/Out 30 FSO Frame Sync-CODEC Ch.0 Output 11. ED? External Data Bus In/Out 31 INTO Interrupt Input 12 TXD Serial Output Data Output 32 UO0 User Output Output 13 ED8 External Data Bus In/Out 33 UO0O1 User Output Output 14 ED9 External Data Bus In/Out 34 ~FS1 Frame Sync-CODEC Ch.1 Output 15 Vsgs Ground 35 Vss Ground 16 ED10 External Data Bus In/Out 36 EDO External Data Bus In/Out 17 ED11 External Data Bus In/Out 3/ D1 External Data Bus In/Out 18 Ul1 User Input Input 38 ED2 External Data Bus In/Out 19 UIO User Input Input 39 Vss Ground 20 SCLK CODEC Serial Clock Output 40 RXD Serial Input Data Input Note: HALT, WAIT, INT1 and INT2 are not available in the 40-pin DIP package. DS000300-DSP0199 PRELIMINARY 5Z289321/371 16-Bit Digital Signal Processors PIN DESCRIPTION (Continued) EAO RESET WAIT RD/WR Vpp SCLK UIO Ul1 INT1 INT2 ED11 5888924 825 OSs2etaassa OOO noOoO ooo / 6 1 40 Vsg 47 39 B EDO 4 A ED1 5 A ED2 5 A Vee O 2Z89321/371 = RxD c 44-Pin PLCC L ED12 & A ED13 & A ED14 & A Vv oO a EDI 7 A 18 28 UUUOUCUuUU ooo 6 88 B&S5ORS ge ouw>oow as mw > Q Figure 4. Z89321/371 44-Pin PLCC Pin Assignments Table 2. Z89321/371 44-Pin PLCC Pin Identification ZiLOG Table 2. Z89321/371 44-Pin PLCC Pin Identification No. Symbol Function Direction No. Symbol Function Direction 1 HALT Stop execution Input 23 ED7 External Data Bus In/Out 2 FSO Frame Sync-CODEC Ch.0 Output 24 TXD Serial Output Data Output 3 INTO Interrupt Input 25 ED8& External Data Bus In/Out 4 U0o0 User Output Output 26 ED9 External Data Bus In/Out 5 UO1 User Output Output 27 Vss Ground 6 FS Frame Sync-CODEC Ch. 1 Output 28 ED10 External Data Bus In/Out 7 Vss Ground 29 ED11 External Data Bus In/Out 8 EDO External Data Bus In/Out 30 = INT2 Interrupt Input 9 ED1 External Data Bus In/Out 31 INT1 Interrupt Input 10 ED2 External Data Bus In/Out 32 ~Ud User Input Input 11. Vgs Ground 33 -UI0 User Input Input 12 RXD Serial Input Data Input 34 SCLK CODEC Serial Clock Output 13 ED12 External Data Bus In/Out 35 Vpp Power Supply Input 14 ED13 External Data Bus In/Out 36 RD/WR _ Read/Write select for ED bus Output 15 ED14 External Data Bus In/Out 37 WAIT Wait state Input 16 Vss Ground 38 RESET Reset Input 17 ED15 External Data Bus In/Out 39 EA0 External Address bus Output 18 ED3 External Data Bus In/Out 40 EAI External Address bus Output 19 ED4 External Data Bus In/Out 41 EA2 External Address bus Output 20 Vsg Ground 42 Vpp Power Supply Input 21 EDS5 External Data Bus In/Out 43 DS Data Strobe for ED Bus Output 22 ED6 External Data Bus In/Out 44 CLK Clock Input PRELIMINARY DS000300-DSP0199ZiLOG Vss EDO ED1 ED2 VSS RXD ED12 ED13 ED14 Vss ED15 INTO FSO BOS 255 289321/371 HALT CLK DS 44-Pin PQFP ED3 ED4 Vss EDS ED6 ED7 TXD ED8 EDS Vss Vop EA2 EA1 UUUUUUUUUUU ED10 289321/371 16-Bit Digital Signal Processors EAO RESET WAIT RD/WR Vpp SCLK UlO ult INT1 INT2 ED11 Figure . Z89321/371 44-Pin PQFP Pin Assignments Table 3. Z89321/371 44-Pin PQFP Pin Identification Table 3. Z89321/371 44-Pin PQFP Pin Identification No. Symbol Function Direction No. Symbol Function Direction 1 ED3 External Data Bus In/Out 23 EA1 External Address bus Output 2 ED4 External Data Bus In/Out 24 EA2 External Address bus Output 3. Vgs Ground 25 Vpp Power Supply Input 4 ED5 External Data Bus In/Out 26 DS Data Strobe for ED Bus Output 5 ED6 External Data Bus In/Out 27 CLK Clock Input 6 ED7 External Data Bus In/Out 28 HALT Stop execution Input 7 TXD Serial Output Data Output 29 FSO Frame Sync-CODEC Ch.0 Output 8 ED8 External Data Bus In/Out 30 INTO Interrupt Input 9 ED9 External Data Bus In/Out 31 UO0 User Output Output 10 Vgs Ground 32 U01 User Output Output 11. ED10 External Data Bus In/Out 33 FS1 Frame Sync-CODEC Ch. 1 Output 12 ED11 External Data Bus In/Out 34 Vss Ground 13. INT2 Interrupt Input 35 EDO External Data Bus In/Out | 14. INT1 Interrupt Input 36 ED1 External Data Bus In/Out 15 Ul1 User Input Input 37 ED2 External Data Bus In/Out 16 UIO User Input Input 38 Vgs Ground 17. SCLK CODEC Serial Clock Output 39 RXD Serial Input Data Input 18 Vpp Power Supply Input 40 ED12 External Data Bus In/Out 19 RD/WR_ Read/Write select for ED bus Output 41. ED13 External Data Bus In/Out 20 WAIT Wait state Input 42 ED14 External Data Bus In/Out 21 RESET Reset Input 43 Vss Ground 22 EA0O External Address bus Output 44 ED15 External Data Bus In/Out DS000300-DSP0199 PRELIMINARY 7289321/371 16-Bit Digital Signal Processors ZiLOG ABSOLUTE MAXIMUM RATINGS Min Max Units Stresses greater than those listed under the Absolute Max- Symbol Description . Rei d ne devi imum Ratings may cause permanent damage to the device. Vop Supply voltage V 03 70 This rating is a stress rating only. Operation of the device with respect to Vss at any condition above those indicated in the operational Tstg Storage $5 150 C sections of these specifications is not implied. Exposure to Temperature absolute maximum rating conditions for extended periods Ta Ambient Operating may affect device reliability. Temperature S device 0 70 C E device -40 85 C STANDARD TEST CONDITIONS The characteristics listed below apply for standard test con- ditions as noted. All voltages are referenced to Ground. Positive current I(,) flows into the referenced pin. wy 21 Ka ly Negative current I(_) flows out of the referenced pin. From Output . k4 Under Test 30 pF Ss 9.1K Figure 6. Test Load Diagram DC ELECTRICAL CHARACTERISTICS Table 4. Vpp = 5V 10%, TA = 0C to +70C for S Temperature Range (Ta = -40C to +85C for E temperature range, unless otherwise noted) Sym Parameter Condition Min Typ Max Units lpp Supply Current Vpp = 5.5V 70.0 TBD mA Ipc DC Power Vpp = 5.0V and CLK stopped High 5.0 TBD mA Consumption Vin Input High Level 2.7 Vv ViL Input Low Level 0.8 Vv I Input Leakage 10 yA Von Output High Voltage = Io4=-100 LA Vpp-0.2 V lon = -160 pA 2.4 Vv Vo. _ Output Low Voltage lo. = 1.6 mA 0.4 Vv lo, = 2.0 mA 0.5 Vv le Output Floating 10 yA Leakage Current 8 PRELIMINARY DS000300-DSP0199ZiLOG 289321/371 16-Bit Digital Signal Processors AC ELECTRICAL CHARACTERISTICS Table 5. Vpp = 5V 210%, Ta = 0C to +70C for S Temperature Range (Ta = 40C to +85C for E temperature range, unless otherwise noted) Symbol Parameter Min [ns] Max [ns] Clock TCY CLK Cycle Time 50 31250 CPWH CLK Pulse Width High 21 CPWL CLK Pulse Width Low 21 Tr CLK Rise Time 2 Tf CLK Fall Time 2 External Peripheral Bus DSVALID DS Valid Time from CLK Fall 0 15 DSHOLD DS Hold Time from CLK Rise 0 15 EASET EA Setup Time to DS Fall 10 EAHOLD EA Hold Time from DS Rise 4 RWSET Read/Write Setup Time to DS Fall 10 RWHOLD Read/Write Hold Time from DS Rise 0 RDSET Data Read Setup Time to DS Rise 15 RDHOLD Data Read Hold Time from DS Rise 0 WRVALID Data Write Valid Time from DS Fall 5 WRHOLD Data Write Hold Time from DS Rise 2 Reset RSET Reset Setup Time to CLK Fall for synchronous 15 operation RWIDTH Reset Low Pulse Width 2 TCY RRISE Reset Rise Time 50 Interrupt INTSET Interrupt Setup Time to CLK Fall 7 INTWIDTH Interrupt Low Pulse Width 1 TCY Halt HSET Halt Setup Time to CLK Rise 4 HHOLD Halt Hold Time from CLK Rise 12 Wait State WSET Wait Setup Time to CLK Rise 20 WHOLD Wait Hold Time from CLK Rise 10 CODEC Interface SSET SCLK Setup Time from CLK Rise 15 FSSET FSYNC Setup Time from SCLK Rise 7 TXSET TXD Setup Time from SCLK Rise 7 RXSET RXD Setup Time to SCLK Fall 7 RXHOLD RXD Hold Time from SCLK Fall 0 DS000300-DSP0199 PRELIMINARY289321/371 16-Bit Digital Signal Processors ZiLOG TIMING DIAGRAMS } TCY >| Tr>| -e cPWH>|_s | x TF l< psHOLD cpwi >| DSVALID < Ds \ / EASET >| < > }- EAHOLD EA(2:0) xX Valid Address Out xX RDAWR / \ _>| RDHOLD RDSET | < ED(15:0) Tri-Stated x Data x Tri-Stated Figure 7. Read Timing NN A NN Sf QV Sf WAIT Sf N EA(2:0) 4 Valid Address Out x RD/WR ED(15:0) Tri-Stated xX Data x Tri-Stated Figure 8. External Data (ED) Bus Read Timing Using WAIT Pin 10 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors OSHOLD DSVALID < ~ \ |f EASET < > }* EAHOLD x Valid Address Out x | RWSET < _> WRHOLD WRVALID *] ED(15:0) Tri-Stated x Data x Tri-Stated Figure 9. Write Timing EA(2:0) RD/WR |< Tov >| CLK | } sseT Souk Ne AN Nae Ana Ae - j< FSSET FSSET FSO0,FS1 WA \ 1 >}| = RXHOLD [< RXSET | < RXD 4 0 1 0 1 Figure 10. CODEC Interface Timing DS000300-DSP0199 PRELIMINARY 11Z89321/371 16-Bit Digital Signal Processors TIMING DIAGRAMS (Continued) ZiLOG j Tcy >| es SVS / YI VS \/\ INTSET >| a INT 0,1,2 (NYS | INTWidth \~ Program Fetch N-1 Fetch N Fetch N+1 Fetch Int_Addr Fetch | Fetch 141 Address 7 Execute x K ecu N-1 x Execute N Kea Int Routine Keene Int Routine xX Figure 11. Interrupt Timing }x TCcY >| | HHOLD HSET>| e HALT / \ Figure 12. HALT Timing 12 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors }< TCY >| aK LY VFN YVvVYNVv\YV\Y4\ RSET > RsEeT>{ e RESET \ / }< RWIDTH >| RRISE INTERNAL \ RESET / EXECUTE x Cycle 0 x Cycle 1 x Cycle 2 x Cycle 3 x Cycle 4 x Cycle 5 x Eccteon OK RD/WR / \ cs Sf NK UOD, UO1 / \ EA2-EAQ / ED15-ED0 4 Tri-Stated x PA15-PAQ x Tri-Stated D.< Access Reset Vector x RAM/ REGISTERS xX Unchanged xX STATUS Re /. REGISTER Figure 13. Synchronous Reset Timing DS000300-DSP0199 PRELIMINARY 13289321/371 16-Bit Digital Signal Processors FUNCTIONAL DESCRIPTION Instruction Timing. Most instructions are executed in one machine cycle. A multiplication or multiply/accumulate in- struction requires a single cycle. Long immediate instruc- tions (and Jump or Call instructions) are executed in two machine cycles. Specific instruction cycle times are de- scribed in the Instruction Description section. Multiply/Accumulate. The multiplier can perform a 16-bit x 16-bit multiply (or multiply/accumulate) in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result; however, only the 24 most significant bits are saved for the next instruction or accumulation. For operations on very small numbers, where the least-significant bits are important, the data should first be scaled to avoid truncation errors. DDATA XDATA X Register (16) Y Register (16) MULTIPLIER P Register (24) Shift Unit 4 2 *Options: No Shift Multiplier Unit 8 Bits Right Output Figure 14. Multiplier Block Diagram All inputs to the multiplier should be fractional twos-com- plement, 16-bit binary numbers, putting them in the range [-1 to 0.9999695]. The result is in 24 bits, so the range is [-1 to 0.9999999]. If 8000H is loaded into both the X and Y registers, the mul- tiplication will produce an incorrect result. A positive one (+1) cannot be represented in fractional notation. The mul- tiplier will actually yield the result 8000H x 8000H = 8000H (-I| x -| =-1). The user should avoid this case to prevent erroneous results. A shifter between the P Register and the Multiplier Unit Output can shift the data by three bits right or no shift. ZiLOG Data Bus Bank Switch. There is a switch that connects the X Bus to the DDATA Bus that allows both the X and Y reg- isters to be loaded with the same operand for a one cycle squaring operation. The switch is also used to read the X register. ALU. The ALU has two input ports. One is connected to the output of the 24-bit Accumulator. The other input selects either the Multiplier Unit Output or the 16-bit DDATA bus (left-justified with zeros in the eight LSBs). The ALU per- forms arithmetic, logic, and shift operations. Multiplier Unit Output Accumulator (24) Figure 15. ALU Block Diagram Hardware Stack. A six-level hardware stack is connected to the DDATA bus to hold subroutine return addresses or data. The Call instruction pushes PC+2 onto the stack, and the RET instruction pops the contents of the stack to the PC. User Inputs and Outputs. The 7893x1 has two user in- puts, UIO and UI1, and two user outputs, UOO and UO1. The input pins are connected directly to status register bits S10 and S11. These bits can be read, or they can be used as a condition code in any conditional instruction. The output pins are connected directly to status register bits SS and S6, and can be written to. Note: The value at the output pin is inverted from the value in the register. 14 PRELIMINARY DS000300-DSP0199ZiLOG Interrupts. The 7893x1 has three positive edge-triggered interrupt inputs. An interrupt is serviced at the end of an in- struction execution. Two machine cycles are required to en- ter an interrupt instruction sequence. The PC is pushed onto the stack. At the end of the interrupt service routine, a RET instruction is used to pop the stack into the PC. The priority of the interrupts is INTO = highest, INT2 = lowest. When those peripherals are enabled, INT1 is dedicated to the CO- DEC Interface and INT2 is dedicated to the 13-bit timer. The Set-Interrupt-Enable-Flag (SIEF) instruction enables the interrupts. Interrupts are automatically disabled when entering an interrupt service routine. Before exiting an in- terrupt service routine, the SIEF instruction can be used to re-enable interrupts. Registers. The Z893x1 has 19 internal registers and up to seven user-defined 16-bit external registers (EXTOEXT6). The external register address space for EXT4-EXT6 is used by the Z893x]1 internal peripherals. Disabling a peripheral allows access to these addresses for general-purpose use. External Register Usage. The external registers EXT0-EXT6 are accessed using the External Address Bus EA2-EA0, the External Data Bus (ED Bus) ED15ED0, and control signals DS, WAIT, and RD/WR. These registers provide a convenient data transfer capability with external peripherals. Data transfers can be performed in a single-cy- cle. An internal Wait-State generator is provided to accom- modate slower external peripherals. A single wait state can be implemented through control register EXT72. For ad- 289321/371 16-Bit Digital Signal Processors ditional wait states, the WAIT pin can be used. The WAIT pin is monitored only during execution of a read or write instruction to external peripherals on the ED bus. Wait-State Generator. An internal Wait-State generator is provided to accommodate slow external peripherals. A sin- gle Wait-State can be implemented through a control reg- ister. For additional states, a dedicated pin (WAIT) can be held Low. The WAIT pin is monitored only during execu- tion ofa read or write instruction to external peripherals (ED bus). CODEC Interface. The CODEC Interface provides the necessary control signals for transmission of CODEC in- formation to/from the processor. The CODEC Interface ac- commodates external 8-bit PCM or 16/64-bit linear CO- DECs. The CODEC Interface can also be used with external A/D and D/A converters. The interface can also be used as a high-speed serial port. p-Law Compression. The CODEC Interface provides op- tional hardware p-Law compression from 13-bit format to 8-bit format. Decompression is performed in software using a 128-word lookup table. Timers. Two programmable timers, a general purpose 13- bit Timer, and a dedicated 12-bit Counter/Timer are pro- vided to support the CODEC Interface. The 13-bit Timer can be operated in either continuous or one-shot mode. If the CODEC Interface is not enabled, its 12-bit Counter/Timer is also available for general-purpose use. DS000300-DSP0199 PRELIMINARY 15289321/371 16-Bit Digital Signa! Processors ZiLOG MEMORY MAP Program Memory. Programs of up to 4K words can be masked into internal ROM (Z89321) or programmed into an OTP (Z89371). Four locations are dedicated to the vector addresses for the three interrupts (OFFDHOFFFH) and the starting address following a RESET (OFFCH). Interna] ROM is mapped from 0000H to OFFFH, and the highest lo- cation for program instructions is OFFBH. Internal Data RAM. All Z893x1 family members have in- ternal 512 x 16-bit data RAM organized as two banks of 256 x 16-bit words each (RAMO and RAM 1). The three address- ing modes available to access the data RAM are direct ad- dressing, short form direct, and register indirect. The contents of both data RAM banks can be read simul- taneously and loaded into the X and Y inputs of the multi- plier during a multiply instruction. The addresses for each data RAM bank are: 0-255 {(OQOOOH-OOFFH) for RAMO 256-511 (O100H-O1FFH) for RAM1 Data RAM Pointers. In register indirect, each data RAM bank is addressed by one of three data RAM address point- ers: Pn:b, where n = pointer number = O, 1, or 2 b = bank = Oor1, Data Memory FFFF Not Used 512 Words O1FF DRAM1 0100 0088 DRAMO 0000 thus, PO:0, P1:0, P2:0 for RAMO PO:1, P1:1, P2:1 for RAM1 In auto-increment, loop-increment, and loop-decrement in- direct addressing, the pointer is automatically modified. The data RAM pointers, which may be read or written di- rectly, are 8-bit registers connected to the lower byte of the internal 16-bit DDATA Bus. Program Memory Pointers. The first 16 locations of each data RAM bank can be used as pointers to locations in Pro- gram Memory. These locations can be an efficient way to address coefficients. The programmer selects a pointer lo- cation using two bits in the status register and two bits in the operand. At any one time, there are eight usable pointers, four per bank, and the four pointers are in consecutive lo- cations. Dn:b, where n = pointer number = O, 1, 2, or 3 b = bank = Oor 1, thus, DO:0, D1:0, D2:0, D3:0 for RAMO DO:1, D1:1, D2:1, D3:1 for RAM1 For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in data RAM Bank 0. Program Memory FFFF Not Used 4KW ISRO-ISR2 Vectors | OFFF-D RESET Vector 4FFC 1FFB 0000 Figure 16. Memory Map 16 PRELIMINARY DS000300-DSP0199ZiLOG 289321/371 16-Bit Digital Signal Processors REGISTERS The internal registers are defined in Table 6 below: Table 6. Register Definitions PC is the Program Counter. Any instruction which may modify this register requires two clock cycles. SR is the status register. It contains the ALU status and pro- Register Definition cessor control bits (Table 7). X Multiplier X Input, 16-bits . . . Y Multiplier Y Input, 16-bits Table 7. Status Register Bit Functions P Multiplier Output, 24-bits SR Bit Function Read/Write A Accumulator, 24-bits $15 (N) ALU Negative RO Pn:b Six Data RAM Pointers, 8-bits each $14 (OV) ALU Overflow RO PC Program Counter, 16-bits $13 (Z) ALU Zero RO SR Status Register, 16-bits $12 (L) Carry RO EXT4 13-bit Timer Configuration Register S11 (UI1) User Input 1 RO EXT5-1 CODEC Interface Channel 0 Data $10 (UIO) User Input 0 RO EXT5-2 CODEC Interface Channel 0 Data S9 (SH3) MPY ouput Arunmetically RW EXT61 CODEC Interface Channel 1 Data ones ight by Three EXT6-2 CODEC Interface Channel 1 Data S8 (OP) Overflow Protection RIW EXT/71 CODEC Interface Configuration Register S7 (IE) Interrupt Enable RIW EXT7-2 Wait-State Generator and CODEC S6 (UO1) User Output 1 RIW Interface Configuration Register $5 (UO0) User Output 0 RIW $4-S3 Short Form Direct bits R/V S2-SO (RPL} RAM Pointer Loop Size R/W Note: The loading and reading of the three pairs of CODEC In- terface registers (EXT51,2 EXT61,2 and EXT7-1,2) are described in the CODEC Interface section. X and Y are two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. P holds the result of multiplications and is read-only. A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data is transferred into this reg- ister, it is placed into the 16 MSBs, and the least significant eight bits are set to zero. Only the upper 16 bits are trans- ferred to the destination register when the Accumulator is selected as a source register in transfer instructions. Pn:bare the pointer registers for accessing data RAM where n= 0, 1, or 2, and b = 0 or 1. These registers can perform Note: RO =read only, RW = read/write. The status register can always be read in its entirety. S15-S12 are set/reset by the ALU after an operation. S11-S10 are set/reset by the user inputs. If S9 is set, and a multiply/shift option is used, the shifter shifts the result three bits right. This feature allows the data to be scaled and prevents overflows. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. S7 enables interrupts. either a direct read or write function, and each can pointto _._s@ are control bits. locations in data RAM. DS000300-DSP0199 PRELIMINARY 17Z89321/371 16-Bit Digital Signal Processors REGISTERS (Continued) Table 8. RPL Description $2 $1 So Loop Size 0 0 0 256 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 The following are not actually registers; however, they have aread/write function that acts primarily the same way as the hardware registers do on the chip: Register Register Definition BUS DDATA Bus Dn:b Program Memory Pointers EXTn External Registers BUS is a read-only register which, when accessed, returns the contents of the D-Bus. BUS is used for emulation only. Dn:b refers to locations in RAM that can be used as a pointer to locations in program memory. These locations make the Z89321/371 capable for coefficient addressing. The pro- grammer decides which location to choose from based on two bits in the status register and two bits in the operand; only the lower 16 possible locations in RAM can be spec- ified. At any one time, there are eight usable pointers, four per bank, and the four pointer are in consecutive locations in RAM. For example, if S3/S4=1 in the status register, then D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in RAM Bank 0. N OV Z c ZiLOG Note: When the data pointers are being written to, a number is actually being loaded to Data RAM. In effect, these data pointers can be used as a limited method for writing to RAM. EXTO-EXT3 are used to map external peripherals into the address space of the processor. ult Ul0 SH3 OP Note: The actual register RAM does not exist on the chip, but would exist as part of the external device (such as an A/D result latch). The External Address Bus, EA2EA0, the External Data Bus, ED15EDO and the control signals DS, WAIT and RD/WR, are used to access external pe- ripherals. EXT4 is used by the 13-bit Timer. If the Timer is disabled, then this address can be used to access an external peripheral on the External Data Bus. EXTS5 and EXT6 are used by the CODEC Interface channels 0 and 1 respectively. If a CODEC channel is disabled, the corresponding address can be used to access an external pe- ripheral. EXT7 is used to program wait states for EXTO-EXT6, and is not available for accessing an external peripheral. If both the Timer and CODEC Interface are disabled, there are 7 addresses available to access external peripherals. If both the Timer and CODEC Interface are enabled, there are 4 addresses available to access external peripherals. IE U0O1 UOO RPL }s15]s14[ S13] siz] s11] sto] so | sa { s7 | se} ss | sa | ss | s2| si] so| Negative on Overflow Zero Carry User Input 0-1 (Read Only) MPY output arithmetically shifted right by three bits Overflow protection | Ram Loop Pointer Size 000 256 001 2 0710 4 o11 8 100 16 101 32 110 64 111 128 "Short Form Direct" bits Reserved Global interrupt Enable Figure 17. Status Register 18 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors PERIPHERAL OPERATION Overview At power on, and after a RESET, the CODEC Interface is The peripherals for the Z893x1 family consist of a general purpose 13-bit Timer and a dual channel CODEC Interface. The CODEC Interface contains its own 12-bit Counter/Timer. When the CODEC Interface is disabled, the Counter/Timer is available for general purpose use. The output of the 12-bit Counter/Timer can also be linked with the input of the 13-bit Timer for extended timing. See the EXT4 and EXT7 register definitions for more informa- tion and examples. Enabling and Disabling Peripherals At power on, and after a RESET, the 13-bit general purpose Timer is enabled, but count operation is disabled. See the EXT4 register definition for more information concerning the operation of the Timer. While the Timer is enabled, it disabled. See EXT5, EXT6, and EXT7 register definitions for more information concerning the operation of the CO- DEC Interface. While the CODEC Interface is enabled, it uses INT1 to signal the end of a frame. When a CODEC Interface channel is disabled, its corresponding EXT ad- dress is available. When both channels are disabled, EXT5, EXT6, and INT1I are available for use by an external pe- ripheral. EXT7 is always reserved for internal use. If an internal peripheral is enabled, the External Bus data and data strobe signals for the corresponding register ad- dress are not available on the External Bus (internal periph- eral data transfers are processed internally). Interrupts The Z893x1 interrupts are: uses INT2 to signal a time out. When the Timer is disabled, INTO General-Purpose Use EXT4 and INT2 are available for use by an external periph- 'NT1 = CODEC Interface (when enabled), or else User eral. INT2 Timer (when enabled), or else User DS000300-DSP0199 PRELIMINARY 19Z89321/371 16-Bit Digital Signal Processors 13-BIT GENERAL PURPOSE TIMER The General-Purpose Timer can be enabled or disabled. At power-on or RESET, the counter is enabled. When the Tim- er is disabled, it can only be re-enabled by another RESET. The Timer operates in a continuous or one-shot mode, and can be stopped. The Timer utilizes a 13-bit down-counter. Continuous Mode With a load instruction, the user sets the Timer to run the mode, selects the clock source, and loads a non-zero count value: 1. When the down-counter reaches zero, an interrupt is generated on INT2, 2. The non-zero count value is automatically reloaded into the down-counter, 3. The process continues at step #1. One-Shot ModeWith a load instruction, the user sets the Timer to run the mode, selects the clock source, and loads a non-zero count value: 4. When the down-counter reaches zero, an interrupt is generated on INT2, 5. The user interrupt service routine must load a zero value into the Count Operation bit (D14 of EXT4), 6. The process stops. Timing IntervalsIf the Timer clock source is CLK/2: Time Interval = (count value) x (2/CLK) Timer Frequency = (CLK/2) / (count value) where CLK denotes the system clock frequency. ZiLOG Extended Timing IntervalsThe Timer interval can be ex- tended beyond 13-bits by using the Timer in conjunction with the CODEC Interface Counter/Timer. The count is thus extended to a maximum of 25 bits: 12-bits from the CODEC counter/timer 13-bits from the Timer If the Timer clock source is the CODEC counter output: Time Interval =(Timer count value) x (CODEC counter/timer period) Timer Freq. = (CODEC counter/timer freq.) + (Timer count value) Timer Interrupt BehaviorThe following clarifies the be- havior of the Timer interrupt: @ while the Timer is enabled, it utilizes theINT2 service routine address. @ The Timer is enabled after RESET; however, the Tim- er is in stop mode. @ = The INT2 pin has an internal pull-down. When the Timer is in run mode, it generates an inter- rupt each time it counts down to zero. @ When the Timer is disabled, INT2 can be controlled by an external peripheral. Note: Ifthe Timer is to be disabled, and an external peripheral is driving INT2, it should hold INT2 High while the Tim- er is being disabled. 20 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors EXT4 D15}014 fD13 |D12,D11]D10] DS | DB | D7 | D6 | DS | D4 | D3 | D2 | D1 | DO Count Value (down-counter) Clock Source 0 = CLK/2 (default) 1 = CODEC Counter Output Count Operation 0 = Stop (default) 1 = Run Counter 0 = Disable Default Setting After Reset 1 = Enable (default) Figure 18. Timer Register EXT4 DS000300-DSP0199 PRELIMINARY 21Z89321/371 16-Bit Digital Signal Processors CODEC INTERFACE Overview The CODEC Interface not only supports a variety of exter- nal 8-bit, 16-bit linear, 64-bit sigma-delta stereo CODECs, and external A/D and D/A Converters, but the interface can also be used as a general purpose high-speed serial port. The CODEC Interface includes optional hardware p-Law com- pression. The CODEC Interface is designed to support both Half-Duplex and Full-Duplex operation. The CODEC In- ZiLOG terface is designed to operate in master mode only. The CO- DEC Interface generates a serial clock and two Frame Sync signals, which allows for two channels of data. Hardware The CODEC Interface hardware uses six 16-bit registers, u-Law compression logic, and general-purpose control log- ic to control transfers to/from the appropriate registers. L Data Bus f A A A y 16 p-Law 16 16 Compression i Y Yv EXT5-1 ~< EXT6-1 ~< \ eo EXT7-1 A A A 16 16 16 EXT5-2 ~ L EXT6-2 re EXT7-2 A yy A YYVY Y Clock & TXD RXD Control Logic Figure 19. CODEC Interface Block Diagram CODEC Interface Control Signals SCLK. Serial Clock (output). This pin provides the clock signal for operating the external CODEC. A 4-bit prescaler is used to divide down the system clock (CLK) to produce the desired output frequency of SCLK. An internal divide- by-two is performed on CLK before passing it to the SCLK prescaler: SCLK = (CLK/2) + PS where PS = 2s complement of the 4-bit Pre-Scaler value (PS is an up-counter). TXD. Serial Output Data (output). This pin provides 8, 16, and 64-bit data transfers. Each bit is clocked out of the pro- cessor by the rising edge of SCLK, with the MSB transmit- ted first. RXD. Serial Input Data (input). This pin provides 8, 16, and 64-bit data transfers. Each bit is clocked into the processor by the falling edge of SCLK, with the MSB received first. 22 PRELIMINARY DS000300-DSP0199289321/371 16-Bit Digital Signal Processors FSO, FS1. Frame Sync 0 and Frame Sync | (output). These pins are used to mark data transfer/receive frames. The ris- ing and falling edge of the Frame Sync signals indicate the beginning and the end of each serial data transmission. CODEC Interface Interrupt Behavior When the transmission of serial data is completed, the CO- DEC Interface generates an internal interrupt which vectors to the INT1 service routine address. This interrupt is coin- cident with the falling edge of FS1. The following clarifies the behavior of the CODEC Interface interrupt: @ While the CODEC Interface is enabled, it utilizes the INT1 service routine address. @ The CODEC Interface will be disabled after RESET. @ = The INT! pin has an internal pull-down. @ If INTI1 is tied High, the CODEC Interface generates an interrupt at the end of each frame transfer. IfINT! is not connected, or tied Low, the CODEC In- terface not only generates an interrupt when first en- abled, but generates an interrupt at the end of each frame transfer. @ When the CODEC Interface is disabled, INT] can be controlled by an external peripheral. Note: In single channel! applications, use Channel | because INTI coincides with FS1, not FSO. Registers The CODEC Interface registers (EXT5, EXT6 and EXT7) each act as a 2-deep FIFO. See the CODEC Interface Block Diagram for more information, Figure 19. Two operations may be required for some data transfers. EXT5 and EXT6. The CODEC Interface constantly trans- fers and receives data during normal operation. The reading of receive data, and the writing of transmit data, are inter- leaved. An example of Channel | operation in 8 or 16-bit mode, where one can wait for the input data, is as follows: LD<dest>, EXT6 : Read previous input data from EXT6-1 LD EXT6, <xmit data> ; Push current data from EXT6-2 to EXT6-1 : Load EXT6-2 with data to be transmitted ZiLOG To obtain the input data as soon as it arrives, and extra in- struction is required: LD EXT6,<anything> ; Push current input data from EXT6-2 to EXT6~-1 ; Read current input data from EXT6-1 LD EXT6, <xmit data> ; Load EXT62 with data to be transmitted LD<test>, EXT6 For 64-bit mode, one can use the following code sequence: LD <Ch. 0 MSW input dest>, ; Get MSW of Ch. 0 input EXT5 LD <Ch. 1 MSW input dest>, ; Get MSW of Ch 1 input EXT6 LD EXT5, ; Move LSB of Ch. 0 input <Ch. 0 MSW output data> and Load MSW of output LD EXT6, ; Move LSB of Ch. 1 input <Ch. 1 MSW output data> LD<Ch. 0 LSW input test>, and Load MSW of output ; Get LSW of Ch. 0 input EXT5 LD<Ch. 1 LSW input test>, ; Get LSW of Ch. 1 input EXT6 LD EXT5, ; Load LSW of Ch. 0 output <Ch. 0 LSW output data> LD EXT6, ; Load LSW of Ch. 1 output <Ch. 1 LSW output data> Note: EXT# denotes EXTS or EXT6. In the 8 and 16-bit modes, EXT52 and EXT62 are the shift registers for Channel 0 and Channel 1, respectively. In 8- bit mode, the 8-bits reside in the least significant byte for both transmit and receive. In 64-bit mode, the output/input order is EXT 51 first, followed by EXT5~2, EXT61, and finally by EXT62. In all modes, the MSB is shifted out/in first. Channel 0 uses FSO, EXT51, and EXT52. Channel | uses FS1, EXT61, and EXT62. EXT7. This register contains the configuration information for the CODEC Interface and the Wait-State Generator. In normal operation, the user writes configuration data for EXT7-1 followed by configuration data for EXT72. Write EXT7 LD EXT7, <config data1> ; Move data to 7-2 LD EXT7, <config data2> ; Move data to 7-1 23 PRELIMINARY DS000300-DSP0199Z89321/371 16-Bit Digital Signal Processors ZiLOG CODEC INTERFACE (Continued) FSO | | 1 rt 64 cycles >| | 1 | I I 3 1 J p< _ 16 cycles > FS1 Figure 20. 64-Bit CODEC Frame Synchronization FSO | 16 cycles >} \ ' FS1 < 16 cycles > 16 cycles > Figure 21. 16-Bit CODEC Frame Synchronization FSO | 1 ' r, $Scycles < I ! __- 24 cycles ---_---__-______> FS1 i 1 m, 8cycles (< Figure 22. 8-Bit CODEC Frame Synchronization 24 PRELIMINARY DS000300-DSP0199289321/371 16-Bit Digital Signal Processors ZiLOG CODEC INTERFACE (Continued) EXT7-1 D15 }D14 7013 [D12 |D11 | D107 O09 | DS | D7 | DG | DS | 04 | 03 | D2] D1 | DO Lo SCLK Prescaler Value (up-counter) SCLK/FSYNC Ratio Prescaler Value (up-counter) CODEC Mode 00 = 8-bit with Hardware p-Law 01 = 8-bit without Hardware p-Law 10 = 16-bit Linear 11 = 64-bit Stereo FSYNC 0 = Disable (default) 1 = Enable CODEC Channel 0 Example:EXT7-1 = #%x00DCLK = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz 0 = Disable (default) EXT7-1 = #%xOQ0DCLK = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz 1 = Enable EXT7-1 = #%xF FXNo interrupt EXT7-1 = #%x000Max interrupt period (667 js for CLK = 12.288 MHz) Figure 23. CODEC Interface Control Register EXT7-2 D15]D14 | 013 [D12]D11] D010} D9 | D& | D7 | D6 | D5 | D4 | D3 | D2 | D1 | DO tT L Wait State EXTO ~{ Wait State EXT1 00 read (nws), write (nws) Wait State EXT2 01 read (nws), write (ws) 10 read (ws), write (nws) Wait State EXT3 11 read (ws), write (ws) Wait State EXT4 nws = no wait states ws = one wait state Wait State EXT5 Wait State EXT6 __1 SCLK 0 = Disable (default) 1 = CLK/2 CODEC Channel 1 0 = Disable (default) 1 = Enable Figure 24. Wait-State Generator and CODEC Interface Control Register 25 PRELIMINARY DS000300-DSP0199289321/371 16-Bit Digital Signal Processors ZiLOG INSTRUCTION SET The addressing modes are: <pregs>, <hwregs> These modes are used for loads to and from registers within the chip, such as loading to the accu- mulator, or loading from a pointer register. The names of the registers are specified in the operand field (destination first, then source). <dregs> This mode is used for access to the lower 16 ad- dresses in each bank of RAM. The 4-bit address comes from 2 bits of the status register and 2 bits of the operand field of the data pointer. Data registers can be used to access data in RAM, but typically these registers are used as pointers to access data from the program memory. <accind> Similar to the previous mode, the address for the program memory read is stored in the Accumulator. Hence, @A in the second operand field loads the number in mem- ory specified by the address in A. <direct> The direct mode allows read or write to data RAM from the Accumulator by specifying the absolute address of the RAM in the operand of the instruction. A number be- tween 0 and 255 indicates a location in RAM bank 0, and a number between 256 and 511 indicates a location in RAM bank 1. <limm> This address mode indicates a long immediate op- erand. A 16-bit word can be loaded directly from the oper- and into the specified register or memory location. <simm> This address mode indicates a short immediate op- erand. It is used to load 8-bit data into the specified RAM pointer. <regind> This mode is used for indirect access to the data RAM. The address of the RAM location is stored in the pointer. The @ symbol indicates indirect and precedes the pointer. For example, @P1:1 refers to the location in RAM bank | specified by the value in the pointer. <memind> This mode is used for indirect access to the pro- gram memory. The address of the memory is located in a RAM location, which is specified by the value in a pointer. Therefore, @@P1:1 instructs the processor to read from a location in memory. This instruction specifies a value in RAM, and the location of the RAM is, in turn, specified by the value in the pointer. Note: The data pointer can also be used for a memory access in this manner, but only one @ precedes the pointer. In both cases, each time the addressing mode is used, the memory address stored in RAM is incremented by one to allow easy transfer of sequential data from program memory. Table 9. Instruction Set Addressing Modes Symbolic Name Syntax Description <pregs> Pn:b Pointer Registers <dregs> (points to RAM) Dn:b Data Registers <hwregs> X, Y, PC, SR, P, EDn, A, BUS Hardware Registers <accind> (points to Program Memory) @A Accumulator Memory Indirect <direct> <expression> Direct Address Expression <limm> #<const exp> Long (16-bit) Immediate Vaiue <simm> #<const exp> Short (8-bit) Immediate Value <regind> (points to RAM) @Pn:b Pointer Register Indirect @Pn:b+ Pointer Register Indirect with Increment @Pn:b-LOOP Pointer Register Indirect with Loop Decrement @Pn:b+LOOP Pointer register Indirect with Loop Increment <memind> (points to Program @@Pn:b Pointer Register Memory Indirect Memory) @Dn:b Data Register Memory Indirect @@Pn:b-LOOP Pointer Register Memory Indirect with Loop Decrement @@Pn:b+LOOP Pointer Register Memory Indirect with Loop Increment @@Pn:b+ Pointer Register Memory Indirect with Increment 26 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors CONDITION CODES The following Instruction Description defines thecondition of its addressing modes, the instruction will only execute codes supported by the DSP assembler. Ifthe instructionde- _if the condition is true. scription refers to the < cc > (condition code) symbol in one Code Description Cc Carry EQ Equal (same as Z) F False IE Interrupts Enabled MI Minus NC No Carry NE Not Equal (same as NZ) NIE No Interrupts Enabled NOV No Overflow NUO Not User Zero NU1 Not User One NZ Not zero OV Overflow PL Plus (Positive) UO User Zero U4 User One UGE Unsigned Greater Than or Equal (Same as NC) ULT Unsigned Less Than (Same as C) Z Zero DS000300-DSP0199 PRELIMINARY 27289321/371 16-Bit Digital Signal Processors ZiLOG INSTRUCTION DESCRIPTIONS Inst. Description Synopsis Operands Words Cycles Examples ABS Absolute Value ABS[<cc>,]<src> <cc>,A 4 1 ABS NC, A A 1 1 ABSA ADD Addition ADD<dest>,<src> A,<pregs> 1 1 ADD A,P0:0 A,<dregs> 1 1 ADD A,D0:0 A,<limm> 2 2 ADD A,#%1234 A,<memind> 1 3 ADD A,@@P0:0 A,<direct> 1 1 ADD A,%F2 A,<regind> 1 1 ADD A,@P1:1 A,<hwregs> 1 1 ADD A,X A,<simm> 1 1 ADD A, #%12 AND Bitwise AND AND<dest>,<src> A,<pregs> 1 4 AND A,P2:0 A,<dregs> 1 1 AND A,D0:1 A,<limm> 2 2 AND A,#%1234 A,<memind> 1 3 AND A,@@P1:0 A,<direct> 1 1 AND A,%2C A,<regind> 1 1 AND A,@P1:2+LOOP A,<hwregs> 1 1 AND A,EXT3 A,<simm> 1 1 AND A, #%12 CALL Subroutine call CALL [<cc>,]<address> <cc>,<direct> 2 2 CALL Z,sub2 <direct> 2 2 CALL sub1 CCF Clear C flag CCF None 1 1 CCF CIEF Clear IE Flag CIEF None 1 1 CIEF COPF Clear OP flag COPF None 1 1 COPF CP Comparison CP<src1>,<src2> A,<pregs> 1 1 CP A,P0:0 A,<dregs> 1 1 CP A,D3:1 A,<memind> 1 3 CP A,@@P0:1 A,<direct> 1 1 CP A,%FF A,<regind> 1 1 CP A,@P2:1+ A,<hwregs> 1 1 CP A,STACK A,<limm> 2 2 CP A,#%FFCF A,<simm> 1 1 CP A, #%12 DEC Decrement DEC [<cc>,]<dest> <cc>,A 1 1 DEC NZ,A A 1 1 DECA INC Increment INC [<cc>,] <dest> <cc>,A 4 1 INC PL,A A 1 1 INC A JP Jump JP [<cc>,]<address> <cc>,<direct> 2 2 JP C,Labe! <direct> 2 2 JP Label LD Load destination LD<dest>,<src> A,<hwregs> 1 1 LD A,X with source A,<dregs> 1 4 LD A,DO:0 A,<pregs> 1 1 LD A,P0:1 A,<regind> 1 1 LD A,@P1:1 A,<memind> 1 3 LD A,@D0:0 A,<direct> 1 1 LD A,124 <direct>,A 1 1 LD 124,A <dregs>,<hwregs> 1 1 LD DO:0,EXT7 <pregs>,<simm> 1 1 LD P1:1,#%FA <pregs>,<hwregs> 1 1 LD P1:1,EXT1 <regind>,<limm> 1 1 LD@P1:1,#1234 <regind>,<hwregs> 1 1 LD @P1:1+,X <hwregs>,<pregs> 1 1 LD Y,P0:0 <hwregs>,<dregs> 4 1 LD SR,DO0:0 <hwregs>,<limm> 2 2 LD PC,#%1234 <hwregs>,<accind> 1 3 LD X,@A <hwregs>,<memind> 1 3 LD Y,@D0:0 <hwregs>,<regind> 1 1 LD A,@P0:0-LOOP <hwregs>,<hwregs> 1 1 LD X,EXT6 28 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors Inst. Description Synopsis Operands Words Cycles Examples Notes: 1. When <dest> is <hwregs>, <dest> cannot be P. 2. When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be EXTn if <src> is EXTn, <dest> cannot be X if <src> is X, <dest> cannot be SR if <src> is SR. 3. When <src> is <accind> <dest> cannot be A. MLD Multiply MLD <src1>,<src2> <hwregs>,<regind> 1 1 MLD A,@P0:0+LOOP L,<bank switch>] <hwregs>,<regind>,< 1 1 MLD A,@P1:0,OFF bank switch> 1 1 MLD @P1:1,@P2:0 <regind>,<regind> 1 1 MLD @P0:1,@P1:0,ON <regind>,<regind>, <bank switch> Notes: 1. If srct is <regind> it must be a bank 1 register. Src2s <regind must be a bank 0 register. 2. <hwregs> for src1 cannot be X. 3. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank switch> defaults to ON. MPYA Multiply and add MPYA <src1>,<src2> <hwregs>,<regind> 1 1 MPYA A,@P0:0 [,<bank switch>] <hwregs>,<regind>,< 1 1 MPYA A,@P1:0,OFF bank switch> 1 1 MPYA @P1:1,@P2:0 <regind>,<regind> 1 1 MPYA@P0:1,@P1:0,ON <regind>,<regind>, <bank switch> Notes: 1. If src1 is <regind> it must be a bank 1 register. Src2s <regind> must be a bank 0 register. 2. <hwregs> for src1 cannot be X. 3. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, the <bank switch> defaults to ON. MPYS Multiply and MPYS <src1>,<src2> <hwregs>,<regind> 1 1 MPYS A,@P0:0 subtract [,<bank switch>] <hwregs>,<regind>,< 1 1 MPYS A,@P1:0,OFF bank switch> 1 1 MPYS @P1:1,@P2:0 <regind>,<regind> 1 1 MPYS <regind>,<regind>, @P0:1,@P1:0,ON <bank switch> Notes: 1. If src1 is <regind> it must be a bank 1 register. Src2s <regind> must be a bank 0 register. 2. <hwregs> for src1 cannot be X. 3. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, <regind> the <bank switch> defaults to ON. NEG Negate NEG <cc>,A <cc>, A 1 1 NEG MILA A 1 1 NEGA NOP No operation NOP None 1 1 NOP OR Bitwise OR OR <dest>,<src> A,<pregs> 1 1 OR A,P0:1 A,<dregs> 1 1 OR A, DO:1 A,<limm> 2 2 OR A#%2C21 A,<memind> 1 3 OR A,@@P2:1+ A,<direct> 1 1 OR A, %2C A,<regind> 1 1 OR A,@P1:0-LOOP A,<hwregs> 1 1 OR A,EXT6 A,<simm> 1 1 OR A,#%12 POP Pop value POP <dest> <pregs> 1 4 POP P0:0 from stack <dregs> 1 1 POP DO:1 <regind> 1 1 POP @P0:0 <hwregs> 1 1 POP A DS000300-DSP0199 PRELIMINARY 29289321/371 16-Bit Digital Signal Processors ZiLOG INSTRUCTION DESCRIPTIONS (Continued) Inst. Description Synopsis Operands Words Cycles Examples PUSH Push value PUSH <src> <pregs> 1 1 PUSH P0:0 onto stack <dregs> 1 1 PUSH D0:1 <regind> 1 1 PUSH @P0:0 <hwregs> 1 1 PUSH BUS <limm> 2 2 PUSH #12345 <accind> 1 3 PUSH @A <memind> 1 3 PUSH @@P0:0 RET Return from RET None 1 2 RET subroutine RL Rotate Left RL <cc>,A <cc>,A 1 1 RL NZ,A A 1 1 RLA RR Rotate Right RR <cc>,A <cc>,A 1 1 RRC,A A 1 1 RRA SCF Set C flag SCF None 1 1 SCF SIEF Set IE flag SIEF None 1 1 SIEF SLL Shift left SLL [<cc>, JA 1 1 SLL NZ,A logical A 1 4 SLLA SOPF _ Set OP flag SOPF None 1 1 SOPF SRA Shift right SRA<cc>,A <cc>,A 1 1 SRA NZ,A arithmetic A 1 1 SRAA SUB Subtract SUB<dest>,<src> A,<pregs> 1 1 SUB A,P1:1 A,<dregs> 1 1 SUB A,DO:1 A,<limm> 2 2 SUB A,#%2C2C A,<memind> 1 3 SUB A,@D0:1 A,<direct> 1 4 SUB A,%15 A,<regind> 1 1 SUB A,@P2:0-LOOP A,<hwregs> 1 1 SUB A,STACK A,<simm> 1 1 SUB A, #%12 XOR Bitwise XOR <dest>,<src> A,<pregs> 1 1 XOR A,P2:0 exclusive OR A,<dregs> 1 1 XOR A,DO:1 A,<limm> 2 2 XOR A,#13933 A,<memind> 1 3 XOR A,@@P2:1+ A,<direct> 1 1 XOR A,%2F A,<regind> 1 1 XOR A,@P2:0 A,<hwregs> 1 4 XOR A,BUS A,<simm> 1 1 XOR A, #%12 Bank Switch Operand. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether the bank switch is set ON or OFF. To more clearly represent this capacity, the keywords ON and OFF are used to state the status of the switch. These keywords are referenced in the instruction descriptions through the <bank switch> symbol. The most notable capability this item provides is that a source operand can be multiplied by itself (squared). 30 PRELIMINARY DS000300-DSP0199ZiLOG PACKAGE INFORMATION Z289321/371 16-Bit Digital Signal Processors Boone SYMBOL MILLIMETER INCH MIN MAX MIN MAX Al 0.51 1.02 020 -040 q Ps A2 3.18 3.94 125 BES) 0,38 0.53 015 021 81 1.02 1,52 -040 .060 c 0.23 0.38 009 015 OORT OMTO MOMS eescies D $2.07 | 52.58 | 2.050 2.070 E 15.24 | 15.75 600 620 D 3] 13.59 | 14.22 535 560 a 2.54 TYP 100 TYP eA 15.49 46.76 610 -660 Ql L 3,05 3.81 120 150 t Q1 1.52 | 1.91 | .060 | .075 4 A2 s 1,52 2.29 060 .090 1 L reer y yyy at be CONTROLLING DIMENSIONS : INCH c + a __~+| Figure 25. 40-Pin Package Diagram Le A D Al 0.66/05) 026/7.020 39 ea ; L219/1.067 ws h .0487.042 Bu p od Op De Ze p El E Sui Q ue p a H zo0 p Ap peo to FE 7 g 114/064 0457.025 NCH sympa. |_MILLIMETER I NOTES: MIN MAX MIN MAX 5 CERNE Ciiah tee w, ER Loser Las fs [ao 3. DIMENSION : _MM_ Al 2.41 [| ase | .095] 15 INCH B/E 17.40 17.65 | 685 695 DIVEL | 16.51 | 16.66 | .650 656 De 15.24 | 16.00 | 600 630 g 127 TYP 050 TYP Figure 26. 44-Pin PLCC Package Diagram DS000300-DSP0199 PRELIMINARY 31289321/371 16-Bit Digital Signal Processors ZiLOG PACKAGE INFORMATION (Continued) ~ A2 - Al SYMBOL MILLIMETER INCH MIN MAX MIN MAX Al 0.05 0.25 -002 010 A2 2.00 2.25 078 -089 b 0.25 0.45 010 018 c 0.13 0.20 -005 -004 HD 13.70 14,15 +939 +557 D 9.90 10.10 390 398 HE 13.70 14,15 539 397 E 9.90 10.10 390 -398 & 0.80 TYP 0315 TYP L oso | 1.20 | .o2a | .047 NOTES: 1, CONTROLLING DIMENSIONS ; MILLIMETER 2, LEAD COPLANARITY : MAX .10 . 004 Figure 27. 44-Pin QFP Package Diagram 32 PRELIMINARY DS000300-DSP0199289321/371 ZiLOG 16-Bit Digital Signal Processors ORDERING INFORMATION 289321 For fast results, contact your local ZiLOG sales office for 78932120PSC assistance in ordering the part desired. 28932120VSC 28932120VEC 28932120FSC 28932120FEC 289371 28937120PSC Z8937120VSC 28937120FSC Codes Package P = Plastic DIP V = Plastic PLCC F = Plastic PQFP Temperature S$ = 0C to +70C E =-40C to 85C Speed 20 = 20 MHz Environmental C = Plastic Standard Example: Z 8932120V SC is a 289321, 20 MHz, PLCC, 0 to +70C, Plastic Standard Flow L Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix DS000300-DSP0199 PRELIMINARY 33ZiLOG Preliminary Product Specification DS000300-DSP0199 Pre-Characterization Product: The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. 1999 by ZiLOG, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of ZiLOG, Inc. The information in this document is subject to change without notice. Devices sold by ZiLOG, Inc. are covered by warranty and patent indemnification provisions appearing in ZiLOG, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. 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