MC14066BCPG - ON Semiconductor - Datasheet.Directory

June, 2011 − Rev. 8

1Publication Order Number:

MC14066B/D

MC14066B

Quad Analog Switch/Quad

Multiplexer

The MC14066B consists of four independent switches capable of

controlling either digital or analog signals. This quad bilateral switch

is useful in signal gating, chopper, modulator, demodulator and

CMOS logic implementation.

The MC14066B is designed to be pin−for−pin compatible with the

MC14016B, but has much lower ON resistance. Input voltage swings

as large as the full supply voltage can be controlled via each

independent control input.

Features

•Triple Diode Protection on All Control Inputs

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Linearized Transfer Characteristics

•Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical

•Pin−for−Pin Replacement for CD4016, CD4016, MC14016B

•For Lower RON, Use The HC4066 High−Speed CMOS Device

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin Input Current (DC or Transient)

per Control Pin

±10 mA

ISW Switch Through Current ±25 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

1

14

PDIP−14

P SUFFIX

CASE 646

MC14066BCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

1

14

14066BG

AWLYWW

14

066B

ALYW



1

14

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or  = Pb−Free Package

SOEIAJ−14

F SUFFIX

CASE 965

1

14

MC14066B

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

MC14066B

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2

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 4

IN 4

CONTROL 4

CONTROL 1

VDD

IN 3

OUT 3

IN 2

OUT 2

OUT 1

IN 1

VSS

CONTROL 3

CONTROL 2

LOGIC DIAGRAM AND TRUTH TABLE

(1/4 OF DEVICE SHOWN)

BLOCK DIAGRAM

IN/OUT

CONTROL

OUT/IN

IN 4

CONTROL 4

IN 3

CONTROL 3

IN 2

CONTROL 2

IN 1

CONTROL 1

OUT 1

OUT 2

OUT 3

OUT 4

13

1

5

4

6

8

12

11

2

3

9

10

VDD = PIN 14

VSS = PIN 7

Control Switch

0=V

SS OFF

1=V

DD ON

Logic Diagram Restrictions

VSS ≤ Vin ≤ VDD

VSS ≤ Vout ≤ VDD

CIRCUIT SCHEMATIC

(1/4 OF CIRCUIT SHOWN)

VDD VDD

VDD

VDD VDD VDD VDD

VSS VSS

VSS

300

W

CMOS

INPUT

MC14066B

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎ

VDD

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎ

−55C

ÎÎÎÎÎÎÎ

25C

ÎÎÎÎÎ

125C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎ

Min

ÎÎÎÎ

Typ (2)

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

ÎÎÎÎÎÎÎÎ

Power Supply Voltage

Range

ÎÎÎÎ

VDD

ÎÎ

—

ÎÎÎÎÎÎÎ

ÎÎÎ

3.0

ÎÎÎ

18

ÎÎ

3.0

ÎÎÎÎ

−

ÎÎÎ

18

ÎÎÎ

3.0

ÎÎÎ

18

ÎÎ

V

ÎÎÎÎÎÎÎÎ

Quiescent Current Per

Package

ÎÎÎÎ

IDD

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎ

Control Inputs:

Vin = VSS or VDD,

Switch I/O: VSS v VI/O

v VDD, and

DVswitch v 500 mV (3)

ÎÎÎ

−

ÎÎÎ

0.25

0.5

1.0

ÎÎ

−

ÎÎÎÎ

0.005

0.010

0.015

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎ

7.5

15

30

ÎÎ

mA

ÎÎÎÎÎÎÎÎ

Total Supply Current

(Dynamic Plus Quiescent,

Per Package

ÎÎÎÎ

ID(AV)

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎ

TA = 25C only The

channel component,

(Vin – Vout)/Ron, is

not included.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

(0.07 mA/kHz) f + IDD

Typical (0.20 mA/kHz) f + IDD

(0.36 mA/kHz) f + IDD

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CONTROL INPUTS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ

Low−Level Input Voltage

ÎÎÎÎ

VIL

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎ

Ron = per spec,

Ioff = per spec

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎ

−

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎ

V

ÎÎÎÎÎÎÎÎ

High−Level Input Voltage

ÎÎÎÎ

VIH

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎ

Ron = per spec,

Ioff = per spec

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎ

3.5

7.0

11

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎ

V

ÎÎÎÎÎÎÎÎ

Input Leakage Current

ÎÎÎÎ

Iin

ÎÎ

15

ÎÎÎÎÎÎÎ

Vin = 0 or VDD

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎ

−

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎ

mA

ÎÎÎÎÎÎÎÎ

Input Capacitance

ÎÎÎÎ

Cin

ÎÎ

−

ÎÎÎÎÎÎÎ

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHES IN AND OUT (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎ

Recommended Peak−to−

Peak Voltage Into or Out

of the Switch

ÎÎÎÎ

VI/O

ÎÎ

−

ÎÎÎÎÎÎÎ

Channel On or Off

ÎÎÎ

0

ÎÎÎ

VDD

ÎÎ

0

ÎÎÎÎ

−

ÎÎÎ

VDD

ÎÎÎ

0

ÎÎÎ

VDD

ÎÎ

Vp–p

ÎÎÎÎÎÎÎÎ

Recommended Static or

Dynamic Voltage Across

the Switch (3) (Figure 1)

ÎÎÎÎ

DVswitch

ÎÎ

−

ÎÎÎÎÎÎÎ

Channel On

ÎÎÎ

0

ÎÎÎ

600

ÎÎ

0

ÎÎÎÎ

−

ÎÎÎ

600

ÎÎÎ

0

ÎÎÎ

300

ÎÎ

mV

ÎÎÎÎÎÎÎÎ

Output Offset Voltage

ÎÎÎÎ

VOO

ÎÎ

−

ÎÎÎÎÎÎÎ

Vin = 0 V, No Load

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

−

ÎÎÎÎ

10

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

mV

ÎÎÎÎÎÎÎÎ

ON Resistance

ÎÎÎÎ

Ron

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎ

DVswitch v 500 mV (3),

Vin = VIL or VIH

(Control), and Vin =

0 to VDD (Switch)

ÎÎÎ

−

ÎÎÎ

800

400

220

ÎÎ

−

ÎÎÎÎ

250

120

80

ÎÎÎ

1050

500

280

ÎÎÎ

−

ÎÎÎ

1200

520

300

ÎÎ

W

ÎÎÎÎÎÎÎÎ

DON Resistance Between

Any Two Channels

in the Same Package

ÎÎÎÎ

DRon

ÎÎ

5.0

10

15

ÎÎÎÎÎÎÎ

ÎÎÎ

−

ÎÎÎ

70

50

45

ÎÎ

−

ÎÎÎÎ

25

10

ÎÎÎ

70

50

45

ÎÎÎ

−

ÎÎÎ

135

95

65

ÎÎ

W

ÎÎÎÎÎÎÎÎ

Off−Channel Leakage

Current (Figure 6)

ÎÎÎÎ

Ioff

ÎÎ

15

ÎÎÎÎÎÎÎ

Vin = VIL or VIH

(Control) Channel to

Channel or Any One

Channel

ÎÎÎ

−

ÎÎÎ

±100

ÎÎ

−

ÎÎÎÎ

± 0.05

ÎÎÎ

±100

ÎÎÎ

−

ÎÎÎ

±1000

ÎÎ

nA

ÎÎÎÎÎÎÎÎ

Capacitance, Switch I/O

ÎÎÎÎ

CI/O

ÎÎ

−

ÎÎÎÎÎÎÎ

Switch Off

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

−

ÎÎÎÎ

10

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

pF

ÎÎÎÎÎÎÎÎ

Capacitance, Feedthrough

(Switch Off)

ÎÎÎÎ

CI/O

ÎÎ

−

ÎÎÎÎÎÎÎ

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

−

ÎÎÎÎ

0.47

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎ

pF

2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the

current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the

Maximum Ratings are exceeded. (See first page of this data sheet.)

MC14066B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25C unless otherwise noted.)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ (5)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Times VSS = 0 Vdc

Input to Output (RL = 10 kW)

tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns

tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns

tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns

ÎÎÎÎ

tPLH, tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

20

10

7.0

ÎÎÎÎ

40

20

15

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Control to Output (RL = 1 kW) (Figure 2)

Output “1” to High Impedance

ÎÎÎÎ

tPHZ

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

40

35

30

ÎÎÎÎ

80

70

60

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output “0” to High Impedance

ÎÎÎÎ

tPLZ

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

40

35

30

ÎÎÎÎ

80

70

60

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High Impedance to Output “1”

ÎÎÎÎ

tPZH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

60

20

15

ÎÎÎÎ

120

40

30

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High Impedance to Output “0”

ÎÎÎÎ

tPZL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

60

20

15

ÎÎÎÎ

120

40

30

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Second Harmonic Distortion VSS = – 5 Vdc

(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,

RL = 10 kW, f = 1.0 kHz)

ÎÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

0.1

ÎÎÎÎ

−

ÎÎÎ

%

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc

(RL = 1 kW, 20 Log (Vout/Vin) = − 3 dB, CL = 50 pF,

Vin = 5 Vp−p)

ÎÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

65

ÎÎÎÎ

−

ÎÎÎ

MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc

(Vin = 5 Vp−p, RL = 1 kW, fin = 1.0 MHz) (Figure 3)

ÎÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

– 50

ÎÎÎÎ

−

ÎÎÎ

dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Channel Separation (Figure 4) VSS = – 5 Vdc

(Vin = 5 Vp−p, RL = 1 kW, fin = 8.0 MHz)

(Switch A ON, Switch B OFF)

ÎÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

– 50

ÎÎÎÎ

−

ÎÎÎ

dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Crosstalk, Control Input to Signal Output (Figure 5)

VSS = – 5 Vdc

(R1 = 1 kW, RL = 10 kW, Control tTLH = tTHL = 20 ns)

ÎÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

300

ÎÎÎÎ

−

ÎÎÎ

mVp−p

4. The formulas given are for the typical characteristics only at 25C.

5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14066B

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5

ORDERING INFORMATION

Device Package Shipping†

MC14066BCPG PDIP−14

(Pb−Free) 500 Units / Rail

MC14066BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14066BDR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC14066BDTR2G TSSOP−14* 2500 / Tape & Reel

MC14066BFG SOEIAJ−14

(Pb−Free) 50 Units / Rail

MC14066BFELG SOEIAJ−14

(Pb−Free) 2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC14066B

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6

TEST CIRCUITS

Figure 1. DV Across Switch Figure 2. Turn−On Delay Time Test Circuit

and Waveforms

Figure 3. Bandwidth and

Feedthrough Attenuation

Figure 4. Channel Separation

Figure 5. Crosstalk,

Control to Output

Figure 6. Off Channel Leakage

CONTROL

SECTION

OF IC

SOURCE

V

LOAD

ON SWITCH

Vout

VC

Vout

Vin

RLCL

20 ns VDD

VSS

90%

50%

10%

tPZH tPHZ

tPZL tPLZ

10%

90%

10%

Vx

Vout

CL

RL

VDD VSS

VC

Vin

VDD - VSS

2

VDD - VSS

2

Vin

VDD

VSS

RLCL

Vin

1 k

Vout

RLCL = 50 pF

VC = -5.0 V TO +5.0 V SWING

VC = VDD FOR BANDWIDTH TEST

VC = VSS FOR FEEDTHROUGH TEST

OFF CHANNEL UNDER TEST

VDD

VSS

VDD

A

CONTROL

SECTION

OF IC

90%

Vin = VDD

Vx = VSS

Vin = VSS

Vx = VDD

10 k

MC14066B

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7

Figure 7. Channel Resistance (RON) Test Circuit

VDD

VSS

10 k

VDD

KEITHLEY 160

DIGITAL

MULTIMETER

1 kW

RANGE X-Y

PLOTTER

TYPICAL RESISTANCE CHARACTERISTICS

Figure 8. VDD = 7.5 V, VSS = − 7.5 V Figure 9. VDD = 5.0 V, VSS = − 5.0 V

RON, “ON” RESISTANCE (OHMS)

350

300

250

200

150

100

0

50

-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

-55°C

RON, “ON” RESISTANCE (OHMS)

350

300

250

200

150

100

0

50

-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

-55°C

Figure 10. VDD = 2.5 V, VSS = − 2.5 V

RON, “ON” RESISTANCE (OHMS)

700

600

500

400

300

200

0

100

-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

-55°C

Figure 11. Comparison at 25°C, VDD = −VSS

RON, “ON” RESISTANCE (OHMS)

350

300

250

200

150

100

0

50

-8.0-10 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 25°C

VDD = 2.5 V

5.0 V

7.5 V

MC14066B

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8

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The

0−to−5 V digital control signal is used to directly control a

5 V peak−to−peak analog signal.

The digital control logic levels are determined by VDD

and VSS. The VDD voltage is the logic high voltage, the VSS

voltage is logic low. For the example, VDD = + 5 V = logic

high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by VDD

and VSS. The analog voltage must not swing higher than

VDD or lower than VSS.

The example shows a 5 V peak−to−peak signal which

allows no margin at either peak. If voltage transients above

VDD and/or below VSS are anticipated on the analog

channels, external diodes (Dx) are recommended as shown

in Figure B. These diodes should be small signal types able

to absorb the maximum anticipated current surges during

clipping.

The absolute maximum potential difference between

VDD and VSS is 18 V. Most parameters are specified up to

15 V which is the recommended maximum difference

between VDD and VSS.

Figure A. Application Example

+5 V

VDD VSS

5 Vp-p

ANALOG SIGNAL

0-TO-5 V DIGITAL

CONTROL SIGNALS

SWITCH

IN

MC14066B

SWITCH

OUT

5 Vp-p

ANALOG SIGNAL

+5.0 V

+2.5 V

GND

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

Figure B. External Germanium or Schottky Clipping Diodes

VDD VDD

VSS VSS

DXDX

SWITCH

IN

SWITCH

OUT

MC14066B

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9

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01



NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC14066B

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10

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

H

14 8

71

M

0.25 B M

C

h

X 45

SEATING

PLANE

A1

A

M



S

A

M

0.25 B S

C

b

13X

B

A

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

 

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14066B

http://onsemi.com

11

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.



S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14066B

http://onsemi.com

12

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

10 0

10 

LE

Q1



NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

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