Power Management & Multimarket
Datasheet
Rev 3.0, 08/20/2016
IR3883
800kHz 3A IR MOSFET IPOL Synchronous Buck Regulator
IR3883
IPOL Synchronous Buck Regulator
Product Overview
Datasheet 2 Rev 3.0 08/20/2016
1 Product Overview
Figure 1-1 IR3883 Part Number Configuration Code
Features
• Wide Input Voltage Range (2.5V-14V) with an
external Vcc
• Single Input Voltage Range (4.5V to 14V)
• Continuous 3A Load Capability
• 800kHz Switching Frequency
• 10uA Supply Current at Shutdown
• Enhanced Stability engine with Ceramic
Capacitors and no External Compensation
• Enhanced Light Load Efficiency with Reduced
Switching Frequency and Diode Emulation
• Forced Continuous Conduction Mode Option
• Thermally Compensated Peak Over-Current
Protection with three selectable levels
• Internal Soft-Start
• Enable Input
• Pre-bias Start Up
• Thermal Shut Down
• Power Good Output
• Precision Reference Voltage (0.5V+/-0.6%)
• Small Size 3mmx3mm QFN
• Lead-free, Halogen-free and RoHS6 Compliant
Description
The IR3883 is an easy-to-use, fully
integrated and highly efficient monolithic DC/DC
regulator. The on-chip PWM controller and
MOSFETs make IR3883 a space-efficient solution,
providing accurate power delivery. The IR3883
employs an Enhanced Stability (EaSy) engine that
makes it stable with ceramic capacitors without
compensation.
IR3883 can operate in Forced Continuous
Conduction Mode (FCCM) or can enter Diode
Emulation mode during light loads to save power.
With ultra-light loads, IR3883 can enter a low
quiescent current mode making it ideal for Standby
power supplies.
It features important protection functions, such as
Pre-bias startup, internal soft-start, hiccup over-
current protection and thermal shutdown to give
required system level security in the event of fault
conditions.
Applications
• Server and Computing
• Storage Applications
• Communications Infrastructure
• General DC-DC Converters
• Distributed Point of Load Power Architectures
Table 1-1 Ordering Information
Part Number Package Type Standard Pack Part Number
Form Quantity
IR3883 PQFN 3 mm x 3 mm Tape and Reel 3000 IR3883MTRPBF
IR3883
PBF
TR
M
Lead Free
Tape and Reel
Package Type
IR3883
IPOL Synchronous Buck Regulator
Basic Application
Datasheet 3 Rev 3.0 08/20/2016
2 Basic Application
Figure 2-1 IR3883 Basic Application Circuit
Figure 2-2 IR3883 Performance Curves
Boot
Vcc
Fb
Gnd PGnd
SW
PGood
PGood
En/FCCM
V<Vin<14V
PVin
Vo
PGND
Vin
OCSet
(Optional)
60
65
70
75
80
85
90
95
100
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Efficiency(%)
Io(A)
IR3883Efficiency@PVin=12VandFCCM
5V
3.3V
2.5V
1.8V
1.2V
1.0V
IR3883
IPOL Synchronous Buck Regulator
Block Diagram
Datasheet 4 Rev 3.0 08/20/2016
3 Block Diagram
Figure 3-1 Simplified block diagram
PWM
GATE
DRIVE
LOGIC
ADAPTIVE
ON-TIME
GENERATOR
+
-
SOFT
START
CONTROL
LOGIC
Zcross
PV in
Fault
VCC
SE T
FB
Vin
BOOT
SW
PGND
Vo
PVIN
EN/
FCCM
GND
PWM
COMP
VCC
VCC
Current Limit
Control
Zero Cross
DETECTION
LDrVin
HDrv
LDrv
LDrVin
LDrVin
FCCM_EN
OV
Fault
Fault
OV
FCCM
Vcc
THERMAL
SHUT-DOWN
OV
DETECTION
FB
OV
SS
OV
Fault
INTERNAL REFERENCE
INDUCTOR CURRENT
RIPPLE EMULATOR
+
VREF
OCSet
HDrVin
PO R
HDrVin
+
PO R
PG ND
+
Enable
LDO
PGood
POR
IR3883
IPOL Synchronous Buck Regulator
Pinout Diagram and Pin Description
Datasheet 5 Rev 3.0 08/20/2016
4 Pinout Diagram and Pin Description
Figure 4-1 Pinout Diagram: PQFN 3 mm x 3 mm (Top View)
Table 4-1 Pin Description
Pin No. Name Pin
Type
Function
1 Vin S Input supply to the internal LDO.
2 Vcc S Input bias for the internal control circuitry and driver. Supplied by an internal
LDO or an external Vcc voltage. A 2.2uF ceramic capacitor must be used
between Vcc and the Power ground (PGND).
3 OCSet I Over Current Protection (OCP) limit set point. Three user selectable OCP
limits are available by floating this pin, connecting it to Vcc or connecting it to
PGnd.
4 Gnd S Signal ground for internal reference and control circuitry.
5 En/FCCM I Multifunction pin: (1) Enable pin to turn on and off the IC.
(2) Enable Diode Emulation (DE) Mode operation when En/FCCM voltage is
lower than FCCM stop threshold, or Forced Continuous Conduction Mode
(FCCM) operation, when En/FFCM voltage is higher than FCC start threshold.
6 PGood O Power Good status output pin is open drain. Connect a pull up resistor of 50kΩ
from this pin to Vcc or an external bias voltage.
7 Fb I Output voltage feedback pin. Connect this pin to the output of the regulator via
a resistor divider to set the output voltage.
8 Vo I Vo sense pin. Connect this pin directly to the output of the regulator to set the
on-time.
9 Boot I Supply voltage for the high-side driver. Connect this pin to the SW node of the
regulator through a bootstrap capacitor.
16 15 14 13
12
11
10
9
8765
4
3
2
1
PVin PGND
SW
BOOT
PVin PGND
SW
SW
Vo
FbPG
EN/
FCCM
GND
OCset
Vcc
Vin
Exposed
Pad
IR3883
IPOL Synchronous Buck Regulator
Pinout Diagram and Pin Description
Datasheet 6 Rev 3.0 08/20/2016
10, 11, 12 SW O Switch node. This pin is connected to the output inductor.
13, 14 PGND S Power Ground. This pin serves as a separated ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
15, 16 PVin S Input supply for the power stage.
Exposed
Pad
- Exposed pad needs to be connected to PGND with PCB layout design.
Thermal via holes can be placed on the exposed pad to aid thermal
dissipation.
Table 4-1 Pin Description
Pin No. Name Pin
Type
Function
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 7 Rev 3.0 08/20/2016
5 Specifications
5.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 5-1 may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
Note:
1. Must not exceed 6V.
2. PGND pin and GND pin are connected together.
3. Maximum SW node voltage should not exceed the absolute maximum rating defined in Table 5-1.
Note:
4. θJA is measured with components mounted on a high effective thermal conductivity test board in free air
Table 5-1 Absolute Maximum Ratings
Parameter Min Max Units Conditions
PVin, Vin, En/FCCM to PGND -0.3 16 V 2. 3.
Vcc to PGND -0.3 6 V 2.
Boot to PGND -0.3 22 V (DC) 2.
-0.3 24 V (AC, 10ns) 2.
SW to PGND -0.3 16 V (DC) 2.
-4.0 18 V (AC, 10ns) 2.
Boot to SW -0.3 VCC + 0.3 V 1.
Vo, Fb to GND -0.3 6 V (DC) 2.
-0.3 6.5 V (AC, 10us) 2.
OCSet, Pgood to GND -0.3 6 V 2.
PGnd to Gnd -0.3 0.3 V
Table 5-2 Thermal Information
Parameter Value / Units Condition
Junction-to-ambient thermal resistance θJA 40oC/W 4.
Junction to PCB thermal resistance θJ - PCB 6oC/W
Junction to case top thermal resistance θJ - CTop 38oC/W
Storage Temperature Range -55oC to 150oC
Junction Temperature Range -40oC to 150oC
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 8 Rev 3.0 08/20/2016
5.2 Recommended Operating Conditions
Note:
5. Vin is connected to Vcc to bypass the internal LDO.
6. Vin is connected to PVin. For single-rail applications with PVin=Vin=4.5V-5.5V, Vcc (the internal LDO output
voltage) is in dropout mode. Please refer to the application information in the internal LDO and the Over
Current Protection sections.
5.3 Electrical Characteristics
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 14V, 0°C < TJ < 125°C.
Typical values are specified at Ta = 25°C.
Table 5-3 Recommended Operating Conditions
Symbol Parameter Min Max Units Condition
PVin Input Voltage Range with External Vcc 2.5 14 V 5. 3.
PVin, Vin Input Voltage Range with Internal LDO 5.5 14 V 6. 3.
Vcc Supply Voltage Range 4.5 5.5 V 3.
VoOutput Voltage Range 0.5 5 V
IoContinuous Output Current Range 0 3 A
TJOperating Junction Temperature -40 125 oC
Table 5-4 Electrical Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
Power Stage
Rds(on)_Top Top Switch VBoot - Vsw= 5.2V, Tj =25°C - 82 106.4 mΩ
Rds(on)_Bot Bottom Switch Vcc = 5.2V, Tj =25°C - 26 33.9 mΩ
Boot Diode Forward Voltage IBoot = 10mA 200 300 mV
Supply Current
Iin(Standby) Vin Supply Current (standby) En = Low - 1.8 10 μA
Iin(Static) Vin Supply Current (static) En = 2V, No Switching - 137 200 μA
Iin(Dyn) Vin Supply Current
(dynamic)
En = High, Fs = 800kHz,
Vin = 12V
-4.55.5mA
Soft-Start
SSrate Soft-Start Ramp Rate 0.16 0.2 0.24 mV/µs
Feedback Voltage
VFB Feedback Voltage - 0.5 V
Accuracy 0°C <Tj < 85°C, Vout =0.5V -0.6 +0.6 %
-40°C <Tj < 125°C, Vout =0.5V7. -1 +1 %
IVFB VFB Input Current VFB = 0.5V, Tj = 25°C -0.4 0 +0.4 μA
On-Time Timer Control
Ton On-Time Vin = 12V, Vo = 1.05V 109 ns
Ton(Min) Minimum On-Time Vin = 12V, Vo = 0V 8. 20 50 ns
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 9 Rev 3.0 08/20/2016
Note:
7. Hot and Cold temperature performance is assured via correlation using statistical quality control. Not tested in
production.
8. Ensured by design but not tested in production.
Toff(Min) Minimum Off-Time VFB = 0V, Tj = 25°C 240 320 ns
Internal Regulator (LDO)
VCC LDO Output Voltage 5.5V < Vin < 14V, 0A - 5.5mA 4.9 5.2 5.4 V
4.5V < Vin < 5.5V, 0A - 5.5mA 4.4 - - V
VLN Line Regulation 5.5V < Vin < 14V, 5.5mA - - 30 mV
VLD Load Regulation 0A - 5.5mA - - 100 mV
Ishort Short Circuit Current - 90 - mA
Thermal Shutdown
Thermal Shutdown 8. -145- oC
Hysteresis 8. -25-oC
Under Voltage Lockout
VCC_UVLO_
Start
VCC Start Threshold VCC Rising Trip Level 4 4.2 4.4 V
VCC_UVLO_
Stop
VCC Stop Threshold VCC Falling Trip Level 3.6 3.8 4.1 V
Enable_High Enable Threshold Ramping up 1.14 1.2 1.36 V
Enable_Low Ramping down 0.9 1 1.06 V
REN Input Impedance 500 1000 1500 kΩ
VFCCM_start FCCM Start Threshold 2.6 - - V
VFCCM_stop FCCM Stop Threshold - - 2.3 V
Current Limit
IOC Current Limit Threshold 0°C<Tj<125°C, OCSET=PGND 4.0 5.14 5.9
A
0°C<Tj<125°C, OCSET=float8. 3.2 4.04 4.6
0°C<Tj<125°C, OCSET= VCC8. 2.3 2.95 3.4
Tblk_Hiccup Hiccup Blanking Time 8. -20-ms
Over Voltage Protection
VOVP Output OV Protection
Threshold
OVP detect 115 120 125 %
TOVPDEL Output OV Protection Delay - 5 - μs
Power Good
VPG(upper) Power Good Threshold Fb Rising 85 90 95 % Vref
VPG(lower) Power Good Threshold Fb Falling 80 85 90 % Vref
IPG Power Good Sink Current PG = 0.5V, En = 2V 2.5 5 - mA
VPG(low) Power Good Voltage Low
when no supply
Vin = Vcc = 0V, Rpull-up = 50kΩ
to 3.3V
-0.30.5V
Table 5-4 Electrical Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 10 Rev 3.0 08/20/2016
5.4 Typical Operating Characteristics -40°C To +125°C
Figure 5-1 Typical Operation Characteristics (Set 1 of 3)
0
20
40
60
80
100
120
140
‐40 ‐20 0 20 40 60 80 100 120 140
(mΩ)
Te m pe r at u re (°C)
R
DS(on)
atVcc=5.1V
ControlFET SyncFET
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
‐40 ‐20 0 20 40 60 80 100 120 140
(μA)
Te m p e ra tu r e (°C)
I
in
(Standby)
4.55
4.60
4.65
4.70
4.75
4.80
‐40 ‐20 0 20 40 60 80 100 120 140
(mA)
Te m p e r a t u re (°C)
I
in
(Dyn)
80
90
100
110
120
130
140
150
‐40 ‐20 0 20406080100120140
(μA)
Te m pe r at ure (°C)
I
in
(Static)
4.4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
‐40 ‐20 0 20406080100120140
Vcc(V)
Te m pe ra t ur e (°C)
Vcc@Icc=5.5mA
Vin=5.5V
Vin=4.5V
4.9
4.95
5
5.05
5.1
5.15
5.2
5.25
5.3
5.35
5.4
‐40 ‐20 0 20406080100120140
(V)
Te m p e ra tu r e (°C)
VccVoltage
Icc=0mA
Icc=5.5mA
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
‐40 ‐20 0 20406080100120140
(V)
Te m pe r atu r e (°C)
VccUVLO
VccUVLOStart
VccUVLOStop
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
‐40 ‐20 0 20 40 60 80 100 120 140
(V)
Te m pe r at u re (°C)
EnUVLO
EnableUVLOStart
EnableUVLOStop
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 11 Rev 3.0 08/20/2016
Figure 5-2 Typical Operation Characteristics (Set 2 of 3)
2.50
3.00
3.50
4.00
4.50
5.00
5.50
‐40 ‐20 0 20406080100120140
(A)
Te m pe r a tu re (°C)
Iocp
2.38
2.4
2.42
2.44
2.46
2.48
2.5
2.52
‐40 ‐20 0 20406080100120140
(V)
Te m p e ra t ur e (°C)
FCCMStart/StopThreshold
FCCMStart
FCCMStop
575
580
585
590
595
600
605
610
615
620
625
‐40 ‐20 0 20406080100120140
(mV)
Te m p e ra tu r e (°C)
OVP_Vth
420
425
430
435
440
445
450
455
‐40 ‐20 0 20 40 60 80 100 120 140
(mV)
Te m pe r at ure (°C)
PowerGoodThreshold
VPG(on)
VPG(lower)
OCSet=Gnd
OCSet=Floating
OCSet=Vcc
105
106
107
108
109
110
111
112
113
114
115
‐40 ‐20 0 20 40 60 80 100 120 140
On‐Time(ns)
Te m pe r at u re (°C)
On‐TimePVin=12V,Vo=1.05V
700
750
800
850
900
950
1000
0 0.5 1 1.5 2 2.5 3
Fsw(kHz)
Iout(A)
Fswvs.Ioutatroomtemperature
Vin=12V,Vo=3.3V,L=XAL5030‐222,Co=2x22uF
3.15
3.2
3.25
3.3
3.35
3.4
3.45
00.511.522.53
Vo(V)
Io(A)
LoadRegulationatroomtemperature
PVin=12V,Vo=3.3V,fsw=800kHz,L=2.2uH,Co=2x22uF
FCCM,Cff=220pF DEM,Cff=220pF
497.00
498.00
499.00
500.00
501.00
502.00
503.00
‐40 ‐20 0 20 40 60 80 100 120 140
(mV)
Te m pe r at u re (°C)
VFB
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 12 Rev 3.0 08/20/2016
Figure 5-3 Typical Operation Characteristics (Set 3 of 3)
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 13 Rev 3.0 08/20/2016
5.5 12V Typical Efficiency and Power Loss Curves
PVin = 12V, VCC = Internal LDO, Io = 0A-3A, Room Temperature, No Air Flow. Note that the efficiency and power
loss curves include the losses of IR3883, the inductor losses and the losses of the input and output capacitors.
The table below shows the inductors used for each of the output voltages in the efficiency measurement.
Figure 5-4 12V Efficiency and all power losses including inductor losses and losses of input and output
capacitors in Forced Continuous Conduction Mode.
Figure 5-5 Diode Emulation Mode improves efficiency at light load (12Vin)
Table 5-5 Inductor List for IR3883 12V Efficiency Measurement
VOUT (V) LOUT (µH) P/N DCR (m)
1.0 1.0 XEL4030-102 8.89
1.2 1.0 XEL4030-102 8.89
1.8 1.5 XEL4030-152 15.1
2.5 2.2 XAL5030-222 13.2
3.3 2.2 XAL5030-222 13.2
5 3.3 XAL5030-332 21.2
60
65
70
75
80
85
90
95
100
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Efficiency(%)
Io(A)
IR3883Efficiency@PVin=12VandFCCM
5V
3.3V
2.5V
1.8V
1.2V
1.0V
0
0.2
0.4
0.6
0.8
1
1.2
00.511.522.533.5
PowerLosses(W)
Io(A)
IR3883PowerLosses@PVin=12VandFCCM
5V
3.3V
2.5V
1.8V
1.2V
1.0V
0
0.05
0.1
0.15
0.2
0.25
0.3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
PowerLosses(W)
Io(A)
IR3883PowerLosses@PVin=12VandDEM
5V
3.3V
2.5V
1.8V
1.2V
1.0V
IR3883
IPOL Synchronous Buck Regulator
Specifications
Datasheet 14 Rev 3.0 08/20/2016
5.6 5V Typical Efficiency and Power Loss Curves
PVin = Vin = VCC = 5V, Io = 0A-3A, Room Temperature, No Air Flow. Note that the efficiency and power loss curves
include the losses of IR3883, the inductor losses and the losses of the input and output capacitors. The table below
shows the inductors used for each of the output voltages in the efficiency measurement.
Figure 5-6 5V Efficiency and all power losses including inductor losses and losses of input and output
capacitors in Forced Continuous Conduction Mode.
Table 5-6 Inductor List for IR3883 5V Efficiency Measurement
VOUT (V) LOUT (µH) P/N DCR (m)
0.9 1.0 XEL4030-102 8.89
1.0 1.0 XEL4030-102 8.89
1.2 1.0 XEL4030-102 8.89
1.8 1.5 XEL4030-152 15.1
2.5 1.5 XEL4030-152 15.1
IR3883
IPOL Synchronous Buck Regulator
Theory of Operation
Datasheet 14 Rev 3.0 08/20/2016
6 Theory of Operation
The IR3883 is an easy-to-use, fully integrated and highly efficient monolithic DC/DC regulator. The on-chip PWM
controller and MOSFETs make IR3883 a space-efficient solution, providing accurate power delivery.
The IR3883 offers two different operation modes: Forced Continuous Conduction Mode (FCCM) and Diode
Emulation Mode (DEM). With FCCM, the device always operates as a synchronous buck converter with a pseudo
constant switching frequency of 800 kHz and small output voltage ripples. In DEM, the synchronous FET is turned
off when the inductor current drops to zero, which provides better efficiency at the light load.
6.1 Enhanced Stability engine
The IR3883 uses the Enhanced Stability engine that comprises Constant on-time control with proprietary
internal ramp compensation to offer stability across a wide range of conditions.
Unlike conventional COT devices, which usually require a certain amount of output ripple voltages to ensure the
stability, the IR3883 includes proprietary internal ramp compensation, facilitating the use of low ESR ceramic
output capacitors without resorting to the injection of external ripple voltage.
In addition, the internal ramp implements the input voltage feedfoward feature, which helps to preserve the same
loop response with a wide input voltage range.
The operation of IR3883 is described as follows. The output voltage of the regulator is fed to the FB pin through a
resistor divider. Combined with the proprietary internal ramp, the FB voltage is then compared to an internal
reference voltage. If the combined voltage is lower than the reference voltage, the control FET is turned on for a
fixed duration to charge the output capacitor. When the on-time of the control FET is finished, the synchronous
FET is turned on. In FCCM, synchronous FET stays on till the combination of FB voltage and the internal ramp
drops below the reference voltage and a new PWM pulse is initiated. In DEM, synchronous FET will be turned off
when the inductor current drops to zero.
6.2 Pseudo Constant Switching Frequency
The IR3883 operates with a pseudo constant frequency of 800 kHz within the recommended operation range. To
achieve the constant switching frequency, the on-time of the control FET is automatically adjusted for different
input and output voltages.
The on-time is determined by the ratio of the voltages at Vo pin and PVin pin, and can be calculated as follows:
6.3 Soft-Start
The IR3883 has an internal digital soft-start circuit to control the output voltage rise time, and to limit the current
surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when Enable and Vcc voltages
rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft-start signal
linearly rises at the rate of 0.2mV/us. The nominal Vout start-up time is fixed, and is equal to:
The over-current protection (OCP) and over-voltage protection (OVP) are enabled during the soft-start to protect
the device for any short circuit or over voltage condition. Figure 6-1 illustrates the theoretical operation waveforms
during the start-up.
kPV
V
T
in
on
800
1
0
×=
ms
usmV
V
T
start
5.2
/2.0
5.0 ==
IR3883
IPOL Synchronous Buck Regulator
Theory of Operation
Datasheet 15 Rev 3.0 08/20/2016
Figure 6-1 Theoretical Waveforms during Soft-Start
6.4 EN/FCCM
En/FCCM is a multi-function pin. It can be used to:
• On/Off the IR3883
• Select the operation mode: FCCM or DEM
• Implement Under-Voltage Lockout of the Input Voltage
When En/FCCM voltage is higher than the Enable_high threshold, 1.2V typical, the IR3883 is turned on with DEM.
In order to operate in FCCM, the En/FCCM voltage needs to be above 2.6V. The Enable/FCCM thresholds are
designed to be compatible with 3.3V logic.
The IR3883 has a precise Enable_high threshold voltage, which is internally monitored by the Under-Voltage
Lockout (UVLO) circuit. As shown in configuration_1 in Figure 6-2, the input of the Enable pin can be derived from
the PVin voltage by a set of resistive divider, REN1 and REN2. By selecting different divider ratios, users can
program the UVLO threshold voltage. The bus voltage UVLO is a very desirable feature. It prevents the IR3883
from regulating at PVin lower than the desired voltage level.
For some space constrained designs, the En/FCCM pin can be directly connected to PVin without using the
external resistor dividers.
The En/FCCM pin should not be left floating. A pull down resistor in the range of tens of kilo ohms is recommended.
Cofiguration_2 and Configuration_3 in Figure 6-2 include the connections of En/FCCM without using the external
resistor divider. Figure 6-3 illustrates the theoretical start-up waveforms.
Figure 6-2 EN/FCCM Configurations
POR
PGood
Internal
Softstart
FB
0.9*Vref
0. 5V
REN1
REN2
PVin
En/FCCM IR3883
PVin
PVin
En/FCCM IR3883
PVin
Vin Vin
Vcc Vcc
5V
En/FCCM IR3883
PVin Vin
Vcc
Configuration_1:
Single supply with internal LDO,
adjustable PVin UVLO and
optional FCCM or DEM
Configuration_2:
Single supply with internal LDO
and FCCM operation
Configuration_3:
Single supply with 5V input,
external Vcc and FCCM operation
IR3883
IPOL Synchronous Buck Regulator
Theory of Operation
Datasheet 16 Rev 3.0 08/20/2016
Figure 6-3 EN/FCCM theoretical start-up waveforms
6.5 Pre-bias Start-up
The IR3883 is able to start up into a pre-charged output without causing oscillations and disturbances of the output
voltage. When IR3883 starts up with a pre-biased output voltage, both control FET and Synch FET are kept off till
the internal soft-start signal exceeds the FB voltage.
During pre-bias start-up, PGood signal is held low till the first gate signal for control FET is generated.
6.6 Internal Low Dropout (LDO)
IR3883 has an integrated low dropout LDO regulator, providing the DC bias voltage for the internal circuitry.
The typical LDO output voltage is 5.2V. A 2.2uF low ESR ceramic capacitor is required to be placed close to the
VCC pin. For internally biased single rail operation, VIN pin should be connected to PVIN pin, as shown in the first
2 configurations of Figure 6-2. If an external bias voltage is used, VIN pin should be connected to VCC pin to
bypass the internal LDO, as shown in Figure 6-4.
To minimize the standby current, the internal LDO is disabled when the Enable of IR3883 is below the Enable_high
threshold.
Figure 6-4 Use an external bias voltage
Pvin= Vin=12V
Vcc
Enable >1.2V
Fb
0V
0V
0V
0V
Vcc_UVLO
0V
90% of Vref
PGood
Pgood stays at logic low
Start-up with Enable up after PVin and Vin.
PGood is pulled up to an external supply. Start-up with PVin, Vin and Enable tied together.
PGood is pulled up to an external supply
Vcc
Fb
0V
0V
0V
Vcc_UVLO
0V
90% of Vref
PGood
Pgood stays at logic low
PVin=Vin=Enable=12V
En Threshold
PVin
En/FCCM IR3883
PVin Vin
Vcc
Ext Vcc
IR3883
IPOL Synchronous Buck Regulator
Theory of Operation
Datasheet 17 Rev 3.0 08/20/2016
6.7 Over Current Protection
IR3883 offers three selectable over current limits using OCSet pin. The Over Current Protection (OCP) is
performed by sensing the peak inductor current through the RDS(on) of the Sync MOSFET. This method
enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related
noise issues. The current limit is pre-set internally and is compensated according to the IC temperature to minimize
the OCP limit variation induced by temperature. However, OCP limits are not Vcc compensated. If Vcc drops
below the regulation, OCP limits are also reduced.
OCP circuit senses the current of the Sync MOSFET at the end of 100ns after Control FET is turned off. If the
current exceeds the OCP limit, PGood and soft-start signal will be pulled low. Sync FET remains on till the current
is decreased to zero, then IR3883 enters hiccup mode. Both Control FET and Sync FET remain off during the
hiccup blanking time. After the hiccup blanking time expires, IR3883 will try to restart. If the over current fault is
still detected, the preceding actions will be repeated. IR3883 stays in the hiccup mode till the over current fault is
removed. OCP is activated in start-up also. Figure 6-5 illustrates the operation of OCP.
Figure 6-5 OCP with Hiccup Mode Illustrations
6.8 Minimum On-Time and Off-Time
The minimum on-time refers to the shortest time for control FET to be reliably turned on. Typically, it is 20ns for
IR3883.
The minimum off-time refers to the minimum time duration in which the Sync FET stays on for each switching
cycle. The minimum off-time is needed for IR3883 to charge the bootstrap capacitor and to monitor the current of
the Sync FET for OCP.
For high duty-cycle applications, it is important to make sure the desired off-time is larger than the minimum off-
time specified in the Electrical Table.
In real applications, the switching frequency can increase with the load current, in order to compensate for the
power losses induced voltage drop in the circuitry. The following formula could be used to estimate the off-time
when the conduction losses of power stage and DCR losses of the inductor are considered.
Inductor
Current
Current Limit
HDrv
LDrv
PGood
100ns
Hiccup
Blanking time
IR3883
IPOL Synchronous Buck Regulator
Theory of Operation
Datasheet 18 Rev 3.0 08/20/2016
Where RDS(on)Ctrl and RDS(on)Sync are the RDS(on) of the Control FET and Sync FET respectively. DCR is the DC
resistance of the inductor.
To ensure a proper operation, Toff should meet the following criterion.
Where (minimum off - time)max = 320ns. Please note that the actual Toff is usually smaller than the calculated value
as shown above because the switching losses, losses on the PCB losses etc. are not considered in the calculation.
6.9 Over Voltage Protection (OVP)
The IR3883 senses the voltage at FB pin for Over-Voltage Protection (OVP). When FB voltage exceeds the OVP
threshold for the duration longer than the output OV protection delay (typical value is 5μs), OVP circuitry is tripped.
Control FET is turned off immediately and PGood is pulled low. Sync FET is turned on to discharge the output
capacitor, till the FB voltage drops below the OVP threshold.
Once OVP is tripped, Control FET remains latched off till a reset is performed by cycling either VCC voltage or
Enable signal. Figure 6-6 illustrates the operation of over voltage protection.
Figure 6-6 Operation of Over Voltage Protection
6.10 Power Good Output
The PGood pin is the open drain of an internal NFET and needs to be externally pulled high through a pull-up
resistor. PGood signal is high when three criteria are satisfied.
1. Enable and VCC voltages are above their respective thresholds.
2. No fault occurs including over current, over voltage and over temperature.
3. Vout is within regulation.
0)(0
0)(0
)(
)(
IDCRRV
IDCRRVV
TT
SynconDS
CtrlonDSin
onoff
×++
×
+
−
−
×=
max
time)-off mimum( >
off
T
120%Vref
90%Vref
OVP delay =5us
115%Vref
LDrv
HDrv
PGood
FB
Vref
IR3883
IPOL Synchronous Buck Regulator
Theory of Operation
Datasheet 19 Rev 3.0 08/20/2016
In order to detect if Vout is in regulation, PGood comparator continuously monitors the FB voltage. When FB
voltage ramps up above the upper threshold – 90% of Vref, PGood signal is pulled high. When FB voltage ramps
down below the lower threshold – 85% of Vref, PGood signal is pulled low. Figure 6-7 illustrates the PGood upper
and lower thresholds.
For pre-biased start-up, PGood is not active until the first gate signal of the control FET is initiated.
IR3883 also integrates an additional PFET in parallel to the PGood NFET, as shown in Figure 3-1. This PFET
allows PGood signal to stay at logic low when the bias voltage of IR3883 is low, and/or the En is low, but the
external PGood bias voltage still presents. Please refer to Figure 6-3. A 50kΩ pull-up resistor is needed for 3.3V
PGood bias voltage to maintain PGood low when IR3883 is disabled.
Figure 6-7 Power Good Thresholds
6.11 Over Temperature Protection
Temperature sensing is provided inside IR3883. The Over Temperature Protection (OTP) threshold is typically set
to 145oC. When OTP threshold is exceeded, both MOSFETs are turned off, and the internal soft-start is reset. The
internal LDO is still in operation when OTP is tripped.
Automatic restart is initiated when the sensed temperature drops below the OTP threshold. The hysteresis of the
OTP threshold is 25oC.
85%V
ref
90%V
ref
90%V
ref
FB
PGood
V
ref
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 20 Rev 3.0 08/20/2016
7 Application Information
The following key parameters shall be used as an example for typical IR3883 applications. The application circuit
is shown in Figure 7-1.
•PV
in = 12V (±10%)
•V
o = 3.3V
•I
o = 3A
•V
o Ripple Voltage = ±1% of Vo
• Transient response = ± 3% of Vo (for 30% Load Transient)
7.1 Enabling IR3883
To enable IR3883 in Diode Emulation Mode (DEM), the voltage at EN/FCCM pin should be higher than the Enable
threshold, but lower than FCCM stop threshold. If a resistor divider is used to generate the Enable voltage from
PVin as shown in Figure 6-2 configuration 1, the resistor divider can be selected as follows.
Where PVin(min) and PVin(max) are the minimum and maximum input voltages respectively.
To enable IR3883 in FCCM, the voltage at EN/FCCM pin should be no less than the FCCM start threshold. The
EN/FCCM pin can be connected directly to PVIN, or a resistor divider can be used. Following criterion should be
satisfied when selecting the resistor divider for FCCM.
7.2 Input Capacitor Selection
Without input capacitors, the pulse current of control FET is directly from the input supply power. Due to the
impedance on the cable, the pulse current can cause disturbance on the input voltage and potential EMI issues.
The input capacitors filter the pulse current of the control FET, resulting in almost constant current from the input
supply.
The input capacitors should be selected to tolerate the input pulse current, and to reduce the input voltage ripple.
The RMS value of the input ripple current can be expressed by:
Where:
IRMS is the RMS value of the input capacitor current.
Io is the output current. D is the Duty Cycle
To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as follows.
36.1
21
2
(min)
≥
+
×
ENEN
EN
in
RR
R
PV
3.2
21
2
(max)
≤
+
×
ENEN
EN
in
RR
R
PV
6.2
21
2
(min)
≥
+
×
ENEN
EN
in
RR
R
PV
)1(
0
DDII
RMS
−××=
in
V
V
D
0
=
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 21 Rev 3.0 08/20/2016
Where ∆Vin(max) is the maximum allowable peak-to-peak input ripple voltage.
Ceramic capacitors are recommended as input capacitors due to low ESR, ESL and high RMS current capability.
In addition, a bulk capacitor is recommended if the input supply is not located close to the voltage regulator.
7.3 Inductor Selection
The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor
value causes large ripple current, resulting in the smaller size, faster response to a load transient but lower
efficiency and high output noise. Generally, the desired peak-to-peak ripple current in the inductor (∆i) is found
between 20% and 50% of the output current.
The saturation current of the inductor is desired to be higher than the over current limit. An inductor with soft-
saturation characteristic is recommended. For some core material, inductor saturation current may decrease as
the increase of temperature. So it is important to check the inductor saturation current at the high temperature
For the buck converter, the inductor value for the desired operating ripple current can be determined using the
following relation:
Where:
PVinmax = Maximum input voltage
Vo = Output Voltage
∆iLmax = Maximum Inductor Peak-to-Peak Ripple Current
FS= Switching Frequency
Tonmin = On-time when PVin = PVinmax
Dmin = Minimum Duty Cycle
7.4 Output Capacitor Selection
To ensure the loop stability, a minimum of 22uF output capacitor is suggested. The voltage ripple and transient
requirements determine the output capacitor selection. Please refer to Table 7-1.
The following formula calculates the peak-to-peak output voltage ripple due to the inductor ripple current charging
the output capacitor.
Therefore,
Where:
∆VOmin = Minimum allowable peak-peak output ripple voltage.
(max)
0
(min)
)1(
insw
in
Vf
DDI
CΔ×
−
×
×
>
min
max
max
on
L
oin
T
i
LVPV
Δ
×=−
s
on
F
D
T
min
min
=
;
sL
oin
Fi
D
VPVL×Δ
×−=
max
min
max
)(
max
0
min
in
V
V
D=
;
sw
L
fC
i
V××
Δ
=Δ
0
max
0
8
sw
L
fV
i
C×Δ×
Δ
>
min0
max
0
8
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 22 Rev 3.0 08/20/2016
∆ILmax = Maximum Inductor Ripple Current
The ESR and ESL of the output capacitors, as well as the parasitic resistance or inductance due to PCB layout,
can also contribute to the output voltage ripple. For most applications, it is suggested to use Multi-Layer Ceramic
Capacitor (MLCC) as output capacitors for their low ESR, ESL and small size.
To meet the transient response requirements, the output capacitors should also meet the following criterion.
Where ∆VOL_max is the max allowable Vo deviation during the load transient. ∆Iomax is the maximum step load
current. Please note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM
latency is not considered in the calculation shown above. Extra capacitance is usually needed to meet the transient
requirements.
7.5 Output Voltage Programming
Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal
reference voltage of 0.5V. The divider ratio is set to provide 0.5V at the FB pin when the output is at its desired
value. The calculation of the feedback resistor divider is shown below.
Where RFB1 and RFB2 are the top and bottom feedback resistors. RFB2 is recommended not to be greater than
20kΩ, in order to avoid the interference with the internal circuitry.
7.6 Feedforward Capacitor
A small MLCC capacitor, Cff, can be placed in parallel with the top feedback resistor, RFB1, to improve the transient
response. As a general rule of thumb, for a fixed RFB1 of 16.5kΩ, 100pF can be used for Vo less than 1.8V, and
220pF for Vo equal to/higher than 1.8V. Please refer to Table 7-1.
7.7 Bootstrap Capacitor Selection
For most applications, a 0.1uF ceramic capacitor is recommended for bootstrap capacitor placed between SW
node and Boot Pin.
7.8 VCC Bypass Capacitor
A 2.2uF ceramic capacitor must be placed between VCC and GND.
0max_0
2
max0
0
2VV
IL
C
L
×Δ×
Δ×
>
)1(
2
1
0
FB
FB
ref
R
R
VV +×=
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 23 Rev 3.0 08/20/2016
7.9 Recommended Configurations
Table 7-1 lists recommended configurations for a few commonly used output voltages.
Note:
1. The output capacitors are selected to meet ±1% output ripple voltage and ±3% undershoot/overshoot at 30%
of max load transient with 2.5A/µs slew rate. More output capacitors might be needed for more stringent
transient load requirements. Please note that 22uF is rated capacitance at 0V DC bias voltage.
2. RFB1 and RFB2 are the top and bottom feedback resistor respectively, shown as R6 and R7 respectively in
Figure 7-1.
3. The selection of L is based on 20% - 50% of max output current.
Table 7-1 Recommended Configurations
Vin (V) Iomax (A) Vo (V) RFB1(k)
Note 2.
RFB2(k)
Note 2.
L (H)
Note 3.
Cff (pF) Minimum Co (F)
Note 1.
53
0.9 15.0 18.7
1.0 100
2 x 22μF
1.0 16.5 16.5
1.2 16.5 11.8
1.8 16.5 6.34
1.5 220
2.5 16.5 4.12
12 3
0.9 15.0 18.7
1.0 100
2 x 22μF
1.0 16.5 16.5
1.2 16.5 11.8
1.8 16.5 6.34 1.5
220
2.5 16.5 4.12
2.2
3.3 16.5 2.94
5.0 16.0 1.78 3.3
12 1.5
0.9 15.0 18.7
2.2 100
2 x 22μF
1.0 16.5 16.5
1.2 16.5 11.8
1.8 16.5 6.34 3.3
220
2.5 16.5 4.12
4.7
3.3 16.5 2.94
5.0 16.0 1.78
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 24 Rev 3.0 08/20/2016
Table 7-2 List of Inductors
L (H)Part Number (P/N) Manufacturer Isat (A) DCR (m)Size (L x W x H) (mm)
1.0 XEL4030 - 102 Coilcraft 9.0 8.89 4 x 4 x 3.1
1.0 XFL5030 - 102 Coilcraft 6.5 4.2 5.28 x 5.48 x 3.1
1.0 CMLE053T - 1R0 Delta 11 8.4 4.85 x 4.7 x 2.8
1.0 SPM5030 - 1R0 TDK 8.5 11.44 5.2 x 5.0 x 3.0
1.5 XEL4030 - 152 Coilcraft 8.5 15.1 4 x 4 x 3.1
1.5 CMLB051H - 1R5 Delta 9 23 5.4 x 5.75 x 1.8
2.2 XAL5030 - 222 Coilcraft 9.2 13.2 5.28 x 5.48 x 3.1
2.2 CMLE053T - 2R2 Delta 8.2 21 4.9 x 5.2 x 3.0
3.3 XAL5030 - 332 Coilcraft 8.7 21.2 5.28 x 5.48 x 3.1
3.3 CMLE053T - 3R3 Delta 7.3 29.7 4.9 x 5.2 x 3.0
4.7 XAL5030 - 472 Coilcraft 6. 36 5.28 x 5.48 x 3.1
4.7 CMLE063T - 4R7 Delta 8 23.6 6.8 x 7.3 x 3.0
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 25 Rev 3.0 08/20/2016
7.10 Application Diagram and Bill of Materials
Figure 7-1 Application Circuit for a 12V to 3.3V, 3A Point of Load Converter
Table 7-3 Suggested Bill of Materials for the Application Circuit
Qua
ntity
Part Ref. Value Description Part Number Manufactur
er
1C12.2μF CAP CER 2.2UF 16V 10% X5R 0402 GRM155R61C225KE44D Murata
1C2 1μF CAP CER 1UF 16V 10% X5R 0402 GRM155R61C105KE01D Murata
2 C4, C5 0.1μF CAP CER 0.1UF 16V 10% X7R 0402 GRM155R71C104KA88D Murata
2 C6, C7 22μF CAP CER 22UF 16V 20% X5R 0805 C2012X5R1C226M125AC TDK
2 C10, C11 22μF CAP CER 22uF 6.3V X5R 20% 0805 C2012X5R0J226M TDK
1 C9 220pF CAP CER 220PF 50V 10% X7R 0402 GCM155R71H221KA37D Murata
1L12.2μH 5.28x5.48x3mm, DCR=13.2mÙ,
Isat=7.2A
XAL5030-222 Coilcraft
2 R2, R5 49.9k RES SMD 49.9K OHM 1% 1/10W 0402 ERJ-2RKF4992X Panasonic
1R3
16.5k
(FCCM)
RES SMD 16.5K OHM 1% 1/10W 0402 ERJ-2RKF1652X Panasonic
8.06k
(DEM)
RES SMD 8.06K OHM 1% 1/10W 0402 ERJ-2RKF8061X Panasonic
1 R4 0 RES SMD 0.0 OHM JUMPER 1/10W ERJ-2GE0R00X Panasonic
1 R7 2.94k RES SMD 2.94K OHM 1% 1/10W 0402 ERJ-2RKF2941X Panasonic
2 R6, R10 16.5k RES SMD 16.5K OHM 1% 1/10W 0402 ERJ-2RKF1652X Panasonic
1 U1 IR3883 3mmx3mm 3A POL Regulator IR3883MTRPBF Infineon
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 26 Rev 3.0 08/20/2016
7.11 Typical Operating Waveforms
PVin = Vin = 12.0V, Vo=3.3V, Io=0A - 3A, No airflow, room temperature
Figure 7-2 Start up at 3A Load, Enable = En/FCCM (Ch1:PVin, Ch2:Vo, Ch3:PGood, Ch4:VCC)
Figure 7-3 Start up at 0A Load, Enable = En/DEM (Ch1:PVin, Ch2:Vo, Ch3:PGood, Ch4:VCC)
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 27 Rev 3.0 08/20/2016
Figure 7-4 Start up at 0A load with a pre-bias voltage of 2.64V, FCCM (Ch1:SW, Ch2:Vo, Ch3:PGood, Ch4:En)
Figure 7-5 Start up at 0A load with a pre-bias voltage of 2.64V, DEM (Ch1:SW, Ch2:Vo, Ch3:PGood, Ch4:En)
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 28 Rev 3.0 08/20/2016
Figure 7-6 FCCM, SW node, 3A
Figure 7-7 Diode Emulation Mode, SW node, 0.3A
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 29 Rev 3.0 08/20/2016
Figure 7-8 FCCM, Vo ripple, 3A load, Vout
Figure 7-9 DEM, Vo ripple, 0.3A load
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 30 Rev 3.0 08/20/2016
Figure 7-10 Short circuit (Hiccup) recover (FCCM) (CH1=SW, CH2=Vout, CH3=PGood, CH4=Io)
Figure 7-11 Enter OCP Hiccup mode (FCCM) (CH1=SW, CH2=Vout, CH3=PGood, CH4=Io)
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 31 Rev 3.0 08/20/2016
Figure 7-12 Transient Response, 0A to 3.0A step, FCCM (CH2=Vout, CH4= Iout, Undershoot: -43mV,
Overshoot: 49mV)
Figure 7-13 Transient Response, 0.03A to 3.0A step, DEM (CH2=Vout, CH4= Iout, Undershoot: -31mV,
Overshoot: 61mV)
IR3883
IPOL Synchronous Buck Regulator
Application Information
Datasheet 32 Rev 3.0 08/20/2016
7.12 IR3883 Thermal Image
Figure 7-14 IR3883 Thermal Image
Thermal Image of the board at Vin = 12V, Vo = 3.3V, Io = 3A, no
airflow; IR3883 =55ºC, L= 46ºC, Amb = 25ºC
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 33 Rev 3.0 08/20/2016
8 Layout Recommendations
The pinout of IR3883 makes it easy to route the PCB layout. General PCB design guidelines should be followed
to achieve the best performance.
• Bypass capacitors, including input/output capacitors and Vcc bypass capacitor, should be placed as close as
possible to the corresponding pins.
• SW node area should be minimized and be limited to the top layer only
• Output voltage should be sensed with a separated trace directly from the output capacitor. The sensing trace
should be away from the inductor and SW node to avoid the interference of switching noises.
• Analog ground and power ground are connected through a single point connection.
• The feedback resistor divider should be connected to the analog ground.
• The exposed pad can be connected to power ground plane through via holes to aid thermal dissipation.
• Wide copper polygons are desired for input and output power connections in favor of power losses reduction
and thermal dissipation. Sufficient via holes should be used to connect the power traces between different
layers.
Figure 8-1 IRDC3883 Demo Board Layout – Top Layer
PVin PGND Vo
PGND
Single point connection
between AGND and PGND
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 34 Rev 3.0 08/20/2016
Figure 8-2 IRDC3883 Demo Board Layer – Signal Layer 1
Figure 8-3 IRDC3883 Demo Board Layout – Signal Layer 2
PGND
To aid thermal dissipation ,
exposed pad is connected to
PGND through 4 via holes
Feedback trace is away
from L and SW node .
PGND
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 35 Rev 3.0 08/20/2016
Figure 8-4 IRDC3883 Demo Board Layer – Bottom Layer
8.1 PCB Metal and Component Placement
Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown
in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-
centering behavior is highly dependent on solders and processes and experiments should be run to confirm the
limits of self-centering on specific processes.
For further information, please refer to SupIRBuck® Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note.” (AN1132)
PVin
PGND
Vo
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 36 Rev 3.0 08/20/2016
Figure 8-5 PCB metal pad sizing and spacing (all dimensions in mm)
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 37 Rev 3.0 08/20/2016
8.2 Stencil Design
Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010”). Stencils thinner than 0.100mm
are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high
reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008”), with
suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved
using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005”). The
reduction should be adjusted for stencils of other thicknesses.
Figure 8-6 Stencil pad spacing (all dimensions in mm)
8.3 Marking Information
Figure 8-7 Marking information
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 38 Rev 3.0 08/20/2016
8.4 Package Information
Figure 8-8 Package Dimensions
IR3883
IPOL Synchronous Buck Regulator
Layout Recommendations
Datasheet 39 Rev 3.0 08/20/2016
Figure 8-9 Package Dimensions Table
8.5 Environmental Qualifications†
† Qualification standards can be found at Infineon web site: www.infineon.com
Table 8-1 Environmental Qualifications†
Qualification Level Industrial
Moisture Sensitivity Level PQFN 3 mm x 3 mm JEDEC Level 1 @ 260°C
ESD
Human Body Model
(JESD22-A114F)
Class 2
≥ 2000V to < 4000V
Charged Device Model
(JESD22-C101F)
Class C3
≥1000V
RoHS Compliant Yes
IR3883
IPOL Synchronous Buck Regulator
Datasheet 40 Rev 3.0 08/20/2016
Revision History:
Revision / Date Subjects (major changes since previous revision)
IIR3883 Rev 3.0, 08/20/2016
3.0 08-20-16 • 1st release to web (production version)
• Changed OCP limits based on characterization data (compared with prelim datasheet)
• Changed CDM from JESD22-C101D Class 3 (<1000V) to JESD22-C101F Class C3
(≥1000V)
• Added 5V efficiency curves & OCP vs Vcc curve
IR3883
IPOL Synchronous Buck Regulator
Datasheet 41 Rev 3.0 08/20/2016
Edition 08/20/2016
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com)
Published by Infineon Technologies AG
www.infineon.com