IDT71P74804S250BQ8 - Integrated Device Technology

SEPTEMBER 2008

DSC-6111/02

1

18Mb Pipelined

QDR™II SRAM

Burst of 4

IDT71P74804

IDT71P74604

Description

The IDT QDRIITM Burst of four SRAMs are high-speed synchro-

nous memories with independent, double-data-rate (DDR), read and

write data ports. This scheme allows simultaneous read and write

access for the maximum device throughput, with four data items passed

with each read or write. Four data word transfers occur per clock

cycle, providing quad-data-rate (QDR) performance. Comparing this

with standard SRAM common I/O (CIO), single data rate (SDR) de-

vices, a four to one increase in data access is achieved at equivalent

clock speeds. Considering that QDRII allows clock speeds in excess of

standard SRAM devices, the throughput can be increased well beyond

four to one in most applications.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

The QDRII has a single SDR address bus with read addresses

and write addresses multiplexed. The read and write addresses inter-

leave with each occurring a maximum of every other cycle. In the event

that no operation takes place on a cycle, the subsequest cycle may

begin with either a read or write. During write operations, the writing of

individual bytes may be blocked through the use of byte write control

signals.

Functional Block Diagram

DATA

REG

ADD

REG

CTRL

LOGIC

CLK

GEN

(Note1)

D

(Note2)

SA

R

W

(Note3)

BWx

K

C

SELECT OUTPUT CONTROL

WRITE/READDECODE

SENSEAMPS

OUTPUTREG

OUTPUTSELECT

WRITE DRIVER

(Note2)

CQ

Q

(Note1)

18M

MEMORY

ARRAY

CQ

OUTPUTSELECT

6111 drw16

(Note 4)(Note 4)

Features

•18Mb Density (1Mx18, 512kx36)

•Separate, Independent Read and Write Data Ports

- Supports concurrent transactions

•Dual Echo Clock Output

•4-Word Burst on all SRAM accesses

•Multiplexed Address Bus One Read or One Write request per

clock cycle

•DDR (Double Data Rate) Data Bus

- Four word burst data per two clock cycles on each port

- Four word transfers per clock cycle

•Depth expansion through Control Logic

•HSTL (1.5V) inputs that can be scaled to receive signals from

1.4V to 1.9V .

•Scalable output drivers

- Can drive HSTL, 1.8V TTL or any voltage level from 1.4V

to 1.9V .

- Output Impedance adjustable from 35Ω to 70Ω

•1.8V Core V oltage (VDD)

•165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

•JT AG Interface

Notes

1) Represents 18 data signal lines for x18 and 36 signal lines for x36.

2) Represents 18 address signal lines for x18 and 17 address signal lines for x36.

3) Represents 2 signal lines for x18 and 4 signal lines for x36.

4) Represents 36 signal lines for x18 and 72 signal lines for x36.

6.422

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

The QDRII has echo clocks, which provide the user with a clock

that is precisely timed to the data output, and tuned with matching imped-

ance and signal quality. The user can use the echo clock for down-

stream clocking of the data. Echo clocks eliminate the need for the user

to produce alternate clocks with precise timing, positioning, and signal

qualities to guarantee data capture. Since the echo clocks are gener-

ated by the same source that drives the data output, the relationship to

the data is not significantly affected by voltage, temperature and process,

as would be the case if the clock were generated by an outside source.

All interfaces of the QDRII SRAM are HSTL, allowing speeds be-

yond SRAM devices that use any form of TTL interface. The interface

can be scaled to higher voltages (up to 1.9V) to interface with 1.8V

systems if necessary. The device has a VDDQ and a separate Vref,

allowing the user to designate the interface operational voltage, inde-

pendent of the device core voltage of 1.8V VDD. The output impedance

control allows the user to adjust the drive strength to adapt to a wide

range of loads and transmission lines.

The device is capable of sustaining full bandwidth on both the input

and output ports simultaneously. All data is in four word bursts, with

addressing capability to the burst level.

Clocking

The QDRII SRAM has two sets of input clocks, namely the K, K

clocks and the C, C clocks. In addition, the QDRII has an output “echo”

clock, CQ, CQ.

The K and K clocks are the primary device input clocks. The K clock

is, used to clock in the control signals (R, W and BWx), the address, first

and third words of the data burst during a write operation. The K clock

is used to clock in the control signals (BWx) and the second and fourth

words of the data burst during a write operation. The K and K clocks are

also used internally by the SRAM. In the event that the user disables the

C and C clocks, the K and K clocks will be used to clock the data out of

the output register and generate the echo clocks.

The C and C clocks may be used to clock the data out of the output

register during read operations and to generate the echo clocks. C and

C must be presented to the SRAM within the timing tolerances. The

output data from the QDRII will be closely aligned to the C and C input,

through the use of an internal DLL. When C is presented to the QDRII

SRAM, the DLL will have already internally clocked the first data word to

arrive at the device output simultaneously with the arrival of the C clock.

The C and second data word of the burst will also correspond. The third

and fourth data words will follow on the next clock cycle of C and C,

respectively.

Single Clock Mode

The QDRII SRAM may be operated with a single clock pair . C and

C may be disabled by tying both signals high, forcing the outputs and

echo clocks to be controlled instead by the K and K clocks.

DLL Operation

The DLL in the output structure of the QDRII SRAM can be used to

closely align the incoming clocks C and C with the output of the data,

generating very tight tolerances between the two. The user may disable

the DLL by holding Doff low . With the DLL off, the C and C (or K and K

if C and C are not used) will directly clock the output register of the

SRAM. With the DLL off, there will be a propagation delay from the time

the clock enters the device until the data appears at the output.

Echo Clock

The echo clocks, CQ and CQ, are generated by the C and C clocks

(or K, K if C, C are disabled). The rising edge of C generates the rising

edge of CQ, and the falling edge of CQ. The rising edge of C generates

the rising edge of CQ and the falling edge of CQ. This scheme improves

the correlation of the rising and falling edges of the echo clock and will

improve the duty cycle of the individual signals.

The echo clock is very closely aligned with the data, guaranteeing

that the echo clock will remain closely correlated with the data, within the

tolerances designated.

Read and Write Operations

QDRII devices internally store the 4 words of the burst as a single,

wide word and will retain their order in the burst. There is no ability to

address to the single word level or reverse the burst order; however, the

byte write signals can be used to prevent writing any individual bytes, or

combined to prevent writing one word of the burst.

Read and write operations may be interleaved with each occurring

on every other clock cycle. In the event that two reads or two writes are

requested on adjacent clock cycles, the operation in progress will com-

plete and the second request will be ignored. In the event that both a

read and write are requested simultaneously , the read operation will win

and the write operation will be ignored.

Read operations are initiated by holding the read port select (R) low ,

and presenting the read address to the address port during the rising

edge of K which will latch the address. The data will then be read and will

appear at the device output at the designated time in correspondence

with the C and C clocks.

Write operations are initiated by holding the write port select (W) low

and presenting the designated write address to the address bus. The

QDRII SRAM will receive the address on the rising edge of clock K. On

the following rising edge of K clock, the QDRII SRAM will receive the first

data item of the four word burst on the data bus. Along with the data, the

byte write (BWx) inputs will be accepted, indicating which bytes of the

data inputs should be written to the SRAM. On the following rising edge

of K, the next word of the write burst and BWx will be accepted. The

subsequent K and K rising edges will receive the last two words of the

four word burst, with their BWx enables.

Output Enables

The QDRII SRAM automatically enables and disables the Q[X:0]

outputs. When a valid read is in progress, and data is present at the

output, the output will be enabled. If no valid data is present at the output

(read not active), the output will be disabled (high impedance). The

echo clocks will remain valid at all times and cannot be disabled or turned

off. During power-up the Q outputs will come up in a high impedance

state.

Programmable Impedance

An external resistor , RQ, must be connected between the ZQ pin on

the SRAM and Vss to allow the SRAM to adjust its output drive imped-

ance. The value of RQ must be 5X the value of the intended drive

impedance of the SRAM. The allowable range of RQ to guarantee

impedance matching with a tolerance of +/- 10% is between 175 ohms

and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted

every 1024 clock cycles to correct for drifts in supply voltage and tem-

perature. If the user wishes to drive the output impedance of the SRAM

to it’s lowest value, the ZQ pin may be tied to VDDQ.

6.42

3

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Sym bol Pi n Function Descrip tion

D [ X: 0] Inpu t Sy n c h ron ous Data input sig nals, sampled on the rising edge of K and K clocks d uring valid write operatio ns

1M x 18 -- D[17: 0]

512K x 36 -- D[ 35: 0]

BW

0

, BW

1

BW

2

, BW

3

Inpu t Sy n c h ron ous

Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising ed ge of K clocks

during write operations. Used to select which byte is written into the device during the current portion o f the write operations.

Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the d ata. Deselecting a Byte Write

Sele ct will cause the corresponding byte of d ata to be ignored and not written in to the device.

1M x 18 -- BW

0

co ntro ls D[ 8:0] and BW

1

co ntro ls D[ 17:9]

512K x 36 -- BW

0

co ntro ls D[ 8: 0], BW

1

co ntrols D[17:9], BW

2

co ntro ls D[26: 18] and BW

3

c ontro l s D[35 : 27]

S A Inpu t Sy n c h ron ous Address inputs are sampled on the rising edg e of K clo ck during active read or write operations. These address inputs are

multiplexed so a read and write can be initiated on alternate clock cycles. These inputs are ignored when the appro priate port is

deselected.

Q[X:0] Output Sy nc hrono us Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge

of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is

deselected, Q[X:0] are automatically three-stated.

WInpu t Sy n c h ron ous

Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operatio

n

is initiated. Deasserting will deselect the Write port, causing D[X:0] to be ignored. If a write operation has successfully been

initiated, it will c ontinue to co mpletion, ignoring the W on the following clock cycle. This allows the user to continuously hold W lo w

while bursting data into the SRAM.

RInpu t Sy n c h ron ous

Read Control Log ic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read op eration is

initiated. Deasserting will cause the Read port to be deselected. When deselected, the pend ing access is allowed to

complete and the o utput drivers are automatically three-stated following the next rising edge of the C clock. Each read access

co nsists o f a burst of fo ur se quential transfer. If a re ad ope ration has succe ssfully b een ini tiate d, it will co ntinue to com pletion,

ig no ri ng the R o n the fo llowing cloc k cycle. This allows the user to continuously hold R l o w whi le b u rs tin g d ata from the S RA M .

CInput Clock

P os i tiv e Ou tp ut Cl o c k Inp ut. C is us e d i n c o njunc ti o n with C to c loc k o ut the Re a d d ata fr o m th e de v ice . C and C can be used

together to d eskew the flight times of various devices on the board back to the controlle r. See application example for further

details.

CInput Clock Ne ga ti ve O utpu t C l oc k In put. C i s use d in c o njun c tio n with C to c l o c k o ut th e Re ad d ata fro m the d e v ice . C and C can be used

together to d eskew the flight times of various devices on the board back to the controlle r. See application example for further

details.

K Inp ut Clo c k Positive Inp ut Clock Input. The rising edge of K is used to capture synchrono us inputs to the device and to d rive out data

through Q[X:0] when in single clock mode. All accesses are initiated on the rising e dge of K.

KInput Clock Ne g ati ve Inp ut Cl o c k Input. K is used to capture synchronous inputs being presented to the device and to drive out data

thro ug h Q[ X:0] whe n in si ngle cl o ck mod e.

CQ, CQ Outp ut Clock Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outp uts and

can be used as a data valid ind ication. These signals are free running and do not stop when the output data is three-stated .

ZQ Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[X:0]

outp ut imp edance is set to 0.2 x RQ, where RQ is a resistor connected betwe en ZQ and gro und. Alternately, this pin can be

connected directly to V

DDQ,

whic h enab le s the minimum i mp ed anc e mo d e . This pin c anno t b e co nne c ted d ire c tly to GND or left

unconnected.

6111 tbl 02 a

Pin Definitions

6.424

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Symbol Pin Function Description

Doff Input

DLL Turn Off. When low this input will turn off the DLL insid e the d evice . The AC timings with the

DLL turned off will be diffe rent from those listed in this data sheet. There will b e an incre as ed

propagation delay from the incidence of C and C to Q, or K and K to Q as c o nfi g ure d . The

p ropag ation delay is not a te sted parame ter, but will be similar to the p rop agatio n d elay o f othe r

SRAM devices in this speed grade.

TDO Output TDO p in fo r JTAG.

TCK Inp ut TCK p in for J TAG.

TDI Input TDI pin fo r JTAG. An inte rnal re sisto r will pull TDI to V

DD

when the pin is unconnected.

TMS Input TMS p in for JTAG. An inte rnal resisto r will pull TMS to V

DD

when the pin is unconnected.

NC No Connect No connects inside the package. Can be tied to any voltage level

V

REF

Input

Reference Refe renc e Vo l tage i nput. S tatic i nput us ed to s e t the referenc e l e v e l for HS TL i np uts and Outp uts

as we ll as AC me asure me nt po ints.

V

DD

Power

Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.

V

SS

Ground Ground for the device. Should be connected to ground of the system.

V

DDQ

Power

Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for

HSTL or scaled to the desired output voltage.

6111 tbl 02b

Pin Definitions continued

6.42

5

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Pin Configuration IDT71P74804 (1M x 18)

1234567891011

ACQ V

SS/

SA

(3)

NC/

SA

(1)

WBW

1

KNC RSA V

SS/

SA

(2)

CQ

BNC Q

9

D

9

SA NC K BW

0

SA NC NC Q

8

CNC NC D

10

V

SS

SA NC SA V

SS

NC Q

7

D

8

DNC D

11

Q

10

V

SS

V

SS

V

SS

V

SS

V

SS

NC NC D

7

ENC NC Q

11

V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC D

6

Q

6

FNC Q

12

D

12

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC Q

5

GNC D

13

Q

13

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC D

5

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC D

14

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC Q

4

D

4

KNC NC Q

14

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC D

3

Q

3

LNC Q

15

D

15

V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC Q

2

MNC NC D

16

V

SS

V

SS

V

SS

V

SS

V

SS

NC Q

1

D

2

NNC D

17

Q

16

V

SS

SA SA SA V

SS

NC NC D

1

PNC NC Q

17

SASA CSASANCD

0

Q

0

RTDO TCK SA SA SA CSA SA SA TMS TDI

6111 tbl 12b

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A3 is reserved for the 36Mb expansion address.

2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P748 04) devices.

3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.

6.426

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Pin Configuration IDT71P74604 (512K x 36)

165-ball FBGA Pinout

TOP VIEW

1234567891011

ACQ V

SS

/

SA

(4)

NC/

SA

(2)

WBW

2

KBW

1

RNC/

SA

(1)

V

SS

SA

(3)

CQ

BQ

27

Q

18

D

18

SA BW

3

KBW

0

SA D

17

Q

17

Q

8

CD

27

Q

28

D

19

V

SS

SA NC SA V

SS

D

16

Q

7

D

8

DD

28

D

20

Q

19

V

SS

V

SS

V

SS

V

SS

V

SS

Q

16

D

15

D

7

EQ

29

D

29

Q

20

V

DDQ

V

SS

V

SS

V

SS

V

DDQ

Q

15

D

6

Q

6

FQ

30

Q

21

D

21

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

D

14

Q

14

Q

5

GD

30

D

22

Q

22

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

Q

13

D

13

D

5

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JD

31

Q

31

D

23

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

D

12

Q

4

D

4

KQ

32

D

32

Q

23

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

Q

12

D

3

Q

3

LQ

33

Q

24

D

24

V

DDQ

V

SS

V

SS

V

SS

V

DDQ

D

11

Q

11

Q

2

MD

33

Q

34

D

25

V

SS

V

SS

V

SS

V

SS

V

SS

D

10

Q

1

D

2

ND

34

D

26

Q

25

V

SS

SA SA SA V

SS

Q

10

D

9

D

1

PQ

35

D

35

Q

26

SA SA C SA SA Q

9

D

0

Q

0

RTDO TCK SA SA SA CSA SA SA TMS TDI

6111 tbl 1 2 c

NOTES:

1. A9 is reserved for the 36Mb expansion address.

2. A3 is reserved for the 72Mb expansion address.

3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.

4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.

6.42

7

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Absolute Maximum Ratings(1) (2) Capacitance (T A = +25°C, f = 1.0MHz)(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. VDDQ must not exceed VDD during normal operation.

NOTE:

1. T ested at characterization and retested after any design or process

change that may affect these parameters.

Symbol Parameter Conditions Max. Unit

C

IN

Input Capacitance V

DD

= 1.8V

V

DDQ

= 1.5V

5pF

C

CLK

Clock Input Capacitance 6 pF

C

O

Output Capacitance 7 pF

6111 tbl 06

Symbol Rating Value Unit

V

TERM

Supply Voltage on V

DD

with

Re s p e ct to GND –0.5 to +2.9 V

V

TERM

Supply Voltage on V

DDQ

with

Re s p e ct to GND –0.5 to V

DD

+0.3 V

V

TERM

Vo lta g e o n Inp ut te rminals with

re s p e ct to GND –0.5 to V

DD

+0.3 V

V

TERM

Voltage on Output and I/O

te rminal s wi th re sp e c t to GND. –0.5 to V

DDQ

+0.3 V

T

BIAS

Temperature Under Bias –55 to +125 °C

T

STG

Storage Temperature –65 to +150 °C

I

OUT

Continuous Current into Outputs + 20 mA

6111 tbl 05

Recommended DC Operating and

Temperture Conditions

Symbol Parameter Min. Typ. Max. Unit

V

DD

Power Supply

Voltage 1.7 1.8 1.9 V

V

DDQ

I/O Supply Voltage 1.4 1.5 1.9 V

V

SS

Ground 0 0 0 V

V

REF

Inp ut Re fe re nc e

Voltage 0.68 V

DDQ

/2 0.95 V

T

A

Ambient

Temperature

(1)

025+70

oc

6111 tbl 04

NOTES:

1) All byte write (BWx) signals are sampled on

the rising edge of K and again on K. The data that is present on the

data bus in the designated byte will be latched into the input if

the corresponding BWxis held low . The rising edge of K

will sample the first and third bytes of the four word burst and

the rising edge of K will sample the second and fourth bytes

of the four word burst.

2) The availability of the BWx on designated devices is de

scribed in the pin description table.

3) The QDRII Burst of four SRAM has data forwarding. A read request

that is initiated on the cycle following a write request to the same

address will produce the newly written data in response to the read

request.

Signal BW

0

BW

1

BW

2

BW

3

Write Byte 0 LXXX

Write By te 1 X L X X

Write By te 2 X X L X

Write By te 3 X X X L

6111 tb l 09

Write Descriptions(1,2) NOTE:

1. During production testing, the case temperarure equals the ambient

temperature.

6.428

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Application Example

6.42

9

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

DC Electrical Characteristics Over the Operating T emperature and

Supply V oltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)

P arameter S ym bol Test Condi ti ons Mi n Max Uni t Note

Input Leakag e Curre nt I

IL

V

DD

= Max V

IN

= V

SS

to V

DDQ

-2 +2 µA

Outp ut Le ak ag e Curre nt I

OL

Outp ut Disabled -2 +2 µA

Operating Current

(x36): DDR I

DD

V

DD

= Max,

I

OUT

= 0mA (outputs open),

Cycle Time > t

KHKH

Min

250MH

Z

- 1100

mA 1200MHz - 950

167MHz - 850

Operating Current

(x18): DDR I

DD

V

DD

= Max,

I

OUT

= 0mA (outputs open),

Cycle Time > t

KHKH

Min

250MH

Z

- 850

mA 1200MHz - 750

167MHz - 650

S tand b y Curre nt: NOP I

SB1

Device De selec te d (in NOP state)

I

OUT

= 0mA (outputs open),

f=Max,

All Inputs <0. 2V or > V DD -0. 2V

250MH

Z

- 375

mA 2200MHz - 335

167MHz - 300

Outp ut Hig h Vo ltag e V

OH1

RQ = 250Ω, I

OH

= -15mA V

DDQ

/2-0.12 V

DDQ

/2+0.12 V 3,7

Outp ut Lo w Vo ltag e V

OL1

RQ = 250Ω, I

OL

= 15mA V

DDQ

/2-0.12 V

DDQ

/2+0.12 V 4,7

Outp ut Hig h Vo ltag e V

OH2

I

OH

= -0. 1mA V

DDQ

-0.2 V

DDQ

V5

Outp ut Lo w Vo ltag e V

OL2

I

OL

= 0.1mA V

SS

0.2 V 6

6 111 tbl 10c

NOTES:

1. Operating Current is measured at 100% bus utilization.

2. Standby Current is only after all pending read and write burst operations are completed.

3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This

parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This

parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an

impedance measurement point.

6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance

measurement point.

7. Programmable Impedance Mode.

6.4210

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Parameter Symbol Min Max Unit Notes

Input High Voltage, DC V

IH

(DC

)V

REF

+0.1 V

DDQ

+0.3 V 1,2

Inp u t Low Vo l tag e, DC V

IL

(DC)

-0.3 V

REF

-0.1 V 1,3

Input High Voltage, AC V

IH

(AC)

V

REF

+0.2 - V 4,5

Inp ut Lo w Voltage , AC V

IL

(AC)

-V

REF

-0.2 V 4,5

6111 tbl 10d

Input Electrical Characteristics Over the Operating T emperature and

Supply V oltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)

NOTES:

1. These are DC test criteria. DC design criteria is VREF + 50mV . The AC VIH/VIL levels are defined separately for measuring timing

parameters.

2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))

3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))

4. This conditon is for AC function test only , not for AC parameter test.

5. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)

b) Reach at least the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)

V

IL

V

DD

V

DD

+0.25

V

DD

+0.5

2

0

%

t

K

H

K

H

(

M

I

N

)

6111 drw 2

1

V

SS

V

IH

V

SS

-0.25V

V

SS

-0.5V

20% tKHKH (MIN)

6111 drw 2

2

Overshoot Timing Undershoot Timing

6.42

11

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

AC T est Load

Device

R

L

=50

Ω

Z

0

=50

Ω

V

DDQ

/2

Under

Test

V

REF

OUTPUT

6111 drw 04

ZQ R

Q

=250

Ω

DDQ

/2

V

AC T est Conditions

Parameter Symbol Value Unit

Co re P o we r S up p l y Vo l tag e V

DD

1.7-1.9 V

Output Power Supply Voltage V

DDQ

1.4-1.9 V

Input High Level V

IH

(V

DDQ

/2)+ 0.5 V

Input Lo w Le v e l V

IL

(V

DDQ

/2)- 0.5 V

In put R efer en ce Level VR E F V

DDQ

/2 V

Input Ris e/Fall Time TR/TF 0.3/0.3 ns

Outp ut Timing Re fe renc e Le ve l V

DDQ

/2 V

6 111 t b l 11 a

NOTE:

1. Parameters are tested with RQ=250Ω

Input Waveform

Output Waveform

6111 drw 08

V

DDQ

/2 V

DDQ

/2Test points

(V

DDQ

/2) + 0.5V

(V

DDQ

/2) - 0.5V

6111 drw 07

V

DDQ

/2 V

DDQ

/2Test points

6.4212

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V,TA = 0 T O 70°C)(3,7)

Symbol Parameter

250MHz 200MHz 167MHz

Unit Notes

Min. Max Min. Max Min. Max

Clock P arameters

t

KHKH

Clock Cycle Time (K,K,C,C) 4.00 8.40 5.00 8.40 6.00 8.40 ns

t

KC var

Clock Phase Jitter (K,K,C,C) - 0.20 - 0.20 - 0.20 ns 1,5

t

KHKL

Clock High Time (K,K,C,C) 1.60 - 2.00 - 2.40 - ns 8

t

KLKH

Clock LOW Time (K,K,C,C) 1.60 - 2.00 - 2.40 - ns 8

t

KHKH

Clock to clock (K →K,C→C) 1.80 - 2.20 - 2.70 - ns 9

t

KHKH

Clock to clock (K→K,C→C) 1.80 - 2.20 - 2.70 - ns 9

t

KHCH

Clock to data clock (K→C,K→C) 0.00 1.80 0.00 2.30 0.00 2.80 ns

t

KC lock

DLL lo ck time (K, C) 1024 - 1024 - 1024 - cycles 2

t

KC reset

K s tatic to DLL re se t 30 - 30 - 30 - ns

Output P arameters

t

CHQV

C,C HIGH to o utp ut valid - 0. 45 - 0.45 - 0. 50 ns 3

t

CHQX

C,C HIGH to o utp ut ho l d -0. 45 - -0. 45 - -0.50 - ns 3

t

CHCQV

C,C HIGH to echo clock valid - 0.45 - 0.45 - 0.50 ns 3

t

CHCQX

C,C HIGH to e c ho c lo c k ho ld -0. 45 - -0. 45 - -0. 50 - ns 3

t

CQHQV

CQ,CQ HIGH to o utput val id - 0.30 - 0.35 - 0. 40 ns

t

CQHQX

CQ,CQ HIGH to o utp ut ho ld -0. 30 - -0. 35 - -0.40 - ns

t

CHQZ

C HIGH to o utp ut Hi g h-Z - 0.45 - 0.45 - 0. 50 ns 3,4, 5

t

CHQX1

C HIGH to o utp ut Low-Z -0.45 - -0.45 - -0.50 - ns 3,4, 5

Set-Up Tim es

t

AVKH

Address valid to K,K rising edge 0.50 - 0.60 - 0.70 - ns 6

t

IVKH

R,W inputs valid to K,K rising ed ge 0.50 - 0.60 - 0.70 - ns

t

DVKH

Data-in and BWx valid to K, K ris ing

edge 0.35 - 0.40 - 0.50 - ns

Hol d Ti mes

t

KHAX

K,K rising edge to address hold 0.50 - 0.60 - 0.70 - ns 6

t

KHIX

K,K rising edge to R,W inp uts ho ld 0. 50 - 0.60 - 0. 70 - ns

t

KHDX

K, K rising edge to data-in and BWx

hold 0.35 - 0.40 - 0.50 - ns

6111 t bl 11

NOTES:

1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

3. If C,C are tied High, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention

because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter

(worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. This parameter is guaranteed by device characterization, but not production tested.

6. All address inputs must meet the specified setup and hold times for all latching clock edges.

7. During production testing, the case temperature equals T A.

8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).

9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).

6.42

13

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Timing Waveform of Combined Read and Write Cycles

K

123

R

SA

Q

tKHCH

tKHKL

tKHIX

tIVKH

tKHAXtAVKH

C

CQ

tCHQX

tCHQX1

tKLKH

tCHCQV

tCHCQX

W

D

tDVKH

4567

tKLKH tKHKH tKHKH

A2A1

A0 A3

tKHDX tKHDX

D10 D12

Qx3

tCHQV

tCHQV tCHQX

tCQHQV

tKHCH tKHKH tKHKHtKHKL

tCHCQX

tCHCQV

NOP Read A0 Write A1 Write A3Read A2 NOP

tKHIXtIVKH

D11 D13 D30 D32

D31 D33

Qx2

Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23

tCHQZ

NOP

6111 drw09

.

tCQHQX

6.4214

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

JTAG Bloc k Diagram JTAG Instr uction Coding

IR2 IR1 IR0 Instruction TDO Output Notes

0 0 0 EXTEST Bound ary Scan Reg ister

0 0 1 IDCODE Identification register 2

0 1 0 SAMPLE-Z Boundary Scan Reg ister 1

0 1 1 RESERVED Do No t Use 5

1 0 0 SAMPLE/PRELOAD Bound ary Scan registe r 4

1 0 1 RESERVED Do No t Use 5

1 1 0 RESE RVED Do No t Us e 5

1 1 1 BYPASS Byp ass Register 3

6111tbl 13

NOTES:

1. Places Qs in Hi-Z in order to sample all input data regardless of

other SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the

serial shift of the external TDI data.

3. Bypass register is initialized to Vss when BYP ASS instruction is

invoked. The Bypass Register also holds serially loaded TDI

when existing the Shift DR states.

4. SAMPLE instruction does not place output pins in Hi-Z.

5. This instruction is reserved for future use.

TAP Controller State Diagram

Test Logic Reset

Run Test Idle Select DR

Capture DR

Pause DR

Exit 2 DR

Update DR

Shift DR

Exit 1 DR

Select IR

Capture IR

Pause IR

Exit 2 IR

Update IR

Shift IR

Exit 1 IR

0

1

0

6111 drw 17

0

1

0

1

0

SRAM

CORE

BYPASS Reg.

Identification Reg.

Instruction Reg

.

Control Signal

s

TAP Controller

A,D

K,K

C,C

Q

CQ

TDI

TMS

TCK

TDO

6111 drw 18

S

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JT AG

This part contains an IEEE standard 1 149.1 Compatible Test Ac-

cess Port (T AP). The package pads are monitored by the Serial Scan

circuitry when in test mode. This is to support connectivity testing during

manufacturing and system diagnostics. In conformance with IEEE 1 149.1,

the SRAM contains a T AP controller , Instruction register, Bypass Regis-

ter and ID register . The T AP controller has a standard 16-state machine

that resets internally upon power-up; therefore, the TRST signal is not

required. It is possible to use this device without utilizing the TAP. To

disable the T AP controller without interfacing with normal operation of the

SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and

TDI are designed so an undriven input will produce a response identical

to the application of a logic 1, and may be left unconnected, but they may

also be tied to VDD through a resistor . TDO should be left unconnected.

6.42

15

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Part Instrustion

Register Bypass

Register ID

Register Boundry

Scan

512Kx 36 3 b i ts 1 b it 32 b i ts 107 bi ts

1M x18 3 b i ts 1 b i t 32 b its 107 bits

6111 tbl14

INSTRUCTION FIELD ALL DEVI CES DESCRIPTION PART NUMB ER

Re v i s ion Num b e r (31: 29) 0x 0 Rev is i o n Num b e r

Device ID (28:12) 0x0280

0x0281 512Kx36 QDRII BURST OF 4

1Mx18 71P74604S

71P74804S

IDT JE DE C ID CODE (11: 1) 0x 033 A l l o ws u n ique i denti fi c a ti on of SRA M

vendor.

ID Registe r Presence Indicator (0) 1 Indicates the presence of an ID register.

6 111 t bl 1 5

Scan Register Definition

Identification Register Definitions

6.4216

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Boundary Scan Exit Order

ORDER PI N ID

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

6111 tbl 16

ORDER PIN ID

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 1H

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 1D

6111 tbl 17

ORDER PIN ID

73 2C

74 3E

75 2D

76 2E

77 1E

78 2F

79 3F

80 1G

81 1F

82 3G

83 2G

84 1J

85 2J

86 3K

87 3J

88 2K

89 1K

90 2L

91 3L

92 1M

93 1L

94 3N

95 3M

96 1N

97 2M

98 3P

99 2N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

6111 tb l 18

6.42

17

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Parameter Symbol Min Typ Max Unit Note

Output Po we r Supp ly V

DDQ

1.4 - 1.9 V

Power Supp ly Voltage V

DD

1.7 1.8 1.9 V

Inp ut Hi g h Le v e l V

IH

1.3 - V

DD

+0.3 V

Inp ut Lo w Le v e l V

IL

-0.3 - 0.5 V

TCK Input Leakage Current I

IL

-5 - +5 µA

TMS, TDI Input Leakage Current I

IL

-15 - +15 µA

TDO Output Leak age Current I

OL

-5 - +5 µA

Output High Voltage (IOH = -1mA) V

OH

V

DDQ

- 0 .2 - V

DDQ

V

1

Outp ut Lo w Vo ltag e (IOL = 1m A) V

OL

V

SS

-0.2V

1

6111 tbl 19

Parameter Symbol Value Unit Note

Inp ut Hi g h Le v e l V IH 1.8 V

Inp ut Lo w Le ve l V IL 0V

Input Rise/Fall Time TR/TF 1.0/1.0 ns

Input and Outp ut Ti ming Re fe re nce Le ve l 0.9 V 1

6 111 t bl 20

JTAG DC Operating Conditions

NOTE:

1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with

the external resistor connected to ZQ.

JT AG AC T est Conditions

NOTE:

1. For SRAM outputs see AC test load on page 13.

JT AG Input T est Waveform

JT AG Output T est Waveform

JTAG AC T est Load

6111 drw 23

0.9 V 0.9 VTest points

1.8 V

0V

6111 drw 23a

0.9 V 0.9 VTest points

0.9 V

50Ω

TDO

Z

0

=50Ω

6111 drw 24

,

6.4218

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Parameter Symbol Min Max Unit Note

TC K C y cl e Ti m e t

CHCH

50 - ns

TCK High Pulse Width t

CHCL

20 - ns

TCK Lo w Pulse Width t

CLCH

20 - ns

TMS Input Setup Ti me t

MVCH

5-ns

TM S In p u t Hold Tim e t

CHMX

5-ns

TD I In p u t S e t up Time t

DVCH

5-ns

TD I In p u t Hold Tim e t

CHDX

5-ns

SRAM Inp ut Se tup Time t

SVCH

5-ns

SRAM Inp ut Ho ld Ti me t

CHSX

5-ns

Clo c k Lo w to Outp ut Valid t

CLQV

010ns

6111 tbl 21

JT AG AC Characteristics

JT AG Timing Diagram

6111 drw 19

TCK

TMS

TDI/

SRAM

Inputs

TDO

t

MVCH

t

DVCH

t

SVCH

t

CHCL

t

CHMX

t

CHDX

t

CHSX

t

CLCH

t

CLQV

S

RAM

O

utputs

t

CHCH

6.42

19

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Package Diagram Outline for 165-Ball Fine Pitch Grid Array

6.4220

IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Ordering Information

“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

CORPORA TE HEADQUARTERS for SALES: for T ech Support:

6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com

San Jose, CA 95138 408-284-8200 800-345-7015

fax: 408-284-2775

www.idt.com

IDT71P74804 (1M x 18 x -Bit) 71P74604 (512K x 36-Bit)

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

REVISION DATE PAGES DESCRIPTION

0 07/20/05 p. 1-22 Released Final datasheet

1 12/07/07 p. 1-22 Removed 71P4204 and 71P4104 speed grades.

2 09/23/08 p. 12 Change 250MHz and 200MHz max tKHKH from 6.30 and 7.88 to 8.40ns.

Revision History