Document No. U15836EJ4V0UD00 (4th edition)
Date Published November 2003 N CP(K)
Printed in Japan
µ
PD780101
µ
PD780101(A)
µ
PD780101(A1)
µ
PD780101(A2)
µ
PD780102
µ
PD780102(A)
µ
PD780102(A1)
µ
PD780102(A2)
µ
PD780103
µ
PD780103(A)
µ
PD780103(A1)
µ
PD780103(A2)
µ
PD78F0103
µ
PD78F0103(A)
µ
PD78F0103(A1)
78K0/KB1
8-Bit Single-Chip Microcontrollers
User’s Manual
c
User’s Manual U15836EJ4V0UD
2
[MEMO]
User’s Manual U15836EJ4V0UD 3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are tradema rks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U15836EJ4V0UD
4
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of June, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
User’s Manual U15836EJ4V0UD 5
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J03.4
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Succursale Française
• Filiale Italiana
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Tel: 02-66 75 41
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
User’s Manual U15836EJ4V0UD
6
INTRODUCTION
Readers This manual is intende d for user engineers who wish to understand the functions of the
78K0/KB1 and design and develop application systems and programs for these
devices.
The target products are as follows.
78K0/KB1:
µ
PD780101, 780102, 780103, 78F0103, 780101(A), 780102(A),
780103(A), 78F0103(A), 780101(A 1), 780102(A1), 780103(A1),
78F0103(A1), 780101(A2), 7801 02(A2), 780103(A2)
Purpose This manual is intended to giv e users an und erstanding of the functions described in the
Organization below.
Organization The 78K0/KB1 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
78K0/KB1
User’s Manual
(This Manual)
78K/0 Series
User’s Manual
Instructions
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
• CPU functions
• Instruction set
• Explanation of each instruction
User’s Manual U15836EJ4V0UD 7
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• When using this manual as the manual for (A) grade, (A1) grade, and (A2) grade
products:
→ Only the quality grade differs between standard products and (A) grade, (A1)
grade, and (A2) grade product s . Read the part number as follows.
•
µ
PD780101 →
µ
PD780101(A), 780101(A1), 780101(A2)
•
µ
PD780102 →
µ
PD780102(A), 780102(A1), 780102(A2)
•
µ
PD780103 →
µ
PD780103(A), 780103(A1), 780103(A2)
•
µ
PD78F0103 →
µ
PD78F0103(A), 78F0103(A1)
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark shows major
revised points.
• How to interpret the register format:
→ For a bit num b er encl osed in brackets, the bi t name is d efined as a r eserv ed wor d
in the assembler, and is already defined in t he header file named sfrbit.h in the C
compiler.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX C REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
Caution Examples in this manual employ the “standard” quality grade for
general electronics. When using examples in this manual for the
“special” quality grade, review the quality grade of each part and/or
circuit actually used.
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
...×××× or ××××B
Decimal
...××××
Hexadecimal
...××××H
User’s Manual U15836EJ4V0UD
8
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0/KB1 User’s Manual U15836E
78K/0 Series Instructions User’s Manual U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
Operation U14445E
Language U14446E
RA78K0 Assembler Package
Structured Assembly Language U11789E
Operation U14297E CC78K0 C Compiler
Language U14298E
Operation (WindowsTM Based) U15373E SM78K Series System Simulator Ver. 2.30 or Later
External Part User Open Interface
Specifications U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) U15185E
Fundamentals U11537E RX78K0 Real-Time OS
Installation U11536E
Project Manager Ver. 3.12 or Later (Windows Based) U14610E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
IE-78K0-NS In-Circuit Emulator U13731E
IE-78K0-NS-A In-Circuit Emulator U14889E
IE-78K0K1-ET In-Circuit Emulator To be prepared
IE-780148-NS-EM1 Emulation Board To be prepared
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP3 Flash Memory Programmer User’s Manual U13502E
PG-FP4 Flash Memory Programmer User’s Manual U15260E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U15836EJ4V0UD 9
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U15836EJ4V0UD
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CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................16
1.1 Features ...................................................................................................................................... 16
1.2 Applications................................................................................................................................ 17
1.3 Ordering Information .................................................................................................................18
1.4 Pin Configuration (Top View).................................................................................................... 20
1.5 K1 Family Lineup........................................................................................................................ 21
1.5.1 78K0/Kx1 product lineup................................................................................................................ 21
1.5.2 V850ES/Kx1 product lineup........................................................................................................... 23
1.6 Block Diagram............................................................................................................................25
1.7 Outline of Functions ..................................................................................................................26
CHAPTER 2 PIN FUNCTIONS...............................................................................................................28
2.1 Pin Function List........................................................................................................................28
2.2 Description of Pin Functions....................................................................................................30
2.2.1 P00 to P03 (port 0) ........................................................................................................................ 30
2.2.2 P10 to P17 (port 1) ........................................................................................................................ 30
2.2.3 P20 to P23 (port 2) ........................................................................................................................ 31
2.2.4 P30 to P33 (port 3) ........................................................................................................................ 31
2.2.5 P120 (port 12)................................................................................................................................ 31
2.2.6 P130 (port 13)................................................................................................................................ 32
2.2.7 AVREF ............................................................................................................................................. 32
2.2.8 AVSS............................................................................................................................................... 32
2.2.9 RESET........................................................................................................................................... 32
2.2.10 X1 and X2...................................................................................................................................... 32
2.2.11 VDD................................................................................................................................................. 32
2.2.12 VSS ................................................................................................................................................. 32
2.2.13 VPP (flash memory versions only) .................................................................................................. 32
2.2.14 IC (mask ROM versions only)........................................................................................................ 32
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 33
CHAPTER 3 CPU ARCHITECTURE......................................................................................................35
3.1 Memory Space............................................................................................................................ 35
3.1.1 Internal program memory space.................................................................................................... 40
3.1.2 Internal data memory space .......................................................................................................... 41
3.1.3 Special function register (SFR) area.............................................................................................. 41
3.1.4 Data memory addressing............................................................................................................... 42
3.2 Processor Registers ..................................................................................................................46
3.2.1 Control registers ............................................................................................................................ 46
3.2.2 General-purpose registers............................................................................................................. 50
3.2.3 Special Function Registers (SFRs)................................................................................................ 51
3.3 Instruction Address Addressing ..............................................................................................55
3.3.1 Relative addressing ....................................................................................................................... 55
3.3.2 Immediate addressing ................................................................................................................... 56
3.3.3 Table indirect addressing............................................................................................................... 57
3.3.4 Register addressing....................................................................................................................... 57
User’s Manual U15836EJ4V0UD 11
3.4 Operand Address Addressing..................................................................................................58
3.4.1 Implied addressing .........................................................................................................................58
3.4.2 Register addressing........................................................................................................................59
3.4.3 Direct addressing............................................................................................................................60
3.4.4 Short direct addressing...................................................................................................................61
3.4.5 Special function register (SFR) addressing ....................................................................................62
3.4.6 Register indirect addressing...........................................................................................................63
3.4.7 Based addressing...........................................................................................................................64
3.4.8 Based indexed addressing .............................................................................................................65
3.4.9 Stack addressing............................................................................................................................66
CHAPTER 4 PORT FUNCTIONS........................................................................................................... 67
4.1 Port Functions............................................................................................................................ 67
4.2 Port Configuration ..................................................................................................................... 68
4.2.1 Port 0..............................................................................................................................................69
4.2.2 Port 1..............................................................................................................................................72
4.2.3 Port 2..............................................................................................................................................77
4.2.4 Port 3..............................................................................................................................................78
4.2.5 Port 12............................................................................................................................................79
4.2.6 Port 13............................................................................................................................................80
4.3 Registers Controlling Port Function........................................................................................ 80
4.4 Port Function Operations.......................................................................................................... 84
4.4.1 Writing to I/O port ...........................................................................................................................84
4.4.2 Reading from I/O port.....................................................................................................................84
4.4.3 Operations on I/O port....................................................................................................................84
CHAPTER 5 CLOCK GENERATOR...................................................................................................... 85
5.1 Functions of Clock Generator .................................................................................................. 85
5.2 Configuration of Clock Generator............................................................................................85
5.3 Registers Controlling Clock Generator ................................................................................... 87
5.4 System Clock Oscillator............................................................................................................ 93
5.4.1 X1 oscillator....................................................................................................................................93
5.4.2 Ring-OSC oscillator........................................................................................................................95
5.4.3 Prescaler ........................................................................................................................................95
5.5 Clock Generator Operation....................................................................................................... 95
5.6 Time Required to Switch Between Ring-OS C Clo ck and X1 Input Clock .......................... 100
5.7 Time Required for CPU Clock Switchover ............................................................................ 100
5.8 Clock Switching Flowchart and Register Setting................................................................. 101
5.8.1 Switching from Ring-OSC clock to X1 input clock ........................................................................101
5.8.2 Switching from X1 input clock to Ring-OSC clock ........................................................................102
5.8.3 Register settings...........................................................................................................................103
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00........................................................................... 104
6.1 Functions of 16-Bit Timer/Event Counter 00......................................................................... 104
6.2 Configuration of 16-Bit Timer/Event Counter 00 .................................................................. 105
6.3 Registers Controlling 16-Bit Timer/Event Counter 00.......................................................... 109
6.4 Operation of 16-Bit Timer/Event Counter 00......................................................................... 115
6.4.1 Interval timer operation.................................................................................................................115
User’s Manual U15836EJ4V0UD
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6.4.2 PPG output operations .................................................................................................................118
6.4.3 Pulse width measurement operations...........................................................................................121
6.4.4 External event counter operation..................................................................................................129
6.4.5 Square-wave output operation......................................................................................................132
6.4.6 One-shot pulse output operation...................................................................................................134
6.5 Cautions for 16-Bit Timer/Event Counter 00 .........................................................................139
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50............................................................................. 142
7.1 Functions of 8-Bit Timer/Event Counter 50...........................................................................142
7.2 Configuration of 8-Bit Timer/Event Counter 50.....................................................................143
7.3 Registers Controlling 8-Bit Timer/Event Counter 50............................................................145
7.4 Operations of 8-Bit Timer/Event Counter 50 ......................................................................... 148
7.4.1 Operation as interval timer............................................................................................................148
7.4.2 Operation as external event counter.............................................................................................150
7.4.3 Operation as square-wave output.................................................................................................151
7.4.4 Operation as PWM output.............................................................................................................152
7.5 Cautions for 8-Bit Timer/Event Counter 50............................................................................154
CHAPTER 8 8-BIT TIMERS H0 AND H1 ..........................................................................................155
8.1 Functions of 8-Bit Timers H0 and H1..................................................................................... 155
8.2 Configuration of 8-Bit Timers H0 and H1...............................................................................155
8.3 Registers Controlling 8-Bit Timers H0 and H1......................................................................159
8.4 Operation of 8-Bit Timers H0 and H1 .....................................................................................163
8.4.1 Operation as interval timer/square-wave output ...........................................................................163
8.4.2 Operation as PWM output mode...................................................................................................166
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 172
9.1 Functions of Watchdog Timer ................................................................................................ 172
9.2 Configuration of Watchdog Timer.......................................................................................... 174
9.3 Registers Controlling Watchdog Timer .................................................................................175
9.4 Operation of Watchdog Timer.................................................................................................177
9.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option ......177
9.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask
option............................................................................................................................................178
9.4.3 Watchdog timer operation in ST OP mode (wh en “Ring-OSC can be stopped by software” is
selected by mask option)..............................................................................................................179
9.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is
selected by mask option)..............................................................................................................181
CHAPTER 10 A/D CONVERTER .........................................................................................................182
10.1 Function of A/D Converter ......................................................................................................182
10.2 Configuration of A/D Converter..............................................................................................183
10.3 Registers Used in A/D Converter............................................................................................185
10.4 A/D Converter Operations....................................................................................................... 189
10.4.1 Basic operations of A/D converter ................................................................................................189
10.4.2 Input voltage and conversion results ............................................................................................191
10.4.3 A/D converter operation mode......................................................................................................192
10.5 How to Read A/D Converter Characteristics Table...............................................................195
User’s Manual U15836EJ4V0UD 13
10.6 Cautions for A/D Converter..................................................................................................... 197
CHAPTER 11 SERIAL INTERFACE UA RT0 (
µ
PD780102, 780103, 78F0103 ONLY)...................... 202
11.1 Functions of Serial Interface UART0 ..................................................................................... 202
11.2 Configuration of Serial Interface UART0............................................................................... 203
11.3 Registers Controlling Serial Interface UART0 ...................................................................... 206
11.4 Operation of Serial Interface UART0...................................................................................... 211
11.4.1 Operation stop mode....................................................................................................................211
11.4.2 Asynchronous serial interface (UART) mode................................................................................212
11.4.3 Dedicated baud rate generator.....................................................................................................218
CHAPTER 12 SERIAL INTERFACE UART6...................................................................................... 223
12.1 Functions of Serial Interface UART6 ..................................................................................... 223
12.2 Configuration of Serial Interface UART6............................................................................... 227
12.3 Registers Controlling Serial Interface UART6 ...................................................................... 230
12.4 Operation of Serial Interface UART6...................................................................................... 238
12.4.1 Operation stop mode....................................................................................................................238
12.4.2 Asynchronous serial interface (UART) mode................................................................................239
12.4.3 Dedicated baud rate generator.....................................................................................................254
CHAPTER 13 SERIAL INTERFACE CSI10........................................................................................ 261
13.1 Functions of Serial Interface CSI10........................................................................................ 261
13.2 Configuration of Serial Interface CSI10................................................................................. 261
13.3 Registers Controlling Serial Interface CSI10 ........................................................................ 263
13.4 Operation of Serial Interface CSI10........................................................................................ 266
13.4.1 Operation stop mode....................................................................................................................266
13.4.2 3-wire serial I/O mode ..................................................................................................................267
CHAPTER 14 INTERRUPT FUNCTIONS............................................................................................ 275
14.1 Interrupt Function Types......................................................................................................... 275
14.2 Interrupt Sources and Configuration..................................................................................... 275
14.3 Registers Controlling Interrupt Function .............................................................................. 278
14.4 Interrupt Servicing Operations............................................................................................... 284
14.4.1 Maskable interrupt request acknowledgment ...............................................................................284
14.4.2 Software interrupt request acknowledgment.................................................................................286
14.4.3 Multiple interrupt servicing............................................................................................................287
14.4.4 Interrupt request hold ...................................................................................................................290
CHAPTER 15 STANDBY FUNCTION.................................................................................................. 291
15.1 Standby Function and Configuration..................................................................................... 291
15.1.1 Standby function...........................................................................................................................291
15.1.2 Registers controlling standby function..........................................................................................293
15.2 Standby Function Operation................................................................................................... 295
15.2.1 HALT mode ..................................................................................................................................295
15.2.2 STOP mode..................................................................................................................................298
CHAPTER 16 RESET FUNCTION ....................................................................................................... 302
16.1 Register for Confirming Reset Source .................................................................................. 308
User’s Manual U15836EJ4V0UD
14
CHAPTER 17 CLOCK MONITOR ........................................................................................................309
17.1 Functions of Clock Monitor..................................................................................................... 309
17.2 Configuration of Clock Monitor .............................................................................................. 309
17.3 Register Controlling Clock Monitor........................................................................................ 310
17.4 Operation of Clock Monitor..................................................................................................... 311
CHAPTER 18 POWER-ON-CLEAR CIRCUIT......................................................................................316
18.1 Functions of Power-on-Clear Circuit...................................................................................... 316
18.2 Configuration of Power-on-Clear Circuit...............................................................................317
18.3 Operation of Power-on-Clear Circuit......................................................................................317
18.4 Cautions for Power-on-Clear Circuit......................................................................................318
CHAPTER 19 LOW-VOLTAGE DETECTOR .......................................................................................320
19.1 Functions of Low-Voltage Detector........................................................................................320
19.2 Configuration of Low-Voltage Detector................................................................................. 320
19.3 Registers Controlling Low-Voltage Detector ........................................................................321
19.4 Operation of Low-Voltage Detector........................................................................................323
19.5 Cautions for Low-Voltage Detector........................................................................................327
CHAPTER 20 MASK OPTIONS ........................................................................................................... 330
CHAPTER 21
µ
PD78F0103.................................................................................................................... 331
21.1 Internal Memory Size Switching Register..............................................................................332
21.2 Writing with Flash Programmer..............................................................................................333
21.3 Programming Environment..................................................................................................... 340
21.4 Communication Mode..............................................................................................................340
21.5 Handling of Pins on Board...................................................................................................... 344
21.5.1 VPP pin ..........................................................................................................................................344
21.5.2 Serial interface pins......................................................................................................................344
21.5.3 RESET pin....................................................................................................................................346
21.5.4 Port pins........................................................................................................................................346
21.5.5 Other signal pins...........................................................................................................................346
21.5.6 Power supply................................................................................................................................346
21.6 Programming Method.............................................................................................................. 347
21.6.1 Controlling flash memory..............................................................................................................347
21.6.2 Flash memory programming mode...............................................................................................347
21.6.3 Selecting communication mode....................................................................................................348
21.6.4 Communication commands ..........................................................................................................349
CHAPTER 22 INSTRUCTION SET.......................................................................................................350
22.1 Conventions Used in Operation List...................................................................................... 350
22.1.1 Operand identifiers and specification methods.............................................................................350
22.1.2 Description of operation column ...................................................................................................351
22.1.3 Description of flag operation column.............................................................................................351
22.2 Operation List........................................................................................................................... 352
22.3 Instructions Listed by Addressing Type................................................................................360
User’s Manual U15836EJ4V0UD 15
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE
PRODUCTS) .................................................................................................................. 363
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)................................ 380
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................ 395
CHAPTER 26 PACKAGE DRAWING .................................................................................................. 405
CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS............................................................ 406
CHAPTER 28 CAUTIONS FOR WAIT................................................................................................ 408
28.1 Cautions for Wait ..................................................................................................................... 408
28.2 Peripheral Hardware That Generates Wait............................................................................ 409
28.3 Example of Wait Occurrence.................................................................................................. 410
APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 411
A.1 Software Package .................................................................................................................... 414
A.2 Language Processing Software ............................................................................................. 415
A.3 Control Software...................................................................................................................... 416
A.4 Flash Memory Writing Tools................................................................................................... 416
A.5 Debugging Tools (Hardware).................................................................................................. 417
A.5.1 When using in-circuit emulat ors IE-78K0-NS and IE-78K0-NS-A.................................................417
A.5.2 When using in-circuit emulator IE- 78K0K1-ET .............................................................................418
A.6 Debugging Tools (Software)................................................................................................... 419
A.7 Embedded Software ................................................................................................................ 420
APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 421
APPENDIX C REGISTER INDEX......................................................................................................... 423
C.1 Register Index (In Alphabetical Ord e r with Respect to Register Names).......................... 423
C.2 Register Index (In Alphabetical Ord e r with Respect to Register Symbol)......................... 426
APPENDIX D REVISION HISTORY..................................................................................................... 429
D.1 Major Revisions in This Edition.............................................................................................. 429
D.2 Revision History of Previous Editions................................................................................... 433
User’s Manual U15836EJ4V0UD
16
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.2
µ
s: @ 10 MHz operation with X1
input clock) to low-speed (3.2
µ
s: @ 10 MHz operation with X1 input clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Part Number
Item
Program Memory
(ROM) Data Memory
(Internal High-Speed RAM)
µ
PD780101 8 KB 512 bytes
µ
PD780102 16 KB
µ
PD780103
Mask ROM
24 KB
µ
PD78F0103 Flash memory 24 KBNote
768 bytes
Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the on-chip Ring-OSC
{ On-chip clock monitor function using on-chip Ring-OSC
{ On-chip watchdog timer (operable with Ring-OSC clock)
{ I/O ports: 22
{ Timer: 5 channels
{ Serial interface: 2 channels
UART (LIN (Local Interconnect Network)-bus supported): 1 channel
CSI1/UARTNote: 1 channel (
µ
PD780101 only, CSI1: 1 channel)
{ 10-bit resolution A/D converter: 4 channels
{ Supply voltage: VDD = 2.7 to 5.5 V (standard products, (A) grade products)
V
DD = 3.3 to 5.5 V ((A1) grade, (A2) grade products)
{ Operating ambient temperature: TA = −40 to +85°C (standard product, (A) grade product)
T
A = −40 to +105°C (flash memory version of (A1) grade product)
T
A = −40 to +110°C (mask ROM version of (A1) grade product)
TA = −40 to +125°C (mask ROM version of (A2) grade product)
Note Select either of the functions of these alternate-function pins.
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD 17
1.2 Applications
{ Automotive equipment
• System control for body electricals (power windows, keyless entry reception, etc.)
• Sub-microcontrollers for control
{ Home audio, car audio
{ AV equipment
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
• Outdoor air conditioner units
• Microwave ovens, electric rice cookers
{ Industrial equipment
• Pumps
• Vending machines
• FA (Factory Automation)
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD
18
1.3 Ordering Information
(1) Mask ROM version
Part Number Package Quality Grade
µ
PD780101MC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD780102MC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD780103MC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD780101MC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780102MC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780103MC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780101MC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780102MC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780103MC(A1)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780101MC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780102MC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD780103MC(A2)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
(2) Flash memory version
Part Number Package Quality Grade
µ
PD78F0103M1MC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F0103M2MC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F0103M3MC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F0103M4MC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F0103M5MC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F0103M6MC-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard
µ
PD78F0103M1MC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M2MC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M3MC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M4MC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M5MC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M6MC(A)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M1MC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M2MC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M5MC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
µ
PD78F0103M6MC(A1)-5A4 30-pin plastic SSOP (7.62 mm (300)) Special
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended
applications.
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD 19
Mask ROM versions (
µ
PD780101, 780102, and 780103) include mask options. When ordering, it is possible to
select “Power-on-clear (POC) circuit can be used/cannot be used” and “Ring-OSC clock can be stopped/cannot be
stopped by software”.
Flash memory versions supporting the mask options of the mask ROM versions are as follows.
Table 1-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions
Mask Option
POC Circuit Ring-OSC
Flash Memory Versions
(Part Number)
Cannot be stopped
µ
PD78F0103M1MC-5A4
µ
PD78F0103M1MC(A)-5A4
µ
PD78F0103M1MC(A1)-5A4
POC cannot be used
Can be stopped by software
µ
PD78F0103M2MC-5A4
µ
PD78F0103M2MC(A)-5A4
µ
PD78F0103M2MC(A1)-5A4
Cannot be stopped
µ
PD78F0103M3MC-5A4
µ
PD78F0103M3MC(A)-5A4
POC used (VPOC = 2.85 V ±0.15 V)
Can be stopped by software
µ
PD78F0103M4MC-5A4
µ
PD78F0103M4MC(A)-5A4
Cannot be stopped
µ
PD78F0103M5MC-5A4
µ
PD78F0103M5MC(A)-5A4
µ
PD78F0103M5MC(A1)-5A4
POC used (VPOC = 3.5 V ±0.2 V)
Can be stopped by software
µ
PD78F0103M6MC-5A4
µ
PD78F0103M6MC(A)-5A4
µ
PD78F0103M6MC(A1)-5A4
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD
20
1.4 Pin Configuration (Top View)
• 30-pin plastic SSOP (7.62 mm (300))
P33/INTP4
P32/INTP3
P31/INTP2
P30/INTP1
IC (V
PP
)
V
SS
V
DD
X1
X2
P03
RESET
P02
P01/TI010/TO00
P00/TI000
P10/SCK10/TxD0
Note
28
27
26
30
29
25
24
23
22
21
20
19
18
16
P120/INTP0
AV
SS
AV
REF
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P130
P17/TI50/TO50
P15/TOH0
P16/TOH1/INTP5
P14/RxD6
P13/TxD6
P12/SO10
P11/SI10/RxD0
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVSS pin to VSS.
3. Connect the VPP pin to VSS during normal operation.
Remark Figures in pare ntheses apply only to the
µ
PD78F0103.
Pin Identification
ANI0 to ANI3: Analog input
AVREF: Analog reference voltage
IC: Internally connected
INTP0 to INTP5: External interrupt input
P00 to P03: Port 0
P10 to P17: Port 1
P20 to P23: Port 2
P30 to P33: Port 3
P120: Port 12
P130: Port 13
RESET: Reset
RxD0Note, RxD6: Receive data
SCK10: Serial clock input/output
SI10: Serial data input
SO10: Serial data output
TI000, TI010, TI50: Timer input
TO00, TO50, TOH0, TOH1: Timer output
TxD0Note, TxD6: Transmit data
VDD: Power supply
VPP: Programming power supply
VSS: Ground
X1, X2: Crystal oscillator (X1 input clock)
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD 21
1.5 K1 Family Lineup
1.5.1 78K0/Kx1 product lineup
PD78F0103 Flash memory: 24 KB, RAM: 768 bytes
Mask ROM: 24 KB, RAM: 768 bytes
Mask ROM: 16 KB, RAM: 768 bytes
Mask ROM: 8 KB, RAM: 512 bytes
PD780103
PD780102
PD780101
78K0/KB1: 30-pin SSOP (7.62 mm 0.65 mm pitch)
PD78F0114 Flash memory: 32 KB, RAM: 1 KB
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
Mask ROM: 16 KB, RAM: 512 bytes
PD780114
PD780113
PD780112
Mask ROM: 8 KB, RAM: 512 bytes
PD780111
78K0/KC1: 44-pin LQFP (10 × 10 mm 0.8 mm pitch)
PD78F0124 Flash memory: 32 KB, RAM: 1 KB
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
Mask ROM: 16 KB, RAM: 512 bytes
PD780124
PD780123
PD780122
Mask ROM: 8 KB, RAM: 512 bytes
PD780121
78K0/KD1: 52-pin LQFP (10 × 10 mm 0.65 mm pitch)
PD78F0148 Flash memory: 60 KB, RAM: 2 KB
Mask ROM: 60 KB, RAM: 2 KB
Mask ROM: 48 KB, RAM: 2 KB
Mask ROM: 32 KB, RAM: 1 KB
PD780148
PD780146
PD780144
Mask ROM: 24 KB, RAM: 1 KB
PD780143
78K0/KF1: 80-pin TQFP, QFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
PD78F0134 Flash memory:
32 KB, RAM: 1 KB
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
Mask ROM: 16 KB, RAM: 512 bytes
PD780134
PD780133
PD780132
Mask ROM: 8 KB, RAM: 512 bytes
PD780131
PD78F0138 Flash memory:
60 KB, RAM: 2 KB
Mask ROM: 60 KB, RAM: 2 KB
Mask ROM:
48 KB, RAM
:
2 KB
PD780138
PD780136
78K0/KE1: 64-pin LQFP, TQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD
22
The list of functions in the 78K0/Kx1 is shown below.
Part Number
Item 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1
Package 30 pins 44 pins 52 pins 64 pins 80 pins
16 K 8 K 24 K 8 K 24 K 8 K 24 K 48 K 24 K 48 KMask ROM 8 K
24 K
−
16 K 32 K
−
16 K 32 K
−
16 K 32 K
−
60 K
−
32 K 60 K
−
Flash memory − 24 K − 32 K − 32 K − 32 K − 60 K − 60 K
Internal
memory
(bytes)
RAM 512 768 512 1 K 512 1 K 512 1 K 2 K 1 K 2 K
Power supply voltage VDD = 2.7 to 5.5 V
Minimum instruction execution time 0.2
µ
s (when 10 MHz, VDD =
4.0 to 5.5 V)
0.24
µ
s (when 8.38 MHz, VDD =
3.3 to 5.5 V)
0.4
µ
s (when 5 MHz, VDD = 2.7
to 5.5 V)
<Connect REGC pin to VDD>
0.2
µ
s (when 10 MHz, VDD = 4.0 to 5.5 V)
0.24
µ
s (when 8.38 MHz, VDD = 3.3 to 5.5 V)
0.4
µ
s (when 5 MHz, VDD = 2.7 to 5.5 V)
X1 input 2 to 10 MHz
Sub − 32.768 kHz
Clock
Ring-OSC 240 kHz (TYP.)
CMOS I/O 17 19 26 38 54
CMOS input 4 8
CMOS output 1
Port
N-ch open-drain I/O − 4
16 bits (TM0) 1 ch 2 ch 1 ch 2 ch
8 bits (TM5) 1 ch 2 ch
8 bits (TMH) 2 ch
For watch − 1 ch
Timer
WDT 1 ch
3-wire CSINote 1 ch 2 ch 1 ch 2 ch
Automatic transmit/
receive 3-wire CSI − 1 ch
UARTNote − 1 ch
Serial
interface
UART supporting LIN-bus 1 ch
10-bit A/D converter 4 ch 8 ch
External 6 7 8 9 9 Interrupt
Internal 11 12 15 16 19 17 20
Key return input − 4 ch 8 ch
RESET pin Provided
POC 2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by mask option)
LVI 3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Clock monitor Provided
Reset
WDT Provided
Multiplier/divider − 16 bits × 16 bits, 32 bits ÷ 16 bits
ROM correction − Provided −
Standby function HALT/STOP mode
Operating ambient temperature Standard products, special (A) products: −40 to +85°C
Special (A1) products: −40 to +110°C (mask ROM version),
−40 to +105°C (flash memory version)
Special (A2) products: −40 to +125°C (mask ROM version)
Note Select either of the functions of these alternate-function pins.
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD 23
1.5.2 V850ES/Kx1 product lineup
144-pin plastic LQFP (fine pitch) (20 ×
2
0)
PD703217Y
PD703217 Mask ROM: 128 KB, RAM: 6 KB
I2C products
PD703216Y
PD703216 Mask ROM: 96 KB, RAM: 6 KB
I2C products
V850ES/KJ1
100-pin plastic LQFP (fine pitch) (14 ×
14)
PD703213Y
PD703213 Mask ROM: 96 KB, RAM: 4 KB
I2C products
PD703212Y
PD703212 Mask ROM: 64 KB, RAM: 4 KB
I2C products
V850ES/KG1
80-pin plastic QFP (14 ×
14)
80-pin plastic TQFP (fine pitch) (12 ×
12)
PD703209Y
PD703209 Mask ROM: 96 KB, RAM: 4 KB
I2C products
PD703208Y
PD703208 Mask ROM: 64 KB, RAM: 4 KB
I2C products
V850ES/KF1
PD70F3217Y
PD70F3217 Flash memory: 128 KB, RAM: 6 KB
I2C products
PD70F3214Y
PD70F3214 Flash memory: 128 KB, RAM: 6 KB
I2C products
PD703214Y
PD703214 Mask ROM: 128 KB, RAM: 6 KB
I2C products
PD70F3210Y
PD70F3210 Flash memory: 128 KB, RAM: 6 KB
I2C products
PD703210Y
PD703210 Mask ROM: 128 KB, RAM: 6 KB
I2C products
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD
24
The list of functions in the V850ES/Kx1 is shown below.
Timer Serial Interface Function
Part No. 8-Bit 16-Bit TMH Watch WDT CSI CSIA UART I2C
A/D D/A RTO I/O Other
µ
PD703208 –
µ
PD703208Y 1 ch
µ
PD703209 –
µ
PD703209Y 1 ch
µ
PD703210 –
µ
PD703210Y 1 ch
µ
PD70F3210 –
V850ES/KF1
µ
PD70F3210Y
2 ch 2 ch 2 ch 1 ch 2 ch 2 ch 1 ch 2 ch
1 ch
8 ch – 6 ch 67 –
µ
PD703212 –
µ
PD703212Y 1 ch
µ
PD703213 –
µ
PD703213Y 1 ch
µ
PD703214 –
µ
PD703214Y 1 ch
µ
PD70F3214 –
V850ES/KG1
µ
PD70F3214Y
2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch
1 ch
8 ch 2 ch 6 ch 84 –
µ
PD703216 –
µ
PD703216Y 2 ch
µ
PD703217 –
µ
PD703217Y 2 ch
µ
PD70F3217 –
V850ES/KJ1
µ
PD70F3217Y
2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch
2 ch
16 ch 2 ch 12 ch 128 –
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD 25
1.6 Block Diagram
16-bit timer/
event counter 00
TO00/TI010/P01
TI000/P00
Serial interface
CSI10
SI1/P11
SO10/P12
SCK10/P10
ANI0/P20 to
ANI3/P23
Interrupt control
8-bit timer H0
TOH0/P15
8-bit timer H1
TOH1/P16
TI50/TO50/P17 8-bit timer/
event counter 50
4A/D converter
78K/0
CPU
core
Internal
high-speed
RAM
ROM
(Flash
memory)
Port 0 P00 to P03
4
Port 1 P10 to P17
Port 2 P20 to P23
4
Port 3 P30 to P33
4
Port 12 P120
Port 13 P130
System control RESET
X1
X2
RxD0
Note
/P11
TxD0
Note
/P10 Serial interface
UART0
Note
Watchdog timer
RxD6/P14
TxD6/P13 Serial interface
UART6
V
SS
IC
(V
PP
)
V
DD
AV
REF
AV
SS
INTP1/P30 to
INTP4/P33 4
INTP0/P120
Clock monitor
Power-on-clear/
low voltage
indicator
POC/LVI
control
Reset control
Ring-OSC
8
Note
µ
PD780102, 780103, and 78F0103 only.
Remark Items in parentheses are available only i n the
µ
PD78F0103.
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD
26
1.7 Outline of Functions
Item
µ
PD780101
µ
PD780102
µ
PD780103
µ
PD78F0103
ROM 8 KB 16 KB 24 KB 24 KB
(flash memory)
Internal memory
High-speed RAM 512 bytes 768 bytes
Memory space 64 KB
X1 input clock (oscillation frequency) Ceramic/crystal/external clock oscillation
Standard products,
(A) grade products 10 MHz (VDD = 4.0 to 5.5 V), 8.38 MHz (VDD = 3.3 to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V)
(A1) grade products 10 MHz (VDD = 4.5 to 5.5 V), 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V)
(A2) grade products 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V)
Ring-OSC clock
(oscillation frequency) On-chip Ring oscillation (240 kHz (TYP.))
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
0.2
µ
s/0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s (X1 input clock: @ fXP = 10 MHz operation) Minimum instruction execution time
8.3
µ
s/16.6
µ
s/33.2
µ
s/66.4
µ
s/132.8
µ
s (TYP.)
(Ring-OSC clock: @ fR = 240 kHz (TYP.) operation)
Instruction set • 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O ports Total: 22
CMOS I/O 17
CMOS input 4
CMOS output 1
Timers • 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 1 channel
• 8-bit timer: 2 channels
• Watchdog timer: 1 channel
Timer outputs 4 (PWM: 3)
A/D converter 10-bit resolution × 4 channels
Serial interface • UART mode supporting LIN-bus: 1 channel
• 3-wire serial I/O mode/UART modeNote: 1 channel (
µ
PD780101 only, 3-wire serial
I/O mode: 1 channel)
Internal 10 12 Vectored
interrupt sources External 6
Reset • Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by clock monitor
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
Supply voltage • Standard products, (A) grade products: VDD = 2.7 to 5.5 V
• (A1) grade products, (A2) grade products: VDD = 3.3 to 5.5 V
Operating ambient temperature • Standard products, (A) grade products: TA = −40 to +85°C
• (A1) grade products: TA = −40 to +110°C (mask ROM version), −40 to +105°C (flash
memory version)
• (A2) grade products: TA = −40 to +125°C (mask ROM versions)
Package 30-pin plastic SSOP (7.62 mm (300))
Note Select either of the functions of these alternate-function pins.
CHAPTER 1 OUTLINE
User’s Manual U15836EJ4V0UD 27
An outline of the timer is shown below.
8-Bit Timers H0 and H1 16-Bit Timer/Event
Counter 00 8-Bit Timer/Event
Counter 50 TMH0 TMH1
Watchdog Timer
Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel
Operation
mode External event counter 1 channel 1 channel − − −
Timer output 1 output 1 output 1 output 1 output −
PPG output 1 output − − − −
PWM output − 1 output 1 output 1 output −
Pulse width measurement 2 inputs − − − −
Square-wave output 1 output 1 output 1 output 1 output −
Function
Interrupt source 2 1 1 1 −
User’s Manual U15836EJ4V0UD
28
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power
supplies and the pins is show n below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P23
VDD Pins other than P20 to P23
(1) Port pins
Pin Name I/O Function After Reset Alternate Function
P00 TI000
P01 TI010/TO00
P02
P03
I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
−
P10 SCK10/TxD0Note
P11 SI10/RxD0Note
P12 SO10
P13 TxD6
P14 RxD6
P15 TOH0
P16 TOH1/INTP5
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
TI50/TO50
P20 to P23 Input Port 2.
4-bit input-only port. Input ANI0 to ANI3
P30 to P33 I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input INTP1 to INTP4
P120 I/O
Port 12.
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input INTP0
P130 Output
Port 13.
1-bit output-only port. Output −
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15836EJ4V0UD 29
(2) Non-port pins
Pin Name I/O Function After Reset Alternate Function
INTP0 P120
INTP1 to INTP4 P30 to P33
INTP5
Input External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
Input
P16/TOH1
SI10 Input Serial data input to serial interface Input P11/RxD0Note
SO10 Output Serial data output from serial interface Input P12
SCK10 I/O Clock input/output for serial interface Input P10/TxD0Note
RxD0Note P11/SI10
RxD6
Input Serial data input to asynchronous serial interface Input
P14
TxD0Note P10/SCK10
TxD6
Output Serial data output from asynchronous serial interface Input
P13
TI000 External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
P00
TI010
Input
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
Input
P01/TO00
TO00 Output 16-bit timer/event counter 00 output Input P01/TI010
TI50 Input External count clock input to 8-bit timer/event counter 50 Input P17/TO50
TO50 Output 8-bit timer/event counter 50 output Input P17/TI50
TOH0 8-bit timer H0 output P15
TOH1
Output
8-bit timer H1 output
Input
P16/INTP5
ANI0 to ANI3 Input A/D converter analog input Input P20 to P23
AVREF Input
A/D converter reference voltage input and positive power
supply for port 2 − −
AVSS − A/D converter ground potential. Make the same potential as
VSS. − −
RESET Input System reset input − −
X1 Input − −
X2 −
Connecting resonator for X1 input clock
− −
VDD − Positive power supply − −
VSS − Ground potential − −
IC − Internally connected. Connect directly to VSS. − −
VPP − Flash memory programming mode setting. High-voltage
application for program write/verify. Connect to VSS in normal
operation mode.
− −
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15836EJ4V0UD
30
2.2 Description of Pin Functions
2.2.1 P00 to P03 (port 0)
P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 to P03 function as timer I/O.
(a) TI000
This is the pins for inputting a n extern al count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.
(b) TI010
This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event
counter 00.
(c) TO00
This is a timer output pin.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins f or external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial data input pin of the serial interface.
(b) SO10
This is a serial data output pin of the serial interface.
(c) SCK10
This is a serial clock I/O pin of the serial interface.
(d) RxD0Note, RxD6
These are the serial data input pins of the asynchro nous serial interface.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15836EJ4V0UD 31
(e) TxD0Note, TxD6
These are serial data output pins of the asynchronous serial interface.
Note TxD0 and RxD0 are ava ilable only in the
µ
PD780102, 780103, and 78F0103.
(f) TI50
This is the pin for inputting an external count clock to 8-bit ti mer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (risi ng edge, falling edge, or both risin g
and falling edges) can be specified.
2.2.3 P20 to P23 (port 2)
P20 to P23 function as a 4-bit input-only port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P23 function as a 4-bit input-only port.
(2) Control mode
P20 to P23 function as A/D converter analog input pi ns (ANI0 to ANI3). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI3/P23 in 10.6 Cautions for A/D Converter.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input pins (INTP1 to INTP4) for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be specified.
2.2.5 P120 (port 12)
P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output in 1-bit units using port mode register 12
(PM12). Use of an on-chip pull-up resistor ca n be specified by pull-up resis tor option register 12 (PU12).
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User’s Manual U15836EJ4V0UD
32
(2) Control mode
P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
2.2.6 P130 (port 13)
P130 functions as a 1-bit output-only port.
2.2.7 AVREF
This is the A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin directly to VDD.
2.2.8 AVSS
This is the A/D converter ground potential pin. Ev en when the A/D conver ter is not used, always use this pin with
the same potential as the VSS pin.
2.2.9 RESET
This is the active-low system reset input pin.
2.2.10 X1 and X2
These are the pins for connecting a resonator for X1 input clock oscillation.
When supplying an external cl ock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
2.2.11 VDD
This is the positive power supply pin.
2.2.12 VSS
This is the ground potential pin.
2.2.13 VPP (flash memory versions only)
This is a pin for flash memory programming mode setting and high-voltage application for program write/verify.
Connect to VSS in the normal operation mode.
2.2.14 IC (mask ROM versions only)
The IC (Internally Connected) pin is prov ided to set the test mode to check the 78K0/KB1 at shi pment. Connect it
directly to VSS with the shortest possible wire in the normal operation mode.
When a potential difference is pr oduced between the IC p in and the VSS pi n because the wiring betw een these two
pins is too long or external noise is input to the IC pin, the user’s program may not operate normally.
• Connect the IC pin directly to VSS.
As short as possible
ICV
SS
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15836EJ4V0UD 33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuit and the recommended connections of unus ed pins.
Refer to Figure 2-1 for the configuration of the I/O circuits of each type.
Table 2-2. Pin I/O Circuit Types
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI000
P01/TI010/TO00
P02
P03
P10/SCK10/TxD0Note
P11/SI10/RxD0Note
8-A
P12/SO10
P13/TxD6
5-A
P14/RxD6 8-A
P15/TOH0 5-A
P16/TOH1/INTP5
P17/TI50/TO50
8-A
I/O Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P20/ANI0 to P23/ANI3 9-C Input Connect to VDD or VSS.
P30/INTP1 to P33/INTP4 Input: Independently connect to VSS via a resistor.
Output: Leave open.
P120/INTP0
8-A I/O
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P130 3-C Output Leave open.
RESET 2 Input −
AVREF Input Connect directly to VDD.
AVSS
IC
Connect directly to VSS.
VPP
−
−
Connect to VSS.
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15836EJ4V0UD
34
Figure 2-1. Pin I/O Circuit List
Type 3-C
Type 2 Type 8-A
Type 5-A
Type 9-C
Schmitt-triggered input with hysteresis characteristics
IN
Pull-up
enable
Data
Output
disable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
V
DD
P-ch
N-ch
Data OUT
IN Comparator
V
REF
(threshold voltage)
AV
SS
P-ch
N-ch
Input
enable
+
–
Pull-up
enable
Data
Output
disable
Input
enable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
User’s Manual U15836EJ4V0UD 35
CHAPTER 3 CPU ARCHI TECTURE
3.1 Memory Space
Products in the 78K0/KB1 can each access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps.
Caution Regardless of the internal memory capacity, the initial values of internal memory size switching
register (IMS) of all products in the 78K0/KB1 are fixed (IMS = CFH). Therefore, set the value
corresponding to each product as indicated below.
Table 3-1. Internal Memory Size Switching Register (IMS) Set Value
Internal Memory Size Switching Register (IMS)
µ
PD780101 42H
µ
PD780102 04H
µ
PD780103 06H
µ
PD78F0103 Value corresponding to mask ROM version
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
36
Figure 3-1. Memory Map (
µ
PD780101)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
General-purpose
registers
32 × 8 bits
Reserved
Internal ROM
8192 × 8 bits
Program
memory space
Data memory
space
Vector table area
H
CALLT table area
Program area
CALLF entry area
Program area
000
0
H
F30
0H
040
0
H
F70
0H
080
0
HFF7
0H
008
0
H
FFF
0H
000
1
HFFF
1
H
0
00
0
H
FFF
1H
000
2
H
FFC
FH
00D
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 37
Figure 3-2. Memory Map (
µ
PD780102)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
768 × 8 bits
General-purpose
registers
32 × 8 bits
Reserved
Internal ROM
16384 × 8 bits
Program
memory space
Data memory
space
Vector table area
CALLT table area
Program area
CALLF entry area
Program area
H
000
0
H
F30
0H
040
0
H
F70
0H
080
0
HFF7
0H
008
0
H
FFF
0H
000
1
HFFF
3
H
0
00
0
H
FFF
3H
000
4
H
FFB
FH
00C
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
38
Figure 3-3. Memory Map (
µ
PD780103)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
768 × 8 bits
General-purpose
registers
32 × 8 bits
Reserved
Internal ROM
24576 × 8 bits
Program
memory space
Data memory
space
Vector table area
CALLT table area
Program area
CALLF entry area
Program area
H
000
0
H
F30
0H
040
0
H
F70
0H
080
0
HFF7
0H
008
0
H
FFF
0H
000
1
HFFF
5
H
0
00
0
H
FFF
5H
000
6
H
FFB
FH
00C
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 39
Figure 3-4. Memory Map (
µ
PD78F0103)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
768 × 8 bits
General-purpose
registers
32 × 8 bits
Reserved
Flash memory
24576 × 8 bits
Program
memory space
Data memory
space
Vector table area
CALLT table area
Program area
CALLF entry area
Program area
H
000
0
H
F30
0H
040
0
H
F70
0H
080
0
HFF7
0H
008
0
H
FFF
0H
000
1
HFFF
5
H
0
00
0
H
FFF
5H
000
6
H
FFB
FH
00C
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
40
3.1.1 Internal program memory space
The internal program memory space stores t he program and table data. Normally, it is addressed with the program
counter (PC).
78K0/KB1 products incorporate internal ROM (mask ROM or flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
µ
PD780101 8192 × 8 bits (0000H to 1FFFH)
µ
PD780102 16384 × 8 bits (0000H to 3FFFH)
µ
PD780103
Mask ROM
24576 × 8 bits (0000H to 5FFFH)
µ
PD78F0103 Flash memory 24576 × 8 bits (0000H to 5FFFH)
The internal program memory space is div ided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address Interrupt Source Vector Table Address Interrupt Source
0000H RESET input, POC, LVI
clock monitor, WDT 0016H INTST6
0004H INTLVI 0018H INTCSI10/INTST0Note
0006H INTP0 001AH INTTMH1
0008H INTP1 001CH INTTMH0
000AH INTP2 001EH INTTM50
000CH INTP3 0020H INTTM000
000EH INTP4 0022H INTTM010
0010H INTP5 0024H INTAD
0012H INTSRE6 0026H INTSR0Note
0014H INTSR6
Note Available only in the
µ
PD780102, 780103, an d 78F0103.
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can stor e the subroutine entry address of a 1-byte call instruction ( CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 41
3.1.2 Internal data memory space
78K0/KB1 products incorporate the following internal high-speed RAM.
Table 3-4. Internal High-Speed RAM Capacity
Part Number Internal High-Speed RAM
µ
PD780101 512 × 8 bits (FD00H to FEFFH)
µ
PD780102
µ
PD780103
µ
PD78F0103
768 × 8 bits (FC00H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also b e used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardwar e special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Table 3-5 Special Function Register List in 3.2.3 Special Function Registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
42
3.1.4 Data memory addressing
Addressing refers to the method of s pecifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes ar e provided for addr essing the memory relev ant to the exec ution of instructions for th e
78K0/KB1, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-5 to 3-8 show the correspond ence between data memory and addressing. For details of
each addressing mode, refer to 3.4 Operand Address Addressing.
Figure 3-5. Correspondence Between Data Memory and Addressing (
µ
PD780101)
Special function registers (SFR)
256 × 8 bits
Short direct
addressing
SFR addressing
Internal high-speed RAM
512 × 8 bits
General-purpose registers
32 × 8 bits
Reserved
Internal ROM
8192 × 8 bits
Register addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
H
0
00
0
H
FFF
1H
000
2
H
FFC
FH
00D
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
H
F1E
FH
02E
F
H
F1F
FH
02F
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 43
Figure 3-6. Correspondence Between Data Memory and Addressing (
µ
PD780102)
Special function registers (SFR)
256 × 8 bits
Short direct
addressing
SFR addressing
Internal high-speed RAM
768 × 8 bits
General-purpose registers
32 × 8 bits
Reserved
Internal ROM
16384 × 8 bits
Register addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
H
0
00
0
H
FFF
3H
000
4
H
FFB
FH
00C
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
H
F1E
FH
02E
F
H
F1F
FH
02F
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
44
Figure 3-7. Correspondence Between Data Memory and Addressing (
µ
PD780103)
Special function registers (SFR)
256 × 8 bits
Short direct
addressing
SFR addressing
Internal high-speed RAM
768 × 8 bits
General-purpose registers
32 × 8 bits
Reserved
Internal ROM
24576 × 8 bits
Register addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
H
0
00
0
H
FFF
5H
000
6
H
FFB
FH
00C
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
H
F1E
FH
02E
F
H
F1F
FH
02F
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 45
Figure 3-8. Correspondence Between Data Memory and Addressing (
µ
PD78F0103)
Special function registers (SFR)
256 × 8 bits
Short direct
addressing
SFR addressing
Internal high-speed RAM
768 × 8 bits
General-purpose registers
32 × 8 bits
Reserved
Register addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Flash memory
24576 × 8 bits
H
0
00
0
H
FFF
5H
000
6
H
FFB
FH
00C
F
H
FDE
FH
0EE
F
H
FFE
FH
00F
F
H
FFF
F
H
F1E
FH
02E
F
H
F1F
FH
02F
F
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
46
3.2 Processor Registers
78K0/KB1 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuse s and stack memory. The control registers c onsist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the a ddress information of the next program to be executed.
In normal operation, the PC is automat ic ally i ncrement ed ac cordin g to the numb er of bytes of the i nstruction to b e
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-9. Format of Program Counter
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various fla gs to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are reset upo n execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-10. Format of Program Status Word
7 0
PSW IE Z RBS1 AC RBS0 0 ISP CY
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 47
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgment operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and maskable interrupt requests are all
disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and i nterrupt request acknowledgment en able is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a b orrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specifie d by a priority specification flag register (PR0L, PR0H, PR1 L) (refer
to 14.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) can not be acknowledged. Actual
request acknowledgment is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores on overflow or underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction
execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
48
Figure 3-11. Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-12 and 3-13.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before use.
Figure 3-12. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
Register pair lower
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
Register pair upper
FEDEH
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
PC15-PC8
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH PC7-PC0
FEDEH
(c) Interrupt, BRK instructions (when SP = FEE0H)
PC15-PC8
PSW
FEDFH
FEE0H
SP
SP
FEE0H
FEDEH
FEDDH PC7-PC0
FEDDH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 49
Figure 3-13. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
Register pair lower
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
Register pair upper
FEDEH
(b) RET instruction (when SP = FEDEH)
PC15-PC8
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH PC7-PC0
FEDEH
(c) RETI, RETB instructions (when SP = FEDDH)
PC15-PC8
PSW
FEDFH
FEE0H
SP
SP
FEE0H
FEDEH
FEDDH PC7-PC0
FEDDH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers co nsists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit registe r, and two 8-bit registers can also be used in a pair as a 1 6-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be use d for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-14. Configuration of General-Purpose Registers
(a) Absolute name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-bit processing 8-bit processing
FEF0H
FEE8H
(b) Function name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing 8-bit processing
FEF0H
FEE8H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 51
3.2.3 Special Function Registers (SFRs)
Unlike a general-purpose register, each special function register has a special functi on.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
manipulation instructions. The manipul atable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction oper and (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operan d (sfrp).
When specifying an address, describ e an even address.
Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a spec ial function r egister. It is a re served word in the RA78K0, and is defined
by the header file “sfrbit.h” in the CC 78K0. When us i ng the RA78K 0, ID7 8K0-NS, ID78K0, or SM78K0 , symbols
can be written as an instruction oper and.
• R/W
Indicates whether the corresp onding special function register can be rea d or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manip ulation is not possible.
• After reset
Indicates each register status upon RESET input.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD
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Table 3-5. Special Function Register List (1/3)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF00H Port register 0 P0 R/W √ √ − 00H
FF01H Port register 1 P1 R/W √ √ − 00H
FF02H Port register 2 P2 R √ √ − Undefined
FF03H Port register 3 P3 R/W √ √ − 00H
FF08H
FF09H
A/D conversion result register ADCR R − − √ Undefined
FF0AH Receive buffer register 6 RXB6 R − √ − FFH
FF0BH Transmit buffer register 6 TXB6 R/W − √ − FFH
FF0CH Port register 12 P12 R/W √ √ − 00H
FF0DH Port register 13 P13 R/W √ √ − 00H
FF0FH Serial I/O shift register 10 SIO10 R − √ − 00H
FF10H
FF11H
16-bit timer counter 00 TM00 R − − √ 0000H
FF12H
FF13H
16-bit timer capture/compare register 000 CR000 R/W − − √ 0000H
FF14H
FF15H
16-bit timer capture/compare register 010 CR010 R/W − − √ 0000H
FF16H 8-bit timer counter 50 TM50 R − √ − 00H
FF17H 8-bit timer compare register 50 CR50 R/W − √ − 00H
FF18H 8-bit timer H compare register 00 CMP00 R/W − √ − 00H
FF19H 8-bit timer H compare register 10 CMP10 R/W − √ − 00H
FF1AH 8-bit timer H compare register 01 CMP01 R/W − √ − 00H
FF1BH 8-bit timer H compare register 11 CMP11 R/W − √ − 00H
FF20H Port mode register 0 PM0 R/W √ √ − FFH
FF21H Port mode register 1 PM1 R/W √ √ − FFH
FF23H Port mode register 3 PM3 R/W √ √ − FFH
FF28H A/D converter mode register ADM R/W √ √ − 00H
FF29H Analog input channel specification register ADS R/W √ √ − 00H
FF2AH Power-fail comparison mode register PFM R/W √ √ − 00H
FF2BH Power-fail comparison threshold register PFT R/W − √ − 00H
FF2CH Port mode register 12 PM12 R/W √ √ − FFH
FF30H Pull-up resistor option register 0 PU0 R/W √ √ − 00H
FF31H Pull-up resistor option register 1 PU1 R/W √ √ − 00H
FF33H Pull-up resistor option register 3 PU3 R/W √ √ − 00H
FF3CH Pull-up resistor option register 12 PU12 R/W √ √ − 00H
FF48H External interrupt rising edge enable register EGP R/W √ √ − 00H
FF49H External interrupt falling edge enable register EGN R/W √ √ − 00H
FF4FH Input switch control register ISC R/W √ √ − 00H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 53
Table 3-5. Special Function Register List (2/3)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF50H Asynchronous serial interface operation mode
register 6 ASIM6 R/W √ √ − 01H
FF53H Asynchronous serial inte rface reception error
status register 6 ASIS6 R
− √ − 00H
FF55H Asynchronous serial interface transmission
status register 6 ASIF6 R
− √ − 00H
FF56H Clock selection register 6 CKSR6 R/W − √ − 00H
FF57H Baud rate generator control register 6 BRGC6 R/W − √ − FFH
FF58H Asynchronous serial interface control register 6 ASICL6 R/W √ √ − 16H
FF69H 8-bit timer H mode register 0 TMHMD0 R/W √ √ − 00H
FF6AH Timer clock selection register 50 TCL50 R/W − √ − 00H
FF6BH 8-bit timer mode control register 50 TMC50 R/W √ √ − 00H
FF6CH 8-bit timer H mode register 1 TMHMD1 R/W √ √ − 00H
FF70H Asynchronous serial interface operation mode
register 0Note 1 ASIM0 R/W √ √ − 01H
FF71H Baud rate generator control register 0Note 1 BRGC0 R/W − √ − 1FH
FF72H Receive buffer register 0Note 1 RXB0 R
− √ − FFH
FF73H Asynchronous serial inte rface reception error
status register 0Note 1 ASIS0 R
− √ − 00H
FF74H Transmit shift register 0Note 1 TXS0 W
− √ − FFH
FF80H Serial operation mode register 10 CSIM10 R/W √ √ − 00H
FF81H Serial clock selection register 10 CSIC10 R/W √ √ − 00H
FF84H Transmit buffer register 10 SOTB10 R/W − √ − Undefined
FF98H Watchdog timer mode register WDTM R/W − √ − 67H
FF99H Watchdog timer enable register WDTE R/W − √ − 9AH
FFA0H Ring-OSC mode registe r RCM R/W √ √ − 00H
FFA1H Main clock mode register MCM R/W √ √ − 00H
FFA2H Main OSC control register MOC R/W √ √ − 00H
FFA3H Oscillation stabilization time counter status
register OSTC R
√ √ − 00H
FFA4H Oscillation stabilization time select register OSTS R/W − √ − 05H
FFA9H Clock monitor mode register CLM R/W √ √ − 00H
FFACH Reset control flag register RESF R − √ − 00HNote 2
FFBAH 16-bit timer mode control register 00 TMC00 R/W √ √ − 00H
FFBBH Prescaler mode register 00 PRM00 R/W √ √ − 00H
Notes 1.
µ
PD780102, 780103, and 78F0103 only.
2. This value varies depending on the reset source.
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User’s Manual U15836EJ4V0UD
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Table 3-5. Special Function Register List (3/3)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FFBCH Capture/compare control register 00 CRC00 R/W √ √ − 00H
FFBDH 16-bit timer output control register 00 TOC00 R/W √ √ − 00H
FFBEH Low-voltage detection register LVIM R/W √ √ − 00H
FFBFH Low-voltage detection level selection register LVIS R/W − √ − 00H
FFE0H Interrupt request flag register 0L IF0 IF0L R/W √ √ √ 00H
FFE1H Interrupt request flag register 0H IF0H R/W √ √ 00H
FFE2H Interrupt request flag register 1L IF1L R/W √ √ − 00H
FFE4H Interrupt mask flag register 0L MK0 MK0L R/W √ √ √ FFH
FFE5H Interrupt mask flag register 0H MK0H R/W √ √ FFH
FFE6H Interrupt mask flag register 1L MK1L R/W √ √ − FFH
FFE8H Priority specification flag register 0L PR0 PR0L R/W √ √ √ FFH
FFE9H Priority specification flag register 0H PR0H R/W √ √ FFH
FFEAH Priority specification flag register 1L PR1L R/W √ √ − FFH
FFF0H Internal memory size switching registerNote IMS R/W − √ − CFH
FFFBH Processor clock control register PCC R/W √ √ − 00H
Note The default value of IMS is fixed (IMS = CFH) in all products in the 78K0/KB1 regardless of the internal
memory capacity. Therefore, set the following value to each product.
Internal Memory Size Switching Register (IMS)
µ
PD780101 42H
µ
PD780102 04H
µ
PD780103 06H
µ
PD78F0103 Value corresponding to mask ROM version
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 55
3.3 Instruction Address Addressing
An instruction address is determined by program counter ( PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branc hed by
the following addressing (for deta ils of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as sign ed two’s complement data (−128 to +127) and bit 7 becom es a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
+
15 0
876
S
15 0
PC
α
jdisp8
When S = 0, all bits of are 0.
When S = 1, all bits of are 1.
PC indicates the start address
of the instruction after the BR instruction.
...
α
α
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User’s Manual U15836EJ4V0UD
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program co unter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is ex ecuted.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
15 0
PC
87
70
CALL or BR
Low Addr.
High Addr.
In the case of CALLF !addr11 instruction
15 0
PC
87
70
fa10–8
11 10
00001
643
CALLF
fa7–0
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 57
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operati on cod e are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
15 1
15 0
PC
70
Low Addr.
High Addr.
Memory (Table)
Effective address+1
Effective address 01
00000000
87
87
65 0
0
111
765 10
ta
4–0
Operation code
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the progr am counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
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User’s Manual U15836EJ4V0UD
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulat or (A and AX) among the general-purpose registers is a utomatically
(implicitly) addressed.
Of the 78K0/KB1 instruction words, the following instructions empl oy implied addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied a ddressing can be automatically em ployed with an instruction, no particular operand f ormat is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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User’s Manual U15836EJ4V0UD 59
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following o perand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be describ ed by absolute na mes (R0 to R7 and RP0 to RP 3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code 01100010
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 10000100
Register specify code
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3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 10001110 OP code
00000000 00H
11111110 FEH
[Illustration]
Memory
07
addr16 (lower)
addr16 (upper)
OP code
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User’s Manual U15836EJ4V0UD 61
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed s pace is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte sp ace FE20H to FF1FH. Internal RAM and special function r egisters
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated w ith a small number of bytes and clocks.
When 8-bit immediat e data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. Refer to the [Illustration].
[Operand format]
Identifier Description
saddr Immediate data that indicate label or FE20H to FF1FH
saddrp Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code 11110010 OP code
00110000 30H (saddr-offset)
[Illustration]
15 0Short direct memory
Effective address 1111111
87
07
OP code
saddr-offset
α
When 8-bit immediate data is 20H to FFH,
α
= 0
When 8-bit immediate data is 00H to 1FH,
α
= 1
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3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and F F E0H to FFFFH. However, t he SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
sfrp 16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 1 1110110 OP code
0 0100000 20H (sfr-offset)
[Illustration]
15 0SFR
Effective address 1111111
87
07
OP code
sfr-offset
1
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User’s Manual U15836EJ4V0UD 63
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operan d addr ess for address ing the memory. This addressi ng can be
carried out for all the memory spaces.
[Operand format]
Identifier Description
− [DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code 10000101
[Illustration]
16 08
D
7
E
07
7 0
A
DE
The contents of the memory
addressed are transferred.
Memory
The memory address
specified with the
register pair DE
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64
3.4.7 Based addressing
[Function]
8-bit immediate data is adde d as offset data to the contents of the base register, that is , the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is p erformed by expanding the offset data as a positive number to 16 bits. A car ry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code 10101110
00010000
[Illustration]
16 08
H
7
L
07
7 0
A
HL
The contents of the memory
addressed are transferred.
Memory +10
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15836EJ4V0UD 65
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified i n an instruction word are added to t he contents of the bas e register, that
is, the HL register pair in the register bank s pecified by the register bank select flag (RBS0 and RB S1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier Description
− [HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B] (selecting B register)
Operation code 10101011
[Illustration]
16 0
H
78
L
07
B
+
07
7 0
A
HL
The contents of the memory
addressed are transferred.
Memory
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon gener ation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
In the case of PUSH DE (saving DE register)
Operation code 10110101
[Illustration]
E
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
D
Memory 07
FEDEH
User’s Manual U15836EJ4V0UD 67
CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power
supplies and the pins is show n below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P23
VDD Pins other than P20 to P23
78K0/KB1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P30
Port 3
P33
P23
Port 12 P120
Port 2
P00
Port 0
P03
P10
Port 1
P17
P20
Port 13 P130
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User’s Manual U15836EJ4V0UD
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Table 4-2. Port Functions
Pin Name I/O Function After Reset Alternate Function
P00 TI000
P01 TI010/TO00
P02
P03
I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
−
P10 SCK10/TxD0Note
P11 SI10/RxD0Note
P12 SO10
P13 TxD6
P14 RxD6
P15 TOH0
P16 TOH1/INTP5
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input
TI50/TO50
P20 to P23 Input Port 2.
4-bit input-only port. Input ANI0 to ANI3
P30 to P33 I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input INTP1 to INTP4
P120 I/O
Port 12.
1-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input INTP0
P130 Output
Port 13.
1-bit output-only port. Output −
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
4.2 Port Configuration
A port includes the following hardwar e.
Table 4-3. Port Configuration
Item Configuration
Control registers Port mode register (PM0, PM1, PM3, PM12)
Port register (P0 to P3, P12, P13)
Pull-up resistor option register (PU0, PU1, PU3, PU12)
Port Total: 22 (CMOS I/O: 17, CMOS input: 4, CMOS output: 1)
Pull-up resistors Total: 17 (software control only)
CHAPTER 4 PORT FUNCTIONS
User’s Manual U15836EJ4V0UD 69
4.2.1 Port 0
Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor o ption register 0 (PU0).
This port can also be used for timer I/O.
RESET input sets port 0 to input mode.
Figures 4-2 to 4-4 show block diagrams of port 0.
Figure 4-2. Block Diagram of P00
P00/TI000
WR
PU
RD
WR
PORT
WR
PM
PU00
PU0
Alternate function
Output latch
(P00)
PM00
PM0
V
DD
P-ch
Selector
Internal bus
PU0: Pull-up resistor option re gister 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
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Figure 4-3. Block Diagram of P01
P01/TI010/TO00
WRPU
RD
WRPORT
WRPM
PU01
Alternate
function
Output latch
(P01)
PM01
PU0
PM0
Alternate
function
VDD
P-ch
Selector
Internal bus
PU0: Pull-up resistor option re gister 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
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User’s Manual U15836EJ4V0UD 71
Figure 4-4. Block Diagram of P02 and P03
WR
PU
RD
WR
PORT
WR
PM
PU02, PU03
Output latch
(P02, P03)
PM02, PM03
PU0
PM0
V
DD
P-ch
P02, P03
Selector
Internal bus
PU0: Pull-up resistor option re gister 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
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User’s Manual U15836EJ4V0UD
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4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor o ption register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
RESET input sets port 1 to input mode.
Figures 4-5 to 4-9 show block diagrams of port 1.
Caution When using P10/SCK10 (/TxD0Note), P11/SI10 (/RxD0Note), and P12/SO10 as general-purpose ports,
do not write to serial clock selection register 10 (CSIC10).
Figure 4-5. Block Diagram of P10
P10/SCK10 (/TxD0Note)
WRPU
RD
WRPORT
WRPM
PU10
Alternate
function
Output latch
(P10)
PM10
PU1
PM1
Alternate
function
VDD
P-ch
Selector
Internal bus
Note Available only in the
µ
PD780102, 780103, an d 78F0103.
PU1: Pull-up resistor option re gister 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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User’s Manual U15836EJ4V0UD 73
Figure 4-6. Block Diagram of P11 and P14
P11/SI10 (/RxD0Note),
P14/RxD6
WRPU
RD
WRPORT
WRPM
PU11, PU14
Alternate
function
Output latch
(P11, P14)
PM11, PM14
PU1
PM1
VDD
P-ch
Selector
Internal bus
Note Available only in the
µ
PD780102, 780103, an d 78F0103.
PU1: Pull-up resistor option re gister 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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Figure 4-7. Block Diagram of P12 and P15
P12/SO10,
P15/TOH0
WR
PU
RD
WR
PORT
WR
PM
PU12, PU15
Output latch
(P12, P15)
PM12, PM15
PU1
PM1
Alternate
function
V
DD
P-ch
Selector
Internal bus
PU1: Pull-up resistor option re gister 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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User’s Manual U15836EJ4V0UD 75
Figure 4-8. Block Diagram of P13
P13/TxD6
WR
PU
RD
WR
PORT
WR
PM
PU13
Output latch
(P13)
PM13
PU1
PM1
Alternate
function
V
DD
P-ch
Internal bus
Selector
PU1: Pull-up resistor option re gister 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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Figure 4-9. Block Diagram of P16 and P17
P16/TOH1/INTP5,
P17/TI50/TO50
WRPU
RD
WRPORT
WRPM
PU16, PU17
Alternate
function
Output latch
(P16, P17)
PM16, PM17
PU1
PM1
Alternate
function
VDD
P-ch
Selector
Internal bus
PU1: Pull-up resistor option re gister 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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User’s Manual U15836EJ4V0UD 77
4.2.3 Port 2
Port 2 is a 4-bit input-only port.
This port can also be used for A/D converter analog input.
Figure 4-10 shows a block diagram of port 2.
Figure 4-10. Block Diagram of P20 to P23
RD
A/D converter P20/ANI0 to P23/ANI3
Internal bus
RD: Read signal
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4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor o ption register 3 (PU3).
This port can also be used for external interrupt request input.
RESET input sets port 3 to input mode.
Figure 4-11 shows a block diagram of port 3.
Figure 4-11. Block Diagram of P30 to P33
P30/INTP1 to
P33/INTP4
WR
PU
RD
WR
PORT
WR
PM
PU30 to PU33
Alternate
function
Output latch
(P30 to P33)
PM30 to PM33
PU3
PM3
V
DD
P-ch
Selector
Internal bus
PU3: Pull-up resistor option re gister 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
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User’s Manual U15836EJ4V0UD 79
4.2.5 Port 12
Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When the P120 pin is used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor optio n register 12 (PU12).
This port can also be used for external interrupt input.
RESET input sets port 12 to input mode.
Figure 4-12 shows a block diagram of port 12.
Figure 4-12. Block Diagram of P120
P120/INTP0
WR
PU
RD
WR
PORT
WR
PM
PU120
Alternate
function
Output latch
(P120)
PM120
PU12
PM12
V
DD
P-ch
Selector
Internal bus
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
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4.2.6 Port 13
Port 13 is a 1-bit output-only port.
Figure 4-13 shows a block diagram of port 13.
Figure 4-13. Block Diagram of P130
RD
Output latch
(P130)
WR
PORT
P130
Internal bus
RD: Read signal
WR××: Write signal
Remark When r eset is effected, P130 outputs a low l evel. If P130 is set to output a hi gh level immediately after
reset is released, the output signal of P130 c an be dummy-output as the reset signal to the CPU.
4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers.
• Port mode registers (PM0, PM1, PM3, PM12)
• Port registers (P0 to P3, P12, P13)
• Pull-up resistor option registers (PU0, PU1, PU3, PU12)
(1) Port mode registers (PM0, PM1, PM3, and PM12)
These registers specify input or output mode for the port in 1-bit un its.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as al ternate-functi on p ins, set the port mo de reg i ster and output latch as show n i n Table
4-3.
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User’s Manual U15836EJ4V0UD 81
Figure 4-14. Format of Port Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W
PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W
PM12 1 1 1 1 1 1 1 PM120 FF2CH FFH R/W
PMmn Pmn pin I/O mode selection
(m = 0, 1, 3, 12; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Table 4-4. Settings of Port Mode Register and Output Latch When Alternate Function Is Used
Alternate Function Pin Name
Name I/O
PM×× P××
P00 TI000 Input 1 ×
TI010 Input 1
×
P01
TO00 Output 0 0
Input 1
×
SCK10
Output 0 1
P10
TxD0Note Output 0 1
SI10 Input 1
×
P11
RxD0Note Input 1
×
P12 SO10 Output 0 0
P13 TxD6 Output 0 1
P14 RxD6 Input 1 ×
P15 TOH0 Output 0 0
TOH1 Output 0 0 P16
INTP5 Input 1
×
TI50 Input 1
×
P17
TO50 Output 0 0
P30 to P33 INTP1 to INTP4 Input 1 ×
P120 INTP0 Input 1 ×
Note TxD0 and RxD0 are availa ble only in the
µ
PD780102, 780103, and 78F0103.
Remark ×: Don’t care
PM××: Port mode register
P××: Port output latch
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(2) Port registers (P0 to P3, P12, P13)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the outp ut mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H (but P2 is undefined).
Figure 4-15. Format of Port Register
7
0
Symbol
P0
6
0
5
0
4
0
3
P03
2
P02
1
P01
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
7
P17
P1
6
P16
5
P15
4
P14
3
P13
2
P12
1
P11
0
P10 FF01H 00H (output latch) R/W
R
7
0
P2
6
0
5
0
4
0
3
P23
2
P22
1
P21
0
P20 FF02H Undefined
7
0
P3
6
0
5
0
4
0
3
P33
2
P32
1
P31
0
P30 FF03H 00H (output latch) R/W
7
0
P12
6
0
5
0
4
0
3
0
2
0
1
0
0
P120 FF0CH 00H (output latch) R/W
7
0
P13
6
0
5
0
4
0
3
0
2
0
1
0
0
P130 FF0DH 00H (output latch) R/W
m = 0 to 3, 12, 13; n = 0 to 7
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
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User’s Manual U15836EJ4V0UD 83
(3) Pull-up resistor option registers (PU0, PU1, PU3, and PU12)
These registers specify whet her the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P 33, or P120 is to
be used or not. An on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the
pins to which the use of an on-chip pull-up resistor has been specified. On-chip pull-up resistor cannot be
connected for bits set to output mode and bits used as alternate-functi on output pins, regardless of the settings of
PU0, PU1, PU3 and PU12.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 4-16. Format of Pull-up Resistor Option Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PU0 0 0 0 0 PU03 PU02 PU01 PU00 FF30H 00H R/W
7 6 5 4 3 2 1 0
PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W
7 6 5 4 3 2 1 0
PU3 0 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W
7 6 5 4 3 2 1 0
PU12 0 0 0 0 0 0 0 PU120 FF3CH 00H R/W
PUmn Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3, 12; n = 0 to 7)
0 On-chip pull-up resistor not connected
1 On-chip pull-up resistor connected
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the
output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the
pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin st atus does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. T he output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
User’s Manual U15836EJ4V0UD 85
CHAPTER 5 CLOCK GENERATO R
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two system clock oscillators are available.
• X1 oscillator
The X1 osc illator oscillates a clock of fXP = 2.0 to 10.0 MHz . Oscillation can b e stopped by exec uting the STOP
instruction or setting the main OSC control register (MOC).
• Ring-OSC oscillator
The Ring-OSC oscillator oscillates a clock of fR = 240 kHz (TYP.). Oscillation can be stopped by setting the
Ring-OSC mode register (RCM) when “Can be stopped by software” is set by a mask option and the X1 input
clock is used as the CPU clock.
Remarks 1. fXP: X1 input clock oscillation fre quency
2. fR: Ring-OSC clock oscillation frequency
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers Processor clock control register (PCC)
Ring-OSC mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillator X1 oscillator
Ring-OSC oscillator
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Figure 5-1. Block Diagram of Clock Generator
X1
X2 X1 oscillator f
XP
f
X
2
2
Internal bus
Ring-OSC mode
register (RCM)
STOP
MSTOP
Main OSC
control register
(MOC)
f
X
2
3
f
X
2
4
f
X
2
3
Internal bus
Ring-OSC
oscillator
Mask option
1: Cannot be stopped
0. Can be stopped
RSTOP
Controller
PCC1 PCC0
Control
signal
CPU
clock
(f
CPU
)
f
CPU
Processor clock
control register
(PCC)
PCC2
MCM0
MCS
Main clock
mode register
(MCM)
OSTS1 OSTS0OSTS2
X1 oscillation
stabilization time counter
Oscillation
stabilization time
select register
(OSTS)
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
Oscillation
stabilization
time counter
status register
(OSTC)
f
R
Clock to peripheral
hardware
Prescaler
Operation
clock switch
f
X
8-bit timer H1,
watchdog timer
Prescaler
Prescaler
Selector
C
P
U
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15836EJ4V0UD 87
5.3 Registers Controlling Clock Generator
The following six registers are used to control the clock generator.
• Processor clock control register (PCC)
• Ring-OSC mode register (RCM)
• Main clock mode register (MCM)
• Main OSC control register (MOC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC)
This register sets the division ratio of the CPU clock.
PCC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-2. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PCC 0 0 0 0 0 PCC2 PCC1 PCC0
CPU clock selection (fCPU)
PCC2 PCC1 PCC0
MCM0 = 0 MCM0 = 1
0 0 0 fX fR fXP
0 0 1 fX/2 fR/2 fXP/2
0 1 0 fX/22 fR/22 fXP/22
0 1 1 fX/23 fR/23 fXP/23
1 0 0 fX/24 fR/24 fXP/24
Other than above Setting prohibited
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
2. fX: Main system clock oscillation freque ncy (X1 input clock oscillation frequency or Ri ng-OSC clock
oscillation frequency)
3. fR: Ring-OSC clock oscillation frequency
4. fXP: X1 input clock oscill ation frequency
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The fastest instruction can be executed in 2 c locks of the CP U clock in the 78K0/KB1. Therefore, the r elations hip
between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 2/fCPU CPU Clock (fCPU)Note
X1 Input Clock
(at 10 MHz Operation) Ring-OSC Clock
(at 240 kHz (TYP.) Operation)
fX 0.2
µ
s 8.3
µ
s (TYP.)
fX/2 0.4
µ
s 16.6
µ
s (TYP.)
fX/22 0.8
µ
s 33.2
µ
s (TYP.)
fX/23 1.6
µ
s 66.4
µ
s (TYP.)
fX/24 3.2
µ
s 132.8
µ
s (TYP.)
Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC
clock) (see Figure 5-4).
(2) Ring-OSC mode register (RCM)
This register sets the operation mode of Ring-OSC.
This register is valid when “Can be stopped by softwar e” is set for Ring-O SC by a mask option, and th e X1 input
clock is input to the CPU clock. If “Cannot be stopped” is selected for Ring-OSC by a mask option, settings for
this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-3. Format of Ring-OSC Mode Register (RCM)
Address: FFA0H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
RCM 0 0 0 0 0 0 0 RSTOP
RSTOP Ring-OSC oscillating/stopped
0 Ring-OSC oscillating
1 Ring-OSC stopped
Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting
RSTOP.
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User’s Manual U15836EJ4V0UD 89
(3) Main clock mode register (MCM)
This register sets the CPU clock (X1 input clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-4. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/WNote
Symbol 7 6 5 4 3 2 <1> <0>
MCM 0 0 0 0 0 0 MCS MCM0
MCS CPU clock status
0 Operates with Ring-OSC clock
1 Operates with X1 input clock
MCM0 Selection of clock supplied to CPU
0 Ring-OSC clock
1 X1 input clock
Note Bit 1 is read-only.
Caution When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (fX) is supplied to the peripheral
hardware (fX = 240 kHz (TYP.)).
Operation of the peripheral hardware with the Ring-OSC clock cannot be
guaranteed. Therefore, when the Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the clock supplied to the CPU from the X1 input clock to
the Ring-OSC clock. Note, however, that the following peripheral hardware can be
used when the CPU operates on the Ring-OSC clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when fR/27 is selected as the count clock
• Peripheral hardware with an external clock selected as the clock source
(Except when the external count clock of TM00 is selected (TI000 valid edge))
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(4) Main OSC control register (MOC)
This register selects the operation mode of the X1 input clock.
This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock.
Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-5. Format of Main OSC Control Register (MOC)
Address: FFA2H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
MOC MSTOP 0 0 0 0 0 0 0
MSTOP Control of X1 oscillator operation
0 X1 oscillator operating
1 X1 oscillator stopped
Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting
MSTOP.
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User’s Manual U15836EJ4V0UD 91
(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1 clear OSTC to 00H.
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16
MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status
1 0 0 0 0 211/fXP min. (204.8
µ
s min.)
1 1 0 0 0 213/fXP min. (819.2
µ
s min.)
1 1 1 0 0 214/fXP min. (1.64 ms min.)
1 1 1 1 0 215/fXP min. (3.27 ms min.)
1 1 1 1 1 216/fXP min. (6.55 ms min.)
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
3. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz.
2. f
XP: X1 input clock oscillation frequency
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15836EJ4V0UD
92
(6) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released.
The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as the CPU
clock. After STOP mode is released with Ring-OSC selected as the CPU clock, the oscillation stabilization time
must be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
0 0 1 211/fXP (204.8
µ
s)
0 1 0 213/fXP (819.2
µ
s)
0 1 1 214/fXP (1.64 ms)
1 0 0 215/fXP (3.27 ms)
1 0 1 216/fXP (6.55 ms)
Other than above Setting prohibited
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
2. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. Values in parentheses are reference values for operation with fXP = 10 MHz.
2. f
XP: X1 input clock oscillation frequency
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15836EJ4V0UD 93
5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or cer amic resonator (Standard: 10 MHz) connected to the X1
and X2 pins.
An external clock can be input to the X1 oscillator. In this case, input t he clock signal to the X1 pin and in put the
inverse signal to the X2 pin.
Figure 5-8 shows the external circuit of the X1 oscill ator.
Figure 5-8. External Circuit of X1 Oscillator
(a) Crystal, ceramic oscillation (b) External clock
V
SS
X1
X2
Crystal resonator or
ceramic resonator
External
clock X1
X2
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
Figure 5-9 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Figure 5-9 shows examples of incorrect resonator connection.
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Figure 5-9. Examples of Incorrect Resonator Connection
(a) Too long wiring (b) Crossed signal line
X2V
SS
X1 X1V
SS
X2
PORT
(c) Wiring near high alternating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
SS
X1 X2
V
SS
X1 X2
AB C
Pmn
V
DD
High current
High current
(e) Signals are fetched
V
SS
X1 X2
CHAPTER 5 CLOCK GENERATOR
User’s Manual U15836EJ4V0UD 95
5.4.2 Ring-OSC oscillator
A Ring-OSC oscillator is incorporated in the 78K0/KB1.
“Can be stopped by software” or “Cannot be stopped” can be selected by a mask option. The Ring-OSC clock
always oscillates after RESET release (240 kHz (TYP.)).
5.4.3 Prescaler
The prescaler generates v arious clocks by dividing the X1 oscillator output when the X1 input clock is selected as
the clock to be supplied to the CPU.
Caution When the Ring-OSC clock is sel ected as the clock supplied to the CPU, the prescaler generates
various clocks by dividing the Ring-OSC oscillator output (fX = 240 kHz (TYP.)).
5.5 Clock Generator Operation
The clock generator generat es the following clocks and controls the o peration modes of the CPU, such as sta ndby
mode.
• X1 input clock fXP
• Ring-OSC clock fR
• CPU clock fCPU
• Clock to peripheral hardware
The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the
78K0/KB1, thus enabling the followin g.
(1) Enhancement of security function
When the X1 input clock is set as the CPU clock by the default setting, the device c annot operate if the X1 input
clock is damaged or badly connected and th erefore does not operate after reset is released. However, the start
clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset
release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut
down by performing a minimum operation, such as acknowledging a reset source by software or performing
safety processing when there is a malfunction.
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(2) Improvement of performance
Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total
performance can be improved.
A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-10.
Figure 5-10. Timing Diagram of CPU Default Start Using Ring-OSC
Ring-OSC clock
(fR)
CPU clock
X1 input clock
(fXP)
Operation
stopped: 17/fR
X1 oscillation stabilization time: 211/fXP to 216/fXPNote
RESET
Ring-OSC clock X1 input clock
Switched by software
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signa l is generated, bit 0 of the main cloc k mode register (MCM) is set to 0 and the Ring-
OSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the Ring-OSC
clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the
RESET period, oscillation of the X1 input clock and Ring-OS C clock is stopped.
(b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock usi ng bit
0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has
elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter
status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1
(MCS) of MCM.
(c) Ring-OSC can be s et to sto pped/oscillating using the Ring-OSC mode re gister (RCM) when “Can be stopped
by software” is selected for the Ri ng-OSC by a mask optio n, if the X1 input is used as the CPU clock. Make
sure that MCS is 1 at this time.
(d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the
main OSC control register (MOC). Make sure that MCS is 0 at this time.
(e) Select the X1 input clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using the oscillation
stabilization time select register (OSTS) when releasing STOP mode while the X1 input clock is being used
as the CPU clock. In addition, when releasing STOP mode while RESET is released and the Ring-OSC
clock is being used as the CPU clock, check the X1 input clock oscillation stabilization time using the
oscillation stabilization time counter status register (OSTC).
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User’s Manual U15836EJ4V0UD 97
A status transition diagram of this product is shown in Figure 5-11, and the relationship between the operation
clocks in each operation status and between the oscillatio n control flag and oscillatio n status of each clock are show n
in Tables 5-3 and 5-4, respectively.
Figure 5-11. Status Transition Diagram (1/2)
(1) When “Ring-OSC can be stopped by software” is selected by mask option
Status 4
CPU clock: fXP
fXP: Oscillating
f
R
: Oscillation stopped
Status 3
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
Status 1
CPU clock: fR
f
XP
: Oscillation stopped
fR: Oscillating
Status 2
CPU clock: fR
fXP: Oscillating
fR: Oscillating
HALT
Note 4
Interrupt
Interrupt
Interrupt Interrupt
Interrupt Interrupt
Reset release
Interrupt InterruptHALT
instruction
STOP
instruction
STOP
instruction
STOP
instruction
STOP
instruction
RSTOP = 0
RSTOP = 1
Note 1
MCM0 = 0
MCM0 = 1
Note 2
MSTOP = 1
Note 3
MSTOP = 0
HALT
instruction
HALT instruction
HALT
instruction
STOP
Note 4
Reset
Note 5
Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2. Before shifting from status 2 t o status 3 after reset and STOP are re leased, check the X1 input cloc k
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3. When shifting from status 2 to status 1, make sure that MCS is 0.
4. When “Ring-OSC can be stopped by software” is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-O SC does not stop even in the HALT and STOP modes if RSTOP = 0.
5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-11. Status Transition Diagram (2/2)
(2) When “Ring-OSC cannot be stopped” is selected by mask option
Status 3
CPU clock: f
XP
f
XP
: Oscillating
f
R
: Oscillating
HALT
Interrupt Interrupt
Interrupt
STOP
instruction
MCM0 = 0
MCM0 = 1
Note 1
HALT
instruction
HALT
instruction
STOP
Note 3
Reset
Note 4
Status 2
CPU clock: f
R
f
XP
: Oscillating
f
R
: Oscillating
Status 1
CPU clock: f
R
f
XP
: Oscillation stopped
f
R
: Oscillating
Interrupt
STOP
instruction
Interrupt
Interrupt
STOP
instruction
MSTOP = 1
Note 2
MSTOP = 0
HALT instruction
Reset release
Notes 1. Before shifting from status 2 to status 3 after reset a nd STOP are released, check the X1 input cl ock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2. When shifting from status 2 to status 1, make sure that MCS is 0.
3. The watchdog timer operates using Ring-OSC even in STOP mode if “Rin g-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not perform ed, an internal reset signal is generate d at watchdog timer
overflow after STOP instruction execution.
4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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User’s Manual U15836EJ4V0UD 99
Table 5-3. Relationship Between Operation Clocks in Each Operation Status
Ring-OSC Oscillator Prescaler Clock Supplied to
Peripherals
Note 2
Status
Operation
Mode
X1 Oscillator
Note 1
RSTOP = 0 RSTOP = 1
CPU Clock
After
Release MCM0 = 0 MCM0 = 1
Reset Stopped Ring-OSC Stopped
STOP
Stopped
Note 3 Stopped
HALT Oscillating
Oscillating Oscillating Stopped
Note 4 Ring-OSC X1
Notes 1. When “Cannot be stopped” is selected for Ring-OSC by a mask option.
2. When “Can be stopped by software” is selected for Ring-OSC by a mask option.
3. Operates using the CPU clock at STOP instruction execution.
4. Operates using the CPU clock at HALT instruction execution.
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC by a mask
option.
Remark RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
MCM0: Bit 0 of the main clock mode register (MCM)
Table 5-4. Oscillation Control Flags and Clock Oscillation Status
X1 Oscillator Ring-OSC Oscillator
RSTOP = 0 Stopped Oscillating MSTOP = 1
RSTOP = 1 Setting prohibited
RSTOP = 0 Oscillating MSTOP = 0
RSTOP = 1
Oscillating
Stopped
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC
by a mask option.
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
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5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
Bit 0 (MCM0) of the main cl ock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input
clock.
In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions
are executed using the pre-switch over clock after switching MCM0 (see Table 5-5).
Bit 1 (MCS) of MCM is used to judge that operation is performed using either the Ring-OSC clock or X1 input clock.
To stop the original clock after changing the clock, wait for the num ber of clocks shown in Table 5-5.
Table 5-5. Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
PCC Time Required for Switching
PCC2 PCC1 PCC0 X1→Ring-OSC Ring-OSC→X1
0 0 0 fXP/fR + 1 clock
0 0 1 fXP/2fR + 1 clock
0 1 0 fXP/4fR + 1 clock
0 1 1 fXP/8fR + 1 clock
1 0 0 fXP/16fR + 1 clock
2 clocks
Caution To calculate the maximum time, set fR = 120 kHz.
Remarks 1. PCC: Processor clock control register
2. f
XP: X1 input clock oscillation frequency
3. fR: Ring-OSC clock oscillation frequency
4. The maximum time is the number of clocks of the CPU cloc k before switching.
5.7 Time Required for CPU Clock Switchover
The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC).
The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on
the pre-switchover clock for several instructions (see Table 5-6).
Table 5-6. Maximum Time Required for CPU Clock Switchover
Set Value Before
Switchover Set Value After Switchover
PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0PCC2 PCC1 PCC0
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
0 0 0 16 clocks 16 clocks 16 clocks 16 clocks
0 0 1 8 clocks 8 clocks 8 clocks 8 clocks
0 1 0 4 clocks 4 clocks 4 clocks 4 clocks
0 1 1 2 clocks 2 clocks 2 clocks 2 clocks
1 0 0 1 clock 1 clock 1 clock 1 clock
Remark The maximum time is the number of clocks of the CPU clock before switching.
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User’s Manual U15836EJ4V0UD 101
5.8 Clock Switching Flowchart and Register Setting
5.8.1 Switching from Ring-OSC clock to X1 input clock
Figure 5-12. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
; f
CPU
= f
R
; Ring-OSC oscillation
; Ring-OSC clock operation
; X1 oscillation
; Oscillation stabilization time status register
; Oscillation stabilization time f
XP
/2
16
MCM.1 (MCS) is changed from 0 to 1
; X1 oscillation stabilization time status check
X1 oscillation stabilization time has elapsed
X1 oscillation stabilization
time has not elapsed
PCC = 00H
RCM = 00H
MCM = 00H
MOC = 00H
OSTC = 00H
OSTS = 05H
Note
OSTC check
Note
Each processing
After reset release
PCC setting
MCM.0 ← 1
X1 input clock operation
Ring-OSC
clock operation
(dividing set PCC)
Register initial
value after reset
Ring-OSC clock
operation
X1 input clock
operation
Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register
and then switch to the X1 input clock operati on after the oscillation stabilization w ait time has elapsed. The
OSTS register setting is valid only after STOP mode is released by interrupt during X1 input clock operation.
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5.8.2 Switching from X1 input clock to Ring-OSC clock
Figure 5-13. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)
MCM.1 (MCS) is changed from 1 to 0
; Ring-OSC clock operation
; Ring-OSC oscillating?
Ring-OSC clock operation
; X1 input clock operation
No: RSTOP = 0
Yes: RSTOP = 1
MCM = 03H
RCM.0
Note
(RSTOP) = 1?
RSTOP = 0
MCM0 ← 0
Register setting
in X1 input
clock operation
X1 input
clock operation
Ring-OSC
clock operation
Note Require d only when “can be stopped by software” is selected for Ring-OSC by a mask option.
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User’s Manual U15836EJ4V0UD 103
5.8.3 Register settings
The table below shows the statuses of the setting flags and status flags when each mode is set.
Table 5-7. Clock and Register Settings
Setting Flag Status Flag
MCM Register MOC Register RCM Register MCM Register
fCPU Mode
MCM0 MSTOP RSTOPNote 1 MCS
Ring-OSC oscillating 1 0 0 1 X1 input clockNote 2
Ring-OSC stopped 1 0 1 1
X1 oscillating 0 0 0 0 Ring-OSC clock
X1 stopped 0 1 0 0
Notes 1. This is valid only when “can be stopped by software” is selected for Ring-OSC by mask option.
2. Do not set MSTOP to 1 during X1 input clock operation (oscillation of X1 is not stopped even when
MSTOP = 1).
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
• Interval timer
• PPG output
• Pulse width measurement
• External event counter
• Square-wave output
• One-shot pulse output
(1) Interval timer
16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
(2) PPG output
16-bit timer/event counter 00 can o utput a rectangular wave whose freque ncy and output pulse width can be set
freely.
(3) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
(4) External event counter
16-bit timer/event counter 00 can measure the num ber of pulses of an externally input signal.
(5) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
(6) One-shot pulse output
16-bit timer/event counter 00 can output a one-shot pulse whose output pulse width can be set freely.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U15836EJ4V0UD 105
6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 includes the fol lowing hardware.
Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Item Configuration
Timer counter 16 bits (TM00)
Register 16-bit timer capture/compare register: 16 bits (CR000, CR010)
Timer input TI000, TI010
Timer output TO00, output controller
Control registers 16-bit timer mode control register 00 (TMC00)
Capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 0 (PM0)
Port register 0 (P0)
Figure 6-1 shows the block diagram.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
TI010/TO00/P01
f
X
f
X
/2
2
f
X
/2
8
f
X
TI000/P00
Prescaler mode
register 00 (PRM00)
2
PRM001 PRM000
CRC002
16-bit timer capture/compare
register 010 (CR010)
Match
Match
16-bit timer counter 00
(TM00) Clear
Noise
elimi-
nator
CRC002CRC001 CRC000
INTTM000
TO00/TI010/
P01
INTTM010
16-bit timer output
control register 00
(TOC00)
16-bit timer mode
control register 00
(TMC00)
Internal bus
TMC003 TMC002
TMC001
OVF00
TOC004
LVS00 LVR00
TOC001
TOE00
Selector
16-bit timer capture/compare
register 000 (CR000)
Selector
Selector
Selector
Noise
elimi-
nator
Noise
elimi-
nator
Output
controller
OSPE00
OSPT00
Output latch
(P01)
PM01
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U15836EJ4V0UD
106
(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the input clock.
Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)
TM00
Symbol FF11H FF10H
Address: FF10H, FF11H After reset: 0000H R
The count value is reset to 0000H in the following cases.
<1> At RESET input
<2> If TMC003 and TMC002 are cleared
<3> If the valid edge of TI000 is input in the mode in wh ich clear & start occurs when inputting the valid edge of
TI000
<4> If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000
<5> OSPT00 is set in one-shot pulse output mode
(2) 16-bit timer capture/compare register 000 (CR00 0)
CR000 is a 16-bit re gister that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/c ompare control register
00 (CRC00).
CR000 can be set by a 16-bit memory manipulation instructi on.
RESET input clears CR000 to 0000H.
Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)
CR000
Symbol FF13H FF12H
Address: FF12H, FF13H After reset: 0000H R/W
• When CR000 is used as a compare register
The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM000) is generated if they match. The set value is held until C R000 is rewritten.
• When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or
TI010 pin valid edge is set using prescaler mode register 00 (PRM00) (see Table 6-2).
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User’s Manual U15836EJ4V0UD 107
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
TI000 Pin Valid Edge CR000 Capture Trigger
ES001 ES000
Falling edge Rising edge 0 1
Rising edge Falling edge 0 0
No capture operation Both rising and falling edges 1 1
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
TI010 Pin Valid Edge CR000 Capture Trigger
ES101 ES100
Falling edge Falling edge 0 0
Rising edge Rising edge 0 1
Both rising and falling edges Both rising and falling edges 1 1
Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited.
2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
ES101, ES100: Bits 7 and 6 of prescaler mode register 00 (PRM00)
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match
of TM00 and CR000. However, in the free-running mode and in the clear mode using the
valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated
when the value of CR000 changes from 0000H to 0001H following overflow (FFFFH).
2. When P01 is used as the valid edge input pin of TI010, it cannot be used as the timer output
(TO00). Moreover, when P01 is used as TO00, it cannot be used as the valid edge input pin
of TI010.
3. When CR000 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
4. Do not rewrite CR000 during TM00 operation.
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User’s Manual U15836EJ4V0UD
108
(3) 16-bit timer capture/compare register 010 (CR01 0)
CR010 is a 16-bit re gister that has the functions of both a capture register and a compare register. Whether it is
used as a capt ure register or a compare reg ister is set by bit 2 (CRC0 02) of capture/com pare control register 00
(CRC00).
CR010 can be set by a 16-bit memory manipulation instructi on.
RESET input clears CR010 to 0000H.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
CR010
Symbol FF15H FF14H
Address: FF14H, FF15H After reset: 0000H R/W
• When CR010 is used as a compare register
The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and
an interrupt request (INTTM010) is generated if they match. The set value is held until CR010 is rewritten.
• When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
prescaler mode register 00 (PRM00) (see Table 6-3).
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
TI000 Pin Valid Edge CR010 Capture Trigger
ES001 ES000
Falling edge Falling edge 0 0
Rising edge Rising edge 0 1
Both rising and falling edges Both rising and falling edges 1 1
Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited.
2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
CRC002: Bit 2 of capture/compare control register 00 (CRC00)
Cautions 1. If the CR010 register is cleared to 0000H, an interrupt request (INTTM010) is generated after
the TM00 register overflows, after the timer is cleared and started on a match between the
TM00 register and the CR000 register, or after the timer is cleared by the valid edge of TI000
or a one-shot trigger.
2. When CR010 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
3. CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U15836EJ4V0UD 109
6.3 Registers Controlling 16-Bit Timer/Event Counter 00
The following six registers are used to control 16-bit timer/event counter 00.
• 16-bit timer mode control register 00 (TMC00)
• Capture/compare control register 00 (CRC00)
• 16-bit timer output control register 00 (TOC00)
• Prescaler mode register 00 (PRM00)
• Port mode register 0 (PM0)
• Port register 0 (P0)
(1) 16-bit timer mode control register 00 (TMC00)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output
timing, and detects an overflow.
TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC00 to 00H.
Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to
values other than 0, 0 (operation stop mode), respectively. Clear TMC002 and TMC003 to 0, 0 t o
stop operation.
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User’s Manual U15836EJ4V0UD
110
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address FFBAH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00
TMC003 TMC002 TMC001 Operating mode and clear
mode selection TO00 inversion timing
selection Interrupt request
generation
0 0 0
0 0 1
Operation stop
(TM00 cleared to 0) No change Not generated
0 1 0 Free-running mode Match between TM00 and
CR000 or match between
TM00 and CR010
0 1 1 Match between TM00 and
CR000, match between
TM00 and CR010 or TI000
valid edge
1 0 0
1 0 1
Clear & start occurs on TI000
valid edge −
1 1 0
Clear & start occurs on match
between TM00 and CR000 Match between TM00 and
CR000 or match between
TM00 and CR010
1 1 1 Match between TM00 and
CR000, match between
TM00 and CR010 or TI000
valid edge
Generated on match
between TM00 and CR000,
or match between TM00
and CR010
OVF00 16-bit timer counter 00 (TM00) overflow detection
0 Overflow not detected
1 Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
3. If any of the following modes: the mode in which clear & start occurs on match between
TM00 and CR000, the mode in which clear & start occurs at the TI00 valid edge, or free-
running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes
from FFFFH to 0000H, the OVF00 flag is set to 1.
Remark TO00: 16-bit timer/event counter 00 output pin
TI000: 16-bit timer/event counter 00 input pin
TM00: 16-bit timer counter 00
CR000: 16-bit timer capture/compare register 000
CR010: 16-bit timer capture/compare register 010
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User’s Manual U15836EJ4V0UD 111
(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit timer capture/ compare registers (CR000, CR010).
CRC00 can be set by a 1-bit or 8-bit memory manip ulation instruction.
RESET input clears CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CRC00 0 0 0 0 0 CRC002 CRC001 CRC000
CRC002 CR010 operating mode selection
0 Operates as compare register
1 Operates as capture register
CRC001 CR000 capture trigger selection
0 Captures on valid edge of TI010
1 Captures on valid edge of TI000 by reverse phase
CRC000 CR000 operating mode selection
0 Operates as compare register
1 Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC00.
2. When the mode in which clear & start occurs on a match between TM00 and CR000 is
selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified
as a capture register.
3. The capture operation is not performed if both the rising and falling edges are specified as
the valid edge of TI000.
4. To ensure that the capture operation is performed properly, the capture trigger requires a
pulse two cycles longer than the count clock selected by prescaler mode register 00
(PRM00).
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter 00 output c ontroller. It sets/resets the timer
output F/F (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output,
enables/disables the one-s hot pulse output operation, and sets the one-shot pulse output trigger via software.
TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC00 to 00H.
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Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH After reset: 00H R/W
Symbol 7 <6> <5> 4 <3> <2> 1 <0>
TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
OSPT00 One-shot pulse output trigger control via software
0 No one-shot pulse trigger
1 One-shot pulse trigger
OSPE00 One-shot pulse output operation control
0 Successive pulse output mode
1 One-shot pulse output modeNote
TOC004 Timer output F/F control using match of CR010 and TM00
0 Disables inversion operation
1 Enables inversion operation
LVS00 LVR00 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F reset (0)
1 0 Timer output F/F set (1)
1 1 Setting prohibited
TOC001 Timer output F/F control using match of CR000 and TM00
0 Disables inversion operation
1 Enables inversion operation
TOE00 Timer output control
0 Disables output (output fixed to level 0)
1 Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between
the TM00 register and CR000 register, one-s hot pulse output is not possible because an overflow does not
occur.
Cautions 1. Timer operation must be stopped before setting other than TOC004.
2. LVS00 and LVR00 are 0 when they are read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required to write to OSPT00 successively.
6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously.
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User’s Manual U15836EJ4V0UD 113
(4) Prescaler mode register 00 (PRM00)
This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges.
PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PRM00 to 00H.
Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PRM00 ES101 ES100 ES001 ES000 0 0 PRM001 PRM000
ES101 ES100 TI010 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES001 ES000 TI000 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
PRM001 PRM000 Count clock selection
0 0 fX (10 MHz)
0 1 fX/22 (2.5 MHz)
1 0 fX/28 (39.06 kHz)
1 1 TI000 valid edgeNote
Note The external clock requ ires a pulse two cycles longer than the internal clock (fX).
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed. When an
external clock is used and when the Ring-OSC clock is selected and supplied to the CPU, the
operation of 16-bit timer/event counter 00 is not guaranteed, either, because the Ring-OSC
clock is supplied as the sampling clock to eliminate noise.
2. Always set data to PRM00 after stopping the timer operation.
3. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode
using the valid edge of TI000 and the capture trigger.
4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00
(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when re-
enabling operation after the operation has been stopped once, the rising edge is not
detected.
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Caution 5. When P01 is used as the TI010 valid edge input pin, it cannot be used as the timer output
(TO00), and when used as TO00, it cannot be used as the TI010 valid edge input pin.
Remarks 1. fX: X1 input clock oscillation frequency
2. TI000, TI010: 16-bit timer/event counter 00 input p in
3. Figures in parentheses are for operation with fX = 10 MHz.
(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latch of P01 to 0.
Clear PM01 to 0 to when using the P01/ TO00/TI010 pin as a timer input pin. The output l atch of P01 at this time
may be 0 or 1.
PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM0 to FFH.
Figure 6-9. Format of Port Mode Register 0 (PM0)
7
1
6
1
5
1
4
1
3
PM03
2
PM02
1
PM01
0
PM00
Symbol
PM0
Address: FF20H After reset: FFH R/W
PM0n
0
1
P0n pin I/O mode selection (n = 0 to 3)
Output mode (output buffer on)
Input mode (output buffer off)
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User’s Manual U15836EJ4V0UD 115
6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
Setting 16-bit timer mode control reg ister 00 (TMC00) and capture/com pare control register 00 (C RC00) as shown
in Figure 6-10 allows operatio n as an interval timer.
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-10 for the set value).
<2> Set any value to the CR000 register.
<3> Set the count clock by using the PRM000 register.
<4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value).
Caution CR000 cannot be rewritten during TM00 operation.
Remark For how to enable the INTTM000 i nterrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.
Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register
000 (CR000) as the interval.
When the count value of 16-bit timer count er 00 (TM00) matches the value set in CR000, counting continues with
the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.
The count clock of the 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of
prescaler mode register 00 (PRM00).
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Figure 6-10. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0/1
OVF0
0
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
0/1
ES000
0/1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
description of the respective control registers for details.
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Figure 6-11. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00
(TM00) OVF00
Clear
circuit
INTTM000
f
X
f
X
/2
2
f
X
/2
8
TI000/P00
Selector
Noise
eliminator
f
X
Note
Note OVF00 is set to 1 only when CR000 is set to FFFFH.
Figure 6-12. Timing of Interval Timer Operation
Count clock
t
TM00 count value
CR000
INTTM000
0000H
0001H
N
0000H 0001H
N
0000H 0001H
N
NNNN
Timer operation enabled Clear Clear
Interrupt acknowledged Interrupt acknowledged
Remark Interval time = (N + 1) × t
N = 0001H to FFFFH
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6.4.2 PPG output operations
Setting 16-bit timer mode control reg ister 00 (TMC00) and capture/com pare control register 00 (C RC00) as shown
in Figure 6-13 allows operatio n as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-13 for the set value).
<2> Set any value to the CR000 register as the cycle.
<3> Set any value to the CR010 register as the duty factor.
<4> Set the TOC00 register (see Figure 6-13 for the set value).
<5> Set the count clock by using the PRM00 register.
<6> Set the TMC00 register to start the operation (see Figure 6-13 for the set value).
Caution To change the value of the duty factor (the value of the CR010 register) during operation, see
Caution 2 in Figure 6-15 PPG Output Operation Timing.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR00 0), resp ectively.
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Figure 6-13. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0
CRC001
×
CRC000
0CRC00
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00
0
OSPE00
0
TOC004
1
LVS00
0/1
LVR00
0/1
TOC001
1
TOE00
1TOC00
Enables TO00 output
Inverts output on match between TM00 and CR000
Specifies initial value of TO00 output F/F (setting “11” is prohibited.)
Inverts output on match between TM00 and CR010
Disables one-shot pulse output
(d) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
0/1
ES000
0/1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Cautions 1. Values in the following range should be set in CR000 and CR010:
0000H ≤ CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark ×: Don’t care
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Figure 6-14. Configuration of PPG Output
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00
(TM00) Clear
circuit
Noise
eliminator
f
X
f
X
f
X
/2
2
f
X
/2
8
TI000/P00
16-bit timer capture/compare
register 010 (CR010)
TO00/TI010/P01
Selector
Output controller
Figure 6-15. PPG Output Operation Timing
t
0000H 0000H
0001H
0001H
M − 1
Count clock
TM00 count value
TO00
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
N
CR000 capture value
CR010 capture value M
M
N − 1
NN
ClearClear
Cautions 1. CR000 cannot be rewritten during TM00 operation.
2. In the PPG output operation, change the pulse width (rewrite CR010) during TM00 operation
using the following procedure.
<1> Disable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 0)
<2> Disable the INTTM010 interrupt (TMMK010 = 1)
<3> Rewrite CR010
<4> Wait for 1 cycle of the TM00 count clock
<5> Enable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 1)
<6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0)
<7> Enable the INTTM010 interrupt (TMMK010 = 0)
Remark 0000H ≤ M < N ≤ FFFFH
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6.4.3 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer
counter 00 (TM00).
There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate
the necessary pulse width. Clear the overflow flag after che cking it.
The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by
prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating
noise with a short pulse width.
Figure 6-16. CR010 Capture Operation with Rising Edge Specified
Count clock
TM00
TI000
Rising edge detection
CR010
INTTM010
N − 3N − 2N − 1 N N + 1
N
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set the TMC00 register to start the operation (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).
Caution To use two capture registers, set the TI000 and TI010 pins.
Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 14 INTERRUPT
FUNCTIONS.
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(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode
register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare
register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Specify both the rising and falling e dges by using bits 4 and 5 (ES000 and ES001) of PRM00.
Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed
when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.
Figure 6-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register (When TI000 and CR010 Are Used)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
0
TMC002
1
TMC001
0/1
OVF00
0TMC00
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
1
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter
f
X
f
X
/2
2
f
X
/2
8
TI000
16-bit timer counter 00
(TM00) OVF00
16-bit timer capture/compare
register 010 (CR010)
Internal bus
INTTM010
Selector
Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
0000H 0000H
FFFFH
0001H
D0
D0
Count clock
TM00 count value
TI000 pin input
CR010 capture value
INTTM010
OVF00
(D1 – D0) × t (D3 – D2) × t(10000H – D1 + D2) × t
D1 D2 D3
D2 D3
D0 + 1
D1
D1 + 1
Note
Note Clear OVF00 by software.
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(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure
the pulse widths of the two signals input to the TI000 pin an d the TI010 pin.
When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to
the TI000 pin, the value of TM00 is tak en into 16-bit timer capture/comp are register 010 (CR010) and an i nterrupt
request signal (INTTM010) is set.
Also, when the edge specified by bits 6 and 7 (ES100 a nd ES101) of PRM00 is input to the TI010 pin, the value
of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal
(INTTM000) is set.
Specify both the rising and falling edg es as the edges of the TI000 and TI010 pins, by u sing bits 4 and 5 (ES000
and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00.
Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), a nd a capture operati on is
only performed when th e valid level of the TI000 pi n or TI010 pin is detected twice, t hus eliminating noise with a
short pulse width.
Figure 6-20. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
0
TMC002
1
TMC001
0/1
OVF00
0TMC00
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
0
CRC000
1CRC00
CR000 used as capture register
Captures valid edge of TI010 pin to CR000
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101
1
ES100
1
ES001
1
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Specifies both edges for pulse width detection.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
0000H 0000H
FFFFH
0001H
D0
D0
TI010 pin input
CR000 capture value
INTTM010
INTTM000
OVF00
(D1 – D0) × t (D3 – D2) × t(10000H – D1 + D2) × t
(10000H – D1 + (D2 + 1)) × t
D1
D2 + 1D1
D2
D2 D3
D0 + 1
D1
D1 + 1 D2 + 1 D2 + 2
Count clock
TM00 count value
TI000 pin input
CR010 capture value
Note
Note Clear OVF00 by software.
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(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 00 (TM00) is o perated in free-running mode, it is possible to measure the pulse widt h
of the signal input to the TI000 pin.
When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00
(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010
(CR010) and an interrupt request signal (INTTM010) is set.
Also, when the inverse ed ge to that of the capture operation is in put into CR010, the value of TM00 is taken into
16-bit timer capture/compare register 000 (CR000).
Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), a nd a capture operati on is
only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse
width.
Figure 6-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
0
TMC002
1
TMC001
0/1
OVF00
0TMC00
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
1
CRC000
1CRC00
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
0
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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User’s Manual U15836EJ4V0UD 127
Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
0000H 0000H
FFFFH
0001H
D0
D0
INTTM010
OVF00
D2
D1 D3
D2 D3
D0 + 1 D2 + 1
D1
D1 + 1
CR000 capture value
Count clock
TM00 count value
TI000 pin input
CR010 capture value
(D1 – D0) × t (D3 – D2) × t(10000H – D1 + D2) × t
Note
Note Clear OVF00 by software.
(4) Pulse width measurement by means of restart
When input of a valid edge to the TI000 pin i s detected, the count value of 16- bit timer counter 00 (TM0 0) is taken
into 16-bit timer capture/compare register 010 (CR01 0), and then the pulse width of the signal input to the TI00 0
pin is measured by clearing T M 00 and restarting the count operation.
Either of two edgesrising or falli ngcan be selected usi ng bits 4 and 5 (ES000 and ES001) of prescaler mode
register 00 (PRM00).
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a
capture operation is only performed when the valid l evel of the TI000 pin is detected twic e, thus eliminating noise
with a short pulse width.
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Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
0
TMC001
0/1
OVF00
0TMC00
Clears and starts at valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
1
CRC000
1CRC00
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of TI000.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
0
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Figure 6-25. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified)
t
0000H 0001H0000H0001H 0000H 0001H
D0
D0
INTTM010
D1 × t
D2 × t
D2
D1
D2D1
CR000 capture value
Count clock
TM00 count value
TI000 pin input
CR010 capture value
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User’s Manual U15836EJ4V0UD 129
6.4.4 External event counter operation
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see Figure 6-26 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set any value to the CR000 register (0000H cannot be set).
<4> Set the TMC00 register to start the operation (see Figure 6-26 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.
The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer
counter 00 (TM00).
TM00 is incremented each time the valid ed ge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR00 0 (a count operation with 1-bit pulse cannot be carried out).
Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of
prescaler mode register 00 (PRM00).
Sampling is performed using the internal clock (fX) and an operation is only performed when the valid level of the
TI000 pin is detected twice, thus eliminating noise with a short pulse width.
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Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0/1
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
0
ES000
1
3
0
2
0
PRM001
1
PRM000
1PRM00
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U15836EJ4V0UD 131
Figure 6-27. Configuration Diagram of External Event Counter
f
X
Internal bus
16-bit timer capture/compare
register 000 (CR000)
Match
Clear
OVF00
Note
Noise eliminator 16-bit timer counter 00 (TM00)
Valid edge of TI000
INTTM000
Note OVF00 is set to 1 only when CR000 is set to FFFFH.
Figure 6-28. External Event Counter Operation Timing (with Rising Edge Specified)
TI000 pin input
TM00 count value
CR000
INTTM000
0000H 0001H 0002H 0003H 0004H 0005H
N − 1N
0000H 0001H 0002H 0003H
N
Caution When reading the external event counter count value, TM00 should be read.
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6.4.5 Square-wave output operation
Setting
The basic operation setting procedure is as follows.
<1> Set the count clock by using the PRM00 register.
<2> Set the CRC00 register (see Figure 6-29 for the set value).
<3> Set the TOC00 register (see Figure 6-29 for the set value).
<4> Set any value to the CR000 register (0000H cannot be set).
<5> Set the TMC00 register to start the operation (see Figure 6-29 for the set value).
Caution CR000 cannot be rewritten during TM00 operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.
A square wave with any selected freque ncy can be output at intervals determined by the count val ue preset to 16-
bit timer capture/compare register 000 (CR000).
The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 +1 by setting
bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a squar e wav e
with any selected frequency to be output.
Figure 6-29. Control Register Settings in Square-Wave Output Mode (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
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User’s Manual U15836EJ4V0UD 133
Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2)
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00
0
OSPE00
0
TOC004
0
LVS00
0/1
LVR00
0/1
TOC001
1
TOE00
1TOC00
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting “11” is prohibited).
Does not invert output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES001
0/1
ES000
0/1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows a nother function to be used s imultaneously with square-wave o utput. See the
description of the respective control registers for details.
Figure 6-30. Square-Wave Output Operation Timing
Count clock
TM00 count value
CR000
INTTM000
TO00 pin output
0000H 0001H 0002H
N − 1N
0000H 0001H 0002H
N − 1N
0000H
N
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6.4.6 One-shot pulse output operation
16-bit timer/event counter 00 can o utput a one-shot pulse in synchroniz ation with a software trigger or an external
trigger (TI000 pin input).
Setting
The basic operation setting procedure is as follows.
<1> Set the count clock by using the PRM00 register.
<2> Set the CRC00 register (see Figures 6-31 and 6-33 for the set value).
<3> Set the TOC00 register (see Figures 6-31 and 6-33 for the set value).
<4> Set any value to the CR000 and CR010 registers (0000 H cannot be set).
<5> Set the TMC00 register to start the operation (see Figures 6-31 and 6-33 for the set value).
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 14
INTERRUPT FUNCTIONS.
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-31, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit timer capture/com pare register 010 (CR010). After that, the
output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000
(CR000)Note.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00
register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 regist er. Do not set N to M.
Cautions 1. Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the one-
shot pulse again, wait until the current one-shot pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
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Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 00 (TMC00)
0000
7654
0
TMC003
TMC00
TMC002 TMC001 OVF00
Free-running mode
100
(b) Capture/compare control register 00 (CRC00)
00000
76543
CRC00
CRC002 CRC001 CRC000
CR000 as compare register
CR010 as compare register
0 0/1 0
(c) 16-bit timer output control register 00 (TOC00)
0
7
0 1 1 0/1
TOC00
LVR00LVS00TOC004OSPE00OSPT00 TOC001 TOE00
Enables TO00 output
Inverts output upon match
between TM00 and CR000
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010
Sets one-shot pulse output mode
Set to 1 for output
0/1 1 1
(d) Prescaler mode register 00 (PRM00)
0/1 0/1 0/1 0/1 0
PRM00
PRM001 PRM000
Selects count clock.
Setting invalid
(setting “10” is prohibited.)
0 0/1 0/1
ES101 ES100 ES001 ES000
Setting invalid
(setting “10” is prohibited.)
32
Caution Do not set 0000H to the CR000 and CR010 registers.
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Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger
0000H N
NN N N
MM M M
NMN + 1 N – 1 M – 1
0001H
M + 1 M + 2
0000H
Count clock
TM00 count
CR010 set value
CR000 set value
OSPT00
INTTM010
INTTM000
TO00 pin output
Set TMC00 to 0CH
(TM00 count starts)
Caution 16-bit timer counter 00 starts operating as soon as the TMC003 and TMC002 bits are set to a
value other than 00 (operation stop mode).
Remark N < M
(2) One-shot pulse output with external trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-33, and by using the valid edge of the TI000 pin as an external trigger.
The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES001) of prescaler mode register 00
(PRM00). The rising, falling, or both the rising and falling edges can be specified.
When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the
output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010).
After that, the output becomes inactiv e at the count value set in advance to 16-bit timer capture/compare reg ister
000 (CR000)Note.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 regist er. Do not set N to M.
Caution Even if the external trigger is generated again while the one-shot pulse is being output, it is
ignored.
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User’s Manual U15836EJ4V0UD 137
Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
0000
7654
1
TMC003
TMC00
TMC002 TMC001 OVF00
Clears and starts at
valid edge of TI000 pin
000
(b) Capture/compare control register 00 (CRC00)
00000
76543
CRC00
CRC002 CRC001 CRC000
CR000 used as compare register
CR010 used as compare register
0 0/1 0
(c) 16-bit timer output control register 00 (TOC00)
0
7
011 0/1
TOC00
LVR00 TOC001 TOE00OSPE00OSPT00 TOC004 LVS00
Enables TO00 output
Inverts output upon match
between TM00 and CR000
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010
Sets one-shot pulse output mode
0/1 1 1
(d) Prescaler mode register 00 (PRM00)
0/1 0/1 0 1
PRM00
PRM001 PRM000
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
0/1 0/1
ES101 ES100 ES001 ES000
Setting invalid
(setting “10” is prohibited.)
00
32
Caution Do not set the CR000 and CR010 registers to 0000H.
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Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
0000H N
NN N N
MM M M
MN + 1 N + 2 M + 1 M + 2M − 2M − 1
0001H
0000H
Count clock
TM00 count value
CR010 set value
CR000 set value
TI000 pin input
INTTM010
INTTM000
TO00 pin output
When TMC00 is set to 08H
(TM00 count starts)
t
Caution 16-bit timer counter 00 starts operating as soon as the TMC002 and TMC003 bits are set to a
value other than 00 (operation stop mode).
Remark N < M
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U15836EJ4V0UD 139
6.5 Cautions for 16-Bit Timer/Event Counter 00
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Figure 6-35. Start Timing of 16-Bit Timer Counter 00 (TM00)
TM00 count value
0000H 0001H 0002H 0004H
Count clock
Timer start
0003H
(2) 16-bit timer capture/compare register setting (in the mode in which clear & start occurs on match
between TM00 and CR000)
Set 16-bit timer capture/comp are registers 0 00, 010 ( CR00 0, CR010) to other than 000 0 H. This m eans a 1- pulse
count operation cannot be performed when 16-bit timer/event counter 00 is used as an event counter.
(3) Capture register data retention timing
The values of 16-bit timer capture/compare registers 0 00 and 010 (CR000 and CR010) are not guaranteed after
16-bit timer/event counter 00 has been stopped.
(4) Valid edge setting
Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 an d TMC003) of 16-bit timer mode c ontrol
register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4
and 5 (ES000 and ES001) of prescal er mode register 00 (PRM00).
(5) Re-triggering one-shot pulse
(a) One-shot pulse output by software
When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again
until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a
match with the CR010 register, occurs.
(b) One-shot pulse output with external trigger
If the external trigger occurs again while a one-shot pu lse is output, it is ignored.
(c) One-shot pulse output function
When using the one-shot pu lse output of 16-bit timer/ev ent counter 00 wit h a software trigger, do not chang e
the level of the TI000 pin or its alternate function port pin.
Because the external trigger is valid even i n this case, the timer is cleared and started even at the level of the
TI000 pin or its alternate function port pin, re sulting in the output of a pulse at an undesired timing.
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(6) Operation of OVF00 flag
<1> The OVF00 flag is also set to 1 in the following case.
When of the following modes: the mode in which clear & start occurs on a match between TM00 and
CR000, the mode in which clear & start occurs on a TI00 valid edge, or the free-runni ng mode, is selected
↓
CR000 is set to FFFFH
↓
TM00 is counted up from FFFFH to 0000H.
Figure 6-36. Operation Timing of OVF00 Flag
Count clock
CR000
TM00
OVF00
INTTM000
FFFFH
FFFEH FFFFH 0000H 0001H
<2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the
occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.
(7) Conflicting operations
Conflict between the read period of the 16-bit timer capture/compare re gister (CR000/CR 010) and capture trigge r
input (CR000/CR010 used as capture regis ter)
Capture trigger input has priority. The data read from CR000/CR010 is undefined.
Figure 6-37. Capture Register Data Retention Timing
Count clock
TM00 count value
Edge input
INTTM010
Capture read signal
CR010 capture value
N N + 1 N + 2 M M + 1 M + 2
X N + 2
Capture, but
read value is
not guaranteed
Capture
M + 1
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(8) Timer operation
<1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare
register 010 (CR010).
<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins
are not acknowledged.
<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 valid edge. In the mode i n which clear & start occurs on a match between
the TM00 register and CR0 00 register, one-shot pulse o utput is not possible because an overflow does not
occur.
(9) Capture operation
<1> If TI000 vali d edge is specified as the count clock, a c apture operation by the capture register specified as
the trigger for TI000 is not possible.
<2> To ensure the reliability of the capture operati on, the capt ure trigger require s a p ulse two c ycles l onger th an
the count clock selected by prescaler mode r egister 00 (PRM00).
<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input
(INTTM000/INTTM010), however, is generated at the rise of the next count clock.
(10) Compare operation
A capture operation may not be performed for CR00 0/CR010 set in compare mode even if a capture trigger has
been input.
(11) Edge detection
<1> If the TI000 or TI010 pin is high lev el immediately after system reset and the rising edge or both the rising
and falling edges are specified as the valid edge of the TI000 or TI010 p in to enable the 16-bit timer cou nter
00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful
therefore when pullin g up the TI000 or TI010 pin. However, the risin g edge is not detected at restart after
the operation has been stopped once.
<2> The sampling clock used to eliminate noise differs when the TI000 valid edge is used as the count clock
and when it is used as a capture trigg er. In the former case, the count clock is fX, and i n the latter case the
count clock is selected by prescaler mode r egister 00 (PRM00). The capture oper ation is started only after
a valid level is detected twice by sampling th e valid edge, thus eliminating noise with a short pulse width.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
7.1 Functions of 8-Bit Timer/Event Counter 50
8-bit timer/event counter 50 has the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
Figure 7-1 shows the block diagram of 8-bit timer/event counter 50.
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
8-bit timer compare
register 50 (CR50)
TI50/TO50/P17
fX/22
fX/26
fX/28
fX/213
fX
fX/2
Match
Mask circuit
OVF
Clear
3
Selector
TCL502 TCL501 TCL500
Timer clock selection
register 50 (TCL50)
Internal bus
TCE50
TMC506
LVS50 LVR50
TMC501
TOE50
Invert
level
8-bit timer mode control
register 50 (TMC50)
S
R
SQ
R
INV
Selector
To TMH0
To UART0
To UART6
INTTM50
TO50/
TI50/P17
Note 1
Note 2
Selector
8-bit timer
counter 50 (TM50)
Selector
Output latch
(P17)
PM17
Notes 1. Timer output F/F
2. PWM output F/F
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7.2 Configuration of 8-Bit Timer/Event Counter 50
8-bit timer/event counter 50 includes the following hardware.
Table 7-1. Configuration of 8-Bit Timer/Event Counter 50
Item Configuration
Timer register 8-bit timer counter 50 (TM50)
Register 8-bit timer compare register 50 (CR50)
Timer input TI50
Timer output TO50
Control registers Timer clock selection register 50 (TCL50)
8-bit timer mode control register 50 (TMC50)
Port mode register 1 (PM1)
Port register 1 (P1)
(1) 8-bit timer counter 50 (TM50)
TM50 is an 8-bit register that counts the count pulses and is read-only.
The counter is incremented is synchronization with the rising edge of the count clock.
Figure 7-2. Format of 8-Bit Timer Counter 50 (TM50)
Symbol
TM50
Address: FF16H After reset: 00H R
In the following situations, the count value is cleared to 00H.
<1> RESET input
<2> When TCE50 is cleared
<3> When TM50 and CR50 match in clear & start mode if this mode was entered upon a match of TM50 and
CR50 values.
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(2) 8-bit timer compare register 50 (CR50)
CR50 can be read and written by an 8-bit memory manipulation instruction.
Except in PWM mode, the v alue set in CR50 is constantly comp ared wit h the 8- bit timer counter 50 (TM50) c ount
value, and an interrupt request (INTTM50) is generated if they match.
In PWM mode, when the TO50 pin becomes high level due to a TM50 overflow and the values of TM50 and
CR50 match, the TO50 pin becomes inactive.
The value of CR50 can be set within 00H to FFH.
RESET input clears this register to 00H.
Figure 7-3. Format of 8-Bit Timer Compare Register 50 (CR50)
Symbol
CR50
Address: FF17H After reset: 00H R/W
Cautions 1. In the clear & start mode entered on a match of TM50 and CR50 (TMC506 = 0), do not write
other values to CR50 during operation.
2. In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock
selected by TCL50) or more.
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7.3 Registers Controlling 8-Bit Timer/Event Co unter 50
The following four registers ar e used to co ntrol 8-bit timer/event counter 50.
• Timer four selection register 50 (TCL50)
• 8-bit timer mode control register 50 (TMC50)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Timer clock selection register 50 (TCL50)
This register sets the count clock of 8-bit timer/event counter 50 and the valid edge of TI50 input.
TCL50 can be set by an 8-bit memory manip ulation instruction.
RESET input clears this register to 00H.
Figure 7-4. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL50 0 0 0 0 0 TCL502 TCL501 TCL500
TCL502 TCL501 TCL500 Count clock selection
0 0 0 TI50 falling edge
0 0 1 TI50 rising edge
0 1 0 fX (10 MHz)
0 1 1 fX/2 (5 MHz)
1 0 0 fX/22 (2.5 MHz)
1 0 1 fX/26 (156.25 kHz)
1 1 0 fX/28 (39.06 kHz)
1 1 1 fX/213 (1.22 kHz)
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer/event counter 50 is not guaranteed.
2. When rewriting TCL50 to other than the same data, stop the timer operation beforehand.
3. Be sure to set bits 3 to 7 to 0.
Remarks 1. f
X: X1 input clock oscillation frequency
2. Figures in parentheses a pply to operation at fX = 10 MHz.
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
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(2) 8-bit timer mode control register 50 (TMC50)
TMC50 is a register that performs the following five types of settings.
<1> 8-bit timer counter 50 (TM50) count operation control
<2> 8-bit timer counter 50 (TM50) operating mode selection
<3> Timer output F/F (flip-flop) status setting
<4> Active level selection in timer F/F control or PWM (free-running) mode
<5> Timer output control
TMC50 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 7-5 shows the TMC50 format.
Figure 7-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH After reset: 00H R/W
Symbol <7> 6 5 4 <3> <2> 1 <0>
TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50
TCE50 TM50 count operation control
0 After clearing to 0, count operation disabled (counter stopped)
1 Count operation start
TMC506 TM50 operating mode selection
0 Clear & start mode by match between TM50 and CR50
1 PWM (free-running) mode
LVS50 LVR50 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F reset (0)
1 0 Timer output F/F set (1)
1 1 Setting prohibited
In other modes (TMC506 = 0) In PWM mode (TMC506 = 1) TMC501
Timer F/F control Active level selection
0 Inversion operation disabled Active high
1 Inversion operation enabled Active low
TOE50 Timer output control
0 Output disabled (TM50 outputs the low level)
1 Output enabled
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
User’s Manual U15836EJ4V0UD 147
Cautions 1. The settings of LVS50 and LVR50 are valid in other than PWM mode.
2. Do not rewrite following bits simultaneously.
• TMC501 and TOE50
• TMC506 and TOE50
• TMC501 and TMC506
• TMC506 and LVS50, LVR50
• TOE50 and LVS50, LVR50
3. Stop operation before rewriting TMC506.
Remarks 1. In PWM mode, PWM output is made inactive by setting TCE50 to 0.
2. If LVS50 and LVR50 are read, 0 is read.
3. The values of the TMC506, LVS50, LVR50, TMC501, and TOE50 bits are reflected at the TO50 pin
regardless of the value of TCE50.
(3) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P17/TO50/TI50 pin for timer output, set PM17 and the output latches of P17 to 0.
Set PM17 to 1 when using the P17/TO50/TI50 pin as a timer input pi n. The output latch of P17 at this ti me may
be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 7-6. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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7.4 Operations of 8-Bit Timer/Event Counter 50
7.4.1 Operation as interval timer
8-bit timer/event counter 50 operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to 8-bit timer compare register 50 (CR50).
When the count value of 8-bit timer counter 50 (TM50) matc hes the v alue set to C R50, countin g continue s with the
TM50 value cleared to 0 and an interrupt request signal (INTTM50) is generated.
The count clock of TM50 can be s elected with bits 0 to 2 ( TCL500 to TCL502) of timer clock selection register 50
(TCL50).
Setting
<1> Set the registers.
• TCL50: Select the count clock.
• CR50: Compare value
• TMC50: Stop the count operation, select clear & start mode entered on a match of TM50 and CR50.
(TMC50 = 0000×××0B × = Don’t care)
<2> After TCE50 = 1 is set, the count operation starts.
<3> If the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H).
<4> INTTM50 is generated repeatedly at the same interval.
Set TCE50 to 0 to stop the count operation.
Caution Do not write other values to CR50 during operation.
Figure 7-7. Interval Timer Operation Timing (1/2)
(a) Basic operation
t
Count clock
TM50 count value
CR50
TCE50
INTTM50
Count start Clear Clear
00H 01H N 00H 01H N 00H 01H N
NNNN
Interrupt acknowledged Interrupt acknowledged
Interval timeInterval time
Remark Interval time = (N + 1) × t
N = 00H to FFH
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User’s Manual U15836EJ4V0UD 149
Figure 7-7. Interval Timer Operation Timing (2/2)
(b) When CR50 = 00H
t
Interval time
Count clock
TM50
CR50
TCE50
INTTM50
00H 00H 00H
00H 00H
(c) When CR50 = FFH
t
Count clock
TM50
CR50
TCE50
INTTM50
01H FEH FFH 00H FEH FFH 00H
FFHFFHFFH
Interval time
Interrupt
acknowledged
Interrupt acknowledged
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7.4.2 Operation as external event counter
The external event counter counts the num ber of external clock puls es to be input to TI50 by 8-bit timer counter 50
(TM50).
TM50 is incremented each time the valid edge specified by timer clock selection register 50 (TCL50) is input.
Either the rising or falling edge can be se lected.
When the TM50 count value matches the value of 8-bit timer compare register 50 (CR50), TM50 is cleared to 0
and an interrupt request signal (INTTM50) is generated.
Whenever the TM50 count value matches the value of CR50, INTTM50 is generated.
Setting
<1> Set each register.
• Set port mode register 1 (PM17) to 1.
• TCL50: Select TI50 edge.
TI50 falling edge → TCL50 = 00H
TI50 rising edge → TCL50 = 01H
• CR50: Compare value
• TMC50: Stop the count operation, select clear & start mode entered on match of TM50 and CR50,
disable the timer F/F inversion operation, disable timer output.
(TMC50 = 0000××00B × = Don’t care)
<2> When TCE50 = 1 is set, the number of pulses input from TI50 is counted.
<3> When the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H).
<4> After these settings, INTTM50 is generated each time the values of TM50 and CR50 match.
Figure 7-8. External Event Counter Operation Timing (with Rising Edge Specified)
TI50
TM50 count value
CR50
INTTM50
00 01 02 03 04 05 N–1 N 00 01 02 03
N
Count start
N = 00H to FFH
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7.4.3 Operation as square-wave output
A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer
compare register 50 (CR50).
The TO50 pin output status is inverted at intervals determined by the count value preset to CR50 by setting bit 0
(TOE50) of 8-bit timer mode control register 50 (TMC50) to 1. This enables a square wave with any selected
frequency to be output (duty = 50%).
Setting
<1> Set each register.
• Set the port output latch (P17) and port mode register 1 (PM17) to 0.
• TCL50: Select the count clock.
• CR50: Compare value
• TMC50: Stop the count operation, select clear & start mode entered on a match of TM50 and CR50.
LVS50 LVR50 Timer Output F/F Status Setting
1 0 High-level output
0 1 Low-level output
Timer output F/F inversion enabled
Timer output enabled
(TMC50 = 00001011B or 00000111B)
<2> After TCE50 = 1 is set, the count operation starts.
<3> The timer output F/F is inverted by a match of TM50 and CR50. After INTTM50 is generated, TM50 is
cleared to 00H.
<4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from
TO50.
The frequency is as follows.
Frequency = 1/2t (N + 1)
(N: 00H to FFH)
Caution Do not write other values to CR50 during operation.
Figure 7-9. Square-Wave Output Operation Timing
Count clock
TM50 count value 00H 01H 02H N − 1N
N
00H N − 1 N 00H01H 02H
CR50
TO50
Note
t
Count start
Note The initial value of TO50 output can be set by bits 2 and 3 (LVR50, LVS50) of 8-bit timer mode control
register 50 (TMC50).
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7.4.4 Operation as PWM output
8-bit timer/event counter 50 operates as a PWM output when bit 6 (TMC506) of 8-bit tim er mode co ntrol register 5 0
(TMC50) is set to 1.
The duty pulse is determined by the value set to 8-bit timer compare register 50 (CR50).
Set the active level width of the PWM pulse to CR50; the active level can be selected with bit 1 of TMC50
(TMC501).
The count clock can be selected with bits 0 to 2 (TCL500 to TCL502) of ti mer clock selection register 50 (TCL50).
PWM output can be enabled/disabled with b it 0 of TMC50 (TOE50).
Caution In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock selected by
TCL50) or more.
(1) PWM output basic operation
Setting
<1> Set each register.
• Set the port output latch (P17) and port mode register 1 (PM17) to 0.
• TCL50: Select the count clock.
• CR50: Compare value
• TMC50: Stop the count operation, select PWM mode.
The timer output F/F is not changed, timer output is ena bled.
TMC501 Active Level Selection
0 Active-high
1 Active-low
(TMC50 = 01000001B or 010000 11B)
<2> The count operation starts when TCE50 = 1.
Set TCE50 to 0 to stop the count operation.
PWM output operation
<1> PWM output (output from TO50) outputs an inactive level until an overflow occurs.
<2> When an overflow occurs, the active level is output.
The active level is output until CR50 matches the count value of 8-bit timer counter 5 0 (TM50).
<3> After the CR50 matches the count value, the inactive level is output until an overflow occurs again.
<4> Operations <2> and <3> are repeated until the count operation stops.
<5> When the count operation is stopped with TCE50 = 0, PW M output becomes inactive.
For details of timing, see Figures 7-10 and 7-11.
The cycle, active-level width, and duty are as follows.
• Cycle = 28t
• Active-level width = Nt
• Duty = N/28
(N = 00H to FFH)
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
User’s Manual U15836EJ4V0UD 153
Figure 7-10. PWM Output Operation Timing
(a) Basic operation (active level = H)
Count clock
TM50
CR50
TCE50
INTTM50
TO50
00H 01H FFH 00H 01H 02H
N N+1
FFH 00H 01H 02H
M
00H
N
<2> Active level Active level<3> Inactive level
<1> <5>
t
(b) CR50 = 00H
Count clock
TM50
CR50
TCE50
INTTM50
TO50 L
Inactive level Inactive level
01H00H FFH 00H 01H 02H
N
N+1
FFH 00H 01H 02H
M
00H
00H
N+2
t
(c) CR50 = FFH
TM50
Count clock
CR50
TCE50
INTTM50
TO50
01H00H FFH 00H 01H 02H
N
N+1 FFH 00H 01H 02H
M
00H
FFH
N+2
Inactive level Active level Inactive level
Active level Inactive level
t
Remark <1> to <3> and <5> in Figur e 7-10 (a) correspond to <1> to <3> and <5> in PWM output oper ation in
7.4.4 (1) PWM output basic operation.
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
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(2) Operation with CR50 changed
Figure 7-11. Timing of Operation with CR50 Changed
(a) CR50 value is changed from N to M before clock rising edge of FFH
→ Value is transferred to CR50 at overflow immediately after change.
Count clock
TM50
CR50
TCE50
INTTM50
TO50
<1> CR50 change (N → M)
N
N + 1 N + 2
FFH 00H 01H
M
M + 1 M + 2
FFH 00H 01H 02H
M
M + 1 M + 2
N
02H
M
H
<2>
t
(b) CR50 value is changed from N to M after clock rising edge of FFH
→ Value is transferred to CR50 at second overflow.
Count clock
TM50
CR50
TCE50
INTTM50
TO50
N
N + 1 N + 2
FFH 00H 01H
N
N + 1 N + 2
FFH 00H 01H 02H
N
02H
N
H
M
M
M+1 M+2
<1> CR50 change (N → M) <2>
t
Caution When reading from CR50 between <1> and <2> in Figure 7-11, the value read differs from the
actual value (read value: M, actual value of CR50: N).
7.5 Cautions for 8-Bit Timer/Event Counter 50
(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counter 50 (TM50) is started asynchronously to the count clock.
Figure 7-12. 8-Bit Timer Counter 50 Start Timing
Count clock
TM50 count value 00H 01H 02H 03H 04H
Timer start
User’s Manual U15836EJ4V0UD 155
CHAPTER 8 8-BIT TIMERS H0 AN D H1
8.1 Functions of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 have the following func tions.
• Interval timer
• PWM output mode
• Square-wave output
8.2 Configuration of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 include the following hardware.
Table 8-1. Configuration of 8-Bit Timers H0 and H1
Item Configuration
Timer register 8-bit timer counter Hn
Registers 8-bit timer H compare register 0n (CMP0n)
8-bit timer H compare register 1n (CMP1n)
Timer outputs TOHn
Control registers 8-bit timer H mode register n (TMHMDn)
Port mode register 1 (PM1)
Port register 1 (P1)
Remark n = 0, 1
Figures 8-1 and 8-2 show the block di agrams.
CHAPTER 8 8-BIT TIMERS H0 AND H1
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Match
Internal bus
TMHE0
CKS02
CKS01
CKS00
TMMD01TMMD00
TOLEV0
TOEN0
8-bit timer H mode control
register 0 (TMHMD0)
8-bit timer H
compare register
10 (CMP10)
Decoder
TOH0/P15
INTTMH0
Selector
f
X
f
X
/2
f
X
/2
2
f
X
/2
6
f
X
/2
10
Interrupt
generator
Output
controller
Level
inversion
1
0
F/F
R
8-bit timer
counter H0
PWM mode signal
Timer H enable signal
Clear
32
8-bit timer H
compare register
00 (CMP00)
Selector
Output latch
(P15)
PM15
8-bit timer/
event counter 50
output
Figure 8-1. Block Diagram of 8-Bit Timer H0
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD 157
Match
Internal bus
TMHE1
CKS12
CKS11
CKS10
TMMD11TMMD10
TOLEV1
TOEN1
8-bit timer H mode control
register 1 (TMHMD1)
8-bit timer H
compare register
11 (CMP11)
Decoder TOH1/
INTP5/
P16
INTTMH1
Selector
fX
fX/22
fX/24
fX/26
fX/212
fR/27
Interrupt
generator Output
controller
Level
inversion
1
0
F/F
R
PWM mode signal
Timer H enable signal
32
8-bit timer H
compare register
01 (CMP01)
8-bit timer
counter H1
Clear
Selector
Output latch
(P16)
PM16
Figure 8-2. Block Diagram of 8-Bit Timer H1
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(1) 8-bit timer H compare register 0n (CMP0n)
This register can be read/written by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n)
Symbol
CMP0n
(n = 0, 1)
Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H R/W
76543210
Caution CMP0n cannot be rewritten during timer count operation.
(2) 8-bit timer H compare register 1n (CMP1n)
This register can be read/written by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 8-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n)
Symbol
CMP1n
(n = 0, 1)
Address: FF19H (CMP10), FF1BH (CMP11) After reset: 00H R/W
76543210
CMP1n can be rewritten during timer count operation.
If the CMP1n value is rewritten during timer operation, transfer is performed at the timing at which the counter
value and CMP1n value match. If the transfer timing and writing from CPU to CMP1n conflict, transfer is not
performed.
Caution In the PWM output mode be sure to set CMP1n when starting the timer count operation (TMHEn =
1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting
the same value to CMP1n).
Remark n = 0, 1
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User’s Manual U15836EJ4V0UD 159
8.3 Registers Controlling 8-Bit Timers H0 and H1
The following three registers are used to control 8-bit timers H0 and H1.
• 8-bit timer H mode register n (TMHMDn)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) 8-bit timer H mode register n (TMHMDn)
This register controls the mode of timer H.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark n = 0, 1
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Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
TMHE0
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE0
0
1
Timer operation enable
TMHMD0
Symbol
CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0
Address: FF69H After reset: 00H R/W
fX
fX/2
fX/22
fX/26
fX/210
TM50 outputNote
CKS02
0
0
0
0
1
1
CKS01
0
0
1
1
0
0
CKS00
0
1
0
1
0
1
(10 MHz)
(5 MHz)
(2.5 MHz)
(156.25 kHz)
(9.77 kHz)
Count clock (fCNT) selection
Setting prohibitedOther than above
Interval timer mode
PWM output mode
Setting prohibited
TMMD01
0
1
TMMD00
0
0
Timer operation mode
Low level
High level
TOLEV0
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN0
0
1
Timer output control
Other than above
<7> 6543 2 <1> <0>
Note To select the TM50 output as a count clock, start operation by setting 8-bit timer/event counter 50 in the
PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then set CKS02, CKS 01, and CKS00 to 1, 0,
and 1, respectively. Set the high/low level width of the count clock so that the specifications of the input
width of TI50 are satisfied (r efer to AC Characteri stics (1) Basic operation in CHAPTER 23 to CHAPTER
25). It is not necessary to enable the TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may
be 0 or 1).
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD 161
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed.
2. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.
3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when
starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped
(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
Remarks 1. f
X: X1 input clock oscillation frequency
2. Figures in parentheses a pply to operation at fX = 10 MHz
Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
TMHE1
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE1
0
1
Timer operation enable
TMHMD1
Symbol
CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
Address: FF6CH After reset: 00H R/W
f
X
f
X
/2
2
f
X
/2
4
f
X
/2
6
f
X
/2
12
f
R
/2
7
CKS12
0
0
0
0
1
1
CKS11
0
0
1
1
0
0
CKS10
0
1
0
1
0
1
(10 MHz)
(2.5 MHz)
(625 kHz)
(156.25 kHz)
(2.44 kHz)
(1.88 kHz (TYP.))
Count clock (f
CNT
) selection
Setting prohibitedOther than above
Interval timer mode
PWM output mode
Setting prohibited
TMMD11
0
1
TMMD10
0
0
Timer operation mode
Low level
High level
TOLEV1
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN1
0
1
Timer output control
Other than above
<7> 6543 2 <1> <0>
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Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer H1 is not guaranteed (except when CKS12,
CKS11, CKS10 = 1, 0, 1 (fR/27)).
2. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited.
3. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when
starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped
(TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).
Remarks 1. fX: X1 input clock oscillation frequ ency
2. f
R: Ring-OSC clock oscillation frequency
3. Figures in parentheses a pply to operation at fX = 10 MHz, fR = 240 kHz (TYP.).
(2) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output
latches of P15 and P16 to 0.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 8-7. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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8.4 Operation of 8-Bit Timers H0 and H1
8.4.1 Operation as interval timer/square-wave output
When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is
generated and 8-bit timer counter Hn is cleared to 00H.
Compare register 1n (CMP1n) is not used in interval timer mode. Sinc e a match of 8-bit timer cou nter Hn and the
CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
By setting bit 0 (TOENn) of timer H m ode register n (TMH MDn) to 1, a s quare w ave of any fre quency (duty = 50%)
is output from TOHn.
(1) Usage
Generates the INTTMHn signal repeatedly at the same interval.
<1> Set each register.
Figure 8-8. Register Setting During Interval Timer/Square-W ave Output Operation
(i) Setting timer H mode register n (TMHMDn)
0 0/1 0/1 0/1 0 0 0/1 0/1
TMMDn0 TOLEVn TOENnCKSn1CKSn2TMHEn
TMHMDn
CKSn0 TMMDn1
Timer output setting
Timer output level inversion setting
Interval timer mode setting
Count clock (fCNT) selection
Count operation stopped
(ii) CMP0n register setting
• Compare value (N)
<2> Count operation starts when TMHEn = 1.
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is g enerated
and 8-bit timer counter Hn is cleared to 00H.
Interval time = (N +1)/fCNT
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set
TMHEn to 0.
Remark n = 0, 1
CHAPTER 8 8-BIT TIMERS H0 AND H1
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(2) Timing chart
The timing of the interval timer/square-wave output operation is shown below.
Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation
00H
Count clock Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
01H N
Clear
Interval time
Clear
N
00H 01H N 00H 01H 00H
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<3><1>
<1> The count oper ation is enabled by settin g the TMHEn bit to 1. The count clock starts counting no m ore than
1 clock after the operation is enabled.
<2> When the values of 8-bit timer counter H n and th e CMP0n register match, the val ue of 8- bit timer count er Hn
is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.
<3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn
operation. If these are inactive from the first, the level is retained.
Remark n = 0, 1
N = 01H to FEH
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD 165
Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (2/2)
(b) Operation when CMP0n = FFH
00H
Count clock Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
01H FEH
Clear
Clear
FFH 00H FEH FFH 00H
FFH
Interval time
(c) Operation when CMP0n = 00H
Count clock Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
00H
00H
Interval time
Remark n = 0, 1
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD
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8.4.2 Operation as PWM output mode
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare regist er 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register
during timer operation is prohibited.
8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register
during timer operation is possible.
The operation in PWM output mode is as follows.
TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the
CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn
and the CMP1n register match.
(1) Usage
In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<1> Set each register.
Figure 8-10. Register Setting in PWM Output Mode
(i) Setting timer H mode register n (TMHMDn)
0 0/1 0/1 0/1 1 0 0/1 1
TMMDn0 TOLEVn TOENnCKSn1CKSn2TMHEn
TMHMDn
CKSn0 TMMDn1
Timer output enabled
Timer output level inversion setting
PWM output mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP0n register
• Compare value (N): Cycle setting
(iii) Setting CMP1n register
• Compare value (M): Duty setting
Remarks 1. n = 0, 1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of 8- bit timer counter Hn and the CMP0n register m atch, 8-bit timer cou nter Hn is clear ed,
an interrupt request signal (I NTTMHn) is generated, and TOHn output becomes active. At the s ame time,
the compare register to be c o mpared with 8- bit timer c ount er Hn is chan ged from th e C MP0n register to the
CMP1n register.
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD 167
<4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the
compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the
CMP0n register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not
generated.
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.
<6> To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock
frequency is fCNT, the PWM pulse output cycle and duty are as follows.
PWM pulse output cycle = (N+1)/fCNT
Duty = Active width : Total width of PWM = (M + 1) : (N + 1)
Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0
bits of the TMHMDn register) are required to transfer the CMP1n register value after
rewriting the register.
2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after
the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to the CMP1n register).
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD
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(2) Timing chart
The operation timing in PWM output mode is shown below.
Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Remark n = 0, 1
Figure 8-11. Operation Timing in PWM Output Mode (1/4)
(a) Basic operation
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
TOHn
(TOLEVn = 1)
00H 01H A5H 00H 01H 02H A5H 00H A5H 00H01H 02H
CMP1n
A5H
01H
<1> <2> <3> <4>
<1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one
count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0).
<2> When the v alues of 8-bit time r counter Hn and the CMP0n register match, the TOHn output level is inverted,
the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
<3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is
returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.
<4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn outp ut inactive.
Remark n = 0, 1
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD 169
Figure 8-11. Operation Timing in PWM Output Mode (2/4)
(b) Operation when CMP0n = FFH, CMP1n = 00H
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
00H 01H FFH 00H 01H 02H FFH 00H FFH 00H01H 02H
CMP1n
FFH
00H
(c) Operation when CMP0n = FFH, CMP1n = FEH
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H
CMP1n
FFH
FEH
Remark n = 0, 1
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD
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Figure 8-11. Operation Timing in PWM Output Mode (3/4)
(d) Operation when CMP0n = 01H, CMP1n = 00H
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
01H
00H 01H 00H 01H 00H 00H 01H 00H 01H
CMP1n 00H
Remark n = 0, 1
CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U15836EJ4V0UD 171
Figure 8-11. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H)
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H
CMP1n 01H
A5H
03H01H (03H)
<1> <3> <4>
<2> <2>'
<5> <6>
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count
clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0).
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer counter H n and the CMP0n register match, the val ue of 8- bit timer cou nter Hn
is cleared, the TOHn output becomes active, and the INTTMHn signal is output.
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of 8-bit timer counter Hn and the CMP1n regist er before the change match, the value is transferred to
the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a m atch signal is generated withi n three count clocks, the chan ged
value cannot be transferred to the register.
<5> When the v alues of 8-bit timer counter Hn and the CMP1n register after the change m atch, the TOHn output
becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<6> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn outp ut inactive.
Remark n = 0, 1
172 User’s Manual U15836EJ4V0UD
CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer is used to detect an ina dvertent program loop. If a program loo p is detected, an internal res et
signal is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 16 RESET FUNCTION.
Table 9-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
During Ring-OSC Clock Operation During X1 Input Clock Operation
fR/211 (8.53 ms) fXP/213 (819.2
µ
s)
fR/212 (17.07 ms) fXP/214 (1.64 ms)
fR/213 (34.13 ms) fXP/215 (3.28 ms)
fR/214 (68.27 ms) fXP/216 (6.55 ms)
fR/215 (136.53 ms) fXP/217 (13.11 ms)
fR/216 (273.07 ms) fXP/218 (26.21 ms)
fR/217 (546.13 ms) fXP/219 (52.43 ms)
fR/218 (1.09 s) fXP/220 (104.86 ms)
Remarks 1. fR: Ring-OSC clock oscillation frequency
2. f
XP: X1 input clock oscillation frequency
3. Figures in parentheses a pply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz
The operation mode of the watchdog timer (WDT) is switched according to the mask option setting of the on-chip
Ring-OSC as shown in Table 9-2.
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User’s Manual U15836EJ4V0UD 173
Table 9-2. Mask Option Setting and Watchdog Timer Operation Mode
Mask Option
Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software
Watchdog timer clock
source Fixed to fRNote 1. • Selectable by software (fXP, fR or
stopped)
• When reset is released: fR
Operation after reset Operation starts with the maximum
interval (fR/218). Operation starts with maximum
interval (fR/218).
Operation mode selection The interval can be changed only
once. The clock selection/interval can be
changed only once.
Features The watchdog timer cannot be
stopped. The watchdog timer can be stopped in
standby modeNote 2.
Notes 1. As lon g as power is be ing supplied, Rin g-OSC oscillation cann ot be stopped (except in the reset
period).
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on
the clock source of the watchdog timer.
<1> If the clock source is fXP, clock supply to the watchdog timer is stopped under the following
conditions.
• When fXP is stopped
• In HALT/STOP mode
• During oscillation stabilization time
<2> If the clock source is fR, clock supply to the watchdog timer is stopped under the following
conditions.
• If the CPU clock is fXP and if fR is stopped by software before execution of the STOP
instruction
• In HALT/STOP mode
Remarks 1. fR: Ring-OSC clock oscillation frequency
2. f
XP: X1 input clock oscillation frequency
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User’s Manual U15836EJ4V0UD
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9.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 9-3. Configuration of Watchdog Timer
Item Configuration
Control registers Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 9-1. Block Diagram of Watchdog Timer
f
R
/2
2
Clock
input
controller
Output
controller Internal reset signal
WDCS2
Internal bus
WDCS1 WDCS0
f
XP
/2
4
WDCS3WDCS4
011
Selector
16-bit
counter or
f
XP
/2
13
to
f
XP
/2
20
f
R
/2
11
to
f
R
/2
18
Watchdog timer enable
register (WDTE) Watchdog timer mode
register (WDTM)
33
2
Clear
Mask option
(to set “Ring-OSC
cannot be stopped” or
“Ring-OSC can be
stopped by software”)
CHAPTER 9 WATCHDOG TIMER
User’s Manual U15836EJ4V0UD 175
9.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the follo wing two registers.
• Watchdog timer mode register (W DTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)
0
WDCS0
1
WDCS1
2
WDCS2
3
WDCS3
4
WDCS4
5
1
6
1
7
0
Symbol
WDTM
Address: FF98H After reset: 67H R/W
WDCS4Note 1 WDCS3Note 1 Operation clock selection
0 0 Ring-OSC clock (f R)
0 1 X1 input clock (fXP)
1 × Watchdog timer operation stopped
Overflow time setting WDCS2Note 2 WDCS1Note 2 WDCS0Note 2
During Ring-OSC clock
operation During X1 input clock operation
0 0 0 fR/211 (8.53 ms) fXP/213 (819.2
µ
s)
0 0 1 fR/212 (17.07 ms) fXP/214 (1.64 ms)
0 1 0 fR/213 (34.13 ms) fXP/215 (3.28 ms)
0 1 1 fR/214 (68.27 ms) fXP/216 (6.55 ms)
1 0 0 fR/215 (136.53 ms) fXP/217 (13.11 ms)
1 0 1 fR/216 (273.07 ms) fXP/218 (26.21 ms)
1 1 0 fR/217 (546.13 ms) fXP/219 (52.43 ms)
1 1 1 fR/218 (1.09 s) fXP/220 (104.86 ms)
Notes 1. If “Ring-OSC cann ot be stopped” is specifie d by a mask option, this can not be set. The Ring-
OSC clock will be selected no matter what value is written.
2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Cautions 1. If data is written to WDTM, a wait cycle is generated. For details, see CHAPTER 28
CAUTIONS FOR WAIT.
2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “Ring-OSC cannot be stopped”
is selected by a mask option, other values are ignored).
CHAPTER 9 WATCHDOG TIMER
User’s Manual U15836EJ4V0UD
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Cautions 3. After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated.
4. WDTM cannot be set by a 1-bit memory manipulation instruction.
Remarks 1. fR: Ring-OSC clock oscillation frequency
2. f
XP: X1 input clock oscillation frequency
3. ×: Don’t care
4. Figures in parentheses a pply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz
(2) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 9AH.
Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)
01234567
Symbol
WDTE
Address: FF99H After reset: 9AH R/W
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
CHAPTER 9 WATCHDOG TIMER
User’s Manual U15836EJ4V0UD 177
9.4 Operation of Watchdog Timer
9.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option
The operation clock of watchdog timer is fixed to Ring-OSC.
After reset is released, operation is started at the maximu m cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Ring-OSC clock
• Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.))
• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2.
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4
(WDCS3, WDCS4) of WDTM, it is ignored.
2. As soon as WDTM is written, the counter of the watchdog timer is cleared.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP
instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as
the count source, so after STOP instruction execution, clear the watchdog timer using the
interrupt request of TMH1 before the watchdog timer overflows. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
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User’s Manual U15836EJ4V0UD
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9.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option
The operation clock of the watchdog timer c an be selected as either the Ring-OSC clock or the X1 input clock.
After reset is released, operation is started at the maximu m cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1) of the Ring-OSC clock.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Ring-OSC clock oscillation frequency (fR)
• Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.))
• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2, 3.
• Operation clock: Any of the following can b e selected using bits 3 and 4 (WDCS3 and WDCS4).
Ring-OSC clock (fR)
X1 input clock (fXP)
Watchdog timer operation stopped
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. As soon as W DTM is written, the counter of the watchdog timer is cleared.
2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. These bits must not be set to other values.
3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
reset signal is not generated even if the following pr ocessing is performed.
• WDTM is written a second time.
• A 1-bit memory manipulation instruction is executed to WDTE.
• A value other than AC H is written to WDTE.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
For the watchdog timer operation d uring STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer
operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode.
CHAPTER 9 WATCHDOG TIMER
User’s Manual U15836EJ4V0UD 179
9.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by
mask option)
The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or
Ring-OSC clock is being used.
(1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (fXP) when the STOP
instruction is executed
When STOP instruction is executed, o peration of the watchdog timer is stopped. After STOP mode is released,
counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
and then counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 9-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
Watchdog timer Operating Operation stopped Operating
fR
fXP
CPU operation Normal
operation STOP Oscillation stabilization time Normal operation
Oscillation
stopped Oscillation stabilization time
(set by OSTS register)
(2) When the CPU clock is the X1 input clock (fXP) and the watchdog timer operation clock is the Ring-OSC
clock (fR) when the STOP instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the o peration was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 9-5. Operation in STOP Mode
(CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
Watchdog timer Operating
f
R
f
XP
CPU operation Normal
operation STOP Oscillation stabilization time Normal operation
Oscillation
stopped Oscillation stabilization time
(set by OSTS register)
Operating Operation stopped
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User’s Manual U15836EJ4V0UD
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(3) When the CPU clock is the Ring-OSC clock (fR) and the watchdog timer operation clock is the X1 input
clock (fXP) when the STOP instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started
using the operation clock bef ore the o per ation w as stopp ed. At this time, the c ount er is not cl eare d to 0 but ho lds
its value.
<1> The oscillation stabilization time set by the oscillation stabilizatio n time select register (OSTS) elapses.
<2> The CPU clock is switched to the X1 input clock (fXP).
Figure 9-6. Operation in STOP Mode
(CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock)
<1> Timing wh en counting is started after the os cillation stabilization time set by the oscillation stabi lization time
select register (OSTS) has elapsed
Watchdog timer Operating Operation stopped Operating
fR
fXP
CPU operation
17 clocks
Normal operation
(Ring-OSC clock) Clock supply stopped
Normal operation (Ring-OSC clock)
Oscillation
stopped
STOP
Oscillation stabilization time
(set by OSTS register)
<2> Timing when counting is started after the CPU clock is switched to the X1 input clock (fXP)
Operating Operation stopped Operating
f
R
f
XP
f
R
→ f
XP
Note
CPU operation
17 clocks
Normal operation
(Ring-OSC clock)
Clock supply
stopped
Normal operation (Ring-OSC clock)
Normal operation (X1 input clock)
CPU clock
Oscillation
stopped
STOP
Oscillation stabilization time
(set by OSTS register)
Watchdog timer
Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register
(OSTC).
CHAPTER 9 WATCHDOG TIMER
User’s Manual U15836EJ4V0UD 181
(4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (fR) during STOP
instruction execution
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the o peration was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 9-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
Watchdog timer Operating
f
R
f
XP
CPU operation
17 clocks
Normal operation
(Ring-OSC clock) Clock supply stopped
Normal operation (Ring-OSC clock)
Oscillation
stopped
STOP
Oscillation stabilization time
(set by OSTS register)
Operating Operation stopped
9.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is selected by
mask option)
The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the
X1 input clock (fXP) or Ring-OSC clock (fR), or whether the operation cl ock of the watchdog timer is the X1 input clock
(fXP) or Ring-OSC clock (fR). After HALT mode is released, countin g is started again using the op eration clock before
the operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
Figure 9-8. Operation in HALT Mode
Watchdog timer Operating
f
R
f
XP
CPU operation Normal operation
Operating
HALT
Operation stopped
Normal operation
User’s Manual U15836EJ4V0UD
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CHAPTER 10 A/D CONVERTER
10.1 Function of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to
ANI3) with a resolution of 10 bits.
The A/D converter has the following two functions.
(1) 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to
ANI3. Each time an A/D conversion operation en ds, an interrupt request (INTAD) is generated.
(2) Power-fail detection function
This function is to detect a voltage drop in a battery. The values of the A/D conversion result (ADCR register
value) and power-fail comparison threshold register (PFT) are compared. INTAD is generated only when a
comparative condition has been matched.
Figure 10-1. Block Diagram of A/D Converter
AVREF
AVSS
INTAD
ADCS bit
2
ADS1 ADS0 ADCS FR2 FR1 ADCEFR0
Sample & hold circuit
AVSS
Voltage comparator
Controller
A/D conversion result
register (ADCR) Power-fail comparison
threshold register (PFT)
Analog input channel
specification register
(ADS)
A/D converter mode
register (ADM)
PFEN PFCM
Power-fail comparison
mode register (PFM)
Internal bus
Comparator
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
Successive
approximation
register (SAR)
Selector
Tap selector
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD 183
10.2 Configuration of A/D Con verter
The A/D converter includes the following hardware.
Table 10-1. Registers of A/D Converter Used on Software
Item Configuration
Registers Successive approximation register (SAR)
A/D conversion result register (ADCR)
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Power-fail comparison mode register (PFM)
Power-fail comparison threshold register (PFT)
(1) ANI0 to ANI3 pins
These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into
digital signals. Pins other than the one selected as t he analog input pin by the analog input c hannel s pecification
register (ADS) can be used as input port pi ns.
(2) Sample & hold circuit
The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D
conversion is started, and holds the sampled analog input voltage value during A/D conversion.
(3) Series resistor string
The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with
the analog input signal.
(4) Voltage comparator
The voltage comparator compares the sampled an alog input voltage and the output volta ge of the series resistor
string.
(5) Successive approximation register (SAR)
This register compares the sample d analog voltage and the voltage of th e series resistor string, and c onverts the
result, starting from the most significant bit (MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D
conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR) .
(6) A/D conversion result register (ADCR)
The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each
time A/D conversion is compl eted, and the ADCR register holds th e result of A/D conversion in its high er 10 bits
(the lower 6 bits are fixed to 0).
(7) Controller
When A/D conversion has been completed or when the power-fail detection function is used, this controller
compares the result of A/D conversion (value of the ADCR register) and the value of the power-fail comparison
threshold register (PFT). It gener ates the interrupt INTAD only if a specified com parison condition is s atisfied as
a result.
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User’s Manual U15836EJ4V0UD
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(8) AVREF pin
This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential
as that of the VDD pin even when the A/D converter is not used.
The signal input to ANI0 to AN I3 is converted into a digit al signal, based on the voltag e applie d across A V REF and
AVSS.
In the standby mode, the current flowing through the ser ies resistor string can be re duced by lower ing the voltage
input to the AVREF pin to the AVSS level.
(9) AVSS pin
This is the ground potential p in of the A/D converter. Alwa ys use this pin at the sam e potential as that of the VSS
pin even when the A/D conver ter is not used.
(10) A/D converter mode register (ADM)
This register is used to set the conversio n time of the anal og input sign al to be conver ted, and to start or stop the
conversion operation.
(11) Analog input channel specification register (ADS)
This register is used to specify the port that inputs the analog voltag e to be converted into a digital signal.
(12) Power-fail comparison mode register (PFM)
This register is used to set the power-fail monitor mode.
(13) Power-fail comparison threshold register (PFT)
This register is used to set the threshold v alue that is to be compared wit h the value of the A/D conversion res ult
register (ADCR).
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User’s Manual U15836EJ4V0UD 185
10.3 Registers Used in A/D Converter
The A/D converter uses the following five registers.
• A/D converter mode register (ADM)
• Analog input channel specific ation register (ADS)
• A/D conversion result register (ADCR)
• Power-fail comparison mode register (PFM)
• Power-fail comparison threshold register (PFT)
(1) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation in struction.
RESET input clears this register to 00H.
Figure 10-2. Format of A/D Converter Mode Register (ADM)
144 s
120 s
96 s
72 s
60 s
48 s
ADCE00FR0FR1FR20ADCS
A/D conversion operation control
Stops conversion operation
Enables conversion operation
ADCS
0
1
Conversion time selection
Note 1
288/f
X
240/f
X
192/f
X
144/f
X
120/f
X
96/f
X
Setting prohibited
FR2
0
0
0
1
1
1
Other than above
FR1
0
0
1
0
0
1
FR0
0
1
0
0
1
0
<0>123456<7>
ADM
Address: FF28H After reset: 00H R/W
Symbol
µ
µ
µ
µ
µ
µ
34.3 s
28.6 s
22.9 s
17.2 s
14.3 s
11.5 s
28.8 s
24.0 s
19.2 s
14.4 s
12.0 s
9.6 s
µ
µ
µ
µ
µ
µ
f
X
= 8.38 MHz
f
X
= 10 MHz
Boost reference voltage generator operation control
Note 2
Stops operation of reference voltage generator
Enables operation of reference voltage generator
ADCE
0
1
µ
µ
µ
µ
µ
µ
f
X
= 2 MHz
Notes 1. Set so that the A/D conversion time is as follows.
• Standard products, (A) grade products: 14
µ
s or longer but less than 100
µ
s
• (A1) grade products: 14
µ
s or longer but less than 60
µ
s
• (A2) grade products: 16
µ
s or longer but less than 48
µ
s
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Notes 2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that
generates the reference vo ltage for bo osting is co ntrolled b y ADCE, and it takes 1 4
µ
s from operation
start to operation stabilization. Therefore, when ADCS is set to 1 after 14
µ
s or more has elapsed
from the time ADCE is set to 1, the conversion res ult at that time has pri ority over the first conversion
result.
Remark f
X: X1 input clock oscillation frequency
Table 10-2. Settings of ADCS and ADCE
ADCS ADCE A/D Conversion Operation
0 0 Stop status (DC power consumption path does not exist)
0 1 Conversion waiting mode (only reference voltage generator consumes power)
1 0 Conversion mode (reference voltage generator operation stoppedNote)
1 1 Conversion mode (reference voltage generator operates)
Note Data of first conversion cannot be used.
Figure 10-3. Timing Chart When Boost Reference Voltage Generator Is Used
ADCE
Boost reference voltage
ADCS
Conversion
operation Conversion
operation Conversion stopped
Conversion
waiting
Boost reference voltage generator: operating
Note
Note The time from the rising of the ADCE bit to the falling of the ADCS bit must be 14
µ
s or longer to stabilize
the reference voltage.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the
identical data.
2. For the sampling time of the A/D converter and the A/D conversion start delay time, see (11)
in 10.6 Cautions for A/D Converter.
3. If data is written to ADM, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS
FOR WAIT.
Remark f
X: X1 input clock oscillation frequency
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD 187
(2) Analog input channel specification register (ADS)
This register specifies the analog voltag e input port to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 10-4. Format of Analog Input Channel Specification Register (ADS)
ADS0ADS1000000
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ADS0
0
1
0
1
ADS1
0
0
1
1
01234567
ADS
Address: FF29H After reset: 00H R/W
Symbol
Cautions 1. Be sure to clear bits 2 to 7 of ADS to 0.
2. If data is written to ADS, a wait cycle is generated. For details, see CHAPTER 28
CAUTIONS FOR WAIT.
(3) A/D conversion result register (ADCR)
This register is a 16-bit re gister that stores t he A/D co nversi on result. The lower six bits a re fixed to 0. E ach time
A/D conversion ends, the conversion r esult is loaded from t he successive appr oximation register, and is stored i n
ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion
result, and FF08H indicates the lower 2 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
RESET input makes ADCR undefined.
Figure 10-5. Format of A/D Conversion Result Register (ADCR)
Symbol
Address: FF08H, FF09H After reset: Undefined R
FF09H FF08H
000000
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read the
conversion result following conversion completion before writing to ADM and ADS. Using
timing other than the above may cause an incorrect conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. For details, see CHAPTER 28
CAUTIONS FOR WAIT.
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(4) Power-fail comparison mode register (PFM)
The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the
ADCR register) and the value of the power-fail comparison threshold value register (PFT).
PFM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 10-6. Format of Power-Fail Comparison Mode Register (PFM)
000000PFCMPFEN
Power-fail comparison enable
Stops power-fail comparison (used as a normal A/D converter)
Enables power-fail comparison (used for power-fail detection)
PFEN
0
1
Power-fail comparison mode selection
Interrupt request signal (INTAD) generation
No INTAD generation
INTAD generation
No INTAD generation
Higher 8 bits of
ADCR ≥ PFT
Higher 8 bits of
ADCR < PFT
Higher 8 bits of
ADCR ≥ PFT
Higher 8 bits of
ADCR < PFT
PFCM
0
1
012345<6><7>
PFM
Address: FF2AH After reset: 00H R/W
Symbol
Caution If data is written to PFM, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS
FOR WAIT.
(5) Power-fail comparison threshold register (PFT)
The power-fail comparison thr eshold re gister (PFT) is a r egi ster that sets the thres hold v alue wh en com paring the
values with the A/D conversion result.
8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result.
PFT can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 10-7. Format of Power-Fail Comparison Threshold Register (PFT)
PFT0PFT1PFT2PFT3PFT4PFT5PFT6PFT7
01234567
PFT
Address: FF2BH After reset: 00H R/W
Symbol
Caution If data is written to PFT, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS
FOR WAIT.
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User’s Manual U15836EJ4V0UD 189
10.4 A/D Converter Operations
10.4.1 Basic operations of A/D converter
<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2> Set ADCE to 1 and wait for 14
µ
s or longer.
<3> Set ADCS to 1 and start the conversion operation.
(<4> to <10> are operations performed by hardware.)
<4> The voltage input to the selected analog inp ut channel is sampled by the sample & hold circuit.
<5> When sampling has been done for a certain time, the sample & hold circ uit is placed in the hol d state and the
input analog voltage is held until the A/D conversion operatio n has ended.
<6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
(1/2) AVREF by the tap selector.
<7> The voltage difference between the series resistor string voltage tap and analog input is compared by the
voltage comparator. If the an alog input is greater th an (1/2) AVREF, the MSB of SAR remains set to 1. If the
analog input is smaller than (1/2) AVREF, the MSB is reset to 0.
<8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next com parison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVREF
• Bit 9 = 0: (1/4) AVREF
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
<9> Comparison is continued in this way up to bit 0 of SAR.
<10> Upon completion of th e comparison of 10 bit s, an effective digital res ult value remai ns in SAR, and the r esult
value is transferred to the A/D conversion result register (ADCR) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<11> Repeat steps <4> to <10>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, however, start from <2>.
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Figure 10-8. Basic Operation of A/D Converter
Conversion time
Sampling time
Sampling A/D conversion
Undefined Conversion
result
A/D converter
operation
SAR
ADCR
INTAD
Conversion
result
A/D conversion operatio ns are performed con t inuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If any of ADM, the analog input channel specification register (ADS), power-fail comparison mode register (PFM),
or power-fail comparison threshold register (PFT) is written during an A/D conversion operation, the conversion
operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning.
RESET input makes the A/D conversion result register (ADCR) undefined.
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User’s Manual U15836EJ4V0UD 191
10.4.2 Input voltage and conversion results
The relationship between th e analog inp ut voltage input to the analo g input pins (ANI0 to ANI3) and th e theoretical
A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression.
SAR = INT ( × 1024 + 0.5)
ADCR = SAR × 64
or
(ADCR − 0.5) × ≤ VAIN < (ADCR + 0.5) ×
where, INT( ): Function which returns integer part of value in parentheses
V
AIN: Analog input voltag e
AVREF: AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR: Successive approximation register
Figure 10-9 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 10-9. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
3
2
1
0
FFC0H
FF80H
FF40H
00C0H
0080H
0040H
0000H
A/D conversion result
(ADCR)
SAR ADCR
1
2048 1
1024 3
2048 2
1024 5
2048
Input voltage/AVREF
3
1024 2043
2048 1022
1024 2045
2048 1023
1024 2047
2048
1
VAIN
AVREF
AVREF
1024 AVREF
1024
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10.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One analog input channel is selected from ANI0 to
ANI3 by the analog input channel specificati on register (ADS) and A/D conversion is executed.
In addition, the following two functio ns can be selected by setting bit 7 (PFEN) of the power-fail comparison mod e
register (PFM).
• Normal 10-bit A/D converter (PFEN = 0)
• Power-fail detection function (PFEN = 1)
(1) A/D conversion operation (when PFEN = 0)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail
comparison mode regist er (PFM) to 0, A/D conversion of the voltage a pplied to the analog input pin specified by
the analog input channel specification register (ADS) is started.
When A/D conversion has been comp leted, the result of the A/D c onversion is stored in the A/D conver sion res ult
register (ADCR), and an interrupt request signal (INTAD) is generated. Once the next A/D conversion has started
and when one A/D conversion has been completed, the A/D conversion operation after that is immediately
started. The A/D conversion operations are repeated until new data is written to ADS.
If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register
(PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the
conversion result is undefined.
Figure 10-10. A/D Conversion Operation
ANIn
Rewriting ADM
ADCS = 1 Rewriting ADS ADCS = 0
ANIn
ANIn ANIn ANIm
ANIn ANIm ANIm
Stopped
A/D conversion
ADCR
INTAD
(PFEN = 0)
Conversion is stopped
Conversion result is not retained
Remarks 1. n = 0 to 3
2. m = 0 to 3
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD 193
(2) Power-fail detection function (when PFEN = 1)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail
comparison mode register (PFM) to 1, the A/D conversion oper ation of the voltage appli ed to the analog input pin
specified by the analog input chan nel specification register (ADS) is started.
When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion
result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an
interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM.
<1> When PFEN = 1 and PFCM = 0
The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only
generated when the higher 8 bits of ADCR ≥ PFT.
<2> When PFEN = 1 and PFCM = 1
The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only
generated when the higher 8 bits of ADCR < PFT.
Figure 10-11. Power-Fail Detection (When PFEN = 1 and PFCM = 0)
A/D conversion
Higher 8 bits
of ADCR
PFT
INTAD
(PFEN = 1)
ANIn ANIn
80H
80H
Condition matchFirst conversion
Note
7FH 80H
ANIn ANIn
Note If the conversion result is not read before the end of the next conversio n after INTAD is output, the result is
replaced by the next conversion result.
Remark n = 0 to 3
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The setting methods are described bel ow.
• When used as A/D conversion operation
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<2> Select the channel and conversion time using bits 1 and 0 (ADS1 and AD S0) of the analog input channel
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
<3> Set bit 7 (ADCS) of ADM to 1.
<4> An interrupt request signal (INTAD) is generated.
<5> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<Change the channel>
<6> Change the channel using bits 1 and 0 (ADS1 and ADS0) of ADS.
<7> An interrupt request signal (INTAD) is generated.
<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<Complete A/D conversion>
<9> Clear ADCS to 0.
<10> Clear ADCE to 0.
Cautions 1. Make sure the period of <1> to <3> is 14
µ
s or more.
2. It is no problem if the order of <1> and <2> is reversed.
3. <1> can be omitted. However, do not use the first conversion result after <3> in this
case.
4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.
• When used as power-fail detection function
<1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1.
<2> Set power-fail comparison condition using bi t 6 (PFCM) of PFM.
<3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<4> Select the channel and conversion time using bits 1 and 0 (ADS1 and AD S0) of the analog input channel
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
<5> Set a threshold value to the power-fail comparison threshold register (PFT).
<6> Set bit 7 (ADCS) of ADM to 1.
<7> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<8> The higher 8 bits of ADCR and PFT are com pared and an interrupt reques t signal (INTAD) is generate d
if the conditions match.
<Change the channel>
<9> Change the channel using bits 1 and 0 (ADS1 and ADS0) of ADS.
<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
< 11> The higher 8 bits of ADCR and the power-fa il comparis on threshold register (PFT) are compared and an
interrupt request signal (INTAD) is generated if the conditions match.
<Complete A/D conversion>
<12> Clear ADCS to 0.
<13> Clear ADCE to 0.
Cautions 1. Make sure the period of <3> to <6> is 14
µ
s or more.
2. It is no problem if the order of <3>, <4>, and <5> is changed.
3. <3> must not be omitted if the power-fail function is used.
4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.
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User’s Manual U15836EJ4V0UD 195
10.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Signifi cant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but i s determined by overall error.
(2) Overall error
This shows the maximum error value between the actual m easured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not includ ed in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an
analog input v oltage in a range of ±1/2LSB is converted to the same digit al code, so a quantization error cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 10-12. Overall Error Figure 10-13. Quantization Error
Ideal line
0……0
1……1
Digital output
Overall
error
Analog input AV
REF
0
0……0
1……1
Digital output
Quantization error
1/2LSB
1/2LSB
Analog input
0AVREF
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(4) Zero-scale error
This shows the difference between the actual measuremen t value of the analog input voltage an d the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the d ifference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……001 to 0……010.
(5) Full-scale error
This shows the difference between the actual measuremen t value of the analog input voltage an d the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum valu e of the differe nce betwe en th e actual m eas u rement v alu e and th e i deal str aight li ne
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1 LSB, this indicates the difference b etween the actual measurem ent value
and the ideal value.
Figure 10-14. Zero-Scale Error Figure 10-15. Full-Scale Error
111
011
010
001 Zero-scale error
Ideal line
000012 3 AV
REF
Digital output (Lower 3 bits)
Analog input (LSB)
111
110
101
000 0
AV
REF
AVREF–1AVREF–2AVREF–3
Digital output (Lower 3 bits)
Analog input (LSB)
Ideal line
Full-scale error
Figure 10-16. Integral Linearity Error Figure 10-17. Differential Linearity Error
0
AV
REF
Digital output
Analog input
Integral linearity
error
Ideal line
1……1
0……0
0
AV
REF
Digital output
Analog input
Differential
linearity error
1……1
0……0
Ideal 1LSB width
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD 197
(8) Conversion time
This expresses the time since sampling has been started until digital output is obtai ned.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time Conversion time
10.6 Cautions for A/D Conver ter
(1) Operating current in standby mode
The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by
clearing bit 7 (ADCS) of the A/D converter mode register ( ADM) to 0.
Figure 10-18 shows the circuit configuration of the series resistor string.
Figure 10-18. Circuit Configuration of Series Resistor String
AVREF
AVSS
P-ch
Series resistor string
ADCS
(2) Input range of ANI0 to ANI3
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AVREF or higher and AVSS or lower
(even in the range of absolute maximum rat ings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end
of conversion
ADCR read has priority. After the read operation, the new conversion res ul t is written to ADCR.
<2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel
specification register (ADS) write upon the end of conversion
ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal
(INTAD) generated.
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD
198
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF and ANI0 to ANI3 pins.
Because the effect increases in proportion to the output impedance of the analog input source, it is recommended
that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise.
Figure 10-19. Analog Input Pin Connection
Reference
voltage
input
C = 100 to 1,000 pF
If there is a possibility that noise equal to or higher than AV
REF
or
equal to or lower than AV
SS
may enter, clamp with a diode with a
small V
F
value (0.3 V or lower).
AV
REF
AV
SS
V
SS
ANI0 to ANI3
(5) ANI0/P20 to ANI3/P23
<1> The analog i nput pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).
When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while
conversion is in progress; otherwise the conversion resolution may be degraded.
<2> If a digital pulse is applied to the pins adjacent to the pins currently being used for A/D conversion, the
expected value of the A/D conversion may not be obtained due to coup lin g noise. Therefor e, do not appl y a
pulse to the pins adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI3 pins
In this A/D converter, the internal sampling c apacitor is charged and sampling is performed for approx. one sixth
of the conversion time.
Since only the leakage current flows other than during sampling and the current for charging the capacitor also
flows during sampling, the input impedance fluctuates and has no meaning.
To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input
source 10 kΩ or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI3 pins (s ee Figure 10-19).
(7) AVREF pin input impedance
A series resistor string of several tens of 10 kΩ is connecte d between the AVREF and AVSS pins.
Therefore, if the output impedance of the r eference volta ge source is h igh, this wi ll res ult in a ser ies c onn ection t o
the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD 199
(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just bef ore the ADS re write. Cauti on is therefore re quired sinc e, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not finished.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
INTAD
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion) ADIF is set but ANIm conversion
has not finished.
Remarks 1. n = 0 to 3
2. m = 0 to 3
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 14
µ
s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =
0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(10) A/D conversion result register (ADCR) rea d operation
When a write operation is performed to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the conte nts of ADCR may become undefin ed. Read the conversio n result following
conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an
incorrect conversion result to be read.
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD
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(11) A/D converter sampling time and A/D conversion start delay time
The A/D converter sampling time differs d ependi ng on th e set value of th e A/D conv erter mode r egister (ADM). A
delay time exists until actual sampling is start ed after A/D converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care is required regarding the
contents shown in Figure 10- 21 and Table 10-3.
Figure 10-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS
Wait
period
Conversion time Conversion time
A/D
conversion
start delay
time
Sampling
time
Sampling timing
INTAD
ADCS ← 1 or ADS rewrite
Sampling
time
Table 10-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
A/D Conversion Start Delay TimeNote FR2 FR1 FR0 Conversion Time Sampling Time
MIN. MAX.
0 0 0 288/fX 40/fX 32/fX 36/fX
0 0 1 240/fX 32/fX 28/fX 32/fX
0 1 0 192/fX 24/fX 24/fX 28/fX
1 0 0 144/fX 20/fX 16/fX 18/fX
1 0 1 120/fX 16/fX 14/fX 16/fX
1 1 0 96/fX 12/fX 12/fX 14/fX
Other than above Setting prohibited − − −
Note The A/D conversion start de lay time is the time after the wait period. For the wait function, see CHAPTER 28
CAUTIONS FOR WAIT.
Remark f
X: X1 clock oscillation frequency
CHAPTER 10 A/D CONVERTER
User’s Manual U15836EJ4V0UD 201
(12) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 10-22. Internal Equivalent Circuit of ANIn Pin
ANIn
C1 C2 C3
R1 R2
Table 10-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREF R1 R2 C1 C2 C3
2.7 V 12 kΩ 8 kΩ 8 pF 3 pF 2 pF
4.5 V 4 kΩ 2.7 kΩ 8 pF 1.4 pF 2 pF
Remarks 1. The resistance and capacitance values shown in Table 10-4 are not guaranteed values.
2. n = 0 to 3
User’s Manual U15836EJ4V0UD
202
CHAPTER 11 SERIAL INTERFACE UA RT0 (
µ
PD780102, 780103, 78F0103 ONLY)
11.1 Functions of Serial Interface UART0
Serial interface UART0 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 11.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
The functions of this mode are outlined below.
For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate
generator.
• Two-pin configuration TXD0: Transmit data output pin
R
XB0: Receive data input pin
• Length of communication data can be select ed from 7 or 8 bits.
• Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set
• Transmission and reception can be p erforme d independently.
• Four operating clock inputs selectabl e
• Fixed to LSB-first communication
Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD0 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start
communication.
3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock
after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base
clock, the transmission circuit or reception circuit may not be initialized.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 203
11.2 Configuration of Serial Interface UART0
Serial interface UART0 includes the followin g hardware.
Table 11-1. Configuration of Serial Interface UART0
Item Configuration
Registers Receive buffer register 0 (RXB0)
Receive shift register 0 (RXS0)
Transmit shift register 0 (TXS0)
Control registers Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator control register 0 (BRGC0)
Port mode register 1 (PM1)
Port register 1 (P1)
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD
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Figure 11-1. Block Diagram of Serial Interface UART0
T
x
D0/
SCK10/P10
INTST0
R
x
D0/
SI10/P11
INTSR0
f
X
/2
5
f
X
/2
3
f
X
/2
Transmit shift register 0
(TXS0)
Receive shift register 0
(RXS0)
Receive buffer register 0
(RXB0)
Asynchronous serial
interface reception error
status register 0 (ASIS0)
Asynchronous serial
interface operation mode
register 0 (ASIM0)
Baud rate generator
control register 0
(BRGC0)
8-bit timer/
event counter
50 output
Registers
77
Selector
Baud rate
generator
Baud rate
generator
Reception unit
Reception control
Filter
Internal bus
Transmission control
Transmission unit
Output latch
(P10)
PM10
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 205
(1) Receive buffer register 0 (RXB0)
This 8-bit register stores parallel data converted by receive shift register 0 (RXS0).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 0 (RXS0).
If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is
always 0.
If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.
RXB0 can be read by an 8-bit memory manipulati on instruction. No data can be written to this register.
RESET input or POWER0 = 0 sets this register to FFH.
(2) Receive shift register 0 (RXS0)
This register converts the serial data inp ut to the RXD0 pin into parallel data.
RXS0 cannot be directly manipulat ed by a program.
(3) Transmit shift register 0 (TXS0)
This register is used to set transmit data. Transmission is st arted when data is written to TXS0, and seri al data is
transmitted from the TXD0 pin.
TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read.
RESET input, POWER0 = 0, or TXE0 = 0 sets this register to FFH.
Caution Do not write the next tran smit data to TXS0 before the transmission completion interrupt signal
(INTST0) is generated.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD
206
11.3 Registers Controlling Serial Interface UART0
Serial interface UART0 is controlled by the fol lowing five registers.
• Asynchronous serial interface operation mode register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 0 (ASIM0)
This 8-bit register controls the serial communication operations of serial interface UART0.
This register can be set by a 1-bit or 8-bit memory manipulation instructio n.
RESET input sets this register to 01H.
Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
Address: FF70H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1
POWER0 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
1 Enables operation of the internal operation clock.
TXE0 Enables/disables transmission
0 Disables transmission (syn chronously resets the transmission circuit).
1 Enables transmission.
RXE0 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
1 Enables reception.
Notes 1. The input from the RXD0 pin is fixed to high level when POWER0 = 0.
2. Asynchronous serial interface reception error status regist er 0 (ASIS0), tran smit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 207
Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01 PS00 Transmission operation Reception operation
0 0 Does not output parity bit. Reception without parity
0 1 Outputs 0 parity. Reception as 0 parityNote
1 0 Outputs odd parity. Judges as odd parity.
1 1 Outputs even parity. Judges as even parity.
CL0 Specifies character length of transmit/receive data
0 Character length of data = 7 bits
1 Character length of data = 8 bits
SL0 Specifies number of stop bits of transmit data
0 Number of stop bits = 1
1 Number of stop bits = 2
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to 0,
and then clear POWER0 to 0.
2. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to 0,
and then clear POWER0 to 0.
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE 0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
5. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
6. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
7. Be sure to set bit 0 to 1.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD
208
(2) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register is read-only by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this
register is read.
Figure 11-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After re set: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIS0 0 0 0 0 0 PE0 FE0 OVE0
PE0 Status flag indicating parity error
0 If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.
1 If the parity of transmit data does not match the parity bit on completion of reception.
FE0 Status flag indicating framing error
0 If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.
1 If the stop bit is not detected on completion of reception.
OVE0 Status flag indicating overrun error
0 If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.
1
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. For details, see CHAPTER 28 CAUTIONS
FOR WAIT.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 209
(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
Figure 11-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00
TPS01 TPS00 Base clock (fXCLK0) selection
0 0 TM50 outputNote
0 1 fX/2 (5 MHz)
1 0 fX/23 (1.25 MHz)
1 1 fX/25 (312.5 kHz)
MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5-bit counte r
output clock
0 0
× × × × Setting prohibited
0 1 0 0 0 8 fXCLK0/8
0 1 0 0 1 9 fXCLK0/9
0 1 0 1 0 10 fXCLK0/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 0 1 0 26 fXCLK0/26
1 1 0 1 1 27 fXCLK0/27
1 1 1 0 0 28 fXCLK0/28
1 1 1 1 0 30 fXCLK0/30
1 1 1 1 1 31 fXCLK0/31
Note To select the TM50 output as the base clock, start an operation by setting 8-bit timer/event counter 50 so
that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then
clear TPS01 and TPS00 to 0. It is not necessary to enable the TO50 pin as a timer output pin (bit 0
(TOE50) of the TMC register may be 0 or 1).
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-
OSC clock, the operation of serial interface UART0 is not guaranteed.
2. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
3. The baud rate value is the output clock of the 5-bit counter divided by 2.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD
210
Remarks 1. fXCLK0: Freque ncy of base clock selected by the TPS01 and TPS00 bits
2. f
X: X1 input clock oscillation frequency
3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31)
4. ×: Don’t care
5. Figures in parentheses apply t o operation at fX = 10 MHz
(4) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P10/TxD0/SCK10 pin for serial interface dat a output, clear PM10 to 0 and set the o utput latch of
P10 to 1.
Set PM11 to 1 when using the P11/RxD0/SI1 0 pin as a serial interfac e data input pin. The output latch of P11 a t
this time may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 11-5. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 211
11.4 Operation of Serial Interface UART0
Serial interface UART0 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
11.4.1 Operation stop mode
In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the
pins can be us ed as ordinary port pi ns in this mode. To set the op eration s t op mode, cle ar bits 7, 6, and 5 (POW ER0,
TXE0, and RXE0) of ASIM0 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0).
ASIM0 can be set by a 1-bit or 8-bit memory manipulation in struction.
RESET input sets this register to 01H.
Address: FF70H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1
POWER0 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
TXE0 Enables/disables transmission
0 Disables transmission (synchronously resets the transmission circuit).
RXE0 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
Notes 1. The input from the RXD0 pin is fixed to high level when POWER0 = 0.
2. Asynchronous serial interface reception error status regist er 0 (ASIS0), tran smit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.
To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1.
Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4
PORT FUNCTIONS.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD
212
11.4.2 Asynchronous serial interface (UART) mode
In this mode, 1-byte data is transmitted/received followi ng a start bit, and a full-duplex operation can be performed.
A dedicated UART baud rate gener ator is incorporated, so that communic ation can be executed at a wi de range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mod e register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the UART mode is as follows.
<1> Set the BRGC0 register (see Figure 11-4).
<2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 11-2).
<3> Set bit 7 (POWER0) of the ASIM0 register to 1.
<4> Set bit 6 (TXE0) of the ASIM0 register to 1. → Transmission is enabled.
Set bit 5 (RXE0) of the ASIM0 register to 1. → Reception is enabled.
<5> Write data to the TXS0 register . → Data transmission is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
The relationship between the register settings and pins is shown below.
Table 11-2. Relationship Between Register Settings and Pins
Pin Function POWER0 TXE0 RXE0 PM10 P10 PM11 P11 UART0
Operation TxD0/SCK10/P10 RxD0/SI10/P11
0 0 0 ×Note ×
Note ×
Note ×
Note Stop SCK10/P10 SI10/P11
0 1 ×Note ×
Note 1 × Reception SCK10/P10 RxD0
1 0 0 1 ×Note ×
Note Transmission TxD0 SI10/P11
1
1 1 0 1 1 ×
Transmission/
reception TxD0 RxD0
Note Can b e set as port function.
Remark ×: don’t care
POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
TXE0: Bit 6 of ASIM0
RXE0: Bit 5 of ASIM0
PM1×: Port mode register
P1×: Port output latch
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 213
(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 11-6 and 11-7 show the format and waveform example of the normal transmit/re ceive data.
Figure 11-6. Format of Normal UART Transmit/Receive Data
Start
bit Parity
bit
D0 D1 D2 D3 D4
1 data frame
Character bits
D5 D6 D7 Stop bit
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits (LSB first)
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 0 (ASIM0).
Figure 11-7. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 Parity StopStop
3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD
214
(b) Parity types and operation
The parity bit is used to d etect a bit error in communication data. Usua lly, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlle d so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parit y bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Recepti on is performed assuming that ther e is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 215
(c) Transmission
The TXD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode
register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled.
Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity
bit, and stop bit are automatically appende d to the data.
When transmission is started, the start bit is output from the TXD0 pin, followed by the rest of the data in
order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are
appended and a transmissio n completion interrupt request (INTST0) is generated.
Transmission is stopped until the data to be t r ansmitted next is written to TXS0.
Figure 11-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 11-8. Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
INTST0
D0Start D1 D2 D6 D7 Stop
TXD0 (output) Parity
2. Stop bit length: 2
TXD0 (output)
INTST0
D0Start D1 D2 D6 D7 Parity Stop
CHAPTER 11 SERIAL INTERFACE UART0 (
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PD780102, 780103, 78F0103 ONLY)
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(d) Reception
Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
RXD0 pin input is sampled a gain ( in Figure 11-9). If the RXD0 pin is l ow level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an error interrupt (INT SR0) is generated after completion of reception.
Figure 11-9. Reception Completion Interrupt Request Timing
R
X
D0 (input)
INTSR0
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
RXB0
Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0)
before reading RXB0.
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 217
(e) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt requ est (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the rec eption
error interrupt servicing (INTSR0) (see Figure 11-3).
The contents of ASIS0 are reset to 0 when ASIS0 is read.
Table 11-3. Cause of Reception Error
Reception Error Cause
Parity error The parity specified for transmission does not match the parity of the
receive data.
Framing error Stop bit is not detected.
Overrun error Reception of the next data is completed before data is read from
receive buffer register 0 (RXB0).
(f) Noise filter of receive data
The RXD0 signal is sampled using the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configur ed as shown in Figure 11-10, the internal processing of the r ecepti on opera tion
is delayed by two clocks from the external si gnal status.
Figure 11-10. Noise Filter Circuit
Internal signal B
Internal signal A
Match detector
In
Base clock
R
X
D0/SI10/P11 QIn
LD_EN
Q
CHAPTER 11 SERIAL INTERFACE UART0 (
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PD780102, 780103, 78F0103 ONLY)
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11.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and
generates a serial clock for transmission/reception of UART 0.
Separate 5-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is
supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0
(ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed
to low level when POWER0 = 0.
• Transmission counter
This counter stops, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface
operation mode register 0 (ASIM0) is 0.
It starts counting when POWER0 = 1 and TXE0 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0).
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
Figure 11-11. Configuration of Baud Rate Generator
f
XCLK0
Selector
POWER0
5-bit counter
Match detector Baud rate
BRGC0: MDL04 to MDL00
1/2
POWER0, TXE0 (or RXE0)
BRGC0: TPS01, TPS00
8-bit timer/
event counter
50 output
f
X
/2
5
f
X
/2
f
X
/2
3
Baud rate generator
Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
TXE0: Bit 6 of ASIM0
RXE0: Bit 5 of ASIM0
BRGC0: Baud rate generator control register 0
CHAPTER 11 SERIAL INTERFACE UART0 (
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PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 219
(2) Generation of serial clock
A serial clock can be generated by using ba ud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS0 1 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the divisi on value of the 5-bit counter.
(a) Baud rate
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
(b) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) = − 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Freque ncy of base clock = 2.5 MHz = 2,500,000 Hz
Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16)
Target baud rate = 76,800 bps
Baud rate = 2.5 M/(2 × 16)
= 2,500,000/(2 × 16) = 78125 [bps]
Error = (78,125/76,800 − 1) × 100
= 1.725 [%]
fXCLK0
2 × k
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
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(3) Example of setting baud rate
Table 11-4. Set Data of Baud Rate Generator
fX = 10.0 MHz fX = 8.38 MHz fX = 4.19 MHz
Baud Rate
[bps] TPS01,
TPS00 k Calculated
Value ERR[%] TPS01,
TPS00 k Calculated
Value ERR[%] TPS01,
TPS00 k Calculated
Value ERR[%]
2400 − − − − − − − − 3 27 2425 1.03
4800 − − − − 3 27 4850 1.03 3 14 4676 −2.58
9600 3 16 9766 1.73 3 14 9353 −2.58 2 27 9699 1.03
10400 3 15 10417 0.16 3 13 10072 −3.15 2 25 10475 0.72
19200 3 8 19531 1.73 2 27 19398 1.03 2 14 18705 −2.58
31250 2 20 31250 0 2 17 30809 −1.41 − − − −
38400 2 16 39063 1.73 2 14 38796 −2.58 2 27 38796 1.03
76800 2 8 78125 1.73 1 27 77593 1.03 1 14 74821 −2.58
115200 1 22 113636 −1.36 1 18 116389 1.03 1 9 116389 1.03
153600 1 16 156250 1.73 1 14 149643 −2.58 − − − −
230400 1 11 227273 −1.36 1 9 232778 1.03 − − − −
Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock
(fXCLK0))
k: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31)
f
X: X1 input clock oscillation frequency
ERR: Baud rate error
CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD780102, 780103, 78F0103 ONLY)
User’s Manual U15836EJ4V0UD 221
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 11-12. Permissible Baud Rate Range During Reception
FL 1 data frame (11 × FL)
FLmin
FLmax
Data frame length
of UART0 Start bit Bit 0 Bit 1 Bit 7 Parity bit
Minimum permissible
data frame length
Maximum permissible
data frame length
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit
Latch timing
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
As shown in Figure 11-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows .
FL = (Brate)−1
Brate: Baud rate of UART0
k: Set value of BRGC0
FL: 1-bit data length
Margin of latch timing: 2 clocks
CHAPTER 11 SERIAL INTERFACE UART0 (
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Minimum permissible data frame len gth: FLmin = 11 × FL − × FL = FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows .
BRmax = (FLmin/11)−1 = Brate
Similarly, the maximum permissible data fr ame length can be calculated as follows.
10 k + 2 21k − 2
11 2 × k 2 × k
FLmax = FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 = Brate
The permissible baud rate error between UART0 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 11-5. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error
8 +3.53% −3.61%
16 +4.14% −4.19%
24 +4.34% −4.38%
31 +4.44% −4.47%
Remarks 1. The permissible reception error depends on the number of bits in one frame, input clock
frequency, and division ratio ( k). The high er t he input clock freque ncy and the hig her the divisi on
ratio (k), the higher the permissible recepti on error.
2. k: Set value of BRGC0
k − 2
2k 21k + 2
2k
22k
21k + 2
× FLmax = 11 × FL − × FL = FL
21k − 2
20k
20k
21k − 2
User’s Manual U15836EJ4V0UD 223
CHAPTER 12 SERIAL INTERFACE UA RT6
12.1 Functions of Serial Interface UART6
Serial interface UART6 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 12.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.
For details, see 12.4.2 Asynchronous serial interface (UART) mode and 12.4.3 Dedicated baud rate
generator.
• Two-pin configuration TXD6: Transmit data output pin
R
XB6: Receive data input pin
• Data length of communication data can be selected from 7 or 8 bits.
• Dedicated internal 8- bit baud rate generator allowing any baud rate to be set
• Transmission and reception can be p erforme d independently.
• Twelve operating clock inputs selectable
• MSB- or LSB-first communication selectable
• Inverted transmission operati on
• Synchronous break field transmission from 1 3 to 20 bits
• More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided).
Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception
side. To use this function, the reception side must be ready for reception of inverted data.
2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD6 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
3. If data is continuously transmitted, the communication timing from the stop bit to the next
start bit is extended two operating clocks of the macro. However, this does not affect the
result of communication because the reception side initializes the timing when it has
detected a start bit. Do not use the continuous transmission function if the interface is
incorporated in LIN.
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD
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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuators, and se nsors, and these are conn ected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wir e method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN pr otocol, the master transmits a frame with baud rate informatio n and the slave receives it and
corrects the baud rate error. Therefore, c omm unication is possibl e w hen t he bau d rat e er ror in the slav e
is ±15% or less.
Figures 12-1 and 12-2 outline the transmission and reception operations of LIN.
Figure 12-1. LIN Transmission Operation
Sleep
bus
Wakeup
signal frame
8 bits
Note 1
55H
transmission Data
transmission Data
transmission Data
transmission Data
transmission
13-bit
Note 2
SBF
transmission
Note 3
Synchronous
break field Synchronous
field Indent
field Data field Data field Checksum
field
TX6
INTST6
Notes 1. The wakeup signal frame is substituted by 80H transmissio n in the 8-bit mode.
2. The synchronous break field is output by hardware. The output width is adjusted by baud rate
generator control register 6 (BRGC6) (see 12. 4.2 (2) (h) SBF transmission).
3. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
Remark The interval between each field is controlled by software.
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 225
Figure 12-2. LIN Reception Operation
Sleep
bus
13 bitsNote 2 SF
reception ID
reception Data
reception Data
reception Data
receptionNote 5
Note 3
Note 1
Note 4
Wakeup
signal frame Synchronous
break field Synchronous
field Indent
field Data field Data field Checksum
field
RX6
SBF
reception
Reception interrupt
(INTSR6)
Edge detection
(INTP0)
Capture timer Disable Enable
Disable Enable
Notes 1. The wakeu p signal is detected at the edge of the p in, and enables UART6 and sets the S BF reception
mode.
2. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or
more has been detected, it is assumed that SBF reception has been completed correctly, and an
interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is
assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF
reception mode is restored.
3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception
completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is
suppressed, and error detection processing of UART communication and data transfer of the shift
register and RXB6 is not performed. The shift register holds the reset value FFH.
4. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF
reception, and then re-set baud rate generator control register 6 (BRGC6).
5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6
after reception of the checksum field and to set the SBF reception mode again.
To perform a LIN receive operation, use a configuration like the one shown in Figure 12-3.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
(INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external
event capture operation of 16- bit timer/event counter 00, and the baud rate error can be calculated.
The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD
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Figure 12-3. Port Configuration for LIN Reception Operation
RXD6 input
INTP0 input
TI000 input
P14/RxD6
P120/INTP0
P00/TI000
Port input
switch control
(ISC0)
<ISC0>
0: Select INTP0 (P120)
1: Select RxD6 (P14)
Port mode
(PM14)
Output latch
(P14)
Port mode
(PM120)
Output latch
(P120)
Port input
switch control
(ISC1)
<ISC1>
0: Select TI000 (P00)
1: Select RxD6 (P14)
Selector Selector
Selector
Selector
Selector
Port mode
(PM00)
Output latch
(P00)
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 12-11)
The peripheral functions us ed in the LIN communication ope r ation are shown below.
<Peripheral functions used>
• External interrupt (INTP0); wakeup signal detection
Use: Detects the wakeup signal edges and detects start of communication.
• 16-bit timer/event counter 00 (TI000); baud rate error detection
Use: Detects the baud rate error (measures the TI000 input ed ge i nterval in the capture mod e) by detectin g the
synchronous break field (SBF) length and divides it by the number of bits.
• Serial interface UART6
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 227
12.2 Configuration of Serial Interface UART6
Serial interface UART6 includes the following hardware.
Table 12-1. Configuration of Serial Interface UART6
Item Configuration
Registers Receive buffer register 6 (RXB6)
Receive shift register 6 (RXS6)
Transmit buffer register 6 (TXB6)
Transmit shift register 6 (TXS6)
Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Input switch control register (ISC)
Port mode register 1 (PM1)
Port register 1 (P1)
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD
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Figure 12-4. Block Diagram of Serial Interface UART6
Internal bus
Asynchronous serial interface
control register 6 (ASICL6)
Transmit buffer register 6
(TXB6)
Transmit shift register 6
(TXS6) T
X
D6/
P13
INTST6
Baud rate
generator
Asynchronous serial interface
control register 6 (ASICL6)
Reception control Receive shift register 6
(RXS6)
Receive buffer register 6
(RXB6)
R
X
D6/
P14
TI000, INTP0
Note
INTSR6
Baud rate
generator
Filter
INTSRE6
Asynchronous serial
interface reception error
status register 6 (ASIS6)
Asynchronous serial
interface operation mode
register 6 (ASIM6)
Asynchronous serial
interface transmission
status register 6 (ASIF6)
Transmission control
Registers
f
X
f
X
/2
f
X
/22
f
X
/23
f
X
/24
f
X
/25
f
X
/26
f
X
/27
f
X
/28
f
X
/29
f
X
/210
8-bit timer/
event counter
50 output
8
Reception unit
Transmission unit
Clock selection
register 6 (CKSR6)
Baud rate generator
control register 6
(BRGC6)
Output latch
(P13)
PM13
8
Selector
Note Selectable with input switch control register (ISC).
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 229
(1) Receive buffer register 6 (RXB6)
This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows.
• In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
• In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.
If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.
RXB6 can be read by an 8-bit memory manipulati on instruction. No data can be written to this register.
RESET input sets this register to FFH.
(2) Receive shift register 6 (RXS6)
This register converts the serial data inp ut to the RXD6 pin into parallel data.
RXS6 cannot be directly manipulat ed by a program.
(3) Transmit buffer register 6 (TXB6)
This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.
This register can be read or written by an 8-bit memory manip ul ation instruction.
RESET input sets this register to FFH.
Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynch ronous serial interface t ransmission
status register 6 (ASIF6) is 1.
2. Do not refresh (write the same value to) TXB6 by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation
mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).
(4) Transmit shift register 6 (TXS6)
This register transmits the data transferred from TXB6 from the TXD6 pin as serial dat a. Data is transferred from
TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one
frame was transmitted for continuous transmission. Da ta is transferred fro m TXB6 and tr ansmitted from the T XD6
pin at the falling edge of the base clock.
TXS6 cannot be directly manipulated by a program.
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD
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12.3 Registers Controlling Serial Interface UART6
Serial interface UART6 is controlled by the following nine registers.
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instructio n.
RESET input sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6
POWER6 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
1
Note 3 Enables operation of the internal operation clock
TXE6 Enables/disables transmission
0 Disables transmission (syn chronously resets the transmission circuit).
1 Enables transmission
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when
POWER6 = 0.
2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the
POWER6 bit.
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Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
RXE6 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
1 Enables reception
PS61 PS60 Transmission operation Reception operation
0 0 Does not output parity bit. Reception without parity
0 1 Outputs 0 parity. Reception as 0 parityNote
1 0 Outputs odd parity. Judges as odd parity.
1 1 Outputs even parity. Judges as even parity.
CL6 Specifies character length of transmit/receive data
0 Character length of data = 7 bits
1 Character length of data = 8 bits
SL6 Specifies number of stop bits of transmit data
0 Number of stop bits = 1
1 Number of stop bits = 2
ISRM6 Enables/disables occurrence of reception completion interrupt in case of error
0 “INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
1 “INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0
and then clear POWER6 to 0.
2. At startup, set POW ER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0
and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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(2) Asynchronous serial interface reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this
register is read.
Figure 12-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
Address: FF53H After re set: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIS6 0 0 0 0 0 PE6 FE6 OVE6
PE6 Status flag indicating parity error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1 If the parity of transmit data does not match the parity bit on completion of reception
FE6 Status flag indicating framing error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1 If the stop bit is not detected on completion of reception
OVE6 Status flag indicating overrun error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. For details, see CHAPTER 28
CAUTIONS FOR WAIT.
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(3) Asynchronous serial interface transmission status register 6 (ASIF6)
This register indicates the status of transmission by serial interface UART6. It includes two status flag bits
(TXBF6 and TXSF6).
Transmission can be continue d without disruption even during an i nterrupt period, by writing the next data to the
TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
This register is read-only by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Figure 12-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
Address: FF55H After re set: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIF6 0 0 0 0 0 0 TXBF6 TXSF6
TXBF6 Transmit buffer data flag
0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)
1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6 Transmit shift register data flag
0
If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6
(TXB6) after completion of transfer
1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the T XBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
2. To initialize the transmission unit upon completion of continuous transmission, be sure to
check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,
and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the
transmit data cannot be guaranteed.
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(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UA RT6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 12-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60
TPS63 TPS62 TPS61 TPS60 Base clock (fXCLK6) selection
0 0 0 0 fX (10 MHz)
0 0 0 1 fX/2 (5 MHz)
0 0 1 0 fX/22 (2.5 MHz)
0 0 1 1 fX/23 (1.25 MHz)
0 1 0 0 fX/24 (625 kHz)
0 1 0 1 fX/25 (312.5 kHz)
0 1 1 0 fX/26 (156.25 kHz)
0 1 1 1 fX/27 (78.13 kHz)
1 0 0 0 fX/28 (39.06 kHz)
1 0 0 1 fX/29 (19.53 kHz)
1 0 1 0 fX/210 (9.77 kHz)
1 0 1 1 TM50 outputNote
Other Setting prohibited
Note To select the output of TM50 as t he base c lock, start the op eration by setti ng 8- bit timer/event cou nter 50 so
that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then
set TPS63, TPS62, TPS61, and TPS60 to 1, 0, 1, and 1, respectively. It is not necessary to enable the
TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1).
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-
OSC clock, the operation of serial interface UART6 is not guaranteed.
2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. Figures in parentheses are for operation with fX = 10 MHz
2. f
X: X1 input clock oscillation frequency
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(5) Baud rate generator control register 6 (BRGC6)
This register sets the division value of the 8-bit counter of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 12-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF57H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of
8-bit counter
0 0 0 0 0 × × × × Setting prohibited
0 0 0 0 1 0 0 0 8 fXCLK6/8
0 0 0 0 1 0 0 1 9 fXCLK6/9
0 0 0 0 1 0 1 0 10 fXCLK6/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1 1 1 0 0 252 fXCLK6/252
1 1 1 1 1 1 0 1 253 fXCLK6/253
1 1 1 1 1 1 1 0 254 fXCLK6/254
1 1 1 1 1 1 1 1 255 fXCLK6/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate value is the output clock of the 8-bit counter divided by 2.
Remarks 1. f
XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)
3. ×: Don’t care
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(6) Asynchronous serial interface control register 6 (ASICL6)
This register controls the serial communication operatio ns of serial interface UART6.
ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 16H.
Caution ASICL6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation
because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an
interrupt signal is generated).
Figure 12-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6)
Address: FF58H After re set: 16H R/WNote
Symbol <7> <6> 5 4 3 2 1 0
ASICL6 SBRF6 SBRT6 0 1 0 1 DIR6 TXDLV6
SBRF6 SBF reception status flag
0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
1 SBF reception in progress
SBRT6 SBF reception trigger
0 −
1 SBF reception trigger
DIR6 First bit specification
0 MSB
1 LSB
TXDLV6 Enables/disables inverting TXD6 output
0 Normal output of TXD6
1 Inverted output of TXD6
Note Bits 2 to 5 and 7 are read-only.
Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold
the status of the SBRF6 flag.
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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(7) Input switch control register (ISC)
The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN
(Local Interconnect Network) reception. The input signal is switched by setting ISC.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 12-11. Format of Input Switch Control Register (ISC)
Address: FF4FH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 ISC1 ISC0
ISC1 TI000 input source selection
0 TI000 (P00)
1 RxD6 (P14)
ISC0 INTP0 input source selection
0 INTP0 (P120)
1 RxD6 (P14)
(8) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P13/TxD6 pin for serial interface data out put, clear PM13 to 0 and set the output latch of P13 to
1.
Set PM14 to 1 when using th e P14/RxD6 pin as a serial interface data input pi n. The output latch of P14 at this
time may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 12-12. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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12.4 Operation of Serial Interface UART6
Serial interface UART6 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
12.4.1 Operation stop mode
In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In
addition, the pins can be used as ordinary port pins in this mode. To set t he oper ation stop mode, clear bits 7, 6, and
5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).
ASIM6 can be set by a 1-bit or 8-bit memory manipulation in struction.
RESET input sets this register to 01H.
Address: FF50H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6
POWER6 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
TXE6 Enables/disables transmission
0 Disables transmission operation (synchronously resets the transmission circuit).
RXE6 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when
POWER6 = 0.
2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode.
To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.
Remark To use the RxD6/P14 and TxD6/P13 pins as general-purpose port pins, see CHAPTER 4 PORT
FUNCTIONS.
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12.4.2 Asynchronous serial interface (UART) mode
In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be
performed.
A dedicated UART baud rate gener ator is incorporated, so that communic ation can be executed at a wi de range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mod e register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the UART mode is as follows.
<1> Set the CKSR6 register (see Figure 12-8).
<2> Set the BRGC6 register (see Figure 12-9).
<3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 12-5).
<4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 12-10).
<5> Set bit 7 (POWER6) of the ASIM6 register to 1.
<6> Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.
Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.
<7> Write data to transmit buffer r egister 6 (TXB6). → Data transmission is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
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The relationship between the register settings and pins is shown below.
Table 12-2. Relationship Between Register Settings and Pins
Pin Function POWER6 TXE6 RXE6 PM13 P13 PM14 P14 UART6
Operation TxD6/P13 RxD6/P14
0 0 0 ×Note ×
Note ×
Note ×
Note Stop P13 P14
0 1 ×Note ×
Note 1 × Reception P13 RxD6
1 0 0 1 ×Note ×
Note Transmission TxD6 P14
1
1 1 0 1 1 ×
Transmission/
reception TxD6 RxD6
Note Can b e set as port function.
Remark ×: don’t care
POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
PM1×: Port mode register
P1×: Port output latch
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(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 12-13 and 12-14 show the format and waveform example of the normal transmit/receive data.
Figure 12-13. Format of Normal UART Transmit/Receive Data
1. LSB-first transmission/reception
Start
bit Parity
bit
D0 D1 D2 D3 D4
1 data frame
Character bits
D5 D6 D7 Stop bit
2. MSB-first transmission/reception
Start
bit Parity
bit
D7 D6 D5 D4 D3
1 data frame
Character bits
D2 D1 D0 Stop bit
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 6 (ASIM6).
Whether data is communic ated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial
interface control register 6 (ASICL6).
Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
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Figure 12-14. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin
inverted output
1 data frame
Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 Parity StopStop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
CHAPTER 12 SERIAL INTERFACE UART6
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(b) Parity types and operation
The parity bit is used to d etect a bit error in communication data. Usua lly, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlle d so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parit y bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Recepti on is performed assuming that ther e is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
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(c) Normal transmission
The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode
register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled.
Transmission can be started by writing transmit data to tr ansmit buffer register 6 (TXB6). The start bit, parity
bit, and stop bit are automatically appende d to the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity bit
and stop bit set by ASIM6 are added and a transmission completion interrupt request (INTST6) is generated.
Transmission is stopped until the data to be t r ansmitted next is written to TXB6.
Figure 12-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
Figure 12-15. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
INTST6
D0Start D1 D2 D6 D7 Stop
T
X
D6 (output) Parity
2. Stop bit length: 2
T
X
D6 (output)
INTST6
D0Start D1 D2 D6 D7 Parity Stop
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(d) Continuous transmission
The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift regi ster 6
(TXS6) has started its shift operation. Cons equently, even while the INT ST6 interrupt is being serv iced after
transmission of one data frame, data can be continuously transmitted and an efficient communication rate
can be realized. In add ition, the TXB6 r egist er can be effici ently written tw ice (2 bytes) wi thout h aving to wait
for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface
transmission status register 6 (ASIF6) when the transmission completion in terrupt has occurred.
To transmit data continuously, be s ure to reference the ASIF6 register to check the transmission status and
whether the TXB6 register can be written, and then write the data.
Cautions 1. The TXBF6 and TXSF6 flags of the ASIS register change from “10” to “11”, and to “01”
during continuous transmission. To check the status, therefore, do not use a
combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag
when executing continuous transmission.
2. When the device is incorporated in a LIN, the continuous transmission function cannot
be used. Make sure that asynchronous serial interface transmission status register 6
(ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6).
TXBF6 Writing to TXB6 Register
0 Writing enabled
1 Writing disabled
Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
The communication status can be checked us ing the TXSF6 flag.
TXSF6 Transmission Status
0 Transmission is completed.
1 Transmission is in progress.
Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure
to check that the TXSF6 flag is “0” after generation of the transmission completion
interrupt, and then execute initialization. If initialization is executed while the TXSF6
flag is “1”, the transmit data cannot be guaranteed.
2. During continuous transmission, an overrun error may occur, which means that the
next transmission was completed before execution of INTST6 interrupt servicing after
transmission of one data frame. An overrun error can be detected by developing a
program that can count the number of transmit data and by referencing the TXSF6 flag.
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Figure 12-16 shows an example of the co ntinuous transmission processi ng flow.
Figure 12-16. Example of Continuous Transmission Processing Flow
Write TXB6.
Set registers.
Write TXB6.
Transfer
executed necessary
number of times? Yes
Read ASIF6
TXBF6 = 0? No
No
Yes
Transmission
completion interrupt
occurs?
Read ASIF6
TXSF6 = 0?
No
No
No
Yes
Yes
Yes
Yes
Completion of
transmission processing
Transfer
executed necessary
number of times?
Remark TXB6: Transmit buffer register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)
TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 247
Figure 12-17 shows the timing of starting continuous transmission, and Figure 12-18 shows the timing of
ending continuous transmission.
Figure 12-17. Timing of Starting Continuous Transmission
TXD6 Start
INTST6
Data (1)
Data (1) Data (2) Data (3)
Data (2)Data (1) Data (3)
FF
FF
Parity Stop Data (2) Parity Stop
TXB6
TXS6
TXBF6
TXSF6
Start Start
Note
Note When ASIF6 is read, there is a period in whi ch TXBF6 and TXSF6 = 1, 1. Therefore, judge whether
writing is enabled using only the TXBF6 bit.
Remark T
XD6: TXD6 pin (output)
INTST6: Interrupt request signal
TXB6: Transmit buffer register 6
TXS6: Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
CHAPTER 12 SERIAL INTERFACE UART6
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Figure 12-18. Timing of Ending Continuous Transmission
T
X
D6 Start
INTST6
Data (n − 1)
Data (n − 1) Data (n)
Data (n)Data (n − 1) FF
Parity
Stop Stop Data (n) Parity Stop
TXB6
TXS6
TXBF6
TXSF6
POWER6 or TXE6
Start
Remark TXD6: TXD6 pin (output)
INTST6: Interrupt request signal
TXB6: Transmit buffer register 6
TXS6: Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)
TXE6: Bit 6 of asynchronous serial interface operation mode register (ASIM6)
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 249
(e) Normal reception
Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial
interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the
RXD6 pin input is sampled again ( in Figure 12-19). If the RXD6 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception.
Figure 12-19. Reception Completion Interrupt Request Timing
RXD6 (input)
INTSR6
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity
RXB6
Stop
Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
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(f) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data
reception, a reception error interrupt request (INTSR6/INTSRE6) is ge nerated.
Which error has occurred during reception can be identified by reading the contents of ASIS6 in the rec eption
error interrupt servicing (INTSR6/INTSRE6) (see Figure 12-6).
The contents of ASIS6 are reset to 0 when ASIS6 is read.
Table 12-3. Cause of Reception Error
Reception Error Cause
Parity error The parity specified for transmission does not matc h the parity of the
receive data.
Framing error Stop bit is not detected.
Overrun error Reception of the next data is completed before data is read from
receive buffer register 6 (RXB6).
The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt
(INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to
0.
Figure 12-20. Reception Error Interrupt
1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are
separated)
(a) No error during reception (b) Error during reception
INTSR6
INTSRE6
INTSR6
INTSRE6
2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)
(a) No error during reception (b) Error during reception
INTSRE6
INTSR6
INTSRE6
INTSR6
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 251
(g) Noise filter of receive data
The RXD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configur ed as shown in Figure 12-21, the internal processing of the r ecepti on opera tion
is delayed by two clocks from the external si gnal status.
Figure 12-21. Noise Filter Circuit
Internal signal B
Internal signal A
Match detector
In
Base clock
R
X
D6/P14 QIn
LD_EN
Q
(h) SBF transmission
When the device is incor porated in LIN, the SBF (Synchronous Break Field) transmission co ntrol function is
used for transmission. For the transmission operation of LIN, see Figure 12-1 LIN Transmission
Operation.
SBF transmission is used to transmit an SBF length that is a low-level width of 13 bits or more by adjus ting
the baud rate value of the ordinary UART transmission function.
[Setting method]
Transmit 00H by setting the number of chara cter bits of th e data to 8 bits a nd the p arity bit to 0 p arity or eve n
parity. This enables a low-level transmission of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits
(character bits) + 1 bit (parity bit)).
Adjust the baud rate value to adjust this 10-bit low level to the targeted SBF length.
Example If LIN is to be transmitted under the following conditions
• Base clock of UART6 = 5 MHz (set by clock selection register 6 (CKSR6))
• Target baud rate value = 19200 bps
To realize the above baud rate value, the length of a 13-bit SBF is as follows if the baud rate generator
control register 6 (BRGC6) is set to 130.
• 13-bit SBF length = 0.2
µ
s × 130 × 2 × 13 = 676
µ
s
To realize a 13-bit SBF length in 10 bits, set a value 1.3 times the targeted baud rate to BRGC6. In this
example, set 169 to BRGC6. The transmission length of a 10-bit low level in this case is as follows, and
matches the 13-bit SBF length.
• 10-bit low-level transmission length = 0.2
µ
s × 169 × 2 × 10 = 676
µ
s
CHAPTER 12 SERIAL INTERFACE UART6
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If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of
UART6.
Figure 12-22. Example of Setting Procedure of SBF Transmission (Flowchart)
Start
Read BRGC6 register and save current
set value of BRGC6 register to general-
purpose register.
Clear TXE6 and RXE6 bits of ASIM6
register to 0 (to disable transmission/
reception).
Set value to BRGC6 register to realize
desired SBF length.
Set character length of data to 8 bits
and parity to 0 or even using ASIM6
register.
Set TXE6 bit of ASIM6 register to 1 to
enable transmission.
Set TXB6 register to "00H" and start
transmission.
INTST6 occurred? No
Yes
Clear TXE6 and RXE6 bits of ASIM6
register to 0.
Rewrite saved BRGC6 value to BRGC6
register.
Re-set PS61 bit, PS60 bit, and CL6 bit
of ASIM6 register to desired value.
Set TXE6 bit of ASIM6 register to 1 to
enable transmission.
End
Figure 12-23. SBF Transmission
TXD6
INTST6
1 2 3 4 5 6 7 8 9 10 11 12 13 Stop
Remark T
XD6: TXD6 pin (output)
INTST6: Transmission completion interrupt request
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 253
(i) SBF reception
When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is
used for reception. For the reception operation of LIN, see Figure 12-2 LIN Reception Operation .
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6
(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SB RT6)
of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,
the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable
status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in receive
shift register 6 (RXS6) at the set baud rate. When th e stop bit is received and if the width of SBF is 11 bits or
more, a reception completion interrupt request (INTSR6) is generated as normal processin g. At this time, the
SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as
OVE6, PE6, and FE6 (bits 0 to 2 of asynchr onous s erial i nterface rece ption error status re gister 6 (ASIS6 )) is
suppressed, and error detection processing of UART communication is not performed. In addition, data
transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and
the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error
processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the
SBRF6 and SBRT6 bits are not cleared.
Figure 12-24. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
RXD6
SBRT6
/SBRF6
INTSR6
1234567891011
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
R
X
D6
SBRT6
/SBRF6
INTSR6
12345678910
“0”
Remark RXD6: RXD6 pin (input)
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)
SBRF6: Bit 7 of ASICL6
INTSR6: Reception completion interrupt request
CHAPTER 12 SERIAL INTERFACE UART6
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12.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and
generates a serial clock for transmission/reception of UART 6.
Separate 8-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to
each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is
1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level
when POWER6 = 0.
• Transmission counter
This counter stops, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface
operation mode register 6 (ASIM6) is 0.
It starts counting when POWER6 = 1 and TXE6 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).
If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been
completely transmitted. If there is no d ata to be tra nsmitted next, the cou nter is not cleare d to 0 and continue s
counting until POWER6 or TXE6 is cleared to 0.
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 255
Figure 12-25. Configuration of Baud Rate Generator
Selector
POWER6
8-bit counter
Match detector Baud rate
Baud rate generator
BRGC6: MDL67 to MDL60
1/2
POWER6, TXE6 (or RXE6)
CKSR6: TPS63 to TPS60
fX
fX/2
fX/22
fX/23
fX/24
fX/25
fX/26
fX/27
fX/28
fX/29
fX/210
8-bit timer/
event counter
50 output
f
XCLK6
Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
CKSR6: Clock selection register 6
BRGC6: Baud rate generator control register 6
CHAPTER 12 SERIAL INTERFACE UART6
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(2) Generation of serial clock
A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control
register 6 (BRGC6).
Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.
Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
(a) Baud rate
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
fXCLK6: Frequency of base clock selec t ed by TPS63 to TPS60 bits of CKSR6 register
k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)
(b) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) = − 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Freque ncy of base clock = 10 MHz = 10,000,000 Hz
Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)
Target baud rate = 153600 bps
Baud rate = 10 M/(2 × 33)
= 10000000/(2 × 33) = 151515 [bps]
Error = (151515/153600 − 1) × 100
= −1.357 [%]
fXCLK6
2 × k
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 257
(3) Example of setting baud rate
Table 12-4. Set Data of Baud Rate Generator
fX = 10.0 MHz fX = 8.38 MHz fX = 4.19 MHz
Baud Rate
[bps] TPS63 to
TPS60 k Calculated
Value ERR[%] TPS63 to
TPS60 k Calculated
Value ERR[%] TPS63 to
TPS60 k Calculated
Value ERR[%]
600 6H 130 601 0.16 6H 109 601 0.11 5H 109 601 0.11
1200 5H 130 1202 0.16 5H 109 1201 0.11 4H 109 1201 0.11
2400 4H 130 2404 0.16 4H 109 2403 0.11 3H 109 2403 0.11
4800 3H 130 4808 0.16 3H 109 4805 0.11 2H 109 4805 0.11
9600 2H 130 9615 0.16 2H 109 9610 0.11 1H 109 9610 0.11
10400 2H 120 10417 0.16 2H 101 10371 0.28 1H 101 10475 −0.28
19200 1H 130 19231 0.16 1H 109 19200 0.11 0H 109 19220 0.11
31250 1H 80 31250 0.00 0H 134 31268 0.06 0H 67 31268 0.06
38400 0H 130 38462 0.16 0H 109 38440 0.11 0H 55 38090 −0.80
76800 0H 65 76923 0.16 0H 55 76182 −0.80 0H 27 77593 1.03
115200 0H 43 116279 0.94 0H 36 116388 1.03 0H 18 116389 1.03
153600 0H 33 151515 −1.36 0H 27 155185 1.03 0H 14 149643 −2.58
230400 0H 22 227272 −1.36 0H 18 232777 1.03 0H 9 232778 1.03
Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6))
k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6
(BRGC6) (k = 8, 9, 10, ..., 255)
f
X: X1 input clock oscillation fre quency
ERR: Baud rate error
CHAPTER 12 SERIAL INTERFACE UART6
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(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 12-26. Permissible Baud Rate Range During Reception
FL 1 data frame (11 × FL)
FLmin
FLmax
Data frame length
of UART6 Start bit Bit 0 Bit 1 Bit 7 Parity bit
Minimum permissible
data frame length
Maximum permissible
data frame length
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit
Latch timing
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
As shown in Figure 12-26, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows .
FL = (Brate)−1
Brate: Baud rate of UART6
k: Set value of BRGC6
FL: 1-bit data length
Margin of latch timing: 2 clocks
Minimum permissible data frame len gth: FLmin = 11 × FL − × FL = FL
k − 2
2k 21k + 2
2k
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ4V0UD 259
Therefore, the maximum receivable baud rate at the transmission destination is as follows .
BRmax = (FLmin/11)−1 = Brate
Similarly, the maximum permissible data fr ame length can be calculated as follows.
10 k + 2 21k − 2
11 2 × k 2 × k
FLmax = FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 = Brate
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 12-5. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error
8 +3.53% −3.61%
20 +4.26% −4.31%
50 +4.56% −4.58%
100 +4.66% −4.67%
255 +4.72% −4.73%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio ( k). The high er t he inp ut clock frequency an d the higher th e division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC6
22k
21k + 2
× FLmax = 11 × FL − × FL = FL
21k − 2
20k
20k
21k − 2
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(5) Data frame length during continuous transmission
When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by
two clocks of base clock from the normal value. However, the result of communication is not affected because
the timing is initialized on the reception side when the start bit is detected.
Figure 12-27. Data Frame Length During Continuous Transmission
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
FL
1 data frame
FL FL FL FL FLFLFLstp
Start bit of
second byte
Start bit Bit 0
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following
expression is satisfied.
FLstp = FL + 2/fXCLK6
Therefore, the data frame length during continuous transmission is:
Data frame length = 11 × FL + 2/fXCLK6
User’s Manual U15836EJ4V0UD 261
CHAPTER 13 SERIAL INTERFACE CSI10
13.1 Functions of Serial Interface CSI10
Serial interface CSI10 has the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial communication is not performed and can enable a reduction in the power
consumption.
For details, see 13.4.1 Operation stop mode.
(2) 3-wire serial I/O mode (MSB/LSB-first selectable)
This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK10) and two serial data
lines (SI10 and SO10).
The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission
and reception can be simultaneously executed.
In addition, whether 8-bit dat a is communicated with the MSB or LSB fir st can be specified, so this int erface can
be connected to any device.
The 3-wire serial I/O mode can be used connecting peripheral ICs and display controllers with a clocked serial
interface.
For details, see 13.4.2 3-wire serial I/O mode.
13.2 Configuration of Serial Interface CSI10
Serial interface CSI10 includes the following hardware.
Table 13-1. Configuration of Serial Interface CSI10
Item Configuration
Registers Transmit buffer register 10 (SOTB10)
Serial I/O shift register 10 (SIO10)
Transmit controller
Clock start/stop controller & clock phase controller
Control registers Serial operation mode register 10 (CSIM10)
Serial clock selection register 10 (CSIC10)
Port mode register 1 (PM1)
Port register 1 (P1)
CHAPTER 13 SERIAL INTERFACE CSI10
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Figure 13-1. Block Diagram of Serial Interface CSI10
Internal bus
SI10/P11(/RxD0Note)
INTCSI10
fX/2
fX/22
fX/23
fX/24
fX/25
fX/26
fX/27
SCK10/P10
(/TxD0Note)
Transmit buffer
register 10 (SOTB10)
Transmit controller
Clock start/stop controller &
clock phase controller
Serial I/O shift
register 10 (SIO10) Output
selector SO10/P12
Output latch
8
Transmit data
controller
8
Output latch
(P12)
PM12
Selector
Note
µ
PD780102, 780103, 78F0103 only.
(1) Transmit buffer register 10 (SOTB10)
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial
operation mode register 10 (CSIM10) are 1.
The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and
output to the serial output pin (SO10).
SOTB10 can be written or read by an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication).
(2) Serial I/O shift register 10 (SIO10)
This is an 8-bit register that converts data from parallel data into serial data and vice vers a.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation m ode register 10 (CSIM10)
is 0.
During reception, the data is read from the serial input pin (SI10) to SIO10.
RESET input clears this register to 00H.
Caution Do not access SIO10 when CSOT10 = 1 (during serial communication).
CHAPTER 13 SERIAL INTERFACE CSI10
User’s Manual U15836EJ4V0UD 263
13.3 Registers Controlling Serial Interface CSI10
Serial interface CSI10 is controlled by the following four registers.
• Serial operation mode register 10 (CSIM10)
• Serial clock selection register 10 (CSIC10)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Serial operation mode register 10 (CSIM10)
CSIM10 is used to select the operation mode and enable or disable operation.
CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 13-2. Format of Serial Operation Mode Register 10 (CSIM10)
Address: FF80H After reset: 00H R/WNote 1
Symbol <7> 6 5 4 3 2 1 0
CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10
CSIE10 Operation control in 3-wire serial I/O mode
0 Disables operationNote 2 and asynchronously resets the internal circuitNote 3.
1 Enables operation
TRMD10Note 4 Transmit/receive mode control
0
Note 5 Receive mode (transmission disabled).
1 Transmit/receive mode
DIR10Note 6 First bit specification
0 MSB
1 LSB
CSOT10 Communication status flag
0 Communication is stopped.
1 Communication is in progress.
Notes 1. Bit 0 is a read-only bit.
2. When using P10/SCK10(/TxD0Note 7), P11/SI10(/RxD0Note 7), or P12/SO10 as a general-purpose port, see
CHAPTER 4 PORT FUNTIONS and Caution 3 of Figure 13-3.
3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
4. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).
5. The SO10 output is fixed to the low level when TRMD10 is 0. Reception is started when data is read
from SIO10.
6. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).
7.
µ
PD780102, 780103, and 78F0103 only.
Caution Be sure to clear bit 5 to 0.
CHAPTER 13 SERIAL INTERFACE CSI10
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(2) Serial clock selection register 10 (CSIC10)
This register specifies the timing of the data transmission/reception and s ets the serial cl ock.
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 13-3. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CSIC10 0 0 0 CKP10 DAP10 CKS102 CKS101 CKS100
CKP10 DAP10 Specification of data transmission/reception timing Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
4
CKS102 CKS101 CKS100 CSI10 serial clock selection Mode
0 0 0 fX/2 (5 MHz) Master mode
0 0 1 fX/22 (2.5 MHz) Master mode
0 1 0 fX/23 (1.25 MHz) Master mode
0 1 1 fX/24 (625 kHz) Master mode
1 0 0 fX/25 (312.5 kHz) Master mode
1 0 1 fX/26 (156.25 kHz) Master mode
1 1 0 fX/27 (78.13 kHz) Master mode
1 1 1 External clock input to SCK10 Slave mode
Cautions 1. When the Ring-OSC clock is sel ected as the clock supplied to the CPU, the clock of the Ring-
OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial
interface CSI10 is not guaranteed.
2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
3. Clear CKP10 to 0 to use P10/SCK10(/TxD0Note) as general-purpose port pins.
4. The phase type of the data clock is type 1 after reset.
Note
µ
PD780102, 780103, 78F0103 only.
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Remarks 1. Figures in parentheses are for operati on with fX = 10 MHz
2. f
X: X1 input clock oscillation frequency
(3) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using P10/SCK10(/TxD0Note) as the clock output pins of the serial interface, and P12/SO10 as the data
output pins, clear PM10, PM12, and the output latches of P10, and P12 to 0.
When using P10/SCK10(/TxD0Note) as the clock input pins of the serial interface, and P11/SI10(/RxD0Note) as the
data input pins, set PM10 and PM11 to 1. At this time, the output latches of P10 and P11 may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Note
µ
PD780102, 780103, 78F0103 only.
Figure 13-4. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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13.4 Operation of Serial Interface CSI10
Serial interface CSI10 can be used in the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
13.4.1 Operation stop mode
Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In
addition, the P10/SCK10(/TXD0Note), P11/SI10(/RXD0Note), and P12/SO10 pins can be us ed as ordinary I/O port pins in
this mode.
Note
µ
PD780102, 780103, and 78F0103 only.
(1) Register used
The operation stop mode is set by serial operation mode register 10 (CSIM10).
To set the operation stop mode, clear bit 7 (CSIE10) of CSIM10 to 0.
(a) Serial operation mode register 10 (CSIM10)
CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Address: FF80H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10
CSIE10 Operation control in 3-wire serial I/O mode
0 Disables operationNote 1 and asynchronously resets the internal circuitNo te 2.
Notes 1. When using P10/SCK10(/TxD0Note 3), P11/SI10(RxD0Note 3), or P12/SO10 as general-purpose port
pins, see CHAPTER 4 PORT FUNCTIONS and Caution 3 of Figure 13-3.
2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
3.
µ
PD780102, 780103, and 78F0103 only.
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13.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers that have a clocked
serial interface.
In this mode, communic ation is executed by using three lines: the seri al clock (SCK10), serial output (SO10), and
serial input (SI10) lines.
(1) Registers used
• Serial operation mode register 10 (CSIM10)
• Serial clock selection register 10 (CSIC10)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows.
<1> Set the CSIC10 register (see Figure 13-3).
<2> Set bits 0, 4, and 6 (CSOT10, DIR10, and TRMD10) of the CSIM10 register (see Figure 13-2).
<3> Set bit 7 (CSIE10) of the CSIM10 register to 1. → Transmission/reception is enabled.
<4> Write data to transmit buffer r egister 10 (SOTB10). → Data transmission/reception is started.
Read data from serial I/O shift register 10 (SIO10). → Data reception is started.
Caution Take relationship with the other party of communication when setting the port mode
register and port register.
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The relationship between the register settings and pins is shown below.
Table 13-2. Relationship Between Register Settings and Pins
Pin Function CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 P10 CSI10
Operation P11/SI10
(/RxD0Note 4) P12/SO10 P10/SCK10
(/TxD0Note 4)
0 × ×Note 1 ×
Note 1 ×
Note 1 ×
Note 1 ×
Note 1 ×
Note 1 Stop P11
(/RxD0Note 4) P12 P10
(/TxD0Note 4)Note 2
1 0 1 × ×Note 1 ×
Note 1 1 × Slave
receptionNote 3 SI10 P12
SCK10
(input)Note 3
1 1 ×Note 1 ×
Note 1 0 0 1 × Slave
transmissionNote 3 P11
(/RxD0Note 4) SO10 SCK10
(input)Note 3
1 1 1 × 0 0 1 × Slave
transmission/
receptionNote 3
SI10 SO10
SCK10
(input)Note 3
1 0 1 × ×Note 1 ×
Note 1 0 1 Master
reception SI10 P12
SCK10
(output)
1 1 ×Note 1 ×
Note 1 0 0 0 1 Master
transmission P11
(/RxD0Note 4) SO10 SCK10
(output)
1 1 1 × 0 0 0 1 Master
transmission/
reception
SI10 SO10
SCK10
(output)
Notes 1. Can be set as port function.
2. To use P10/SCK10(/TxD0Note 4) as port pins, clear CKP10 to 0.
3. To use the slave mode, set CKS102, CKS1 01, and CKS100 to 1, 1, 1.
4.
µ
PD780102, 780103, and 78F0103 only.
Remark ×: don’t care
CSIE10: Bit 7 of serial operation mode register 10 (CSIM10)
TRMD10: Bit 6 of CSIM10
CKP10: Bit 4 of serial clock selection register 10 (CSIC10)
CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10
PM1×: Port mode register
P1×: Port output latch
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(2) Communication operation
In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or
received in synchronization with the serial clock.
Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1.
Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition,
data can be received when bit 6 (TRMD10) of serial operat ion mode register 10 (CSIM10) is 0.
Reception is started when data is read from serial I/O shift register 10 (SIO10).
After communication has bee n started, bit 0 (CSOT10) of CSIM10 is set to 1. W hen communication of 8-bit d ata
has been completed, a comm unication completion interrupt requ est flag (CSIIF10) is set, and CSOT10 is cleared
to 0. Then the next communication is enabled.
Caution Do not access the control register and data register when CSOT10 = 1 (during serial
communication).
Figure 13-5. Timing in 3-Wire Serial I/O Mode (1/2)
(1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0)
AAHABH 56H ADH 5AH B5H 6AH D5H
55H (communication data)
55H is written to SOTB10.
SCK10
SOTB10
SIO10
CSOT10
CSIIF10
SO10
SI10 (receive AAH)
Read/write trigger
INTCSI10
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Figure 13-5. Timing in 3-Wire Serial I/O Mode (2/2)
(2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1)
ABH 56H ADH 5AH B5H 6AH D5H
SCK10
SOTB10
SIO10
CSOT10
CSIIF10
SO10
SI10 (input AAH)
AAH
55H (communication data)
55H is written to SOTB10.
Read/write trigger
INTCSI10
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Figure 13-6. Timing of Clock/Data Phase
(a) Type 1; CKP10 = 0, DAP10 = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
Writing to SOTB10 or
reading from SIO10
SI10 capture
CSIIF10
CSOT10
(b) Type 2; CKP10 = 0, DAP10 = 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
Writing to SOTB10 or
reading from SIO10
SI10 capture
CSIIF10
CSOT10
(c) Type 3; CKP10 = 1, DAP10 = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
Writing to SOTB10 or
reading from SIO10
SI10 capture
CSIIF10
CSOT10
(d) Type 4; CKP10 = 1, DAP10 = 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
Writing to SOTB10 or
reading from SIO10
SI10 capture
CSIIF10
CSOT10
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(3) Timing of output to SO10 pin (first bit)
When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin.
The output operation of the first bit at this time is described belo w.
Figure 13-7. Output Operation of First Bit
(1) When CKP10 = 0, DAP10 = 0 (or CKP10 = 1, DAP10 = 0)
SCK10
SOTB10
SIO10
SO10
Writing to SOTB10 or
reading from SIO10
First bit 2nd bit
Output latch
The first bit is directly latched by the SOTB10 register to the outp ut latch at the falling (or rising) ed ge of SCK10,
and output from the SO10 pin via an o utput select or. Then, the v alue of the SOTB10 r e gister is transferred to the
SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of
the receive data is stored in the SIO10 register via the SI10 pin.
The second and subsequent bits are l atched by the SIO10 r egister to the output latch at the next fal ling (or rising)
edge of SCK10, and the data is output from the SO10 pin.
(2) When CKP10 = 0, DAP10 = 1 (or CKP10 = 1, DAP10 = 1)
SCK10
SOTB10
SIO10
SO10
Writing to SOTB10 or
reading from SIO10
First bit 2nd bit 3rd bit
Output latch
The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10
register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the
value of the SOTB10 register is transferred to the SIO10 register at the next falling (or risi ng) ed ge of SCK10, an d
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin.
The second and subsequent bits are l atched by the SIO10 r egister to the o utput latch at the next ris ing (or falli ng)
edge of SCK10, and the data is output from the SO10 pin.
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(4) Output value of SO10 pin (last bit)
After communication has been completed, the SO10 pin holds the output value of the last bit.
Figure 13-8. Output Value of SO10 Pin (Last Bit)
(1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0)
SCK10
SOTB10
SIO10
SO10
Writing to SOTB10 or
reading from SIO10 ( ← Next request is issued.)
Last bit
Output latch
(2) Type 2; when CKP10 = 0 and DAP10 = 1 (or CKP10 = 1, DAP10 = 1)
SCK10
SOTB10
SIO10
SO10 Last bit
Writing to SOTB10 or
reading from SIO10 ( ← Next request is issued.)
Output latch
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(5) SO10 output
The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is
cleared to 0.
Table 13-3. SO10 Output Status
TRMD10 DAP10 DIR10 SO10 Output
TRMD10 = 0Note − − Outputs low levelNote.
DAP10 = 0 − Value of SO10 latch
(low-level output)
DIR10 = 0 Value of bit 7 of SOTB10
TRMD10 = 1
DAP10 = 1
DIR10 = 1 Value of bit 0 of SOTB10
Note Status after reset
Caution If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes.
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CHAPTER 14 INTERRUPT FUNCTIONS
14.1 Interrupt Function Types
The following two types of interrupt function s are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specification flag regi sters (PR0L, PR0H, PR1L).
Multiple interrupt servicing of high-priority interrupts can be applied to low priority interrupts. If two or more
interrupts with the same priority are simultaneously generated, each interrupt is serviced according to its
predetermined priority (see Table 14-1).
A standby release signal is gener ated and the STOP mode and HALT mode are released by maskable interrupts.
Six external interrupt requests and 12 i nternal interrupt requests are provided as maskable interrupts.
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even w hen interrupts
are disabled. The software interrupt does not under go interrupt priority control.
14.2 Interrupt Sources and Configuration
A total of 19 interrupt sources exist for maskable and software interrupts. In addition, maximum total of 5 reset
sources are also provided (see Table 14-1).
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Table 14-1. Interrupt Source List
Interrupt Source
Interrupt
Type Default
PriorityNote 1 Name Trigger
Internal/
External Vector
Table
Address
Basic
Configuration
TypeNote 2
0 INTLVI Low-voltage detection Note 3 Internal 0004H (A)
1 INTP0 0006H
2 INTP1 0008H
3 INTP2 000AH
4 INTP3 000CH
5 INTP4 000EH
6 INTP5
Pin input edge detection External
0010H
(B)
7 INTSRE6 UART6 reception error generation 0012H
8 INTSR6 End of UART6 reception 0014H
9 INTST6 End of UART6 transmission 0016H
10 INTCSI10/
INTST0Note 4 End of CSI10 communication/end of UART0
transmission 0018H
11 INTTMH1
Match between TMH1 and CRH1
(when compare register is specified) 001AH
12 INTTMH0
Match between TMH0 and CRH0
(when compare register is specified) 001CH
13 INTTM50
Match between TM50 and CR50
(when compare register is specified) 001EH
14 INTTM000
Match between TM00 and CR000
(when compare register is specified) 0020H
15 INTTM010
Match between TM00 and CR010
(when compare register is specified) 0022H
16 INTAD End of A/D conversion 0024H
Maskable
17 INTSR0Note 4 End of UART0 reception
Internal
0026H
(A)
Software − BRK BRK instruction execution − 003EH (C)
RESET Reset input
POC Power-on-clear Note 5
LVI Low-voltage detection Note 6
Clock
monitor X1 input clock stop detection
Reset −
WDT WDT overflow
− 0000H −
Notes 1. The default priority is the priority applicable when two or more maskable interrupt are generated
simultaneously. 0 is the highes t priority, and 17 is the lowest.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 14-1.
3. When bit 1 (LVIMD) = 0 is selected for the low-voltage detection register (LVIM).
4. The interrupt sources INTST0 and INTSR0 are available only in the
µ
PD780102, 780103, and
78F0103.
5. When “POC used” is selected by mask option.
6. When LVIMD = 1 is selected.
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Figure 14-1. Basic Configuration of Interrupt Function
(A) Internal maskable interrupt
Internal bus
Interrupt
request IF
MK IE PR ISP
Priority controller Vector table
address generator
Standby release signal
(B) External maskable interrupt (INTP0 to INTP5)
Internal bus
Interrupt
request IF
MK IE PR ISP
Priority controller Vector table
address generator
Standby release signal
External interrupt edge
enable register
(EGP, EGN)
Edge
detector
(C) Software interrupt
Internal bus
Interrupt
request Priority controller Vector table
address generator
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag
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14.3 Registers Controlling Interrupt Function
The following 6 types of registers are used to control the int errupt functio ns.
• Interrupt request flag register (IF0L, IF0H, IF1L)
• Interrupt mask flag register (MK0L, MK0H, MK1L)
• Priority specification flag register (PR0L, PR0H, PR1L)
• External interrupt rising edge enable register (EGP)
• External interrupt falling edge enable register (EGN)
• Program status word (PSW)
Table 14-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding
to interrupt request sources.
Table 14-2. Flags Corresponding to Interrupt Request Sources
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Request Register Register Register
INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L
INTP0 PIF0 PMK0 PPR0
INTP1 PIF1 PMK1 PPR1
INTP2 PIF2 PMK2 PPR2
INTP3 PIF3 PMK3 PPR3
INTP4 PIF4 PMK4 PPR4
INTP5 PIF5 PMK5 PPR5
INTSRE6 SREIF6 SREMK6 SREPR6
INTSR6 SRIF6 IF0H SRMK6 MK0H SRPR6 PR0H
INTST6 STIF6 STMK6 STPR6
INTST0Note 1 DUALIF0Note 2 DUALMK0Note 4 DUALPR0Note 4
INTCSI10 CSIIF10Note 3 CSIMK10Note 3 CSIPR10Note 3
INTTMH1 TMIFH1 TMMKH1 TMPRH1
INTTMH0 TMIFH0 TMMKH0 TMPRH0
INTTM50 TMIF50 TMMK50 TMPR50
INTTM000 TMIF000 TMMK000 TMPR000
INTTM010 TMIF010 TMMK010 TMPR010
INTAD ADIF IF1L ADMK MK1L ADPR PR1L
INTSR0Note 1 SRIF0Note 1 SRMK0Note 1 SRPR0Note 1
Notes 1.
µ
PD780102, 780103, and 78F0103 only.
2. Flag name in the
µ
PD780102, 780103, an d 78F0103. If either of the two types of interru pt sources is
generated, these flags are set (1).
3. Flag name in the
µ
PD780101
4. These are the flag nam es in the
µ
PD780102, 780103, and 78F0103. These flags support two types
of interrupt sources.
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 whe n the corresponding interrupt requ est is generated or an instruction is
executed. They are cleared t o 0 w hen a n in struction is exe cuted upo n ack nowled gment o f an i nterrupt r equest or
upon application of RESET input.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are read with a 16-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Figure 14-2. Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L)
Address: FFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF
Address: FFE1H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0Note 1 STIF6 SRIF6
Address: FFE2H After reset: 00H R/W
Symbol 7 6 5 4 3 2 <1> <0>
IF1L 0 0 0 0 0 0 SRIF0Note 2 ADIF
XXIFX Interrupt request flag
0 No interrupt request signal is generated
1 Interrupt request is generated, interrupt request status
Notes 1. This is CSIIF10 in the
µ
PD780101.
2.
µ
PD780102, 780103, and 78F0103 only.
Cautions 1. Be sure to set bits 2 to 7 of IF1L to 0.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
3. If an interrupt request corresponding to a flag of the interrupt request flag register is
generated while the interrupt request flag register is being manipulated (including by 1-bit
memory manipulation), the flag corresponding to the interrupt request may not be set to 1.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flags are used to enable/disab le the corresponding maskable interrupt servicing.
MK0L, MK0H, and MK1L ar e set by a 1-bit or 8-bit memory manipulation instruction. Wh en MK0L and MK0H are
combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation i nstruction.
RESET input sets these registers to FFH.
Figure 14-3. Format of Interrupt Mask Flag Register (MK0L, MK0H, MK1L)
Address: FFE4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK
Address: FFE5H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0Note 1 STMK6 SRMK6
Address: FFE6H After reset: FFH R/W
Symbol 7 6 5 4 3 2 <1> <0>
MK1L 1 1 1 1 1 1 SRMK0Note 2 ADMK
XXMKX Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Notes 1. This is CSIMK10 in the
µ
PD780101.
2.
µ
PD780102, 780103, and 78F0103 only.
Caution Be sure to set bits 2 to 7 of MK1L to 1.
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(3) Priority specification flag registers (PR0L, PR0H, PR1L)
The priority specification flag registers are used to set the corresponding maskable inter r upt priority order.
PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 14-4. Format of Priority Specification Flag Register (PR0L, PR0H, PR1L)
Address: FFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR
Address: FFE9H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0Note 1 STPR6 SRPR6
Address: FFEAH After reset: FFH R/W
Symbol 7 6 5 4 3 2 <1> <0>
PR1L 1 1 1 1 1 1 SRPR0Note 2 ADPR
XXPRX Priority level selection
0 High priority level
1 Low priority level
Notes 1. This is CSIPRI0 in the
µ
PD780101.
2.
µ
PD780102, 780103, and 78F0103 only.
Caution Be sure to set bits 2 to 7 of PR1L to 1.
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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
These registers specify the valid edge for INTP0 to INTP5.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 14-5. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)
Address: FF48H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP 0 0 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0
Address: FF49H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0
EGPn EGNn INTPn pin valid edge selection (n = 0 to 5)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Table 14-3 shows the ports corresponding to EGPn and EGNn.
Table 14-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register Edge Detection Port Interrupt Request Signal
EGP0 EGN0 P120 INTP0
EGP1 EGN1 P30 INTP1
EGP2 EGN2 P31 INTP2
EGP3 EGN3 P32 INTP3
EGP4 EGN4 P33 INTP4
EGP5 EGN5 P16 INTP5
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when
the external interrupt function is switched to the port function.
Remark n = 0 to 5
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(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple
interrupt servicing are mapped to the PSW .
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,
the contents of the PSW are automatic ally saved into a stack and the IE flag is reset to 0. If a maskable interru pt
request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are
transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction.
They are restored from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 14-6. Format of Program Status Word
<7>
IE
<6>
Z
<5>
RBS1
<4>
AC
<3>
RBS0
2
0
<1>
ISP
0
CYPSW
After reset
02H
ISP
High-priority interrupt servicing (low-priority
interrupt disabled)
IE
0
1
Disabled
Priority of interrupt currently being serviced
Interrupt request acknowledgment enable/disable
Used when normal instruction is executed
Enabled
Interrupt request not acknowledged, or low-
priority interrupt servicing (all maskable
interrupts enabled)
0
1
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14.4 Interrupt Servicing Operations
14.4.1 Maskable interrupt request acknowledgment
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask
(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if
interrupts are in the interrupt enabled state (when the IE fl ag is set to 1). However, a low-priority interrupt request is
not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
The times from generation of a maskable int errupt request until interrupt servicing is performed are listed in Tabl e
14-4 below.
For the interrupt request acknowledgment timing, see Figures 14-8 and 14-9.
Table 14-4. Time from Generation of Maskable Interrupt Request Until Servicing
Minimum Time Maximum TimeNote
When ××PR = 0 7 clocks 32 clocks
When ××PR = 1 8 clocks 33 clocks
Note If an interrupt request is gene r ated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeabl e.
Figure 14-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledge d, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data deter mined for each int errupt request is loaded into the
PC and branched.
Restoring from an interrupt is possible by using the RETI in struction.
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User’s Manual U15836EJ4V0UD 285
Figure 14-7. Interrupt Request Acknowledgment Processing Algorithm
Start
××IF = 1?
××MK = 0?
××PR = 0?
IE = 1?
ISP = 1?
Interrupt request held pending
Yes
Yes
No
No
Yes (interrupt request generation)
Yes
No (Low priority)
No
No
Yes
Yes
No
IE = 1?
No
Any high-priority
interrupt request among those
simultaneously generated
with ××PR = 0?
Yes (High priority)
No
Yes
Yes
No
Vectored interrupt servicing
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Vectored interrupt servicing
Any high-priority
interrupt request among
those simultaneously
generated?
Any high-priority
interrupt request among
those simultaneously generated
with ××PR = 0?
××IF: Interrupt request flag
××MK: Interrupt mask flag
××PR: Priority specification flag
IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt
servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)
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Figure 14-8. Interrupt Request Acknowledgment Timing (Minimum Time)
8 clocks
7 clocks
Instruction Instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
CPU processing
××IF
(××PR = 1)
××IF
(××PR = 0)
6 clocks
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
Figure 14-9. Interrupt Request Acknowledgment Timing (Maximum Time)
33 clocks
32 clocks
Instruction Divide instruction PSW and PC saved,
jump to interrupt
servicing Interrupt servicing
program
CPU processing
××IF
(××PR = 1)
××IF
(××PR = 0)
6 clocks25 clocks
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
14.4.2 Software interrupt request acknowledgment
A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be
disabled.
If a software interrupt request is acknowledged, the content s are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH,
003FH) are loaded into the PC and br anched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Do not use the RETI instruction for restoring from the software interrupt.
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14.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during executio n of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable in terrupt acknowledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is us ed for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
currently being serviced is generate d, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is gener ated during interrupt servicing, it is not acknowl edged
for multiple interrupt servicing.
Interrupt requests that are not ena bled because interrupts are in the interrupt disabled s tate or because they have
a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction execution.
Table 14-5 shows relationship between interr upt requests enabled for multiple interru pt servicing and Figure 14-10
shows multiple interrupt servicing exampl es.
Table 14-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Multiple Interrupt Request Maskable Interrupt Request
PR = 0 PR = 1
Interrupt Being Serviced IE = 1 IE = 0 IE = 1 IE = 0
Software
Interrupt
Request
ISP = 0 × × × Maskable interrupt
ISP = 1 × ×
Software interrupt × ×
Remarks 1. : Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. The ISP and IE are flags contained in the PSW.
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower
priority is being serviced.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in PR0L, PR0H, and PR1L.
PR = 0: Higher priority level
PR = 1: Lower priority level
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Figure 14-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI EI EI
RETI RETI
RETI
INTxx
(PR = 1) INTyy
(PR = 0) INTzz
(PR = 0)
IE = 0 IE = 0 IE = 0
IE = 1 IE = 1 IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple
interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be
issued to enable interrupt request acknowled gment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing INTxx servicing INTyy servicing
INTxx
(PR = 0) INTyy
(PR = 1)
EI
RETI
IE = 0
IE = 0
EI
1 instruction execution
RETI
IE = 1
IE = 1
Interrupt request INTyy issued during servici ng of interrupt INTxx is not acknowledged be cause its priority is lower
than that of INTxx, and multiple interrupt servicing does n ot take place. The INTyy interrupt request is held pending,
and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
PR = 1: Lower priority level
IE = 0: Interrupt request acknowledgment disa bled
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User’s Manual U15836EJ4V0UD 289
Figure 14-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing INTxx servicing INTyy servicing
EI
1 instruction execution
RETI
RETI
INTxx
(PR = 0)
INTyy
(PR = 0)
IE = 0
IE = 0
IE = 1
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt
request INTyy is not acknowledged and mult iple interrupt servicing does not take place. The INTyy interrupt request
is held pending, and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
IE = 0: Interrupt request acknowledgment disa bled
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14.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued for them while another instruction is being
executed, request acknowledgment is held pending until the end of execution of the next instruction. These
instructions (interrupt request hold instruction s) are listed below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW. bit, CY
• MOV1 CY, PSW. bit
• AND1 CY, PSW. bit
• OR1 CY, PSW. bit
• XOR1 CY, PSW. bit
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW. bit, $addr16
• BF PSW. bit, $addr16
• BTCLR PSW. bit, $addr16
• EI
• DI
• Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L register s
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However ,
the software interrupt activated by execu ting the BRK instruction causes the IE fla g to be cleare d
to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK
instruction, the interrupt request is not acknowledged.
Figure 14-11 shows the timing at which interrupt requests are held pending.
Figure 14-11. Interrupt Request Hold
Instruction N Instruction M PSW and PC saved, jump
to interrupt servicing Interrupt servicing
program
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
User’s Manual U15836EJ4V0UD 291
CHAPTER 15 STANDBY FUNCTION
15.1 Standby Function and Configuration
15.1.1 Standby function
Table 15-1. Relationship Between Operation Clocks in Each Operation Status
Ring-OSC Oscillator Prescaler Clock Supplied to
Peripherals
Note 2
Status
Operation
Mode
X1 Oscillator
Note 1
RSTOP = 0 RSTOP = 1
CPU Clock
After
Release MCM0 = 0 MCM0 = 1
Reset Stopped Ring-OSC Stopped
STOP
Stopped
Note 3 Stopped
HALT Oscillating
Oscillating Oscillating Stopped
Note 4 Ring-OSC X1
Notes 1. When “Ca nnot be stopped” is selected for Ring-OSC by a mask option.
2. When “Can be stopped by software” is selected for Ring-OSC by a mask option.
3. Operates using the CPU clock at STOP instruction execution.
4. Operates using the CPU clock at HALT instruction execution.
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC by a mask
option.
Remark RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
MCM0: Bit 0 of the main clock mode register (MCM)
The standby function is designed to reduce the operating current consumption of the system. The following two
modes are available.
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(1) HALT mode
HALT instruction execution sets the HALT mode. The HALT mode is i ntended to sto p t he CP U operation clock. If
the X1 input clock and Ring- OSC clock oscillator are op erating before the HALT mode is set, oscillati on of the X1
input clock and Ring-OSC clock continues. In this mode, operating current is not decreased as much as in the
STOP mode. However, the HALT mode is effective for restarting operation immediately upon interrupt request
generation and carrying out in termittent operations.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the X1 oscillato r stops, stopping the whole
system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released, select the HALT mode if it is necessary to start processing immediately upon interrupt request
generation.
In either of these two modes, all the content s of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction.
2. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode
register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP
instruction.
3. If the Ring-OSC oscillator is operating before the STOP mode is set, oscillation of the Ring-
OSC clock cannot be stopped in the STOP mode. However, when the Ring-OSC clock is used
as the CPU clock, operation is stopped for 17/fR (s) after STOP mode is released.
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15.1.2 Registers controlling standby function
The standby function is controlled by the following two re gisters.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the register s that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
(1) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation st abilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, and
MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H.
Figure 15-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16
MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status
1 0 0 0 0 211/fX min. (204.8
µ
s min.)
1 1 0 0 0 213/fX min. (819.2
µ
s min.)
1 1 1 0 0 214/fX min. (1.64 ms min.)
1 1 1 1 0 215/fX min. (3.27 ms min.)
1 1 1 1 1 216/fX min. (6.55 ms min.)
Cautions 1. After the above time has elapsed, th e bits are set to 1 in order from MOST11 and
remain 1.
2. If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
3. The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
a
STOP mode release
X1 pin voltage
waveform
Remarks 1. Values in parentheses are referenc e values for operation with fX = 10 MHz.
2. fX: X1 input clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait
time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU
clock. After STOP mode is released when the Ring-OSC cl ock is selected , check the oscillati on stabiliza tion time
using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 15-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
0 0 1 211/fX (204.8
µ
s)
0 1 0 213/fX (819.2
µ
s)
0 1 1 214/fX (1.64 ms)
1 0 0 215/fX (3.27 ms)
1 0 1 216/fX (6.55 ms)
Other than above Setting prohibited
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
2. The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
a
STOP mode release
X1 pin voltage
waveform
Remarks 1. Values in parentheses are reference values for operation wit h f X = 10 MHz.
2. f
X: X1 input clock oscillation frequency
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15.2 Standby Function Operation
15.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set when the CPU clock before
the setting was the X1 input clock or Ring-OSC clock.
The operating statuses in the HALT mode ar e shown below.
Table 15-2. Operating Statuses in HALT Mode
When HALT Instruction Is Executed While
CPU Is Operating Using X1 Input Clock When HALT Instruction Is Executed While
CPU Is Operating Using Ring-OSC Clock
HALT Mode Setting
Item Ring-OSC Oscillation
Continues Ring-OSC Oscillation
StoppedNote 1 X1 Input Clock
Oscillation Continues X1 Input Clock
Oscillation Stopped
System clock Clock supply to the CPU is stopped
CPU Operation stopped
Port (output latch) Holds the status before HALT mode was set
16-bit timer/event counter 00 Operable Operation not guaranteed
8-bit timer/event counter 50 Operable Operation not guaranteed when count
clock other than TI50 is selected
8-bit timer H0 Operable Operation not guaranteed when count
clock other than TM50 output is selected
during 8-bit timer/event counter 50
operation
8-bit timer H1 Operable Operation not guaranteed when count
clock other than fR/27 is selected
Ring-OSC cannot be
stoppedNote 2 Operable − Operable
Watchdog
timer
Ring-OSC can be
stoppedNote 2 Operation stopped
A/D converter Operable Operation not guaranteed
UART0Note 3 Operable
UART6 Operable
Operation not guaranteed when serial
clock other than TM50 output is selected
during 8-bit timer/event counter 50
operation
Serial interface
CSI10 Operable Operation not guaranteed when serial
clock other than external SCK10 is
selected
Clock monitor Operable Operation stopped Operable Operation stopped
Power-on-clear functionNote 4 Operable
Low-voltage detection function Operable
External interrupt Operable
Notes 1. When “Stopped by software” is selected for Ring-OSC by a mask option and Ring-OSC is stopped by
software (for mask options, see CHAPTER 20 MASK OPTIONS).
2. “Ring-OSC cannot be stopped” or “Ring-OSC can be stopped by software” can be selected by a mask
option.
3.
µ
PD780102, 780103, and 78F0103 only.
4. When “POC used” is selected by a mask option.
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt
acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is
disabled, the next address instruction is executed.
Figure 15-3. HALT Mode Release by Interrupt Request Generation
HALT
instruction Wait
Wait Operating modeHALT modeOperating mode
Oscillation
X1 input clock or
Ring-OSC clock
Status of CPU
Standby
release signal
Interrupt
request
Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 8 or 9 clocks
• When vectored interrupt servicing is not carried out: 2 or 3 clocks
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(b) Release by RESET input
When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is exe cuted after branching to the reset vector address.
Figure 15-4. HALT Mode Release by RESET Input
(1) When X1 input clock is used as CPU clock
HALT
instruction
RESET signal
X1 input clock
Operating mode HALT mode Reset
period
Operation
stopped
Operating mode
Oscillates
Oscillation
stopped
Oscillates
Status of CPU (X1 input clock)
Oscillation stabilization time
(211/fXP to 216/fXP)
(Ring-OSC clock)
(17/fR)
(2) When Ring-OSC clock is used as CPU clock
HALT
instruction
RESET signal
Ring-OSC clock
Operating mode HALT mode Reset
period
Operation
stopped
Operating mode
Oscillates
Oscillation
stopped
Oscillates
Status of CPU (Ring-OSC clock)(17/f
R
)
(Ring-OSC clock)
Remarks 1. fXP: X1 input clock oscillation frequency
2. f
R: Ring-OSC clock oscillation frequency
Table 15-3. Operation in Response to Interrupt Request in HALT Mode
Release Source MK×× PR×× IE ISP Operation
0 0 0 × Next address
instruction execution
0 0 1 × Interrupt servicing
execution
0 1 0 1
0 1 × 0
Next address
instruction execution
0 1 1 1
Interrupt servicing
execution
Maskable interrupt
request
1 × × × HALT mode held
RESET input − − × × Reset processing
×: Don’t care
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15.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing t he STOP instruction. It can be set when the CPU clock b efore the setting
was the X1 input clock or Ring-OSC clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
Table 15-4. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While
CPU Is Operating Using X1 Input Clock
HALT Mode Setting
Item Ring-OSC Oscillation
Continues Ring-OSC Oscillation
StoppedNote 1
When STOP Instruction Is Executed While
CPU Is Operating Using Ring-OSC Clock
System clock Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped.
CPU Operation stopped
Port (output latch) Holds the status before STOP mode was set
16-bit timer/event counter 00 Operation stopped
8-bit timer/event counter 50 Operable only when TI50 is selected as count clock
8-bit timer H0 Operable when TM50 output is selected as count clock during 8-bit timer/event counter
50 operation
8-bit timer H1 OperableNote 2 Operation stopped OperableNote 2
Ring-OSC cannot be
stoppedNote 3 Operable − Operable
Watchdog
timer
Ring-OSC can be
stoppedNote 3 Operation stopped
A/D converter Operation stopped
UART0Note 4
UART6
Operable only when TM50 output is selected as count clock during 8-bit timer/event
counter 50 operation
Serial interface
CSI10 Operable only when external SCK10 is selected as serial clock
Clock monitor Operation stopped
Power-on-clear functionNote 5 Operable
Low-voltage detection function Operable
External interrupt Operable
Notes 1. When “Stopped by software” is selected for Ring-OSC by a mask option and Ring-OSC is stopped by
software (for mask options, see CHAPTER 20 MASK OPTIONS).
2. Operable only when fR/27 is selected as count clock.
3. “Ring-OSC cannot be stopped” or “Ring-OSC can be stopped by software” can be selected by a mask
option.
4.
µ
PD780102, 780103, and 78F0103 only.
5. When “POC used” is selected by a mask option.
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(2) STOP mode release
Figure 15-5. Operation Timing When STOP Mode Is Released
Ring-OSC clock is
selected as CPU clock
when STOP instruction
is executed
Ring-OSC clock
X1 input clock
X1 input clock is
selected as CPU clock
when STOP instruction
is executed
STOP mode release
STOP mode
Operation stopped
(17/fR)Clock switched
by software
Ring-OSC clock X1 input clock
HALT status
(oscillation stabilization time set by OSTS)
X1 input clock
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The STOP mode can be released by the followin g two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowl edgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is execute d.
Figure 15-6. STOP Mode Release by Interrupt Request Generation
(1) When X1 input clock is used as CPU clock
Operating mode Operating mode
Oscillates
Oscillates
STOP
instruction
STOP mode
Wait
(set by OSTS)
Standby release signal
Oscillation stabilization
wait status
Oscillation stopped
X1 input clock
Status of CPU
Oscillation stabilization time (set by OSTS)
(X1 input clock)(X1 input clock)
(2) When Ring-OSC clock is used as CPU clock
Operating mode Operating mode
Oscillates
STOP
instruction
STOP mode
Standby release signal
Ring-OSC clock
Status of CPU
(Ring-OSC clock)
Operation
stopped
(17/f
R
)
(Ring-OSC clock)
Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby
mode is acknowledged.
2. fR: Ring-OSC clock oscillation freque ncy
CHAPTER 15 STANDBY FUNCTION
User’s Manual U15836EJ4V0UD 301
(b) Release by RESET input
When the RESET signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 15-7. STOP Mode Release by RESET Input
(1) When X1 input clock is used as CPU clock
STOP
instruction
RESET signal
X1 input clock
Operating mode STOP mode Reset
period
Operation
stopped
Operating mode
Oscillates
Oscillation
stopped
Oscillates
Status of CPU (X1 input clock)
Oscillation stabilization time (2
11
/f
XP
to 2
16
/f
XP
)
(Ring-OSC clock)(17/f
R
)
Oscillation stopped
(2) When Ring-OSC clock is used as CPU clock
STOP
instruction
RESET signal
Ring-OSC clock
Operating mode STOP mode Reset
period
Operation
stopped
Operating mode
Oscillates
Oscillation
stopped
Oscillates
Status of CPU (Ring-OSC clock)(17/f
R
)
(Ring-OSC clock)
Remarks 1. fXP: X1 input clock oscillation frequency
2. f
R: Ring-OSC clock oscillation frequency
Table 15-5. Operation in Response to Interrupt Request in STOP Mode
Release Source MK×× PR×× IE ISP Operation
0 0 0 × Next address
instruction execution
0 0 1 × Interrupt servicing
execution
0 1 0 1
0 1 × 0
Next address
instruction execution
0 1 1 1
Interrupt servicing
execution
Maskable interrupt
request
1 × × × STOP mode held
RESET input − − × × Reset processing
×: Don't care
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CHAPTER 16 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by clock monitor X1 clock oscillation stop detection
(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets h ave no functional differences . In both cases, program execution starts at the addr ess
at 0000H and 0001H when the reset signal is input.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation
stop is detected by the clock monitor, or by POC and LVI circuit voltag e detection, an d each item of hardware is set to
the status shown in Table 16-1. Each pin is high impedance during reset input or during the oscillation stabilization
time just after reset release, except for P130, which is low-level outp ut.
When a high level is input to the RESET pin, the reset is released and program execution starts using the Ring-
OSC clock after the CPU clock operation has stopped for 17/fR (s). A reset generated by the watchdog timer and
clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC
clock after the CPU clock operation has stopped for 17/fR (s) (see Figures 16-2 to 16-4). Reset by POC and LVI
circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program
execution starts using the Ri ng-OSC clock af ter the CPU clock op eration has stoppe d for 17/fR (s) (see CHAPTER 18
POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR).
Cautions 1. For an external reset, input a low level for 10
µ
s or more to the RESET pin.
2. During reset input, the X1 input clock and Ring-OSC clock stop oscillating.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance, except for P130, which is set to low-
level output.
CHAPTER 16 RESET FUNCTION
User’s Manual U15836EJ4V0UD 303
Figure 16-1. Block Diagram of Reset Function
CLMRF LVIRF
WDTRF
Reset control flag
register (RESF)
Internal bus
Watchdog timer reset signal
Clock monitor reset signal
RESET
Power-on-clear circuit reset signal
Low-voltage detector reset signal
Reset signal
Reset signal
Reset signal to LVIM/LVIS register
Clear
SetSet
Clear Clear
Set
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltag e detection register
2. LVIS: Low-voltage detection level selection register
CHAPTER 16 RESET FUNCTION
User’s Manual U15836EJ4V0UD
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Figure 16-2. Timing of Reset by RESET Input
Delay Delay
Hi-ZNote
Normal operationCPU clock Reset period
(Oscillation stop)
Operation stop
(17/fR)Normal operation
(Reset processing, Ring-OSC clock)
RESET
Internal
reset signal
Port pin
X1 input clock
Ring-OSC clock
Note The port pins become high im pedance, except for P130, which is set to low-level output.
Figure 16-3. Timing of Reset Due to Watchdog Timer Overflow
Hi-Z
Note
Normal operation Reset period
(Oscillation stop)
CPU clock
Watchdog timer
overflow
Internal
reset signal
Port pin
Operation stop
(17/f
R
)Normal operation
(Reset processing, Ring-OSC clock)
X1 input clock
Ring-OSC clock
Note The port pins become high im pedance, except for P130, which is set to low-level output.
Caution A watchdog timer internal reset resets the watchdog timer.
CHAPTER 16 RESET FUNCTION
User’s Manual U15836EJ4V0UD 305
Figure 16-4. Timing of Reset in STOP Mode by RESET Input
Delay Delay
Hi-Z
Note
Normal
operation
CPU clock Reset period
(Oscillation stop)
RESET
Internal
reset signal
Port pin
STOP instruction execution
Stop status
(Oscillation stop)
Operation stop
(17/f
R
)Normal operation
(Reset processing, Ring-OSC clock)
X1 input clock
Ring-OSC clock
Note The port pins become high im pedance, except for P130, which is set to low-level output.
Remark For the reset ti ming of the power-on-clear circuit and low-voltage detector, see CHAPTER 18 POWER -
ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR.
CHAPTER 16 RESET FUNCTION
User’s Manual U15836EJ4V0UD
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Table 16-1. Hardware Statuses After Reset Acknowledgment (1/2)
Hardware Status After Reset
AcknowledgmentNote 1
Program counter (PC) The contents of the
reset vector table
(0000H, 0001H) are
set.
Stack pointer (SP) Undefined
Program status word (PSW) 02H
Data memory UndefinedNote 2 RAM
General-purpose registers UndefinedNote 2
Port registers (P0 to P3, P12, P13) (output latches) 00H (undefined only
for P2)
Port mode registers (PM0, PM1, PM3, PM12) FFH
Pull-up resistor option registers (PU0, PU1, PU3, PU12) 00H
Input switch control register (ISC) 00H
Internal memory size switching regi ster (IMS ) CFH
Internal expansion RAM size switching register (IXS) 0CH
Processor clock control register (PCC) 00H
Ring-OSC mode register (RCM) 00H
Main clock mode register (MCM) 00H
Main OSC control register (MOC) 00H
Oscillation stabilization time select register (OSTS) 05H
Oscillation stabilization time counter status register (OSTC) 00H
Timer counter 00 (TM00) 0000H
Capture/compare registers 000, 010 (CR000, CR010) 0000H
Mode control register 00 (TMC00) 00H
Prescaler mode register 00 (PRM00) 00H
Capture/compare control register 00 (CRC00) 00H
16-bit timer/event counter 00
Timer output control register 00 (TOC00) 00H
Timer counter 50 (TM50) 00H
Compare register 50 (CR50) 00H
Timer clock selection register 50 (TCL50) 00H
8-bit timer/event counter 50
Mode control register 50 (TMC50) 00H
Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H 8-bit timer/event counters H0, H1
Mode registers (TMHMD0, TMHMD1) 00H
Mode register (WDTM) 67H Watchdog timer
Enable register (WDTE) 9AH
Conversion result register (ADCR) Undefined
Mode register (ADM) 00H
Analog input channel specification register (ADS) 00H
Power-fail comparison mode register (PFM) 00H
A/D converter
Power-fail comparison threshold register (PFT) 00H
Notes 1. During reset input or osc illation stabi lization t ime wait, only t he PC conte nts among the h ardware status es
become undefined. All other h ardware statuses remain unchanged after reset.
2. When a reset is executed i n the standby mode, the pre-reset status is held even after reset.
CHAPTER 16 RESET FUNCTION
User’s Manual U15836EJ4V0UD 307
Table 16-1. Hardware Statuses After Reset Acknowledgment (2/2)
Hardware Status After Reset
Acknowledgment
Receive buffer register 0 (RXB0) FFH
Transmit shift register 0 (TXS0) FFH
Asynchronous serial interface operation mode register 0 (ASIM0) 01H
Serial interface UART0Note 1
Baud rate generator control register 0 (BRGC0) 1FH
Receive buffer register 6 (RXB6) FFH
Transmit buffer register 6 (TXB6) FFH
Asynchronous serial interface operation mode register 6 (ASIM6) 01H
Asynchronous serial interface reception error status register 6
(ASIS6) 00H
Asynchronous serial interface transmission error status register 6
(ASIF6) 00H
Clock selection register 6 (CKSR6) 00H
Baud rate generator control register 6 (BRGC6) FFH
Serial interface UART6
Asynchronous serial interface control register 6 (ASICL6) 16H
Transmit buffer register 10 (SOTB10) Undefined
Serial I/O shift register 10 (SIO10) 00H
Serial operation mode register 10 (CSIM10) 00H
Serial interface CSI10
Serial clock selection register 10 (CSIC10) 00H
Clock monitor Mode register (CLM) 00H
Reset function Reset control flag register (RESF) 00HNote 2
Low-voltage detection register (LVIM) 00HNote 2 Low-voltage detector
Low-voltage detection level selection register (LVIS) 00HNote 2
Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L) 00H
Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L) FFH
Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L) FFH
External interrupt rising edge enable register (EGP) 00H
Interrupt
External interrupt falling edge enable register (EGN) 00H
Notes 1.
µ
PD780102, 780103, and 78F0103 only.
2. These values vary depending on the reset source.
Reset Source
Register
RESET Input Reset by POC Reset by WDT Reset by CLM Reset by LVI
RESF See Table 16-2.
LVIM
LVIS
Cleared (00H) Cleared (00H) Cleared (00H) Cleared (00H) Held
CHAPTER 16 RESET FUNCTION
User’s Manual U15836EJ4V0UD
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16.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0/KB1. The reset control flag register (RESF) is used to
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Figure 16-5. Format of Reset Control Flag Register (RESF)
Address: FFACH After reset: 00HNote R
Symbol 7 6 5 4 3 2 1 0
RESF 0 0 0 WDTRF 0 0 CLMRF LVIRF
WDTRF Internal reset request by watchdog timer (WDT)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
CLMRF Internal reset request by clock monitor (CLM)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
LVIRF Internal reset request by low-voltage detector (LVI)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
Note The value after reset varies depe nding on the reset source.
Caution Do not read data via a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 16-2.
Table 16-2. RESF Status When Reset Request Is Generated
Reset Source
Flag
RESET input Reset by POC Reset by WDT Reset by CLM Reset by LVI
WDTRF Set (1) Held Held
CLMRF Held Set (1) Held
LVIRF
Cleared (0) Cleared (0)
Held Held Set (1)
User’s Manual U15836EJ4V0UD 309
CHAPTER 17 CLOCK MONITOR
17.1 Functions of Clock Monitor
The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset sign al
when the X1 input clock is stopped.
When a reset signal is gener ated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION.
The clock monitor automatically stops under the following conditions.
• Reset is released and during the oscillation stabilization time
• In STOP mode and during the oscillation stabilization time
• When th e X1 i nput clock is stopp ed by software (MSTOP = 1 or M CC = 1) and dur ing the oscill ation stabi lization
time
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
17.2 Configuration of Clock Monitor
The clock monitor includes the following hardware.
Table 17-1. Configuration of Clock Monitor
Item Configuration
Control register Clock monitor mode register (CLM)
Figure 17-1. Block Diagram of Clock Monitor
Operation mode
controller
X1 input clock
Ring-OSC clock
CLME
Clock monitor
mode register (CLM)
Internal bus
X1 oscillation
monitor circuit Internal reset
signal
X1 oscillation control signal
(MSTOP)
X1 oscillation stabilization status
(OSTC overflow)
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
OSTC: Oscillation stabilization time counter status register (OSTC)
CHAPTER 17 CLOCK MONITOR
User’s Manual U15836EJ4V0UD
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17.3 Register Controlling Clock Monitor
The clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
This register sets the operation mode of the clock monitor.
This register can be set by a 1-bit or 8-bit memory manipulation i nstructio n.
RESET input clears this register to 00H.
Figure 17-2. Format of Clock Monitor Mode Register (CLM)
7
0
CLME
0
1
Symbol
CLM
Address: FFA9H After reset: 00H R/W
6
0
Disables clock monitor operation
Enables clock monitor operation
5
0
4
0
3
0
Enables/disables clock monitor operation
2
0
1
0
<0>
CLME
Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal
reset signal.
2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF)
of the reset control flag register (RESF) is set to 1.
CHAPTER 17 CLOCK MONITOR
User’s Manual U15836EJ4V0UD 311
17.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows.
<Monitor start condition>
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1).
< Monitor stop condition>
• Reset is released and during the oscillation stabilization time
• In STOP mode and during the oscillation stabilization time
• When th e X1 i nput clock is stopp ed by software (MSTOP = 1 or M CC = 1) and dur ing the oscill ation stabi lization
time
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
Table 17-2. Operation Status of Clock Monitor (When CLME = 1)
CPU Operation Clock Operation Mode X1 Input Clock Status Ring-OSC Clock Status Clock Monitor Status
Oscillating STOP mode Stopped
StoppedNote
Oscillating RESET input
StoppedNote
Stopped
Oscillating Operating
X1 input clock
Normal operation
mode
HALT mode
Oscillating
StoppedNote Stopped
STOP mode
RESET input
Stopped Oscillating Stopped
Oscillating Operating
Ring-OSC clock
Normal operation
mode
HALT mode Stopped Stopped
Note The Ring-OSC clock is stopped only when the “Ring-OSC can be stopped by software” is selected by a
mask option. If “Ring-OSC cannot be stopped” is selected, the Ring-OSC c lock cannot be stopped.
The clock monitor timing is as shown in Figure 17-3.
CHAPTER 17 CLOCK MONITOR
User’s Manual U15836EJ4V0UD
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Figure 17-3. Timing of Clock Monitor (1/4)
(1) When internal reset is executed by oscillation stop of X1 input clock
4 clocks of Ring-OSC clock
X1 input clock
Ring-OSC clock
Internal reset signal
CLME
CLMRF
(2) Clock monitor status after RESET input
(CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time)
CPU operation
Clock monitor status
CLME
Ring-OSC clock
X1 input clock
Reset
Oscillation
stopped Oscillation stabilization time
Normal
operation Clock supply
stopped Normal operation (Ring-OSC clock)
Monitoring Monitoring stopped Monitoring
Waiting for end
of oscillation
stabilization time
Oscillation
stopped 17 clocks
Set to 1 by software
RESET
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. Even if CLME is set to 1 by software during the oscill ation stabilization time (reset value of OSTS register
is 05H (216/fXP)) of the X1 input clock, monitor ing is not performed until the oscill ation stabilization time of the X1 input
clock ends. Monitoring is automatically started at the end of the oscillation stabilization time.
CHAPTER 17 CLOCK MONITOR
User’s Manual U15836EJ4V0UD 313
Figure 17-3. Timing of Clock Monitor (2/4)
(3) Clock monitor status after RESET input
(CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
CPU operation
Clock monitor status
CLME
RESET
Ring-OSC clock
X1 input clock
Reset
Oscillation stabilization time
Normal
operation Clock supply
stopped Normal operation (Ring-OSC clock)
Monitoring Monitoring stopped Monitoring
17 clocks
Set to 1 by software
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS
register is 05H (216/fXP)) of the X1 input clock, monitoring is started.
(4) Clock monitor status after STOP mode is released
(CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode)
Clock monitor status
Monitoring
Monitoring stopped Monitoring
CLME
Ring-OSC clock
X1 input clock
(CPU clock)
CPU operation Normal
operation STOP Oscillation stabilization time Normal operation
Oscillation
stopped Oscillation stabilization time
(time set by OSTS register)
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the X1 in put clock osc ill atio n stabilizati on t ime. Mon itoring is stop ped in STOP mode
and during the oscillation stabi lization time.
CHAPTER 17 CLOCK MONITOR
User’s Manual U15836EJ4V0UD
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Figure 17-3. Timing of Clock Monitor (3/4)
(5) Clock monitor status after STOP mode is released
(CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode)
Clock monitor status
Monitoring
Monitoring
stopped Monitoring stopped Monitoring
CLME
Ring-OSC clock
(CPU clock)
X1 input clock
CPU operation Normal
operation
17 clocks
Clock supply
stopped Normal operation
Oscillation
stopped Oscillation stabilization time
(time set by OSTS register)
STOP
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the X1 in put clock osc ill atio n stabilizati on t ime. Mon itoring is stop ped in STOP mode
and during the oscillation stabi lization time.
(6) Clock monitor status after X1 input clock oscillation is stopped by software
Clock monitor status
CLME
Ring-OSC clock
MSTOP
X1 input clock
Oscillation stabilization time
(time set by OSTS register)
Normal operation (Ring-OSC clock or subsystem clockNote)
Monitoring
Monitoring
stopped Monitoring
CPU operation
Monitoring stopped
Oscillation
stopped
When bit 0 (CLME) of the clock mon itor mode register (CLM) is set to 1 before or whil e oscillation of the X1 input
clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time.
Monitoring is stopped when oscillation of the X1 input clock is stopped a nd during the oscillation stabil ization time.
CHAPTER 17 CLOCK MONITOR
User’s Manual U15836EJ4V0UD 315
Figure 17-3. Timing of Clock Monitor (4/4)
(7) Clock monitor status after Ring-OSC clock oscillation is stopped by software
Ring-OSC clock
X1 input clock
CPU operation Normal operation (X1 input clock or subsystem clock)
Oscillation stopped
RSTOP
Note
Clock monitor status Monitoring Monitoring
stopped Monitoring
CLME
When bit 0 (CLME) of the c lock monitor mod e register (CL M) is set to 1 before or while oscillation of the Ring-OSC
clock is stopped, monitoring automatically starts after the Ring-OSC clock is stopped. Monitoring is stopped when
oscillation of the Ring-OSC clock is stopped.
Note If it is specified by a mask option that Ring-OSC cannot be stopped, the setting of bit 0 (RSTOP) of the
Ring-OSC mode register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS) of the main
clock mode register (MCM) is 1.
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CHAPTER 18 POWER-ON-CLEAR CIRCUIT
18.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the followi ng functions.
• Generates internal reset signal at power on.
• Compares supply voltage (VDD) and detection voltage (VPOC), and generates internal reset signal when VDD <
VPOC.
• The following can be selected by a mask option.
• POC disabled
• POC used (detection voltage: VPOC = 2.85 V ±0.15 V)Note
• POC used (detection voltage: VPOC = 3.5 V ±0.2 V)
Note This option cannot be selected in (A1) and (A 2) grade pro ducts because the supply volta ge V DD is 3.3 to 5.5
V.
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is
cleared to 00H.
Remark This product incorporates mul tiple hardware functions that generate an internal res et signal. A flag that
indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor.
RESF is not cleared to 00H and the flag is set to 1 when an intern al reset signal is generated by WDT,
LVI, or the clock monitor.
For details of the RESF, see CHAPTER 16 RESET FUNCTION.
CHAPTER 18 POWER-ON-CLEAR CIRCUIT
User’s Manual U15836EJ4V0UD 317
18.2 Configuration of Power-on-Clear Circuit
A block diagram of the power-on-clear circui t is shown in Figure 18-1.
Figure 18-1. Block Diagram of Power-on-Clear Circuit
−
+
Detection
voltage source
(VPOC)
Internal reset signal
V
DD
V
DD
Mask option
Note Selected by mask option.
18.3 Operation of Power-on-Clear Cir cuit
In the power-on-clear circuit, the supply volt age (VDD) and detectio n voltage (VPOC) are compared, and when VDD <
VPOC, an internal reset signal is generated.
Figure 18-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Time
Supply voltage (V
DD
)
POC detection voltage
(V
POC
)
2.7 V
Internal reset signal
CHAPTER 18 POWER-ON-CLEAR CIRCUIT
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18.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 18-3. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Yes
Power-on-clear
; The Ring-OSC clock is set as the CPU clock when the reset signal is generated
;The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
;Change the CPU clock from the Ring-OSC clock to the X1 input clock.
;Check the stabilization of oscillation of the X1 input clock by using the
OSTC register.
;TMIFH1 = 1: Interrupt request is generated.
;Initialization of ports
;8-bit timer H1 can operate with the Ring-OSC clock.
Source: f
R
(480 kHz (MAX.))/2
7
× compare value 200 = 53 ms
(f
R
: Ring-OSC clock oscillation frequency)
No
Note 1
Reset
Checking cause
of reset
Note 2
Check stabilization
of oscillation
Change CPU clock
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing
Start timer
(set to 50 ms)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
CHAPTER 18 POWER-ON-CLEAR CIRCUIT
User’s Manual U15836EJ4V0UD 319
Figure 18-3. Example of Software Processing After Release of Reset (2/2)
• Checking reset cause
Yes
No
Check reset cause
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
clock monitor
Reset processing by
low-voltage detector
No
No
WDTRF of RESF
register = 1?
CLMRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Yes
Yes
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CHAPTER 19 LOW-VOLTAGE DETECTOR
19.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has followin g functions.
• Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or
internal reset signal when VDD < VLVI.
• Detection levels (seven levels)Note of supply voltage can be changed by software.
• Interrupt or reset function can be selected by software.
• Operable in STOP mode.
Note Five levels in the case of (A1) grade products and (A2) gra de products.
When the low-voltage d etector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, see CHAPTER 16 RESET FUNCTION.
19.2 Configuration of Low-Voltage Detector
A block diagram of the low-voltage detector is shown below.
Figure 19-1. Block Diagram of Low-Voltage Detector
LVIS1 LVIS0 LVION LVIE
−
+
Detection
voltage source
(VLVI)
V
DD
Internal bus
N-ch
Low-voltage detection level
selection register (LVIS) Low-voltage detection register
(LVIM)
LVIS2 LVIMD LVIF
INTLVI
Internal reset signal
3
V
DD
Low-voltage detection level selector
Selector
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD 321
19.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage detection reg ister (LVIM)
• Low-voltage detection level selection register (LVIS)
(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LVIM to 00H.
Figure 19-2. Format of Low-Voltage Detection Register (LVIM)
<0>
LVIF
<1>
LVIMD
2
0
3
0
<4>
LVIE
5
0
6
0
<7>
LVION
Symbol
LVIM
Address: FFBEH After reset: 00H R/W
Note 1
LVIONNotes 2, 3 Enables low-voltage detection operation
0 Disables operation
1 Enables operation
LVIENotes 2, 4, 5 Specifies reference voltage generator
0 Disables operation
1 Enables operation
LVIMDNote 2 Low-voltage detection operation mode selection
0 Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI)
1 Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)
LVIFNote 6 Low-voltage detection flag
0 Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled
1 Supply voltage (VDD) < detection voltage (VLVI)
Notes 1. Bit 0 is read-on ly.
2. LVION, LVIE, and LVIMD are cleared to 0 in the case of a reset other than an LVI reset.
These are not cleared to 0 in the case of an LVI reset.
3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until th e voltage is
confirmed at LVIF.
4. If “POC cannot be used” is sel ected by a mask option, wait for 2 ms or more by software from
when LVIE is set to 1 until LVION is set to 1.
5. If “POC used” is selected by a mask option, setting of LVIE is invalid because the reference
voltage generator in the LVI circuit always operates.
6. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD
322
Caution To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then
clear LVIE to 0.
(2) Low-voltage detection level selection register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
RESET input clears LVIS to 00H.
Figure 19-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
0
LVIS0
1
LVIS1
2
LVIS2
3
0
4
0
5
0
6
0
7
0
Symbol
LVIS
Address: FFBFH After reset: 00H R/W
LVIS2 LVIS1 LVIS0 Detection level
0 0 0 VLVI0 (4.3 V ±0.2 V)
0 0 1 VLVI1 (4.1 V ±0.2 V)
0 1 0 VLVI2 (3.9 V ±0.2 V)
0 1 1 VLVI3 (3.7 V ±0.2 V)
1 0 0 VLVI4 (3.5 V ±0.2 V)Note 1
1 0 1 VLVI5 (3.3 V ±0.15 V)Notes 1, 2
1 1 0 VLVI6 (3.1 V ±0.15 V)Notes 1, 2
1 1 1 Setting prohibited
Notes 1. When the detection voltage o f the POC circuit is specified as VPOC = 3.5 V ±0.2 V by a mask
option, do not select VLVI4 to VLVI6 as the LVI detection voltage. Even if VLVI4 to VLVI6 are
selected, the POC circuit has priority.
2. This setting is prohibited in (A1) grad e products and (A2) grade products.
Caution Be sure to clear bits 3 to 7 to 0.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD 323
19.4 Operation of Low-Voltage Detector
The low-voltage detector can be use d in the following two modes.
• Used as reset
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when
VDD < VLVI.
• Used as interrupt
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)
when VDD < VLVI.
The operation is set as follows.
(1) When used as reset
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator
operation).
<4> Use software to instigate a wait of at least 2 ms.
<5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<6> Use software to instigate a wait of at least 0.2 ms.
<7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
<8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection
voltage (VLVI)).
Figure 19-4 shows the timing of the internal reset signal gen erated by the low-voltage det ector. The numbers
in this timing chart correspond to <1> to <8> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <5>.
2. If “POC used” is selected by a mask option, procedures <3> and <4> are not required.
3. If supply voltage (VDD) > detection voltage (VLVI) when LVIM is set to 1, an internal reset
signal is not generated.
• When stopping operation
Either of the following procedu res must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD
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Figure 19-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
Supply voltage (VDD)
LVI detection voltage
(VLVI)
POC detection voltage
(VPOC)
2.7 V
LVIF flag
LVIRF flagNote 3
Note 2
LVI reset signal
POC reset signal
Internal reset signal
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
<2>
<1>Note 1
<5>
<7>
<8>
Time
Clear
Clear
Clear
Clear
<3>
<4> 2 ms or longer
<6> 0.2 ms or longer
LVIMK flag
(set by software)
LVIE flag
(set by software)
LVION flag
(set by software)
LVIMD flag
(set by software)
Notes 1. The LVIMK flag is set to “1” by RESET input .
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 16
RESET FUNCTION.
Remark <1> to <8> in Figure 19- 4 abo ve corres pon d to < 1> to < 8> in the descri ption of “w hen star ting o per ation”
in 19.4 (1) When used as reset.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD 325
(2) When used as interrupt
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator
operation).
<4> Use software to instigate a wait of at least 2 ms.
<5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<6> Use software to instigate a wait of at least 0.2 ms.
<7> Wait until it is checked that (supply voltage (VDD) > detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
<8> Clear the interrupt request flag of LVI (LVIIF) to 0.
<9> Release the interrupt mask flag of LVI (LVIMK).
<10> Execute the EI instruction (when vector interrupts are used).
Figure 19-5 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <9> above.
Caution If “POC used” is selected by a mask option, procedures <3> and <4> are not required.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0 first, and then clear LVIE to 0.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD
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Figure 19-5. Timing of Low-Voltage Detector Interrupt Signal Generation
Supply voltage (VDD)
LVI detection voltage
(VLVI)
POC detection voltage
(VPOC)
2.7 V
Time
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
<2>
<1>Note 1
<5>
<7>
<8>
Cleared by software
<3>
<4> 2 ms or longer
<9> Cleared by software
<6> 0.2 ms or longer
LVIMK flag
(set by software)
LVIE flag
(set by software)
LVION flag
(set by software)
Note 2
Note 2
Notes 1. The LVIMK flag is set to “1” by RESET input .
2. The LVIF and LVIIF flags may be set (1).
Remark <1> to <9> in Figure 19- 5 abo ve corres pon d to < 1> to < 9> in the descri ption of “w hen star ting o per ation”
in 19.4 (2) When used as interrupt.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD 327
19.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection vo ltage
(VLVI), the operation is as follows depend ing on how the low-voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operati on of the micr ocontroller can be arb itrarily set
by taking action (1) below.
(2) When used as interrupt
Interrupt requests may be frequently generat ed. Take action (2) below.
In this system, take the following actions.
<Action>
(1) When used as reset
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD
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Figure 19-6. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Yes
LVI
; The Ring-OSC clock is set as the CPU clock when the reset signal is generated
;The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
;Change the CPU clock from the Ring-OSC clock to the X1 input clock.
;Check the stabilization of oscillation of the X1 input clock by using the
OSTC register.
;TMIFH1 = 1: Interrupt request is generated.
;Initialization of ports
;8-bit timer H1 can operate with the Ring-OSC clock.
Source: f
R
(480 kHz (MAX.))/2
7
× compare value 200 = 53 ms
(f
R
: Ring-OSC clock oscillation frequency)
No
Note 1
Reset
Checking cause
of reset
Note 2
Check stabilization
of oscillation
Change CPU clock
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing
Start timer
(set to 50 ms)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
CHAPTER 19 LOW-VOLTAGE DETECTOR
User’s Manual U15836EJ4V0UD 329
Figure 19-6. Example of Software Processing After Release of Reset (2/2)
• Checking reset cause
Yes
No
Check reset cause
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
clock monitor
Reset processing by
low-voltage detector
No
Yes
WDTRF of RESF
register = 1?
CLMRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Yes
No
(2) When used as interrupt
Check that “supply voltage (VDD) > detection voltag e (VLVI)” in the servicing routine of the LVI interrupt by using bit
0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt req ue st flag register 0L (IF0L)
to 0 and enable interrupts (EI).
In a system where the supply voltag e fluctuation p eriod is long in t he vicinity of the LVI de tection voltage, wait for
the supply voltage fluctuation period, check that “supply voltage (VDD) > detection voltage (VLVI)” using the LVIF
flag, and then enable interrupt s (EI).
User’s Manual U15836EJ4V0UD
330
CHAPTER 20 MASK OPTIONS
Mask ROM versions are provided with the following mask options.
1. Power-on-clear (POC) circuit
• POC cannot be used
• POC used (detection voltage: VPOC = 2.85 V ±0.15 V)Note
• POC used (detection voltage: VPOC = 3.5 V ±0.2 V)
2. Ring-OSC
• Cannot be stopped
• Can be stopped by software
Note This option cannot be selected in (A 1) and (A2) grade pro ducts because the supply voltage V DD is 3.3 to
5.5 V.
Flash memory versions that support the mask options of the mask ROM versions are as follows.
Table 20-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions
Mask Option
POC Circuit Ring-OSC
Flash Memory Version
Cannot be stopped
µ
PD78F0103M1, 78F0103M1(A), 78F0103M1(A1)POC cannot be used
Can be stopped by software
µ
PD78F0103M2, 78F0103M2(A), 78F0103M2(A1)
Cannot be stopped
µ
PD78F0103M3, 78F0103M3(A)
POC used
(VPOC = 2.85 V ±0.15 V) Can be stopped by software
µ
PD78F0103M4, 78F0103M4(A)
Cannot be stopped
µ
PD78F0103M5, 78F0103M5(A), 78F0103M5(A1)
POC used
(VPOC = 3.5 V ±0.2 V) Can be stopped by software
µ
PD78F0103M6, 78F0103M6(A), 78F0103M6(A1)
User’s Manual U15836EJ4V0UD 331
CHAPTER 21
µ
PD78F0103
The
µ
PD78F0103 is provided as the flash memory version of the 78K0/KB1.
The
µ
PD78F0103 replaces the internal mask ROM of the
µ
PD780103 with flash memory to which a program can
be written, erased, and overwritten while mounted on the board. Table 21-1 lists the differences between the
µ
PD78F0103 and the mask ROM versions.
Table 21-1. Differences Between
µ
PD78F0103 and Mask ROM Versions
Item
µ
PD78F0103 Mask ROM Versions
Internal ROM configuration Flash memory Mask ROM
Internal ROM capacity 24 KBNote
µ
PD780101: 8 KB
µ
PD780102: 16 KB
µ
PD780103: 24 KB
Internal high-speed RAM capacity 768 bytesNote
µ
PD780101: 512 bytes
µ
PD780102: 768 bytes
µ
PD780103: 768 bytes
IC pin None Available
VPP pin Available None
Electrical specifications,
recommended soldering conditions Refer to the description of electrical specifications and recommended soldering
conditions.
Note The same capacity as the mask ROM versions can be specified by means of the internal memory size
switching register (IMS).
Caution There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient
evaluations for the commercial samples (not engineering samples) of the mask ROM versions.
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD
332
21.1 Internal Memory Size Switching Register
The
µ
PD78F0103 allows users to select the internal memory capacity using the internal memory size switching
register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory
capacity can be achieved.
IMS is set by an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Caution The initial value of IMS is “setting prohibited (CFH)”. Be sure to set the value of the relevant
mask ROM version at initialization.
Figure 21-1. Format of Internal Memory Size Switching Register (IMS)
Address: FFF0H After reset: CFH R/W
Symbol 7 6 5 4 3 2 1 0
IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0 Internal high-speed RAM capacity selection
0 0 0 768 bytes
0 1 0 512 bytes
Other than above Setting prohibited
ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection
0 0 1 0 8 KB
0 1 0 0 16 KB
0 1 1 0 24 KB
Other than above Setting prohibited
The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 21-2.
Table 21-2. Internal Memory Size Switching Register Settings
Target Mask ROM Versions IMS Setting
µ
PD780101 42H
µ
PD780102 04H
µ
PD780103 06H
Caution When using a mask ROM version, be sure to set IMS to the value indicated in Table 21-2.
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD 333
21.2 Writing with Flash Programmer
Data can be written to the flash memory on- board or off-board, by using a dedicated flash programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the
µ
PD78F0103 has been mounted on the target
system. The connectors that connect the dedicated flash programmer must be mounted on the target system.
(2) Off-board programming
Data can be written to the flas h memory with a dedicate d program a dapter (FA series) bef ore the
µ
PD78F0103 is
mounted on the target system.
Remark The FA series is a product of Naito Densei Machid a Mfg. Co., Ltd.
Table 21-3. Wiring Between
µ
PD78F0103 and Dedicated Flash Programmer (1/2)
(1) 3-wire serial I/O (CSI10)
Pin Configuration of Dedicated Flash Programmer With CSI10 With CSI10+HS
Signal Name I/O Pin Function Pin Name Pin No. Pin Name Pin No.
SI/RxD Input Receive signal SO10/P12 17 SO10/P12 17
SO/TxD Output Transmit signal SI10/RxD0/P11 16 SI10/RxD0/P11 16
SCK Output Transfer clock SCK10/TxD0/P10 15 SCK10/TxD0/P10 15
X1 8 X1 8 CLK Output Clock to
µ
PD78F0103
X2Note 1 9 X2Note 1 9
/RESET Output Reset signal RESET 10 RESET 10
VPP Output Write voltage VPP 5 VPP 5
H/S Input Handshake signal Not needed Not needed HS/P15/TOH0 20
VDD 7 VDD 7 VDD I/O
VDD voltage generation/voltage
monitorNote 2 AVREF 28 AVREF 28
VSS 6 VSS 6 GND − Ground
AVSS 29 AVSS 29
Notes 1. W hen using th e clock out of the flash progr a mmer, connect CLK of the pro grammer to X1, and con nect
its inverse signal to X2.
2. Flashpro III only
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD
334
Table 21-3. Wiring Between
µ
PD78F0103 and Dedicated Flash Programmer (2/2)
(2) UART (UART0, UART6)
Pin Configuration of Dedicated Flash Programmer With UART0 With UART0+HS With UART6
Signal Name I/O Pin Function Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
SI/RxD Input Receive signal TxD0/
SCK10/P10 15 TxD0/
SCK10/P10 15 TxD6/P13 18
SO/TxD Output Transmit signal RxD0/SI10/
P10 16 RxD0/SI10/
P11 16 RxD6/P14 19
SCK Output Transfer clock Not needed
Not
needed Not needed Not
needed Not needed Not
needed
X1 8 X1 8 X1 8 CLK Output Clock to
µ
PD78F0103
X2Note 1 9 X2Note 1 9 X2Note 1 9
/RESET Output Reset signal RESET 10 RESET 10 RESET 10
VPP Output Write voltage VPP 5 VPP 5 VPP 5
H/S Input Handshake signal Not needed
Not
needed HS/P15/TOH0 20 Not needed
Not
needed
VDD 7 VDD 7 VDD 7 VDD I/O
VDD voltage generation/voltage
monitorNote 2 AVREF 28 AVREF 28 AVREF 28
VSS 6 VSS 6 VSS 6 GND − Ground
AVSS 29 AVSS 29 AVSS 29
Notes 1. W hen using th e clock out of the flash progr a mmer, connect CLK of the pro grammer to X1, and con nect
its inverse signal to X2.
2. Flashpro III only
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD 335
Examples of the recommended connection w hen using the adapter for flash memory writing are shown below.
Figure 21-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
LVDD
VDD
GND
SI SO SCK CLK /RESET VPP
WRITER
INTERFACE RESERVE/HS
FRASH
VDD (2.7 to 5.5 V)Note
GND
Note
µ
PD78F0103, 78F0103(A): 2.7 to 5.5 V
µ
PD78F0103(A1): 3.3 to 5.5 V
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD
336
Figure 21-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
LVDD
VDD
GND
SI SO SCK CLK /RESET V
PP
WRITER
INTERFACE RESERVE/HS
FRASH
V
DD
(2.7 to 5.5 V)
Note
GND
Note
µ
PD78F0103, 78F0103(A): 2.7 to 5.5 V
µ
PD78F0103(A1): 3.3 to 5.5 V
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD 337
Figure 21-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
LVDD
VDD
GND
SI SO SCK CLK /RESET V
PP
WRITER
INTERFACE RESERVE/HS
FRASH
GND
V
DD
(2.7 to 5.5 V)
Note
Note
µ
PD78F0103, 78F0103(A): 2.7 to 5.5 V
µ
PD78F0103(A1): 3.3 to 5.5 V
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD
338
Figure 21-5. Example of Wiring Adapter for Flash Memory Writing in UART (UART0 + HS) Mode
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
LVDD
VDD
GND
SI SO SCK CLK /RESET VPP
WRITER
INTERFACE RESERVE/HS
FRASH
VDD (2.7 to 5.5 V)Note
GND
Note
µ
PD78F0103, 78F0103(A): 2.7 to 5.5 V
µ
PD78F0103(A1): 3.3 to 5.5 V
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD 339
Figure 21-6. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode
28
27
26
30
29
25
24
23
22
21
20
19
18
16
1
2
3
4
5
6
7
8
9
10
11
12
13
1714
15
LVDD
VDD
GND
SI SO SCK CLK /RESET V
PP
WRITER
INTERFACE RESERVE/HS
FRASH
V
DD
(2.7 to 5.5 V)
Note
GND
Note
µ
PD78F0103, 78F0103(A): 2.7 to 5.5 V
µ
PD78F0103(A1): 3.3 to 5.5 V
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD
340
21.3 Programming Environment
The environment required for writing a program to the flash memory of the
µ
PD78F0103 is illustrated below.
Figure 21-7. Environment for Writing Program to Flash Memory
RS-232C
USBNote
Host machine
PD78F0103
VPP
VDD
VSS
RESET
CSI10/UART0/UART6
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STAT VE
µ
Note Flashpro IV only
A host machine that controls the dedicated flash programm er is necessary.
To interface between the dedi cated flash programmer a nd the
µ
PD78F0103, CSI10, UART0, or UART6 is used for
manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA
series) is necessary.
21.4 Communication Mode
Communication between the dedicated flash programmer and the
µ
PD78F0103 is established by serial
communication via CSI10, UART0, or UART6 of the
µ
PD78F0103.
(1) CSI10
Transfer rate: 200 kHz to 2 MHz
Figure 21-8. Communication with Dedicated Flash Programmer (CSI10)
PD78F0103
V
PP
V
DD
/AV
REF
V
SS
/AV
SS
RESET
SO10
SI10
SCK10
V
PP
V
DD
GND
/RESET
SI/RxD
SO/TxD
X1CLK X2
SCK
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
µ
CHAPTER 21
µ
PD78F0103
User’s Manual U15836EJ4V0UD 341
(2) CSI communication mode supporting handshake
Transfer rate: 200 kHz to 2 MHz
Figure 21-9. Communication with Dedicated Flash Programmer (CSI10 + HS)
PD78F0103
V
PP
RESET
SO10
SI10
SCK10
HS
V
PP
V
DD
GND
/RESET
SI/RxD
SO/TxD
SCK X1CLK X2
H/S
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
V
DD
/AV
REF
V
SS
/AV
SS
µ
(3) UART0
Transfer rate: 4800 to 38400 bps
Figure 21-10. Communication with Dedicated Flash Programmer (UART0)
PD78F0103
V
PP
RESET
TxD0
X1
V
PP
V
DD
GND
/RESET
SI/RxD
RxD0SO/TxD
CLK
X2
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
V
DD
/AV
REF
V
SS
/AV
SS
µ
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(4) UART communication mode supporting handshake
Transfer rate: 4800 to 38400 bps
Figure 21-11. Communication with Dedicated Flash Programmer (UART0 + HS)
PD78F0103
V
PP
RESET
TxD0
RxD0
HS
V
PP
V
DD
GND
/RESET
SI/RxD
SO/TxD
X1CLK X2
H/S
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
V
DD
/AV
REF
V
SS
/AV
SS
µ
(5) UART6
Transfer rate: 4800 to 76800 bps
Figure 21-12. Communication with Dedicated Flash Programmer (UART6)
PD78F0103
VPP
VDD/AVREF
VSS/AVSS
RESET
TxD6
RxD6
VPP
VDD
GND
/RESET
SI/RxD
SO/TxD
X1CLK X2
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STAT VE
µ
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User’s Manual U15836EJ4V0UD 343
If Flashpro III/Flashpro IV is used as the dedicated flash programmer, Flashpro III/Flashpro IV generates the
following signal for the
µ
PD78F0103. For details, refer to the Flashpro III/Flashpro IV Manual.
Table 21-4. Pin Connection
Flashpro III/Flashpro IV
µ
PD78F0103 Connection
Signal Name I/O Pin Function Pin Name CSI00 UART0 UART6
VPP Output Write voltage VPP
VDD I/O VDD voltage generation/voltage monitorNote 1 VDD, AVREF
GND − Ground VSS, AVSS
CLK Output Clock output to
µ
PD78F0103 X1, X2Note 2 { { {
/RESET Output Reset signal RESET
SI/RxD Input Receive signal SO10/TxD0/TxD6
SO/TxD Output Transmit signal SI10/RxD0/RxD6
SCK Output Transfer clock SCK10 × ×
H/S Input Handshake signal HS ×
Notes 1. Frashpro III only
2. For off-board w riting only: connect the clock output of the flash programm er to X1 and its inverse sign al to
X2.
Remark : Be sure to connect the pin.
{: The pin does not have to be connected if the signal is generated on the target board.
×: The pin does not have to be connected.
: In handshake mode
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21.5 Handling of Pins on Board
To write the flash memory on-board, connectors that con nect the dedicate d flash progr ammer must be provided on
the target system. First provide a function that selects the normal operation mode or flash memory programming
mode on the board.
When the flash memory programming mo de is set, all the pins not used for programming the flash memory are in
the same status as immediately after reset. Therefore, if the external dev ice does not re cogniz e the stat e immediately
after reset, the pins must be handled as described below.
21.5.1 VPP pin
In the normal operati on mode, connect the VPP pin t o VSS. In addition, a write volt age of 10.0 V (TYP.) is sup plied
to the VPP pin in the flash memory programming mode. Perform the following pin handling.
(1) Connect pull-down resistor RVPP = 10 kΩ to the VPP pin.
(2) Switch the input of the VPP pin to the programmer side by using a jum per on the board or to GND directly.
Figure 21-13. Example of Connection of VPP Pin
PD78F0103
VPP Dedicated flash programmer connection pin
Pull-down resistor (RVPP)
µ
21.5.2 Serial interface pins
The pins used by each serial i nterface are listed below.
Table 21-5. Pins Used by Each Serial Interface
Serial Interface Pins Used
CSI10 SO10, SI10, SCK10
CSI10 + HS SO10, SI10, SCK10, HS/P15
UART0 TxD0, RxD0
UART0 + HS TxD0, RxD0, HS/P15
UART6 TxD6, RxD6
To connect the dedicated flas h programmer to the pins of a serial interfac e that is connected to another device on
the board, care must be exercised so that signals d o not collide or that the other device does not malfunction.
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User’s Manual U15836EJ4V0UD 345
(1) Signal collision
If the dedicated flash programmer (output) is connected to a pin (input) of a serial interfac e connected to another
device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other
device, or make the other device go into an output high-impedance state.
Figure 21-14. Signal Collision (Input Pin of Serial Interface)
Input pin Signal collision Dedicated flash programmer
connection pin
Other device
Output pin
In the flash memory programming mode, the signal output by the device
collides with the signal sent from the dedicated flash programmer.
Therefore, isolate the signal of the other device.
PD78F0103
µ
(2) Malfunction of other device
If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface
connected to another device (input), a signal may be output to the other device, causing the device to
malfunction. To avoid this malfunction, either isolate the connection with the other device.
Figure 21-15. Malfunction of Other Device
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
If the signal output by the PD78F0103 in the flash memory programming
mode affects the other device, isolate the signal of the other device.
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
If the signal output by the dedicated flash programmer in the flash memory
programming mode affects the other device, isolate the signal of the other
device.
PD78F0103
µ
µ
PD78F0103
µ
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21.5.3 RESET pin
If the reset signal of the dedicated flash programmer is co nnected to the RESET pin that is connected to the reset
signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the
reset signal generator.
If the reset signal is input from the user system while the flash memory programming mode is set, the flash
memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash
programmer.
Figure 21-16. Signal Collision (RESET Pin)
RESET
Dedicated flash programmer
connection signal
Reset signal generator
Signal collision
Output pin
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the dedicated flash
programmer. Therefore, isolate the signal of the reset signal generator.
PD78F0103
µ
21.5.4 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
21.5.5 Other signal pins
Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock.
To input the operating clock from the programmer, however, connect the clock out of the programmer t o X1, a nd its
inverse signal to X2.
21.5.6 Power supply
To use the supply voltage out put of the flash progr ammer, c onnect the VDD pin to VDD of the flash pr ogrammer, an d
the VSS pin to VSS of the flash programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
Supply the same other power supplies (AVREF and AVSS) as those in the normal operation mode.
Caution VDD In the dedicated flash programmer PG-FP3 or FL-PR3, VDD has a power monitor function. Be
sure to connect VDD and VSS to VDD and GND of the dedicated flash programmer.
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User’s Manual U15836EJ4V0UD 347
21.6 Programming Method
21.6.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 21-17. Flash Memory Manipulation Procedure
Start
Selecting communication mode
Manipulate flash memory
End?
Yes
VPP pulse supply
No
End
Flash memory programming
mode is set
21.6.2 Flash memory programming mode
To rewrite the contents of the flash memory by using the dedicat ed flash programmer, set the
µ
PD78F0103 in the
flash memory programming mode. To set the mode, set the VPP pin and clear the reset signal.
Change the mode by using a jumper when writing the flash memory on-board.
Figure 21-18. Flash Memory Programming Mode
10.0 V
RESET
V
PP
V
DD
V
SS
V
PP
pulse
Flash memory programming mode
12 n• • •
VPP Operation mode
VSS Normal operation mode
10.0 V Flash memory programming mode
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21.6.3 Selecting communication mode
In the
µ
PD78F0103 a commu nication mode i s selected by inputtin g pulses (up to 11 puls es) to the V PP pin after the
dedicated flash memory programming mode is entered. These VPP pulses are generated by the flash programmer.
The following table shows the relatio nship between the number of pulses a nd communication modes.
Table 21-6. Communication Modes
Standard (TYPE) Setting Note 1
Communication Mode
Port
(COMM PORT) Speed
(SIO CLOCK) On Target
(CPU CLOCK) Frequency
(Flashpro Clock) Multiply Rate
(Multiple Rate)
Pins Used Number
of VPP
Pulses
3-wire serial I/O
(CSI10) SIO-ch0
(SIO ch-0) 200 kHz to 2 MHzNote 2 SO10, SI10,
SCK10 0
3-wire serial I/O with
handshake supported
(CSI10 + HS)
SIO-H/S
(SIO ch-3
+ handshake)
200 kHz to 2 MHzNote 2 SO10, SI10,
SCK10,
HS/P15
3
UART
(UART0) UART-ch0
(UART ch-0) 4800 to 38400 bpsNotes 2, 3 TxD0, RxD0 8
UART
(UART6) UART-ch1
(UART ch-1) 4800 to 76800 bpsNotes 2, 3 TxD6, RxD6 9
UART with
handshake supported
(UART0 + HS)
UART-ch3
(UART ch-3) 4800 to 38400 bpsNotes 2, 3
Arbitrary 2 to 10 MHz 1.0
TxD0, RxD0,
HS/P15 11
Notes 1. Selection items for Standard settings on Flashpro IV (TYPE settings on Flashpro III).
2. The possible s etting range differs depend ing on the voltage. For details, refer to the chapters of electrical
specifications.
3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
Caution When UART0 or UART6 is selected, the receive clock is calculated based on the reset command
sent from the dedicated flash programmer after the VPP pulse has been received.
Remark Items enclosed in parentheses in the setting item column are the set value and set item when they differ
from those of Flashpro IV.
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21.6.4 Communication commands
The
µ
PD78F0103 communicat es with th e dedicated flash pro grammer by us ing comma nds. The si gnals s ent from
the flash programmer to the
µ
PD78F0103 are called commands, and the commands sent from the
µ
PD78F0103 to
the dedicated flash programmer are called response commands.
Figure 21-19. Communication Commands
PD78F0103
Command
Response command
Dedicated flash
p
ro
g
rammer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXXXXXXXX
XXXX
XXXX YYYY
STATVE
µ
The flash memory control commands of the
µ
PD78F0103 are listed in the table below. All these commands are
issued from the programmer and the
µ
PD78F0103 performs processing corresponding to the respective commands.
Table 21-7. Flash Memory Control Commands
Classification Command Name Function
Verify Batch verify command Compares the contents of the entire memory
with the input data.
Erase Batch erase command Erases the contents of the entire memory.
Blank check Batch blank check command Checks the erasure status of the entire memory.
High-speed write command Writes data by specifying the write address and
number of bytes to be written, and executes a
verify check.
Data write
Successive write command Writes data from the address following that of
the high-speed write command executed
immediately before, and executes a verify
check.
Status read command Obtains the operation status
Oscillation frequency setting command Sets the oscillation frequency
Erase time setting command Sets the erase time for batch erase
Write time setting command Sets the write time for writing data
Baud rate setting command Sets the baud rate when UART is used
Silicon signature command Reads the silicon signature information
System setting, control
Reset command Escapes from each status
The
µ
PD78F0103 return a response command for the command issued by the dedicated flash programmer. The
response commands sent from the
µ
PD78F0103 are listed below.
Table 21-8. Response Commands
Command Name Function
ACK Acknowledges command/data.
NAK Acknowledges illegal command/data.
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CHAPTER 22 INSTRUCTI ON SET
This chapter lists each instruction set of the 78K0/KB1 in table form. For details of each operation and operation
code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E).
22.1 Conventions Used in Operation List
22.1.1 Operand identifiers and specification methods
Operands are written in the “Operand” column of each instruction in accordance with the specification method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
methods, select one of them. Uppercase lett ers and the symbols #, !, $ and [ ] are keywords and must be written as
they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
write the #, !, $, and [ ] symbols.
For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for specification.
Table 22-1. Operand Identifiers and Specification Methods
Identifier Specification Method
r
rp
sfr
sfrp
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbolNote
Special function register symbol (16-bit manipulatable register even addresses only)Note
saddr
saddrp FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even address only)
addr16
addr11
addr5
0000H to FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H to 0FFFH Immediate data or labels
0040H to 007FH Immediate data or labels (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark For special function register symbols, see Table 3-5 Special Function Register List.
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User’s Manual U15836EJ4V0UD 351
22.1.2 Description of operation column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
RBS: Register bank select flag
IE: Interrupt request enable flag
NMIS: Non-maskable interrupt servicing flag
( ): Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits a nd lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
∨: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
22.1.3 Description of flag operation column
(Blank): Not affected
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved val ue is restored
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22.2 Operation List
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
r, #byte 2 4 − r ← byte
saddr, #byte 3 6 7 (saddr) ← byte
sfr, #byte 3 − 7 sfr ← byte
A, r Note 3 1 2 − A ← r
r, A Note 3 1 2 − r ← A
A, saddr 2 4 5 A ← (saddr)
saddr, A 2 4 5 (saddr) ← A
A, sfr 2 − 5 A ← sfr
sfr, A 2 − 5 sfr ← A
A, !addr16 3 8 9 + n A ← (addr16)
!addr16, A 3 8 9 + m (addr16) ← A
PSW, #byte 3 − 7 PSW ← byte × × ×
A, PSW 2 − 5 A ← PSW
PSW, A 2 − 5 PSW ← A × × ×
A, [DE] 1 4 5 + n A ← (DE)
[DE], A 1 4 5 + m (DE) ← A
A, [HL] 1 4 5 + n A ← (HL)
[HL], A 1 4 5 + m (HL) ← A
A, [HL + byte] 2 8 9 + n A ← (HL + byte)
[HL + byte], A 2 8 9 + m (HL + byte) ← A
A, [HL + B] 1 6 7 + n A ← (HL + B)
[HL + B], A 1 6 7 + m (HL + B) ← A
A, [HL + C] 1 6 7 + n A ← (HL + C)
MOV
[HL + C], A 1 6 7 + m (HL + C) ← A
A, r Note 3 1 2 − A ↔ r
A, saddr 2 4 6 A ↔ (saddr)
A, sfr 2 − 6 A ↔ (sfr)
A, !addr16 3 8 10 + n + m A ↔ (addr16)
A, [DE] 1 4 6 + n + m A ↔ (DE)
A, [HL] 1 4 6 + n + m A ↔ (HL)
A, [HL + byte] 2 8 10 + n + m A ↔ (HL + byte)
A, [HL + B] 2 8 10 + n + m A ↔ (HL + B)
8-bit data
transfer
XCH
A, [HL + C] 2 8 10 + n + m A ↔ (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
4. m is the number of waits when the external memory expansion ar ea is written.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD 353
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
rp, #word 3 6 − rp ← word
saddrp, #word 4 8 10 (saddrp) ← word
sfrp, #word 4 − 10 sfrp ← word
AX, saddrp 2 6 8 AX ← (saddrp)
saddrp, AX 2 6 8 (saddrp) ← AX
AX, sfrp 2 − 8 AX ← sfrp
sfrp, AX 2 − 8 sfrp ← AX
AX, rp Note 3 1 4 − AX ← rp
rp, AX Note 3 1 4 − rp ← AX
AX, !addr16 3 10 12 + 2n AX ← (addr16)
MOVW
!addr16, AX 3 10 12 + 2m (addr16) ← AX
16-bit data
transfer
XCHW AX, rp Note 3 1 4 − AX ↔ rp
A, #byte 2 4 − A, CY ← A + byte × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte × × ×
A, r Note 4 2 4 − A, CY ← A + r × × ×
r, A 2 4 − r, CY ← r + A × × ×
A, saddr 2 4 5 A, CY ← A + (saddr) × × ×
A, !addr16 3 8 9 + n A, CY ← A + (addr16) × × ×
A, [HL] 1 4 5 + n A, CY ← A + (HL) × × ×
A, [HL + byte] 2 8 9 + n A, CY ← A + (HL + byte) × × ×
A, [HL + B] 2 8 9 + n A, CY ← A + (HL + B) × × ×
ADD
A, [HL + C] 2 8 9 + n A, CY ← A + (HL + C) × × ×
A, #byte 2 4 − A, CY ← A + byte + CY × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte + CY × × ×
A, r Note 4 2 4 − A, CY ← A + r + CY × × ×
r, A 2 4 − r, CY ← r + A + CY × × ×
A, saddr 2 4 5 A, CY ← A + (saddr) + CY × × ×
A, !addr16 3 8 9 + n A, CY ← A + (addr16) + CY × × ×
A, [HL] 1 4 5 + n A, CY ← A + (HL) + CY × × ×
A, [HL + byte] 2 8 9 + n A, CY ← A + (HL + byte) + CY × × ×
A, [HL + B] 2 8 9 + n A, CY ← A + (HL + B) + CY × × ×
8-bit
operation
ADDC
A, [HL + C] 2 8 9 + n A, CY ← A + (HL + C) + CY × × ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
4. m is the number of waits when the external memory expansion ar ea is written.
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354
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
A, #byte 2 4 − A, CY ← A − byte × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) − byte × × ×
A, r Note 3 2 4 − A, CY ← A − r × × ×
r, A 2 4 − r, CY ← r − A × × ×
A, saddr 2 4 5 A, CY ← A − (sa ddr) × × ×
A, !addr16 3 8 9 + n A, CY ← A − (addr16) × × ×
A, [HL] 1 4 5 + n A, CY ← A − (HL) × × ×
A, [HL + byte] 2 8 9 + n A, CY ← A − (HL + byte) × × ×
A, [HL + B] 2 8 9 + n A, CY ← A − (HL + B) × × ×
SUB
A, [HL + C] 2 8 9 + n A, CY ← A − (HL + C) × × ×
A, #byte 2 4 − A, CY ← A − byte − CY × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) − byte − CY × × ×
A, r Note 3 2 4 − A, CY ← A − r − CY × × ×
r, A 2 4 − r, CY ← r − A − CY × × ×
A, saddr 2 4 5 A, CY ← A − (sa ddr) − CY × × ×
A, !addr16 3 8 9 + n A, CY ← A − (addr16) − CY × × ×
A, [HL] 1 4 5 + n A, CY ← A − (HL) − CY × × ×
A, [HL + byte] 2 8 9 + n A, CY ← A − (HL + byte) − CY × × ×
A, [HL + B] 2 8 9 + n A, CY ← A − (HL + B) − CY × × ×
SUBC
A, [HL + C] 2 8 9 + n A, CY ← A − (HL + C) − CY × × ×
A, #byte 2 4 − A ← A ∧ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) ∧ byte ×
A, r Note 3 2 4 − A ← A ∧ r ×
r, A 2 4 − r ← r ∧ A ×
A, saddr 2 4 5 A ← A ∧ (saddr) ×
A, !addr16 3 8 9 + n A ← A ∧ (addr16) ×
A, [HL] 1 4 5 + n A ← A ∧ (HL) ×
A, [HL + byte] 2 8 9 + n A ← A ∧ (HL + byte) ×
A, [HL + B] 2 8 9 + n A ← A ∧ (HL + B) ×
8-bit
operation
AND
A, [HL + C] 2 8 9 + n A ← A ∧ (HL + C) ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD 355
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
A, #byte 2 4 − A ← A ∨ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) ∨ byte ×
A, r Note 3 2 4 − A ← A ∨ r ×
r, A 2 4 − r ← r ∨ A ×
A, saddr 2 4 5 A ← A ∨ (saddr) ×
A, !addr16 3 8 9 + n A ← A ∨ (addr16) ×
A, [HL] 1 4 5 + n A ← A ∨ (HL) ×
A, [HL + byte] 2 8 9 + n A ← A ∨ (HL + byte) ×
A, [HL + B] 2 8 9 + n A ← A ∨ (HL + B) ×
OR
A, [HL + C] 2 8 9 + n A ← A ∨ (HL + C) ×
A, #byte 2 4 − A ← A ∨ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) ∨ byte ×
A, r Note 3 2 4 − A ← A ∨ r ×
r, A 2 4 − r ← r ∨ A ×
A, saddr 2 4 5 A ← A ∨ (saddr) ×
A, !addr16 3 8 9 + n A ← A ∨ (addr16) ×
A, [HL] 1 4 5 + n A ← A ∨ (HL) ×
A, [HL + byte] 2 8 9 + n A ← A ∨ (HL + byte) ×
A, [HL + B] 2 8 9 + n A ← A ∨ (HL + B) ×
XOR
A, [HL + C] 2 8 9 + n A ← A ∨ (HL + C) ×
A, #byte 2 4 − A − byte × × ×
saddr, #byte 3 6 8 (saddr) − byte × × ×
A, r Note 3 2 4 − A − r × × ×
r, A 2 4 − r − A × × ×
A, saddr 2 4 5 A − (saddr) × × ×
A, !addr16 3 8 9 + n A − (addr16) × × ×
A, [HL] 1 4 5 + n A − (HL) × × ×
A, [HL + byte] 2 8 9 + n A − (HL + byte) × × ×
A, [HL + B] 2 8 9 + n A − (HL + B) × × ×
8-bit
operation
CMP
A, [HL + C] 2 8 9 + n A − (HL + C) × × ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD
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Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
ADDW AX, #word 3 6 − AX, CY ← AX + word × × ×
SUBW AX, #word 3 6 − AX, CY ← AX − word × × ×
16-bit
operation
CMPW AX, #word 3 6 − AX − word × × ×
MULU X 2 16
− AX ← A × X Multiply/
divide DIVUW C 2 25
− AX (Quotient), C (Remainder) ← AX ÷ C
r 1 2
− r ← r + 1 × × INC
saddr 2 4 6 (saddr) ← (saddr) + 1 × ×
r 1 2
− r ← r − 1 × × DEC
saddr 2 4 6 (saddr) ← (saddr) − 1 × ×
INCW rp 1 4
− rp ← rp + 1
Increment/
decrement
DECW rp 1 4
− rp ← rp − 1
ROR A, 1 1 2 − (CY, A7 ← A0, Am − 1 ← Am) × 1 time ×
ROL A, 1 1 2 − (CY, A0 ← A7, Am + 1 ← Am) × 1 time ×
RORC A, 1 1 2 − (CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time ×
ROLC A, 1 1 2 − (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time ×
ROR4 [HL] 2 10 1 2 + n + m A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,
(HL)3 − 0 ← (HL)7 − 4
Rotate
ROL4 [HL] 2 10 1 2 + n + m A3 − 0 ← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,
(HL)7 − 4 ← (HL)3 − 0
ADJBA 2 4
− Decimal Adjust Accumulator after Addition × × ×
BCD
adjustment ADJBS 2 4
− Decimal Adjust Accumulator after Subtract × × ×
CY, saddr.bit 3 6 7 CY ← (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← sfr.bit ×
CY, A.bit 2 4 − CY ← A.bit ×
CY, PSW.bit 3 − 7 CY ← PSW.bit ×
CY, [HL].bit 2 6 7 + n CY ← (HL).bit ×
saddr.bit, CY 3 6 8 (saddr.bit) ← CY
sfr.bit, CY 3 − 8 sfr.bit ← CY
A.bit, CY 2 4 − A.bit ← CY
PSW.bit, CY 3 − 8 PSW.bit ← CY × ×
Bit
manipulate MOV1
[HL].bit, CY 2 6 8 + n + m (HL).bit ← CY
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
4. m is the number of waits when the external memory expansion ar ea is written.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD 357
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
CY, saddr.bit 3 6 7 CY ← CY ∧ (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← CY ∧ sfr.bit ×
CY, A.bit 2 4 − CY ← CY ∧ A.bit ×
CY, PSW.bit 3 − 7 CY ← CY ∧ PSW.bit ×
AND1
CY, [HL].bit 2 6 7 + n CY ← CY ∧ (HL).bit ×
CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← CY ∨ sfr.bit ×
CY, A.bit 2 4 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 − 7 CY ← CY ∨ PSW.bit ×
OR1
CY, [HL].bit 2 6 7 + n CY ← CY ∨ (HL).bit ×
CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← CY ∨ sfr.bit ×
CY, A.bit 2 4 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 − 7 CY ← CY ∨ PSW.bit ×
XOR1
CY, [HL].bit 2 6 7 + n CY ← CY ∨ (HL).bit ×
saddr.bit 2 4 6 (saddr.bit) ← 1
sfr.bit 3
− 8 sfr.bit ← 1
A.bit 2 4
− A.bit ← 1
PSW.bit 2
− 6 PSW.bit ← 1 × × ×
SET1
[HL].bit 2 6 8 + n + m (HL).bit ← 1
saddr.bit 2 4 6 (saddr.bit) ← 0
sfr.bit 3
− 8 sfr.bit ← 0
A.bit 2 4
− A.bit ← 0
PSW.bit 2
− 6 PSW.bit ← 0 × × ×
CLR1
[HL].bit 2 6 8 + n + m (HL).bit ← 0
SET1 CY 1 2
− CY ← 1 1
CLR1 CY 1 2
− CY ← 0 0
Bit
manipulate
NOT1 CY 1 2
− CY ← CY ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
4. m is the number of waits when the external memory expansion ar ea is written.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD
358
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
CALL !addr16 3 7
− (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLF !addr11 2 5
− (SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L,
PC15 − 11 ← 00001, PC10 − 0 ← addr11,
SP ← SP − 2
CALLT [addr5] 1 6
− (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
BRK 1 6
− (SP − 1) ← PSW, (SP − 2) ← (PC + 1)H,
(SP − 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP − 3, IE ← 0
RET 1 6
− PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI 1 6
− PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3 RRR
Call/return
RETB 1 6
− PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3 RRR
PSW 1 2
− (SP − 1) ← PSW, SP ← SP − 1 PUSH
rp 1 4
− (SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
PSW 1 2
− PSW ← (SP), SP ← SP + 1 R R RPOP
rp 1 4
− rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, #word 4 − 10 SP ← word
SP, AX 2 − 8 SP ← AX
Stack
manipulate
MOVW
AX, SP 2 − 8 AX ← SP
!addr16 3
6 − PC ← addr16
$addr16 2
6 − PC ← PC + 2 + jdisp8
Unconditional
branch BR
AX 2
8 − PCH ← A, PCL ← X
BC $addr16 2
6 − PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2
6 − PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2
6 − PC ← PC + 2 + jdisp8 if Z = 1
Conditional
branch
BNZ $addr16 2
6 − PC ← PC + 2 + jdisp8 if Z = 0
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD 359
Clocks Flag
Instruction
Group Mnemonic Operands Bytes Note 1 Note 2 Operation ZACCY
saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 3 − 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1
BT
[HL].bit, $addr16 3 10 11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16 4 10 11 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if PSW. bit = 0
BF
[HL].bit, $addr16 3 10 11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 0
saddr.bit, $addr16 4 10 12 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16 4 − 12 PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16 4 − 12 PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit × × ×
BTCLR
[HL].bit, $addr16 3 10 1 2 + n + m PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
B, $addr16 2 6 − B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 − C ← C −1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
Conditional
branch
DBNZ
saddr, $addr16 3 8 10 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
SEL RBn 2 4
− RBS1, 0 ← n
NOP 1 2
− No Operation
EI 2
− 6 IE ← 1 (Enable Interrupt)
DI 2
− 6 IE ← 0 (Disable Interrupt)
HALT 2 6
− Set HALT Mode
CPU
control
STOP 2 6
− Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory exp ansion area is read.
4. m is the number of waits when the external memory expansion ar ea is written.
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD
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22.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand
First Operand
#byte A rNote sfr saddr !addr16 PSW [DE] [HL]
[HL + byte]
[HL + B]
[HL + C]
$addr16 1 None
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
XCH MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
r MOV MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV DBNZ INC
DEC
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV ROR4
ROL4
[HL + byte]
[HL + B]
[HL + C]
MOV
X MULU
C DIVUW
Note Except r = A
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD 361
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
#word AX rpNote sfrp saddrp !addr16 SP None
AX ADDW
SUBW
CMPW
MOVW
XCHW MOVW MOVW MOVW MOVW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
sfrp MOVW MOVW
saddrp MOVW MOVW
!addr16 MOVW
SP MOVW MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
A.bit MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit MOV1
BT
BF
BTCLR
SET1
CLR1
CY MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
SET1
CLR1
NOT1
CHAPTER 22 INSTRUCTION SET
User’s Manual U15836EJ4V0UD
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(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
AX !addr16 !addr11 [addr5] $addr16
Basic ins truction BR CALL
BR CALLF CALLT BR
BC
BNC
BZ
BNZ
Compound
instruction BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
User’s Manual U15836EJ4V0UD 363
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
Target products:
µ
PD780101, 780102, 780103, 78F0103, 780101(A), 780102(A), 780103(A), 78F0103(A)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD −0.3 to +6.5 V
VSS −0.3 to +0.3 V
AVREF −0.3 to VDD + 0.3Note 1 V
AVSS −0.3 to +0.3 V
Supply voltage
VPP
µ
PD78F0103, 78F0103(A ) only Note 2 −0.3 to +10.5 V
VI1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, P130, X1, X2, RESET −0.3 to VDD + 0.3Note 1 V Input voltage
VI2 VPP in flash programming mode
(
µ
PD78F0103, 78F0103(A) only) −0.3 to +10.5 V
Output voltage VO −0.3 to VDD + 0.3Note 1 V
Analog input voltage VAN AVSS − 0.3 to AVREF + 0.3Note 1
and −0.3 to VDD + 0.3Note 1 V
Per pin −10 mA
P30 to P33, P120 −30 mA Total of pins
P00 to P03,
P10 to P17, P130 −30 mA
Output current, high IOH
Total of all pins −50 mA
Per pin 20 mA
P30 to P33, P120 35 mA Total of all pins
P00 to P03,
P10 to P17, P130 35 mA
Output current, low IOL
Total of all pins 60 mA
In normal operation mode −40 to +85
Operating ambient
temperature TA
In flash memory programming −10 to +85
°C
µ
PD780101, 780102, 780103,
780101(A), 780102(A), 780103(A) −65 to +150
Storage temperature Tstg
µ
PD78F0103, 78F0103(A) −40 to +125
°C
Note 1. Must be 6.5 V or lower.
(Refer to Note 2 on the next page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-functio n pins are the same as those of port pins.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
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Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (2.7 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (2.7 V) of the operating
voltage range of VDD (see b in the figure below).
2.7 V
VDD
0 V
0 V
VPP 2.7 V
a b
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 365
X1 Oscillator Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 2.0 10
3.3 V ≤ VDD < 4.0 V 2.0 8.38
Ceramic resonator
C1
X2X1V
SS
C2
Oscillation frequency
(fXP)Note
2.7 V ≤ VDD < 3.3 V 2.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 2.0 10
3.3 V ≤ VDD < 4.0 V 2.0 8.38
Crystal resonator
C1
X2X1V
SS
C2
Oscillation frequency
(fXP)Note
2.7 V ≤ VDD < 3.3 V 2.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 2.0 10
3.3 V ≤ VDD < 4.0 V 2.0 8.38
X1 input frequency
(fXP)Note
2.7 V ≤ VDD < 3.3 V 2.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 46 500
3.3 V ≤ VDD < 4.0 V 56 500
External clock
X2X1
X1 input high-/low-
level width (tXH, tXL)
2.7 V ≤ VDD < 3.3 V 96 500
ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Ring-OSC Oscillator Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, V SS = AVSS = 0 V)
Resonator Parameter Conditions MIN. TYP. MAX. Unit
On-chip Ring-OSC oscillator Oscillation frequency (fR) 120 240 480 kHz
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
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Recommended Oscillator Constants
Caution For the resonator selection of the
µ
PD780101(A), 780102(A), and 780103(A) and oscillator
constants, users are required to either evaluate the oscillation themselves or apply to the
resonator manufacturer for evaluation.
(a)
µ
PD780101, 780102, 78 0103
X1 oscillation: Ceramic resonator (TA = −40 to +85°C)
Recommended
Circuit Constants Oscillation
Voltage Range
Manufacturer Part Number SMD/Lead Frequency
(MHz)
C1
(pF) C2
(pF) MIN.
(V) MAX.
(V)
CSTCC2M00G56 SMD 2.00 Internal
(47) Internal
(47)
CSTCR4M00G55
CSTCR4M00G55U
SMD Internal
(39) Internal
(39)
CSTCR4M00G56
CSTCR4M00G56U
Lead
4.00
Internal
(47) Internal
(47)
CSTCR4M19G55
CSTCR4M19G55U
SMD Internal
(39) Internal
(39)
CSTLS4M19G56
CSTLS4M19G56U
Lead
4.194
Internal
(47) Internal
(47)
CSTCR4M91G55
CSTCR4M91G55U
SMD Internal
(39) Internal
(39)
CSTCS4M91G56
CSTCS4M91G56U
Lead
4.915
Internal
(47) Internal
(47)
CSTCR5M00G55
CSTCR5M00G55U
SMD Internal
(39) Internal
(39)
CSTLS5M00G56
CSTLS5M00G56U
Lead
5.00
Internal
(47) Internal
(47)
CSTCR6M00G55
CSTCR6M00G55U
SMD Internal
(39) Internal
(39)
CSTLS6M00G56
CSTLS6M00G56U
Lead
6.00
Internal
(47) Internal
(47)
CSTCE8M00G52 SMD Internal
(10) Internal
(10)
CSTLS8M00G53
CSTLS8M00G53U
Lead
8.00
Internal
(15) Internal
(15)
CSTCE10M0G52 SMD Internal
(10) Internal
(10)
CSTLS10M0G53
Murata Mfg.
CSTLS10M0G53U
Lead
10.0
Internal
(15) Internal
(15)
2.7 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit. The oscillation voltage and oscillation frequency only indicate the
oscillator characteristic. Use the 78K0/KB1 so that the internal operation conditions are within
the specifications of the DC and AC characteristics.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 367
(b)
µ
PD78F0103
X1 oscillation: Ceramic resonator (TA = −40 to +85°C)
Recommended
Circuit Constants Oscillation
Voltage Range
Manufacturer Part Number SMD/Lead Frequency
(MHz)
C1
(pF) C2
(pF) MIN.
(V) MAX.
(V)
CSTCSS2M00G56 SMD 2.00 Internal
(47) Internal
(47)
CSTCC2M45G56 SMD 2.457 Internal
(47) Internal
(47)
CSTCR4M00G53
CSTCR4M00G53093
SMD Internal
(15) Internal
(15)
CSTLS4M00G53
CSTLS4M00G53093
Lead
4.00
Internal
(15) Internal
(15)
CSTCR5M00G53
CSTCR5M00G53093
SMD Internal
(15) Internal
(15)
CSTLS5M00G53
CSTLS5M00G53093
Lead
5.00
Internal
(15) Internal
(15)
CSTCR6M00G53
CSTCR6M00G53U
SMD Internal
(15) Internal
(15)
CSTLS6M00G53
CSTLS6M00G53U
Lead
6.00
Internal
(15) Internal
(15)
CSTCE8M38G52 SMD Internal
(10) Internal
(10)
CSTLS8M38G53
CSTLS8M38G53093
Lead
8.388
Internal
(15) Internal
(15)
CSTCE10M0G52 SMD Internal
(10) Internal
(10)
CSTLS10M0G53
Murata Mfg.
CSTLS10M0G53093
Lead
10.0
Internal
(15) Internal
(15)
2.7 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit. The oscillation voltage and oscillation frequency only indicate the
oscillator characteristic. Use the 78K0/KB1 so that the internal operation conditions are within
the specifications of the DC and AC characteristics.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
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(c)
µ
PD78F0103(A)
X1 oscillation: Ceramic resonator (TA = −40 to +85°C)
Recommended
Circuit Constants Oscillation
Voltage Range
Manufacturer Part Number SMD/Lead Frequency
(MHz)
C1
(pF) C2
(pF) MIN.
(V) MAX.
(V)
CSTCC2M00G56A 2.00 Internal
(47) Internal
(47)
CSTCC2M45G56A 2.457 Internal
(47) Internal
(47)
CSTCR4M00G53A 4.00 Internal
(15) Internal
(15)
2.7 5.5
CSTCR5M00G53A 5.00 Internal
(15) Internal
(15)
CSTCR6M00G53A 6.00 Internal
(15) Internal
(15)
CSTCE8M38G52A 8.388 Internal
(10) Internal
(10)
Murata Mfg.
CSTCE10M0G52A
SMD
10.0 Internal
(10) Internal
(10)
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit. The oscillation voltage and oscillation frequency only indicate the
oscillator characteristic. Use the 78K0/KB1 so that the internal operation conditions are within
the specifications of the DC and AC characteristics.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 369
DC Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V) (1/3)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 4.0 V ≤ V DD ≤ 5.5 V −5 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V −25 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V −25 mA
4.0 V ≤ V DD ≤ 5.5 V −40 mA
Output current, high IOH
Total of all pins
2.7 V ≤ V DD < 4.0 V −10 mA
Per pin 4.0 V ≤ VDD ≤ 5.5 V 10 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V 30 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V 30 mA
4.0 V ≤ V DD ≤ 5.5 V 50 mA
Output current, low IOL
Total of all pins
2.7 V ≤ V DD < 4. 0 V 10 mA
VIH1 P12, P13, P15 0.7VDD VDD V
VIH2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0.8VDD VDD V
VIH3 P20 to P23No te 1 0.7AVREF AVREF V
Input voltage, high
VIH4 X1, X2 VDD − 0.5 VDD V
VIL1 P12, P13, P15 0 0.3VDD V
VIL2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0 0.2VDD V
VIL3 P20 to P23Note 1 0 0.3AVREF V
Input voltage, low
VIL4 X1, X2 0 0.4 V
Total of P30 to P33, P120 pins
IOH = −25 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −5 mA VDD − 1.0 V
Total of P00 to P03, P10 to P17,
P130 pins IOH = −25 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −5 mA VDD − 1.0 V
Output voltage, high VOH
IOH = −100
µ
A 2.7 V ≤ VDD < 4.0 V V DD − 0.5 V
Total of P30 to P33, P120 pins
IOL = 30 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 10 mA 1.3 V
Total of P00 to P03, P10 to P17,
P130 pins IOL = 30 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 10 mA 1.3 V
Output voltage, low VOL
IOL = 400
µ
A 2.7 V ≤ VDD < 4 . 0 V 0.4 V
VI = VDD P00 to P03, P10 to P17, P30 to P33,
P120, RESET 3
µ
A ILIH1
VI = AVREF P20 to P23 3
µ
A
Input leakage current, high
ILIH2 VI = VDD X1, X2Note 2 20
µ
A
ILIL1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, RESET −3
µ
A Input leakage current, low
ILIL2
VI = 0 V
X1, X2Note 2 −20
µ
A
Output leakage current, high ILOH VO = VDD 3
µ
A
Output leakage current, low ILOL VO = 0 V −3
µ
A
Pull-up resistance value R VI = 0 V 10 30 100 kΩ
VPP supply voltage
(
µ
PD78F0103, 78F0103 (A)
only)
VPP1 In normal operation mode 0 0.2VDD V
Notes 1. When used as a digital input port, set AVREF = VDD.
2. When the inverse level of X1 is input to X2.
Remark Unless specified otherwise, the characteristics of alternate-functio n pins are the same as those of port pins.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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DC Characteristics (2/3):
µ
PD78F0103, 78F0103(A)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
When A/D converter is stopped 11.6 19.5 mA
fXP = 10 MHz,
VDD = 5.0 V ±10%Note 3 When A/D converter is operatingNote 4 12.6 21.5 mA
When A/D converter is stopped 4 6.4 mA
IDD1 X1 crystal
oscillation
operating
modeNote 2 fXP = 5 MHz,
VDD = 3.0 V ±10%Note 3 When A/D converter is operatingNote 4 4.6 7.6 mA
When peripheral functions are stopped 1.4 2.8 mA
fXP = 10 MHz,
VDD = 5.0 V ±10% When peripheral functions are operating 5.5 mA
When peripheral functions are stopped 0.32 0.64 mA
IDD2 X1 crystal
oscillation
HALT mode fXP = 5 MHz,
VDD = 3.0 V ±10% When peripheral functions are operating 1.9 mA
VDD = 5.0 V ±10% 0.37 1.51 mA IDD3 Ring-OSC
operating
modeNote 5 VDD = 3.0 V ±10% 0.29 1.16 mA
POC: OFF, RING: OFF 0.1 30
µ
A
POC: OFF, RING: ON 14 58
µ
A
POC: ONNote 6, RING: OFF 3.5 35.5
µ
A
VDD = 5.0 V ±10%
POC: ONNote 6, RING: ON 17.5 63.5
µ
A
POC: OFF, RING: OFF 0.05 10
µ
A
POC: OFF, RING: ON 7.5 25
µ
A
POC: ONNote 6, RING: OFF 3.5 15.5
µ
A
Supply
currentNote 1
IDD4 STOP
mode
VDD = 3.0 V ±10%
POC: ONNote 6, RING: ON 11 30.5
µ
A
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
2. I
DD1 includes peripheral operation current.
3. When PCC = 00H.
4. Total current flowing throu gh VDD and AVREF pins.
5. When X1 oscill ator is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 in the
µ
PD78F0103M1, 78F0103M2, 78F0103M1(A), and
78F0103M2(A).
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 371
DC Characteristics (3/3):
µ
PD780101, 780102, 78 0103, 780101(A), 780102(A), 780103(A)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
When A/D converter is stopped 6 10.9 mA
fXP = 10 MHz,
VDD = 5.0 V ±10%Note 3 When A/D converter is operatingNote 4 7 12.9 mA
When A/D converter is stopped 1.7 3.1 mA
IDD1 X1 crystal
oscillation
operating
modeNote 2 fXP = 5 MHz,
VDD = 3.0 V ±10%Note 3 When A/D converter is operatingNote 4 2.3 4.3 mA
When peripheral functions are stopped 1.3 2.6 mA
fXP = 10 MHz,
VDD = 5.0 V ±10% When peripheral functions are operating 4.8 mA
When peripheral functions are stopped 0.25 0.5 mA
IDD2 X1 crystal
oscillation
HALT
mode fXP = 5 MHz,
VDD = 3.0 V ±10% When peripheral functions are operating 1.1 mA
VDD = 5.0 V ±10% 0.18 0.72 mA IDD3 Ring-OSC
operating
modeNote 5 VDD = 3.0 V ±10% 0.11 0.44 mA
POC: OFF, RING: OFF 0.1 30
µ
A
POC: OFF, RING: ON 14 58
µ
A
POC: ONNote 6, RING: OFF 3.5 35.5
µ
A
VDD = 5.0 V ±10%
POC: ONNote 6, RING: ON 17.5 63.5
µ
A
POC: OFF, RING: OFF 0.05 10
µ
A
POC: OFF, RING: ON 7.5 25
µ
A
POC: ONNote 6, RING: OFF 3.5 15.5
µ
A
Supply
currentNote 1
IDD4 STOP
mode
VDD = 3.0 V ±10%
POC: ONNote 6, RING: ON 11 30.5
µ
A
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
2. I
DD1 includes peripheral operation current.
3. When PCC = 00H.
4. Total current flowing throu gh VDD and AVREF pins.
5. When X1 oscill ator is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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AC Characteristics
(1) Basic operation (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 0.2 16
µ
s
3.3 V ≤ VDD < 4.0 V 0.238 16
µ
s
X1 input clock
2.7 V ≤ VDD < 3.3 V 0.4 16
µ
s
Instruction cycle (mi nim um
instruction execution time) TCY
Ring-OSC clock 4.17 8.33 16.67
µ
s
4.0 V ≤ VDD ≤ 5.5 V 2/fsam+
0.1Note
µ
s
TI000, TI010 input high-level
width, low-level width tTIH0,
tTIL0
2.7 V ≤ VDD < 4.0 V 2/fsam+
0.2Note
µ
s
4.0 V ≤ VDD ≤ 5.5 V 10 TI50 input frequency fTI5
2.7 V ≤ VDD < 4.0 V 5
MHz
4.0 V ≤ VDD ≤ 5.5 V 50 ns
TI50 input high-level width, low-
level width tTIH5,
tTIL5 2.7 V ≤ VDD < 4.0 V 100 ns
Interrupt input high-level width,
low-level width tINTH,
tINTL 1
µ
s
RESET low-level width tRSL 10
µ
s
Note Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode
register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP.
TCY vs. VDD (X1 Input Clock Operation)
5.0
1.0
2.0
0.4
0.2
0.10
10.0
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7 3.3
20.0
16.0
0.238
Guaranteed
operation range
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
µ
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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(2) Serial interface (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
(a) UART mode (UART6, dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 312.5 kbps
(b) UART mode (UART0, dedicated baud rat e generator o utput):
µ
PD780102, 780103, 78F0103, 7 801 02(A),
780103(A), and 78F0103(A) only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 312.5 kbps
(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 200 ns
3.3 V ≤ VDD < 4.0 V 240 ns
SCK10 cycle time tKCY1
2.7 V ≤ VDD < 3.3 V 400 ns
SCK10 high-/low-level width tKH1,
tKL1 t
KCY1/2−10 ns
SI10 setup time (to SCK10↑) tSIK1 30 ns
SI10 hold time (from SCK10↑) tKSI1 30 ns
Delay time from SCK10↓ to
SO10 output tKSO1 C = 100 pFNote 30 ns
Note C is the load capacitance of the SCK10 and SO10 output lines.
(d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK10 cycle time tKCY2 400 ns
SCK10 high-/low-level width tKH2,
tKL2 t
KCY2/2 ns
SI10 setup time (to SCK10↑) tSIK2 80 ns
SI10 hold time (from SCK10↑) tKSI2 50 ns
Delay time from SCK10↓ to
SO10 output tKSO2 C = 100 pFNote 120 ns
Note C is the load capacitance of the SO10 output line.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD Test points 0.8VDD
0.2VDD
Clock Timing
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
1/f
XP
t
XL
t
XH
TI Timing
TI000, TI010
t
TIL0
t
TIH0
TI50
1/f
TI5
t
TIL5
t
TIH5
Interrupt Request Input Timing
INTP0 to INTP5
t
INTL
t
INTH
RESET Input Timing
RESET
t
RSL
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 375
Serial Transfer Timing
3-wire serial I/O mode:
SI10
SO10
tKCYm
tKLm tKHm
tSIKm tKSIm
Input data
tKSOm
Output data
SCK10
Remark m = 1, 2
A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 bit
4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.4 %FSR Overall errorNotes 1, 2
2.7 V ≤ AVREF < 4.0 V ±0.3 ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V 14 100
µ
s Conversion time tCONV
2.7 V ≤ AVREF < 4.0 V 17 100
µ
s
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR Zero-scale errorNotes 1, 2
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR Full-scale errorNot es 1, 2
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB Integral non-linearity errorNote 1
2.7 V ≤ AVREF < 4.0 V ±4.5 LSB
4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB Differential non-linearity error No te 1
2.7 V ≤ AVREF < 4.0 V ±2.0 LSB
Analog input voltage VAIN AVSS AVREF V
Notes 1. Excludes qua ntization error (±1/2 LSB).
2. This value is indicate d as a ratio (%FSR) to the full-scale value.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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POC Circuit Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VPOC0 Mask option = 3.5 VNote 1 3.3 3.5 3.7 V Detection voltage
VPOC1 Mask option = 2.85 VNote 2 2.7 2.85 3.0 V
VDD: 0 V → 2.7 V 0.0015 ms Power supply rise time tPTH
VDD: 0 V → 3.3 V 0.002 ms
Response delay time 1Note 3 tPTHD When power supply rises, after reaching
detection voltage (MAX.) 3.0 ms
Response delay time 2Note 3 tPD When VDD falls 1.0 ms
Minimum pulse width tPW 0.2 ms
Notes 1. When flash memory version
µ
PD78F0103M5, 78F0103M6, 78F0103M5(A), or 78F0103M6(A) is used
2. When flash memory version
µ
PD78F0103M3, 78F0103M4, 78F0103M3(A), or 78F0103M4(A) is used
3. Time required from voltage detection to reset release.
POC Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PTHD
t
PW
t
PD
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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LVI Circuit Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.1 4.3 4.5 V
VLVI1 3.9 4.1 4.3 V
VLVI2 3.7 3.9 4.1 V
VLVI3 3.5 3.7 3.9 V
VLVI4 3.3 3.5 3.7 V
VLVI5 3.15 3.3 3.45 V
Detection voltage
VLVI6 2.95 3.1 3.25 V
Response timeNote 1 tLD 0.2 2.0 ms
Minimum pulse width tLW 0.2 ms
Reference voltage stabilization wait
timeNote 2 tLWAIT0 0.5 2.0 ms
Operation stabilization wait time Note 3 tLWAIT1 0.1 0.2 ms
Notes 1. Time required from voltage detection to interrupt output or internal reset output.
2. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by
mask option (for the flash memory version, when the
µ
PD78F0103M1, 78F0103M2, 78F0103M1(A), or
78F0103M2(A) is used).
3. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. V
LVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6
2. V
POCn < VLVIm (n = 0 or 1, m = 0 to 6)
LVI Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
WAIT0
t
LW
t
LD
t
WAIT1
LVIE ← 1 LVION ← 1
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR When POC-OFF is selected by mask
optionNote 1.6 5.5 V
Release signal set time tSREL 0
µ
s
Note When flash memory version
µ
PD78F0103M1, 78F0103M2, 78F0103M1(A), or 78F0103M2(A) is used
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
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Flash Memory Programming Characteristics:
µ
PD78F0103, 78F0103(A)
(TA = +10 to +60°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
(1) Write erase characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VPP supply voltage VPP2 During flash memory programming 9.7 10.0 10.3 V
VDD supply current IDD When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V 37 mA
VPP supply current IPP VPP = VPP2 100 mA
Step erase timeNote 1 Ter 0.199 0.2 0.201 s
Overall erase timeNote 2 Tera When step erase time = 0.2 s 20 s/chip
Writeback timeNote 3 Twb 49.4 50 50.6 ms
Number of writebacks per 1
writeback commandNote 4 Cwb When writeback time = 50 ms 60 Times
Number of erases/writebacks Cerwb 16 Times
Step write timeNote 5 Twr 48 50 52
µ
s
Overall write time per wordNote 6 Twrw When step write time = 50
µ
s (1 word = 1
byte) 48 520
µ
s
Number of rewrites per chipNote 7 Cerwr 1 erase + 1 write after erase = 1 rewrite 20 Times/
area
Notes 1. The recommended setting value of the step erase time is 0. 2 s.
2. The prewrite time before erasure and the erase verify time (writeback time) are not included.
3. The recommended setting value of the writeback time is 50 ms.
4. Writeback is executed once by the issuance of the writeb ack command. Therefore, the number of re tries
must be the maximum value minus the number of comman ds issue d.
5. The recommended setting value of the step write time is 50
µ
s.
6. The actual write time per word is 100
µ
s longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, “erase → write” and “write only” are both taken as one
rewrite.
Example: P: Write, E: Erase
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
Remark The range of the operating c lo ck during flash memory progra mming is the s ame as the ran ge dur ing norm al
operation.
CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 379
(2) Serial write operation characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Set time from VDD↑ to VPP↑ tDP 10
µ
s
Release time from VPP↑ to RESET↑ tPR 10
µ
s
VPP pulse input start time from
RESET↑ tRP 2 ms
VPP pulse high-/low-level width tPW 8
µ
s
VPP pulse input end time from
RESET↑ tRPE 14 ms
VPP pulse low-level input voltage VPPL 0.8VDD 1.2VDD V
VPP pulse high-level input voltage VPPH 9.7 10.0 10.3 V
Flash Write Mode Setting Timing
VDD
VDD
0 V
VDD
RESET (input) 0 V
VPPH
0 V
VPP VPPL
tRP
tPR
tDP tPW
tPW
tRPE
User’s Manual U15836EJ4V0UD
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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
Target products:
µ
PD780101(A1), 780102(A1), 780103(A1), 78F0103(A1)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD −0.3 to +6.5 V
VSS −0.3 to +0.3 V
AVREF −0.3 to VDD + 0.3Note 1 V
AVSS −0.3 to +0.3 V
Supply voltage
VPP
µ
PD78F0103(A1) only Note 2 −0.3 to +10.5 V
VI1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, P130, X1, X2, RESET −0.3 to VDD + 0.3Note 1 V Input voltage
VI2 VPP in flash programming mode
(
µ
PD78F0103(A1) only) −0.3 to +10.5 V
Output voltage VO −0.3 to VDD + 0.3Note 1 V
Analog input voltage VAN AVSS − 0.3 to AVREF + 0.3Note 1
and −0.3 to VDD + 0.3Note 1 V
Per pin −8 mA
P30 to P33, P120 −24 mA Total of pins
P00 to P03,
P10 to P17, P130 −24 mA
Output current, high IOH
Total of all pins −40 mA
Per pin 16 mA
P30 to P33, P120 28 mA Total of all pins
P00 to P03,
P10 to P17, P130 28 mA
Output current, low IOL
Total of all pins 48 mA
µ
PD780101(A1), 780102(A1),
780103(A1) −40 to +110
In normal operation
mode −40 to +105
Operating ambient
temperature TA
µ
PD78F0103(A1)
In flash memory
programming −10 to +85
°C
µ
PD780101(A1), 780102(A1),
780103(A1) −65 to +150 Storage temperature Tstg
µ
PD78F0103(A1) −40 to +125
°C
Note 1. Must be 6.5 V or lower.
(Refer to Note 2 on the next page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 381
Note 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
V
PP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (3.3 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
V
DD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (3.3 V) of the operating
voltage range of VDD (see b in the figure below).
3.3 V
V
DD
0 V
0 V
V
PP
3.3 V
a b
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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X1 Oscillator Characteristics (TA = −40 to +110°CNote 1, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
4.5 V ≤ VDD ≤ 5.5 V 2.0 10
4.0 V ≤ VDD < 4.5 V 2.0 8.38
Ceramic resonator
C1
X2X1V
SS
C2
Oscillation frequency
(fXP)Note 2
3.3 V ≤ VDD < 4.0 V 2.0 5.0
MHz
4.5 V ≤ VDD ≤ 5.5 V 2.0 10
4.0 V ≤ VDD < 4.5 V 2.0 8.38
Crystal resonator
C1
X2X1V
SS
C2
Oscillation frequency
(fXP)Note 2
3.3 V ≤ VDD < 4.0 V 2.0 5.0
MHz
4.5 V ≤ VDD ≤ 5.5 V 2.0 10
4.0 V ≤ VDD < 4.5 V 2.0 8.38
X1 input frequency
(fXP)Note 2
3.3 V ≤ VDD < 4.0 V 2.0 5.0
MHz
4.5V ≤ VDD ≤ 5.5 V 46 500
4.0 V ≤ VDD < 4.5 V 56 500
External clock
X2X1
X1 input high-/low-
level width (tXH, tXL)
3.3 V ≤ VDD < 4.0 V 96 500
ns
Notes 1. TA = −40 to +110°C:
µ
PD780101(A1), 780102 (A1), 78010 3(A1)
TA = −40 to + 105°C:
µ
PD78F0103(A1)
2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Ring-OSC Oscillator Characteristics
(TA = −40 to +110 °CNote, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Resonator Parameter Conditions MIN. TYP. MAX. Unit
On-chip Ring-OSC oscillator Oscillation frequency (fR) 120 240 490 kHz
Note TA = −40 to +110°C:
µ
PD780101(A1), 780102 (A1), 78010 3(A1)
TA = −40 to +105°C:
µ
PD78F0103(A1)
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 383
DC Characteristics (1/4):
µ
PD78F0103(A1)
(TA = −40 to +105°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 4.0 V ≤ V DD ≤ 5.5 V −4 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V −20 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V −20 mA
4.0 V ≤ V DD ≤ 5.5 V −25 mA
Output current, high IOH
Total of all pins
3.3 V ≤ V DD < 4.0 V −8 mA
Per pin 4.0 V ≤ VDD ≤ 5.5 V 8 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V 24 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V 24 mA
4.0 V ≤ V DD ≤ 5.5 V 30 mA
Output current, low IOL
Total of all pins
3.3 V ≤ V DD < 4.0 V 8 mA
VIH1 P12, P13, P15 0.7VDD VDD V
VIH2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0.8VDD VDD V
VIH3 P20 to P23No te 1 0.7AVREF AVREF V
Input voltage, high
VIH4 X1, X2 VDD − 0.5 VDD V
VIL1 P12, P13, P15 0 0.3VDD V
VIL2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0 0.2VDD V
VIL3 P20 to P23Note 1 0 0.3AVREF V
Input voltage, low
VIL4 X1, X2 0 0.4 V
Total of P30 to P33, P120 pins
IOH = −20 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −4 mA VDD − 1.0 V
Total of P00 to P03, P10 to P17,
P130 pins IOH = −20 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −4 mA VDD − 1.0 V
Output voltage, high VOH
IOH = −100
µ
A 3.3 V ≤ VDD < 4.0 V V DD − 0.5 V
Total of P30 to P33, P120 pins
IOL = 24 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 8 mA 1.3 V
Total of P00 to P03, P10 to P17,
P130 pins IOL = 24 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 8 mA 1.3 V
Output voltage, low VOL
IOL = 400
µ
A 3.3 V ≤ VDD < 4 . 0 V 0.4 V
VI = VDD P00 to P03, P10 to P17, P30 to P33,
P120, RESET 10
µ
A ILIH1
VI = AVREF P20 to P23 10
µ
A
Input leakage current, high
ILIH2 VI = VDD X1, X2Note 2 20
µ
A
ILIL1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, RESET −10
µ
A Input leakage current, low
ILIL2
VI = 0 V
X1, X2Note 2 −20
µ
A
Output leakage current, high ILOH VO = VDD 10
µ
A
Output leakage current, low ILOL VO = 0 V −10
µ
A
Pull-up resistance value R VI = 0 V 10 30 120 kΩ
VPP supply voltage VPP1 In normal operation mode 0 0.2VDD V
Notes 1. When used as a digital input port, set AVREF = VDD.
2. When the inverse level of X1 is input to X2.
Remark Unless specified otherwise, the characteristics of alternate-functio n pins are the same as those of port pins.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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DC Characteristics (2/4):
µ
PD780101(A1), 780102( A1), 7801 03(A1)
(TA = −40 to +110°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 4.0 V ≤ V DD ≤ 5.5 V −4 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V −20 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V −20 mA
4.0 V ≤ V DD ≤ 5.5 V −32 mA
Output current, high IOH
Total of all pins
3.3 V ≤ V DD < 4.0 V −8 mA
Per pin 4.0 V ≤ VDD ≤ 5.5 V 8 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V 24 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V 24 mA
4.0 V ≤ V DD ≤ 5.5 V 40 mA
Output current, low IOL
Total of all pins
3.3 V ≤ V DD < 4.0 V 8 mA
VIH1 P12, P13, P15 0.7VDD VDD V
VIH2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0.8VDD VDD V
VIH3 P20 to P23 0.7AVREF AVREF V
Input voltage, high
VIH4 X1, X2 VDD − 0.5 VDD V
VIL1 P12, P13, P15 0 0.3VDD V
VIL2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0 0.2VDD V
VIL3 P20 to P23Note 1 0 0.3AVREF V
Input voltage, low
VIL4 X1, X2 0 0.4 V
Total of P30 to P33, P120 pins
IOH = −20 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −4 mA VDD − 1.0 V
Total of P00 to P03, P10 to P17,
P130 pins IOH = −20 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −4 mA VDD − 1.0 V
Output voltage, high VOH
IOH = −100
µ
A 3.3 V ≤ VDD < 4.0 V V DD − 0.5 V
Total of P30 to P33, P120 pins
IOL = 24 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 8 mA 1.3 V
Total of P00 to P03, P10 to P17,
P130 pins IOL = 24 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 8 mA 1.3 V
Output voltage, low VOL
IOL = 400
µ
A 3.3 V ≤ VDD < 4 . 0 V 0.4 V
VI = VDD P00 to P03, P10 to P17, P30 to P33,
P120, RESET 10
µ
A ILIH1
VI = AVREF P20 to P23 10
µ
A
Input leakage current, high
ILIH2 VI = VDD X1, X2Note 2 20
µ
A
ILIL1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, RESET −10
µ
A Input leakage current, low
ILIL2
VI = 0 V
X1, X2Note 2 −20
µ
A
Output leakage current, high ILOH VO = VDD 10
µ
A
Output leakage current, low ILOL VO = 0 V −10
µ
A
Pull-up resistance value R VI = 0 V 10 30 120 kΩ
Notes 1. When used as a digital input port, set AVREF = VDD.
2. When the inverse level of X1 is input to X2.
Remark Unless specified otherwise, the characteristics of alternate-functio n pins are the same as those of port pins.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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DC Characteristics (3/4):
µ
PD78F0103(A1)
(TA = −40 to +105°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
When A/D converter is stopped 11.6 20.6 mA IDD1 X1 crystal
oscillation
operating
modeNote 2
fXP = 10 MHz,
VDD = 5.0 V ±10%Note 3 When A/D converter is operatingNote 4 12.6 22.6 mA
When peripheral functions are stopped 1.4 3.9 mA IDD2 X1 crystal
oscillation
HALT mode
fXP = 10 MHz,
VDD = 5.0 V ±10% When peripheral functions are operating 6.6 mA
IDD3 Ring-OSC
operating
modeNote 5
VDD = 5.0 V ±10% 0.37 2.61 mA
POC: OFF, RING: OFF 0.1 1100
µ
A
POC: OFF, RING: ON 14 1200
µ
A
POC: ONNote 6, RING: OFF 3.5 1100
µ
A
Supply
currentNote 1
IDD4 STOP
mode VDD = 5.0 V ±10%
POC: ONNote 6, RING: ON 17.5 1200
µ
A
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
2. I
DD1 includes peripheral operation current.
3. When PCC = 00H.
4. Total current flowing throu gh VDD and AVREF pins.
5. When X1 oscill ator is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 in the
µ
PD78F0103M1(A1) and 78F0103M2(A1).
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DC Characteristics (4/4):
µ
PD780101(A1), 780102( A1), 7801 03(A1)
(TA = −40 to +110°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
When A/D converter is stopped 6 11.7 mA IDD1 X1 crystal
oscillation
operating
modeNote 2
fXP = 10 MHz,
VDD = 5.0 V ±10%Note 3 When A/D converter is operatingNote 4 7 13.7 mA
When peripheral functions are stopped 1.3 3.4 mA IDD2 X1 crystal
oscillation
HALT
mode
fXP = 10 MHz,
VDD = 5.0 V ±10% When peripheral functions are operating 5.6 mA
IDD3 Ring-OSC
operating
modeNote 5
VDD = 5.0 V ±10% 0.18 1.52 mA
POC: OFF, RING: OFF 0.1 800
µ
A
POC: OFF, RING: ON 14 900
µ
A
POC: ONNote 6, RING: OFF 3.5 800
µ
A
Supply
currentNote 1
IDD4 STOP
mode VDD = 5.0 V ±10%
POC: ONNote 6, RING: ON 17.5 900
µ
A
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
2. I
DD1 includes peripheral operation current.
3. When PCC = 00H.
4. Total current flowing throu gh VDD and AVREF pins.
5. When X1 oscill ator is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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AC Characteristics
(1) Basic operation (TA = −40 to +110°CNote 1, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.5 V ≤ VDD ≤ 5.5 V 0.2 16
µ
s
4.0 V ≤ VDD < 4.5 V 0.238 16
µ
s
X1 input clock
3.3 V ≤ VDD < 4.0 V 0.4 16
µ
s
Instruction cycle (mi nim um
instruction execution time) TCY
Ring-OSC clock 4.09 8.33 16.67
µ
s
4.0 V ≤ VDD ≤ 5.5 V 2/fsam+
0.1Note 2
µ
s TI000, TI010 input high-level
width, low-level width tTIH0,
tTIL0
3.3 V ≤ VDD < 4.0 V 2/fsam+
0.2Note 2
µ
s
4.0 V ≤ VDD ≤ 5.5 V 10 TI50 input frequency fTI5
3.3 V ≤ VDD < 4.0 V 5
MHz
4.0 V ≤ VDD ≤ 5.5 V 50 ns TI50 input high-level width, low-
level width tTIH5,
tTIL5 3.3 V ≤ VDD < 4.0 V 100 ns
Interrupt input high-level width,
low-level width tINTH,
tINTL 1
µ
s
RESET low-level width tRSL 10
µ
s
Notes 1. TA = −40 to +110°C:
µ
PD780101(A1), 780102 (A1), 78010 3(A1)
TA = −40 to + 105°C:
µ
PD78F0103(A1)
2. Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode
register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP.
TCY vs. VDD (X1 Input Clock Operation)
5.0
1.0
2.0
0.4
0.2
0.10
10.0
1.0 2.0 3.0 4.0 5.0 6.0
5.5
3.3 4.5
20.0
16.0
0.238
Guaranteed
operation range
Supply voltage VDD [V]
Cycle time T
CY
[ s]
µ
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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(2) Serial interface (TA = −40 to +110°CNote, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Note TA = −40 to +110°C:
µ
PD780101(A1), 780102(A1), 780103(A1)
TA = −40 to +105°C:
µ
PD78F0103(A1)
(a) UART mode (UART6, dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 312.5 kbps
(b) UART mode (UART0, dedicated baud rate generator output):
µ
PD780102(A1), 780103(A1), and 78F0103(A1) only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 312.5 kbps
(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.5 V ≤ VDD ≤ 5.5 V 200 ns
4.0 V ≤ VDD < 4.5 V 240 ns
SCK10 cycle time tKCY1
3.3 V ≤ VDD < 4.0 V 400 ns
SCK10 high-/low-level width tKH1,
tKL1 t
KCY1/2−10 ns
SI10 setup time (to SCK10↑) tSIK1 30 ns
SI10 hold time (from SCK10↑) tKSI1 30 ns
Delay time from SCK10↓ to
SO10 output tKSO1 C = 100 pFNote 30 ns
Note C is the load capacitance of the SCK10 and SO10 output lines.
(d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK10 cycle time tKCY2 400 ns
SCK10 high-/low-level width tKH2,
tKL2 t
KCY2/2 ns
SI10 setup time (to SCK10↑) tSIK2 80 ns
SI10 hold time (from SCK10↑) tKSI2 50 ns
Delay time from SCK10↓ to
SO10 output tKSO2 C = 100 pFNote 120 ns
Note C is the load capacitance of the SO10 output line.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD Test points 0.8VDD
0.2VDD
Clock Timing
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
1/f
XP
t
XL
t
XH
TI Timing
TI000, TI010
t
TIL0
t
TIH0
TI50
1/f
TI5
t
TIL5
t
TIH5
Interrupt Request Input Timing
INTP0 to INTP5
t
INTL
t
INTH
RESET Input Timing
RESET
t
RSL
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Serial Transfer Timing
3-wire serial I/O mode:
SI10
SO10
tKCYm
tKLm tKHm
tSIKm tKSIm
Input data
tKSOm
Output data
SCK10
Remark m = 1, 2
A/D Converter Characteristics (TA = −40 to +110°CNote 1, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 bit
4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.6 %FSR Overall errorNotes 2, 3
3.3 V ≤ AVREF < 4.0 V ±0.3 ±0.8 %FSR
4.0 V ≤ AVREF ≤ 5.5 V 14 60
µ
s Conversion time tCONV
3.3 V ≤ AVREF < 4.0 V 19 60
µ
s
4.0 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Zero-scale errorNotes 2, 3
3.3 V ≤ AVREF < 4.0 V ±0.8 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Full-scale errorNot es 2, 3
3.3 V ≤ AVREF < 4.0 V ±0.8 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±4.5 LSB Integral non-linearity errorNote 2
3.3 V ≤ AVREF < 4.0 V ±6.5 LSB
4.0 V ≤ AVREF ≤ 5.5 V ±2.0 LSB Differential non-linearity error No te 2
3.3 V ≤ AVREF < 4.0 V ±2.5 LSB
Analog input voltage VAIN AVSS AVREF V
Notes 1. TA = −40 to +110°C:
µ
PD780101(A1), 780102 (A1), 78010 3(A1)
TA = −40 to +105°C:
µ
PD78F0103(A1)
2. Excludes quan tization error (±1/2 LSB).
3. This value is indicate d as a ratio (%FSR) to the full-scale value.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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POC Circuit Characteristics (TA = −40 to +110°CNote 1)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 Mask option = 3.5 VNote 2 3.3 3.5 3.72 V
Power supply rise time tPTH VDD: 0 V → 3.3 V 0.002 ms
Response delay time 1Note 3 tPTHD When power supply rises, after reaching
detection voltage (MAX.) 3.0 ms
Response delay time 2Note 3 tPD When VDD falls 1.0 ms
Minimum pulse width tPW 0.2 ms
Notes 1. TA = −40 to +110°C:
µ
PD780101(A1), 780102 (A1), 78010 3(A1)
TA = −40 to +105°C:
µ
PD78F0103(A1)
2. When flash memory version
µ
PD78F0103M5(A1) or 78F010 3M6(A1) is used
3. Time required from voltage detection to reset release.
POC Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PTHD
t
PW
t
PD
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
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LVI Circuit Characteristics (TA = −40 to +110°CNote 1)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.1 4.3 4.52 V
VLVI1 3.9 4.1 4.32 V
VLVI2 3.7 3.9 4.12 V
VLVI3 3.5 3.7 3.92 V
Detection voltage
VLVI4 3.3 3.5 3.72 V
Response timeNote 2 tLD 0.2 2.0 ms
Minimum pulse width tLW 0.2 ms
Reference voltage stabilization wait
timeNote 3 tLWAIT0 0.5 2.0 ms
Operation stabilization wait timeNote 4 tLWAIT1 0.1 0.2 ms
Notes 1. TA = −40 to +110°C:
µ
PD780101(A1), 780102 (A1), 78010 3(A1)
TA = −40 to +105°C:
µ
PD78F0103(A1)
2. Time required from voltage detection to interrupt output or internal reset output.
3. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by
mask option (for the flash memory version, when the
µ
PD78F0103M1(A1) or 78F0103M2(A1) is used).
4. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. V
LVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4
2. VPOCn < VLVIm (n = 0 or 1, m = 0 to 4)
LVI Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
WAIT0
t
LW
t
LD
t
WAIT1
LVIE ← 1 LVION ← 1
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +110°CNote 1)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR When POC-OFF is selected by mask
optionNote 2 2.0 5.5 V
Release signal set time tSREL 0
µ
s
Notes 1. TA = −40 to +110°C:
µ
PD780101(A1), 780102(A1), 780103(A1)
TA = −40 to +105°C:
µ
PD78F0103(A1)
2. When flash memory version
µ
PD78F0103M1(A1) or 78F010 3M2(A1) is used
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 393
Flash Memory Programming Characteristics:
µ
PD78F0103(A1)
(TA = +10 to +60°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
(1) Write erase characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VPP supply voltage VPP2 During flash memory programming 9.7 10.0 10.3 V
VDD supply current IDD When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V 37 mA
VPP supply current IPP VPP = VPP2 100 mA
Step erase timeNote 1 Ter 0.199 0.2 0.201 s
Overall erase timeNote 2 Tera When step erase time = 0.2 s 20 s/chip
Writeback timeNote 3 Twb 49.4 50 50.6 ms
Number of writebacks per 1
writeback commandNote 4 Cwb When writeback time = 50 ms 60 Times
Number of erases/writebacks Cerwb 16 Times
Step write timeNote 5 Twr 48 50 52
µ
s
Overall write time per wordNote 6 Twrw When step write time = 50
µ
s (1 word = 1
byte) 48 520
µ
s
Number of rewrites per chipNote 7 Cerwr 1 erase + 1 write after erase = 1 rewrite 20 Times/
area
Notes 1. The recommended setting value of the step erase time is 0. 2 s.
2. The prewrite time before erasure an d the erase verify time (writeback time) are not included.
3. The recommended setting value of the writeback time is 50 ms.
4. Writeback is executed once by the issuance of the writeback comma nd. Therefore, the number of re tries
must be the maximum value minus the number of comman ds issue d.
5. The recommended setting value of the step write time is 50
µ
s.
6. The actual write time per word is 100
µ
s longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, “erase → write” and “write only” are both taken as one
rewrite.
Example: P: Write, E: Erase
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
Remark The range of the operating c lo ck during flash memory progra mming is the s ame as the ran ge dur ing norm al
operation.
CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
394
(2) Serial write operation characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Set time from VDD↑ to VPP↑ tDP 10
µ
s
Release time from VPP↑ to RESET↑ tPR 10
µ
s
VPP pulse input start time from
RESET↑ tRP 2 ms
VPP pulse high-/low-level width tPW 8
µ
s
VPP pulse input end time from
RESET↑ tRPE 14 ms
VPP pulse low-level input voltage VPPL 0.8VDD 1.2VDD V
VPP pulse high-level input voltage VPPH 9.7 10.0 10.3 V
Flash Write Mode Setting Timing
V
DD
V
DD
0 V
V
DD
RESET (input) 0 V
V
PPH
0 V
V
PP
V
PPL
t
RP
t
PR
t
DP
t
PW
t
PW
t
RPE
User’s Manual U15836EJ4V0UD 395
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
Target products:
µ
PD780101(A2), 780102(A2), 780103(A2)
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD −0.3 to +6.5 V
VSS −0.3 to +0.3 V
AVREF −0.3 to VDD + 0.3Note V
Supply voltage
AVSS −0.3 to +0.3 V
Input voltage VI1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, P130, X1, X2, RESET −0.3 to VDD + 0.3Note V
Output voltage VO −0.3 to VDD + 0.3Note V
Analog input voltage VAN AVSS − 0.3 to AVREF + 0.3Note
and −0.3 to VDD + 0.3Note V
Per pin −7 mA
P30 to P33, P120 −21 mA Total of pins
P00 to P03,
P10 to P17, P130 −21 mA
Output current, high IOH
Total of all pins −35 mA
Per pin 14 mA
P30 to P33, P120 24.5 mA Total of all pins
P00 to P03,
P10 to P17, P130 24.5 mA
Output current, low IOL
Total of all pins 42 mA
Operating ambient
temperature TA In normal operation mode −40 to +125 °C
Storage temperature Tstg −65 to +150 °C
Note Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins ar e the same as those of port pins.
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
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X1 Oscillator Characteristics (TA = −40 to +125°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 2.0 8.38 Ceramic resonator
C1
X2X1V
SS
C2
Oscillation frequency
(fXP)Note 3.3 V ≤ VDD < 4.0 V 2.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 2.0 8.38 Crystal resonator
C1
X2X1V
SS
C2
Oscillation frequency
(fXP)Note 3.3 V ≤ VDD < 4.0 V 2.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 2.0 8.38
X1 input frequency
(fXP)Note 3.3 V ≤ VDD < 4.0 V 2.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 56 500
External clock
X2X1
X1 input high-/low-
level width (tXH, tXL) 3.3 V ≤ VDD < 4.0 V 96 500
ns
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction ex ecution time.
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Ring-OSC Oscillator Characteristics
(TA = −40 to +125 °C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ V DD, VSS = AVSS = 0 V)
Resonator Parameter Conditions MIN. TYP. MAX. Unit
On-chip Ring-OSC oscillator Oscillation frequency (fR) 120 240 495 kHz
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 397
DC Characteristics (1/2)
(TA = −40 to +125°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 4.0 V ≤ V DD ≤ 5.5 V −3.5 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V −17.5 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V −17.5 mA
4.0 V ≤ V DD ≤ 5.5 V −28 mA
Output current, high IOH
Total of all pins
3.3 V ≤ V DD < 4.0 V −7 mA
Per pin 4.0 V ≤ VDD ≤ 5.5 V 7 mA
Total of P30 to P33, P120 4.0 V ≤ VDD ≤ 5.5 V 21 mA
Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V 21 mA
4.0 V ≤ V DD ≤ 5.5 V 35 mA
Output current, low IOL
Total of all pins
3.3 V ≤ V DD < 4.0 V 7 mA
VIH1 P12, P13, P15 0.7VDD VDD V
VIH2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0.8VDD VDD V
VIH3 P20 to P23 0.7AVREF AVREF V
Input voltage, high
VIH4 X1, X2 VDD − 0.5 VDD V
VIL1 P12, P13, P15 0 0.3VDD V
VIL2 P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,
RESET 0 0.2VDD V
VIL3 P20 to P23Note 1 0 0.3AVREF V
Input voltage, low
VIL4 X1, X2 0 0.4 V
Total of P30 to P33, P120 pins
IOH = −17.5 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −3.5 mA VDD − 1.0 V
Total of P00 to P03, P10 to P17,
P130 pins IOH = −17.5 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOH = −3.5 mA VDD − 1.0 V
Output voltage, high VOH
IOH = −100
µ
A 3.3 V ≤ VDD < 4.0 V V DD − 0.5 V
Total of P30 to P33, P120 pins
IOL = 21 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 7 mA 1.3 V
Total of P00 to P03, P10 to P17,
P130 pins IOL = 21 mA 4.0 V ≤ VDD ≤ 5.5 V,
IOL = 7 mA 1.3 V
Output voltage, low VOL
IOL = 400
µ
A 3.3 V ≤ VDD < 4 . 0 V 0.4 V
VI = VDD P00 to P03, P10 to P17, P30 to P33,
P120, RESET 10
µ
A ILIH1
VI = AVREF P20 to P23 10
µ
A
Input leakage current, high
ILIH2 VI = VDD X1, X2Note 2 20
µ
A
ILIL1 P00 to P03, P10 to P17, P20 to P23,
P30 to P33, P120, RESET −10
µ
A Input leakage current, low
ILIL2
VI = 0 V
X1, X2Note 2 −20
µ
A
Output leakage current, high ILOH VO = VDD 10
µ
A
Output leakage current, low ILOL VO = 0 V −10
µ
A
Pull-up resistance value R VI = 0 V 10 30 120 kΩ
Notes 1. When used as a digital input port, set AVREF = VDD.
2. When the inverse level of X1 is input to X2.
Remark Unless specified otherwise, the characteristics of alternate-functio n pins are the same as those of port pins.
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
398
DC Characteristics (2/2)
(TA = −40 to +125°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
When A/D converter is stopped 5.2 10.6 mA IDD1 X1 crystal
oscillation
operating
modeNote 2
fXP = 8.38 MHz,
VDD = 5.0 V ±10%Note 3 When A/D converter is operatingNote 4 6.2 12.6 mA
When peripheral functions are stopped 1.2 3.6 mA IDD2 X1 crystal
oscillation
HALT
mode
fXP = 8.38 MHz,
VDD = 5.0 V ±10% When peripheral functions are operating 5.5 mA
IDD3 Ring-OSC
operating
modeNote 5
VDD = 5.0 V ±10% 0.18 1.92 mA
POC: OFF, RING: OFF 0.1 1200
µ
A
POC: OFF, RING: ON 14 1300
µ
A
POC: ONNote 6, RING: OFF 3.5 1200
µ
A
Supply
currentNote 1
IDD4 STOP
mode VDD = 5.0 V ±10%
POC: ONNote 6, RING: ON 17.5 1300
µ
A
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not inclu ded).
2. I
DD1 includes peripheral operation current.
3. When PCC = 00H.
4. Total current flowing throu gh VDD and AVREF pins.
5. When X1 oscill ator is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option.
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 399
AC Characteristics
(1) Basic operation (TA = −40 to +125°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 0.238 16
µ
s X1 input clock
3.3 V ≤ VDD < 4.0 V 0.4 16
µ
s
Instruction cycle (mi nim um
instruction execution time) TCY
Ring-OSC clock 4.04 8.33 16.67
µ
s
4.0 V ≤ VDD ≤ 5.5 V 2/fsam+
0.1Note
µ
s TI000, TI010 input high-level
width, low-level width tTIH0,
tTIL0
3.3 V ≤ VDD < 4.0 V 2/fsam+
0.2Note
µ
s
4.0 V ≤ VDD ≤ 5.5 V 8.38 TI50 input frequency fTI5
3.3 V ≤ VDD < 4.0 V 5
MHz
4.0 V ≤ VDD ≤ 5.5 V 59.6 ns TI50 input high-level width, low-
level width tTIH5,
tTIL5 3.3 V ≤ VDD < 4.0 V 100 ns
Interrupt input high-level width,
low-level width tINTH,
tINTL 1
µ
s
RESET low-level width tRSL 10
µ
s
Note Selection of fsam = fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode
register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP.
TCY vs. VDD (X1 Input Clock Operation)
5.0
1.0
2.0
0.4
0.2
0.1
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
0
10.0
1.0 2.0 3.0 4.0 5.0 6.0
5.5
3.3
Guaranteed
operation range
20.0
16.0
0.238
µ
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
400
(2) Serial interface (TA = −40 to +125°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
(a) UART mode (UART6, dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 261.9 kbps
(b) UART mode (UART0, dedicated baud rate generator output):
µ
PD780102(A2) and 780103(A2) only
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 261.9 kbps
(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 240 ns SCK10 cycle time tKCY1
3.3 V ≤ VDD < 4.0 V 400 ns
SCK10 high-/low-level width tKH1,
tKL1 t
KCY1/2−10 ns
SI10 setup time (to SCK10↑) tSIK1 30 ns
SI10 hold time (from SCK10↑) tKSI1 30 ns
Delay time from SCK10↓ to
SO10 output tKSO1 C = 100 pFNote 30 ns
Note C is the load capacitance of the SCK10 and SO10 output lines.
(d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK10 cycle time tKCY2 400 ns
SCK10 high-/low-level width tKH2,
tKL2 t
KCY2/2 ns
SI10 setup time (to SCK10↑) tSIK2 80 ns
SI10 hold time (from SCK10↑) tKSI2 50 ns
Delay time from SCK10↓ to
SO10 output tKSO2 C = 100 pFNote 120 ns
Note C is the load capacitance of the SO10 output line.
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 401
AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD Test points 0.8VDD
0.2VDD
Clock Timing
X1 input V
IH4
(MIN.)
V
IL4
(MAX.)
1/f
XP
t
XL
t
XH
TI Timing
TI000, TI010
t
TIL0
t
TIH0
TI50
1/f
TI5
t
TIL5
t
TIH5
Interrupt Request Input Timing
INTP0 to INTP5
t
INTL
t
INTH
RESET Input Timing
RESET
t
RSL
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
402
Serial Transfer Timing
3-wire serial I/O mode:
SI10
SO10
tKCYm
tKLm tKHm
tSIKm tKSIm
Input data
tKSOm
Output data
SCK10
Remark m = 1, 2
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD 403
A/D Converter Characteristics (TA = −40 to +125°C, 3.3 V ≤ VDD ≤ 5.5 V, 3.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 bit
4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.7 %FSR Overall errorNotes 1, 2
3.3 V ≤ AVREF < 4.0 V ±0.3 ±0.9 %FSR
4.0 V ≤ AVREF ≤ 5.5 V 16 48
µ
s Conversion time tCONV
3.3 V ≤ AVREF < 4.0 V 19 48
µ
s
4.0 V ≤ AVREF ≤ 5.5 V ±0.7 %FSR Zero-scale errorNotes 1, 2
3.3 V ≤ AVREF < 4.0 V ±0.9 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±0.7 %FSR Full-scale errorNot es 1, 2
3.3 V ≤ AVREF < 4.0 V ±0.9 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±5.5 LSB Integral non-linearity errorNote 1
3.3 V ≤ AVREF < 4.0 V ±7.5 LSB
4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB Differential non-linearity error No te 1
3.3 V ≤ AVREF < 4.0 V ±3.0 LSB
Analog input voltage VAIN AVSS AVREF V
Notes 1. Excludes qua ntization error (±1/2 LSB).
2. This value is indicate d as a ratio (%FSR) to the full-scale value.
POC Circuit Characteristics (TA = −40 to +125°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 Mask option = 3.5 V 3.3 3.5 3.76 V
Power supply rise time tPTH VDD: 0 V → 3.3 V 0.002 ms
Response delay time 1Note tPTHD When power supply rises, after reaching
detection voltage (MAX.) 3.0 ms
Response delay time 2Note tPD When VDD falls 1.0 ms
Minimum pulse width tPW 0.2 ms
Note Time required from voltage detection to reset release.
POC Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PTHD
t
PW
t
PD
CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
User’s Manual U15836EJ4V0UD
404
LVI Circuit Characteristics (TA = −40 to +125°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.1 4.3 4.56 V
VLVI1 3.9 4.1 4.36 V
VLVI2 3.7 3.9 4.16 V
VLVI3 3.5 3.7 3.96 V
Detection voltage
VLVI4 3.3 3.5 3.76 V
Response timeNote 1 tLD 0.2 2.0 ms
Minimum pulse width tLW 0.2 ms
Reference voltage stabilization wait
timeNote 2 tLWAIT0 0.5 2.0 ms
Operation stabilization wait timeNote 3 tLWAIT1 0.1 0.2 ms
Notes 1. Time required from voltage detection to interrupt output or internal reset output.
2. Time required from setting LVIE to 1 to reference voltage stabilization when POC-OFF is selected by
mask option.
3. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. V
LVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4
2. V
POCn < VLVIm (n = 0 or 1, m = 0 to 4)
LVI Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
WAIT0
t
LW
t
LD
t
WAIT1
LVIE ← 1 LVION ← 1
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +125°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR When POC-OFF is selected by mask
option 2.0 5.5 V
Release signal set time tSREL 0
µ
s
User’s Manual U15836EJ4V0UD 405
CHAPTER 26 PACKAG E DRA WI NG
S
S
H
J
T
I
G
D
E
F
CB
K
PL
U
N
ITEM
B
C
I
L
M
N
30-PIN PLASTIC SSOP (7.62 mm (300))
A
K
D
E
F
G
H
J
P
30 16
115
A
detail of lead end
M
M
T
MILLIMETERS
0.65 (T.P.)
0.45 MAX.
0.13
0.5
6.1±0.2
0.10
9.85±0.15
0.17±0.03
0.1±0.05
0.24
1.3±0.1
8.1±0.2
1.2
+0.08
−0.07
1.0±0.2
3°+5°
−3°
0.25
0.6±0.15
U
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
S30MC-65-5A4-2
User’s Manual U15836EJ4V0UD
406
CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, please contact an NEC Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 27-1. Surface Mounting Type Soldering Conditions (1/2)
(1) 30-pin plastic SSOP (7.62 mm (300))
µ
PD780101MC-×××-5A4, 780102MC-×××-5A4, 780103MC-×××-5A4,
µ
PD780101MC(A)-×××-5A4, 780102MC(A)-×××-5A4, 780103MC(A)-×××-5A4,
µ
PD780101MC(A1)-×××-5A4, 780102MC(A1)-×××-5A4, 780103MC(A1)-×××-5A4,
µ
PD780101MC(A2)-×××-5A4, 780102MC(A2)-×××-5A4, 780103MC(A2)-×××-5A4
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: 3 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
IR35-107-3
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: 3 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 hours)
VP15-107-3
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature), Exposure
limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
WS60-107-1
Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U15836EJ4V0UD 407
Table 27-1. Surface Mounting Type Soldering Conditions (2/2)
(2) 30-pin plastic SSOP (7.62 mm (300))
µ
PD78F0103M1MC-5A4, 78F0103M2MC-5 A4, 78F0103M3MC-5A4, 78F0103M4MC-5A4,
µ
PD78F0103M5MC-5A4, 78F0103M6MC-5 A4, 78F0103M1MC(A)-5A4, 78F0103M2MC(A)-5A4,
µ
PD78F0103M3MC(A)-5A4, 78F0103M4M C(A)-5A4, 78F0103M5MC(A)-5A4,
µ
PD78F0103M6MC(A)-5A4, 78F0103M1M C(A1)-5A4, 78F0103M2MC(A1)-5A4,
µ
PD78F0103M5MC(A1)-5A4, 78F0103M6MC(A1)-5A4
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: 2 times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 hours)
IR35-103-2
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: 2 times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 hours)
VP15-103-2
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C Max. (package surface temperature), Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
WS60-103-1
Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
User’s Manual U15836EJ4V0UD
408
CHAPTER 28 CAUTION S FOR WAIT
28.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data
may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes
processing, until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of
execution clocks of an instruction incr eases by the number of wait clocks (for the number of wait clocks, see Table 28-
1). This must be noted when real-time processing is performed.
CHAPTER 28 CAUTIONS FOR WAIT
User’s Manual U15836EJ4V0UD 409
28.2 Peripheral Hardware That Generates Wait
Table 28-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait
clocks.
Table 28-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral Hardware Register Access Number of Wait Clocks
Watchdog timer WDTM Write 3 clocks (fixed)
Serial interface UART0 ASIS0 Read 1 clock (fixed)
Serial interface UART6 ASIS6 Read 1 clock (fixed)
ADM Write
ADS Write
PFM Write
PFT Write
2 to 5 clocksNote
(when ADM.5 flag = “1”)
2 to 9 clocksNote
(when ADM.5 flag = “0”)
ADCR Read 1 to 5 clocks
(when ADM.5 flag = “1”)
1 to 9 clocks
(when ADM.5 flag = “0”)
A/D converter
<Calculating maximum number of wait clocks>
{(1/fMACRO) × 2/(1/fCPU)} + 1
*The result after the decimal point is truncated if it is less than tCPUL after it has been multiplied by
(1/fCPU), and is rounded up if it exceeds tCPUL.
fMACRO: Macro operating frequency
(When bit 5 (FR2) of ADM = “1”: fX/2, when bit 5 (FR2) of ADM = “0”: fX/22)
fCPU: CPU clock frequency
tCPUL: Low-level width of CPU clock
Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1.
Remark The clock is the CPU clock (fCPU).
CHAPTER 28 CAUTIONS FOR WAIT
User’s Manual U15836EJ4V0UD
410
28.3 Example of Wait Occurrence
<1> Watchdog timer
<On execution of MOV WDTM, A>
Number of execution clocks: 8
(5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).)
<On execution of MOV WDTM, #byte>
Number of execution clocks: 10
(7 clocks when data is written to a register that does not issue a wait (MOV sfr, #byte).)
<2> Serial interface UART6
<On execution of MOV A, ASIS6>
Number of execution clocks: 6
(5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).)
<3> A/D converter
Table 28-2. Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter)
<On execution of MOV ADM, A; MOV ADS, A; or MOV A, ADCR>
• When fX = 10 MHz, tCPUL = 50 ns
Value of Bit 5 (FR2)
of ADM Register fCPU Number of Wait Clocks Number of Execution Clocks
fX 9 clocks 14 clocks
fX/2 5 clocks 10 clocks
fX/22 3 clocks 8 clocks
fX/23 2 clocks 7 clocks
0
fX/24 0 clocks (1 clockNote) 5 clocks (6 clocksNote)
fX 5 clocks 10 clocks
fX/2 3 clocks 8 clocks
fX/22 2 clocks 7 clocks
fX/23 0 clocks (1 clockNote) 5 clocks (6 clocksNote)
1
fX/24 0 clocks (1 clockNote) 5 clocks (6 clocksNote)
Note On execution of MOV A, ADCR
Remark The clock is the CPU clock (fCPU).
f
X: X1 input clock frequency
t
CPUL: Low-level width of CPU clock
User’s Manual U15836EJ4V0UD 411
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0/KB1.
Figure A-1 shows the development tool confi guration.
• Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
• Windows
Unless otherwise specified, “Windows” means the following OSs.
• Windows 3.1
• Windows 95, 98, 2000
• Windows NTTM Ver 4.0
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD
412
Figure A-1. Development Tool Configuration (1/2)
(1) When using the in-circuit emulators IE-78K0-NS, IE-78K0-NS-A
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source file
Note 1
Debugging software
• Integrated debugger
• System simulator
Host machine (PC or EWS)
Interface adapter,
PC card interface, etc.
In-circuit emulator
Note 3
Emulation board
Emulation probe
Conversion socket or
conversion adapter
Target system
Flash programmer
Flash memory
write adapter
Flash memory
• Software package
• Project manager
(Windows only)
Note 2
Software package
Flash memory
write environment
Control software
Embedded software
• Real-time OS
Performance board
Power supply unit
Notes 1. The C library source file is not included in the software package.
2. The proj ect manager is included in the assembler package.
The project manager is only used for Windows.
3. Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD 413
Figure A-1. Development Tool Configuration (2/2)
(2) When using the in-circuit emulator IE-78K0K1-ET
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source fileNote 1
Debugging software
• Integrated debugger
• System simulator
Host machine (PC or EWS)
Interface adapter,
PC card interface, etc.
In-circuit emulatorNote 3
Emulation probe
Conversion socket or
conversion adapter
Target system
Flash programmer
Flash memory
write adapter
Flash memory
• Software package
• Project manager
(Windows only)Note 2
Software package
Flash memory
write environment
Control software
Embedded software
• Real-time OS
Power supply unit
Notes 1. The C library source file is not included in the software package.
2. The proj ect manager is included in the assembler package.
The project manager is only used for Windows.
3. In-circuit emulator IE-78K0K 1-ET is sup plied wit h i ntegrated deb ugger ID78 K0-NS, a devic e file, power
supply unit, and PCI bus interface ada pter IE-70000-PCI-IF-A. Any other products are sold separately.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD
414
A.1 Software Package
Development tools (software) common to the 78K/0 Series are combined in this package.
SP78K0
78K/0 Series software package Part number:
µ
S××××SP78K0
Remark ×××× in the part number differs depending on the host machine and OS used.
µ
S××××SP78K0
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
CD-ROM
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD 415
A.2 Language Processing Software
This assembler converts programs written in mnemonics into object codes executable
with a microcontroller.
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF780103) (sold
separately).
<Precaution when using RA78K0 in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the project manager (included in assembler package) on Windows.
RA78K0
Assembler package
Part number:
µ
S××××RA78K0
This compiler converts programs written in C language into object codes executable with
a microcontroller.
This compiler should be used in combination with an assembler package and device file
(both sold separately).
<Precaution when using CC78K0 in PC environment>
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the project manager (included in assembler package) on Windows.
CC78K0
C compiler package
Part number:
µ
S××××CC78K0
This file contains information peculiar to the device.
This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0,
ID78K0-NS, and ID78K0) (all sold separately).
The corresponding OS and host machine differ depending on the tool to be used.
DF780103Note 1
Device file
Part number:
µ
S××××DF780103
This is a source file of the functions that configure the object library included in the C
compiler package.
This file is required to match the object library included in the C compiler package to the
user’s specifications.
Since this is a source file, its working environment does not depend on any particular
operating system.
CC78K0-LNote 2
C library source file
Part number:
µ
S××××CC78K0-L
Notes 1. The DF780103 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and
ID78K0.
2. The CC78K0-L is not inclu ded in the software package (SP78K0).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD
416
Remark ×××× in the part number differs depending on the host machine and OS used.
µ
S××××RA78K0
µ
S××××CC78K0
×××× Host Machine OS Supply Medium
AB13 Windows (Japanese version)
BB13 Windows (English version)
3.5-inch 2HD FD
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles
Windows (English version)
3P17 HP9000 series 700TM HP-UXTM (Rel. 10.10)
3K17 SPARCstationTM SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
CD-ROM
µ
S××××DF780103
µ
S××××CC78K0-L
×××× Host Machine OS Supply Medium
AB13 Windows (Japanese version)
BB13
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
3.5-inch 2HD FD
3P16 HP9000 series 700 HP-UX (Rel. 10.10) DAT
3K13 3.5-inch 2HD FD
3K15
SPARCstation SunOS (Rel. 4.1.4),
Solaris (Rel. 2.5.1) 1/4-inch CGM T
A.3 Control Software
Project manager This is control software designed to enable efficient user program development in the
Windows environment. All operations used in development of a user program, such as
starting the editor, building, and starting the debugger, can be performed from the project
manager.
<Caution>
The project manager is included in the assembler package (RA78K0).
It can only be used in Windows.
A.4 Flash Memory Writing Tools
Flashpro III
(part number: FL-PR3, PG-FP3)
Flashpro IV
(part number: FL-PR4, PG-FP4)
Flash programmer
Flash programmer dedicated to microcontrollers with on-chip flash memory.
FA-30MC
Flash memory writing adapter Flash memory writing adapter used connected to the Flashpro III/Flashpro IV.
• FA-30MC: For 30-pin plastic SSOP (MC-5A4 type)
Remark FL-PR3, FL-PR4, and FA-30MC are prod ucts of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD 417
A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A
IE-78K0-NS
In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing
application systems using a 78K/0 Series product. It corresponds to the integrated
debugger (ID78K0-NS). This emulator should be used in combination with a power
supply unit, emulation probe, and the interface adapter required to connect this emulator
to the host machine.
IE-78K0-NS-PA
Performance board This board is connected to the IE-78K0-NS to expand its functions. Adding this board
adds a coverage function and enhances debugging functions such as tracer and timer
functions.
IE-78K0-NS-A
In-circuit emulator Product that combines the IE-78K0-NS and IE-78K0-NS-PA
IE-70000-MC-PS-B
Power supply unit This adapter is used for supplying power from a 100 V to 240 V AC outlet.
IE-70000-98-IF-C
Interface adapter This adapter is required when using a PC-9800 series computer (except notebook type)
as the host machine (C bus compatible).
IE-70000-CD-IF-A
PC card interface This is PC card and interface cable required when using a notebook-type computer as
the host machine (PCMCIA socket compatible).
IE-70000-PC-IF-C
Interface adapter This adapter is required when using an IBM PC compatible computer as the host
machine (ISA bus compatible).
IE-70000-PCI-IF-A
Interface adapter This adapter is required when using a computer with a PCI bus as the host machine.
IE-780148-NS-EM1
Emulation board This board emulates the operations of the peripheral hardware peculiar to a device. It
should be used in combination with an in-circuit emulator.
NP-30MC
Emulation probe This probe is used to connect the in-circuit emulator to the target system and is designed
for use with a 30-pin plastic SSOP (MC-5A4 type).
NSPACK30BK
YSPACK30BK
HSPACK30BK
YQ-Guide
Conversion socket
This conversion socket connects the NP-30MC to a target system board designed to
mount a 30-pin plastic SSOP (MC-5A4 type).
• NSPACK30BK: Socket for connecting target
• YSPACK30BK: Socket for connecting emulator
• HSPACK30BK: Cover for mounting device
• YQ-Guide: Guide pin
Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
2. NSPACK30BK, YSPACK30BK, HSPACK30BK, and YQ-Guide are products of TOKYO ELETECH
CORPORATION.
For further information, contact Daimaru Kogyo Co., Ltd.
Tokyo Electronics Department (TEL: +81-3-3820-711 2)
Osaka Electronics Department (TEL: +81-6-6244-6672)
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD
418
A.5.2 When using in-circuit emulator IE-78K0K1-ET
IE-78K0K1-ETNote
In-circuit emulator
The in-circuit emulator serves to debug hardware and software when developing
application systems using a 78K0/Kx1 product. It corresponds to the integrated
debugger (ID78K0-NS). This emulator should be used in combination with a power
supply unit, emulation probe, and the interface adapter required to connect this emulator
to the host machine.
IE-70000-98-IF-C
Interface adapter
This adapter is required when using a PC-9800 series computer (except notebook type)
as the host machine (C bus compatible).
IE-70000-CD-IF-A
PC card interface
This is PC card and interface cable required when using a notebook-type computer as
the host machine (PCMCIA socket compatible).
IE-70000-PC-IF-C
Interface adapter
This adapter is required when using an IBM PC compatible computer as the host
machine (ISA bus compatible).
IE-70000-PCI-IF-A
Interface adapter
This adapter is required when using a computer with a PCI bus as the host machine.
This is supplied with IE-78K0K1-ET.
NP-30MC
Emulation probe
This probe is used to connect the in-circuit emulator to the target system and is designed
for use with a 30-pin plastic SSOP (MC-5A4 type).
NSPACK30BK
YSPACK30BK
HSPACK30BK
YQ-Guide
Conversion socket
This conversion socket connects the NP-30MC to a target system board designed to
mount a 30-pin plastic SSOP (MC-5A4 type).
• NSPACK30BK: Socket for connecting target
• YSPACK30BK: Socket for connecting emulator
• HSPACK30BK: Cover for mounting device
• YQ-Guide: Guide pin
Note IE-78K0K1-ET is supplied with a power supply unit and PCI bus interface adapter IE-70000-PCI-IF-A. It is
also supplied with integrated debugger ID78K0-NS and a device file as control software.
Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
2. NSPACK30BK, YSPACK30BK, HSPACK30BK, and YQ-Guide are products of TOKYO ELETECH
CORPORATION.
For further information, contact Daimaru Kogyo Co., Ltd.
Tokyo Electronics Department (TEL: +81-3-3820-7112)
Osaka Electronics Department (TEL: +81-6-6244-6672)
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD 419
A.6 Debugging Tools (Software)
This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based
software.
It is used to perform debugging at the C source level or assembler level while simulating
the operation of the target system on a host machine.
Use of the SM78K0 allows the execution of application logical testing and performance
testing on an independent basis from hardware development, thereby providing higher
development efficiency and software quality.
The SM78K0 should be used in combination with the device file (DF780103) (sold
separately).
SM78K0
System simulator
Part number:
µ
S××××SM78K0
This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS is
Windows-based software.
It has improved C-compatible debugging functions and can be display the results of
tracing with the source program using an integrating window function that associates the
source program, disassemble display, and me mory display with the trace result. It
should be used in combination with the device file (sold separately).
ID78K0-NS
Integrated debugger
(supporting in-circuit emulator
IE-78K0-NS, IE-78K0-NS-A,
IE-78K0K1-ET)
Part number:
µ
S××××ID78K0-NS
Remark ×××× in the part number differs depending on the host machine and OS used.
µ
S××××SM78K0
µ
S××××ID78K0-NS
×××× Host Machine OS Supply Medium
AB13 Windows (Japanese version)
BB13 Windows (English version)
3.5-inch 2HD FD
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles
Windows (English version)
CD-ROM
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U15836EJ4V0UD
420
A.7 Embedded Software
The RX78K0 is a real-time OS conforming to the
µ
ITRON specifications.
A tool (configurator) for generating the nucleus of the RX78K0 and multiple information
tables is supplied.
Used in combination with an assembler package (RA78K0) and device file (DF780103)
(both sold separately).
<Precaution when using RX78K0 in PC environment>
The real-time OS is a DOS-based application. It should be used in the DOS prompt when
using it in Windows.
RX78K0
Real-time OS
Part number:
µ
S××××RX78013-∆∆∆∆
Caution To purchase the RX78K0, first fill in the purchase application form and sign the user agreement.
Remark ×××× and ∆∆∆∆ in the part number differ depending on the host machine and OS used.
µ
S××××RX78013-∆∆∆∆
∆∆∆∆ Product Outline Maximum Number for Use in Ma ss Production
001 Evaluation object Do not use for mass-produced product.
100K 0.1 million units
001M 1 million units
010M
Mass-production object
10 million units
S01 Source program Object source program for mass production
×××× Host Machine OS Supply Medium
AA13 PC-9800 series Windows (Japanese version)
AB13 Windows (Japanese version)
BB13
IBM PC/AT compatibles
Windows (English version)
3.5-inch 2HD FD
User’s Manual U15836EJ4V0UD 421
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the
configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter
150 mm
Emulation board
IE-780148-NS-EM1
CN1
Emulation probe
NP-30MC Conversion adapter:
YSPACK30BK,
NSPACK30BK
Board on end of NP-30MC
78010X PROBE Board
In-circuit emulator
IE-78K0S-NS, IE-78K0S-NS-A,
or IE-78K0K1-ET
Target system
Remarks 1. The NP-30MC product of Naito Densei Machida Mfg. Co., Ltd.
2. The YSPACK30BK and NSPACK30BK are products of TOKYO ELETECH CORPORATION.
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
User’s Manual U15836EJ4V0UD
422
Figure B-2. Connection Condition of Target System
31 mm
37 mm
Emulation probe
NP-30MC
13 mm
Emulation board
IE-780148-NS-EM1
15 mm
20 mm
5 mm
Board on end of NP-30MC
Conversion adapter
YSPACK30BK,
NSPACK30BK
Guide pin
YQ-Guide
Target system
Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
2. YSPACK30BK, NSPACK30BK, and YQ-Guide are products of TOKYO ELETECH CORPORATION.
User’s Manual U15836EJ4V0UD 423
APPENDIX C REGISTER INDEX
C.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D conversion result register (ADCR) … 187
A/D converter mode register (ADM) … 185
Analog input channel specific ation register (ADS) … 187
Asynchronous serial interface control re gister 6 (ASICL6) … 236
Asynchronous serial interface operation mode register 0 (ASIM0) … 206
Asynchronous serial interface operation mode register 6 (ASIM6) … 230
Asynchronous serial interface reception error status register 0 (ASIS0) … 208
Asynchronous serial interface reception error status register 6 (ASIS6) … 232
Asynchronous serial interface transmission status register 6 (ASIF6) … 233
[B]
Baud rate generator control register 0 (BRGC0) … 209
Baud rate generator control register 6 (BRGC6) … 235
[C]
Capture/compare control register 00 (CRC00) … 111
Clock monitor mode register (CLM) … 310
Clock selection register 6 (CKSR6) … 234
[E]
8-bit timer compare register 50 (CR50) … 144
8-bit timer counter 50 (TM50) … 143
8-bit timer H compare register 00 (CMP00) … 158
8-bit timer H compare register 01 (CMP01) … 158
8-bit timer H compare register 10 (CMP10) … 158
8-bit timer H compare register 11 (CMP11) … 158
8-bit timer H mode register 0 (TMHMD0) … 159
8-bit timer H mode register 1 (TMHMD1) … 159
8-bit timer mode control register 50 (TMC50) … 146
External interrupt falling edge enable register (EGN) … 282
External interrupt rising edge enable register (EGP) … 282
[I]
Input switch control register (ISC) … 237
Internal memory size switching register (IMS) … 332
Interrupt mask flag register 0H (MK0H) … 280
Interrupt mask flag register 0L (MK0L) … 280
Interrupt mask flag register 1L (MK1L) … 280
Interrupt request flag register 0H (IF0H) … 279
Interrupt request flag register 0L (IF0L) … 279
Interrupt request flag register 1L (IF1L) … 279
APPENDIX C REGISTER INDEX
User’s Manual U15836EJ4V0UD
424
[L]
Low-voltage detection level selection register (LVIS) … 322
Low-voltage detection register (LVIM) … 321
[M]
Main clock mode register (MCM) … 89
Main OSC control register (MOC) … 90
[O]
Oscillation stabilization time counter status r egister (OSTC) … 91, 293
Oscillation stabilization time select register (OSTS) … 92, 294
[P]
Port mode register 0 (PM0) … 80, 114
Port mode register 1 (PM1) … 80, 147, 162, 210, 237, 265
Port mode register 12 (PM12) … 80
Port mode register 3 (PM3) … 80
Port register 0 (P0) … 82
Port register 1 (P1) … 82
Port register 12 (P12) … 82
Port register 13 (P13) … 82
Port register 2 (P2) … 82
Port register 3 (P3) … 82
Power-fail comparison mode register (PFM) … 188
Power-fail comparison threshold register (PFT) … 188
Prescaler mode register 00 (PRM00) … 113
Priority specification flag register 0H (PR0H) … 281
Priority specification flag register 0L (PR0L) … 281
Priority specification flag register 1L (PR1L) … 281
Processor clock control register (PCC) … 87
Pull-up resistor option register 0 (PU0) … 83
Pull-up resistor option register 1 (PU1) … 83
Pull-up resistor option register 12 (PU12) … 83
Pull-up resistor option register 3 (PU3) … 83
[R]
Receive buffer register 0 (RXB0) … 205
Receive buffer register 6 (RXB6) … 229
Reset control flag register (RESF) … 308
Ring-OSC mode register (RCM) … 88
[S]
Serial clock selection register 10 (CSIC10) … 264
Serial operation mode registe r 10 (CSIM10) … 263
Serial I/O shift register 10 (SIO10) … 262
16-bit timer capture/compare register 000 (C R000) … 106
16-bit timer capture/compare register 010 (C R010) … 108
16-bit timer counter 00 (TM00) … 106
APPENDIX C REGISTER INDEX
User’s Manual U15836EJ4V0UD 425
16-bit timer mode control register 00 (TMC00) … 109
16-bit timer output control register 00 (TOC00) … 111
[T]
Timer clock selection register 50 (TCL50) … 145
Transmit buffer register 10 (SOTB10) … 262
Transmit buffer register 6 (TXB6) … 229
Transmit shift register 0 (TXS0) … 205
[W]
Watchdog timer enable register (WDTE) … 176
Watchdog timer mode register (WDTM) … 175
APPENDIX C REGISTER INDEX
User’s Manual U15836EJ4V0UD
426
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
[A]
ADCR: A/D conversion result register … 187
ADM: A/D converter mode register … 185
ADS: Analog input channel specification register … 187
ASICL6: Asynchronous serial interface control register 6 … 236
ASIF6: Asynchronous serial interface transmission status register 6 … 233
ASIM0: Asynchronous serial interface operation mode register 0 … 206
ASIM6: Asynchronous serial interface operation mode register 6 … 230
ASIS0: Asynchronous serial interface reception error status register 0 … 208
ASIS6: Asynchronous serial interface reception error status register 6 … 232
[B]
BRGC0: Baud rate generator control register 0 … 209
BRGC6: Baud rate generator control register 6 … 235
[C]
CKSR6: Clock selection register 6 … 234
CLM: Clock monitor mode register … 310
CMP00: 8-bit timer H compare register 00 … 158
CMP01: 8-bit timer H compare register 01 … 158
CMP10: 8-bit timer H compare register 10 … 158
CMP11: 8-bit timer H compare register 11 … 158
CR000: 16-bit timer capture/compare register 000 … 106
CR010: 16-bit timer capture/compare register 010 … 108
CR50: 8-bit timer compare register 50 … 144
CRC00: Capture/compare control register 00 … 111
CSIC10: Serial clock selection register 10 … 264
CSIM10: Serial operation mode register 10 … 263
[E]
EGN: External interrupt falling edge enable register … 282
EGP: External interrupt rising edge enable register … 282
[I]
IF0H: Interrupt request flag register 0H … 279
IF0L: Interrupt request flag register 0L … 279
IF1L: Interrupt request flag register 1L … 279
IMS: Internal memory size switching register … 332
ISC: Input switch control register … 237
[L]
LVIM: Low-voltage detection register … 321
LVIS: Low-voltage detection level selection register … 322
[M]
MCM: Main clock mode register … 89
APPENDIX C REGISTER INDEX
User’s Manual U15836EJ4V0UD 427
MK0H: Interrupt mask flag register 0H … 280
MK0L: Interrupt mask flag register 0L … 280
MK1L: Interrupt mask flag register 1L … 280
MOC: Main OSC control register … 90
[O]
OSTC: Oscillatio n stab ilization time counter status register … 91, 293
OSTS: Oscillation stabilization time select register … 92, 294
[P]
P0: Port register 0 … 82
P1: Port register 1 … 82
P12: Port register 12 … 82
P13: Port register 13 … 82
P2: Port register 2 … 82
P3: Port register 3 … 82
PCC: Processor clock control register … 87
PFM: Power-fail comparison mode register … 188
PFT: Power-fail comparison thresh old register … 188
PM0: Port mode register 0 … 80, 114
PM1: Port mode register 1 … 80, 147, 162, 210, 237, 265
PM12: Port mode register 12 … 80
PM3: Port mode register 3 … 80
PR0H: Priority specification flag register 0H … 281
PR0L: Priority specification flag register 0L … 281
PR1L: Priority specification flag register 1L … 281
PRM00: Prescaler mode register 00 … 113
PU0: Pull-up resistor option re gister 0 … 83
PU1: Pull-up resistor option re gister 1 … 83
PU12: Pull-up resistor option register 12 … 83
PU3: Pull-up resistor option re gister 3 … 83
[R]
RCM: Ring-OSC mod e register … 8 8
RESF: Reset control flag register … 308
RXB0: Receive buffer register 0 … 205
RXB6: Receive buffer register 6 … 229
[S]
SIO10: Serial I/O shift register 10 … 262
SOTB10: Transmit buffer register 10 … 262
[T]
TCL50: Timer clock selection register 50 … 145
TM00: 16-bit timer counter 00 … 10 6
TM50: 8-bit timer counter 50 … 143
TMC00: 16-bit timer mode control register 00 … 109
TMC50: 8-bit timer mode control register 50 … 146
APPENDIX C REGISTER INDEX
User’s Manual U15836EJ4V0UD
428
TMHMD0: 8-bit timer H mode register 0 … 159
TMHMD1: 8-bit timer H mode register 1 … 159
TOC00: 16-bit timer output control register 00 … 111
TXB6: Transmit buffer register 6 … 229
TXS0: Transmit shift register 0 … 20 5
[W]
WDTE: Watchdog timer enable register … 176
WDTM: Watchdog timer mode register … 175
User’s Manual U15836EJ4V0UD 429
APPENDIX D REVISION HISTORY
D.1 Major Revisions in This Edition
(1/4)
Page Description
Addition of products
µ
PD780101(A2), 780102(A2), 780103(A2)
Throughout
Modification of names of the following special function registers (SFRs)
• Ports 0 to 3, 12, and 13 → Port registers 0 to 3, 12, and 13
p. 20 Addition of Cautions 3 to 1.4 Pin Configuration (Top View)
p. 21 Modification of 1.5 K1 Family Lineup
p. 27 Modification of outline of timer in 1.7 Outline of Functions
p. 28 Addition of Table 2-1 Pin I/O Buffer Power Supplies
p. 67 Addition of Table 4-1 Pin I/O Buffer Power Supplies
p. 68 Modification of Table 4-3 Port Configuration
p. 80 Deletion of input switch control register (ISC) from and addition of port registers (P0 to P3, P12,
and P13) to 4.3 Registers Controlling Port Function
p. 86 Modification of Figure 5-1 Block Diagram of Clock Generator
p. 91 Addition of Cautions 2 and 3 to Figure 5-6 Format of Oscillation Stabilization Time Counter
Status Register (OSTC)
pp. 93, 94 Modification of Figure 5-8 External Circuit of X1 Oscillator and Figure 5-9 Examples of
Incorrect Resonator Connection
p. 101 Modification of Note in Figure 5-12 Switching from Ring-OSC Clock to X1 Input Clock
(Flowchart)
p. 106
p. 106
p. 108
Addition of figures
• Figure 6-2 Format of 16-Bit Timer Counter 00 (TM00)
• Figure 6-3 Format of 16-Bit Timer Capture/Compare Register 000 (CR000)
• Figure 6-4 Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
p. 107
p. 108
Modification of tables
• Table 6-2 CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
• Table 6-3 CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
p. 108 Modification of Caution 1 in 6.2 (3) 16-Bit Timer Capture/Compare Register 010 (CR010)
p. 111 Modification of Caution 3 to Figure 6-6 Format of Capture/Compare Control Register 00
(CRC00)
p. 112 Addition of description to Caution 5 in Figure 6-7 Format of 16-Bit Timer Output Control
Register 00 (TOC00), addition of Caution 6
p. 115
p. 118
p. 121
p. 129
p. 132
p. 134
Addition of register settings
• 6.4.1 Interval timer operation
• 6.4.2 PPG output operations
• 6.4.3 Pulse width measurement operations
• 6.4.4 External event counter operation
• 6.4.5 Square-wave output operation
• 6.4.6 One-shot pulse output operation
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD
430
(2/4)
Page Description
p. 116
p. 119
p. 122
p. 124
p. 126
p. 128
p. 130
p. 133
p. 135
p. 137
Addition of setting to prescaler mode register 00 (PRM00)
• Figure 6-10 Control Register Settings for Interval Timer Operation
• Figure 6-13 Control Register Settings for PPG Output Operation
• Figure 6-17 Control Register Settings for Pulse Width Measurement with Free-Running
Counter and One Capture Register (When TI000 and CR010 Are Used)
• Figure 6-20 Control Register Settings for Measurement of Two Pulse Widths with Free-
Running Counter
• Figure 6-22 Control Register Settings for Pulse Width Measurement with Free-Running
Counter and Two Capture Registers (with Rising Edge Specified)
• Figure 6-24 Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified)
• Figure 6-26 Control Register Settings in External Event Counter Mode (with Rising Edge
Specified)
• Figure 6-29 Control Register Settings in Square-Wave Output Mode
• Figure 6-31 Control Register Settings for One-Shot Pulse Output with Software Trigger
• Figure 6-33 Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
p. 117
p. 120
p. 138
Modification of figures
• Figure 6-12 Timing of Interval Timer Operation
• Figure 6-15 PPG Out put Operation Timing
• Figure 6-34 Timing of One-Shot Pulse Output Operation wit h Ex ternal Trigger (wit h
Rising Edge Specified)
p. 143
p. 144
Addition of figures
• Figure 7-2 Format of 8-Bit Timer Counter 50 (TM50)
• Figure 7-3 Format of 8-Bit Timer Compare Register 50 (CR50)
p. 148 Modification of Figure 7-7 Interval Timer Operation Timing
p. 151 Modification of description of frequency in 7.4.3 Operation as square-wave output
p. 152 Addition of description of cycle, active level width, and duty to 7.4.4 (1) PWM output basic
operation
p. 168 Modification of Figure 8-11 Operation Timing in PWM Output Mode
p. 182 Modification of Figure 10-1 Block Diagram of A/D Converter
p. 183 Partial modification of description of 10.2 Configuration of A/D Converter
p. 185 Addition of description of A/D conversion result register (ADCR) to 10.3 Registers Used in A/D
Converter
p. 189 Partial modification of description of 10.4.1 Basic operations of A/D converter
p. 191 Addition of description of successive approximation register (SAR) to 10.4.2 Input voltage and
conversion results
p. 194 Modification of Caution 3 in “When used as power-fail function” in 10.4.3 A/D converter
operation mode
p. 200 Modification of Figure 10-21 Timing of A/D Converter Sampling and A/D Conversion Start
Delay
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD 431
(3/4)
Page Description
p. 201 Addition of description of (12) Internal equivalent circuit to 10.6 Cautions for A/D Converter
pp. 206, 207 Modification of Cautions 1, 2, 4 and addition of Note 2 and Caution 3 to Figure 11-2 Format of
Asynchronous Serial Interface Operation Mode Register 0 (ASIM0)
p. 211 Modification of description of 11.4.1 Operation stop mode
p. 212 Modification of description of 11.4.2 Asynchronous serial interface (UART) mode (1)
Registers used
p. 217 Modification of Table 11-3 Cause of Reception Error
p. 224
p. 225
p. 226
p. 228
Modification of figures
• Figure 12-1 LIN Transmission Operation
• Figure 12-2 LIN Reception Operation
• Figure 12-3 Port Configuration for LIN Recep tion Operation
• Figure 12-4 Block Diagram of Serial Interface UART6
pp. 230, 231 Modification of Cautions 1, 2 and addition of Note 2 and Caution 3 to Figure 12-5 Format of
Asynchronous Serial Interface Operation Mode Register 6 (ASIM6)
p. 230 Addition of input switch control register (ISC) to 12.3 Registers Controlling Serial Interface
UART6
p. 238 Modification of description of 12.4.1 Operation stop mode
p. 239 Modification of description of 12.4.2 Asynchronous Serial Interface (UART) mode (1)
Registers used
p. 245 Modification of description of 12.4.2 (2) (d) Continuous transmission
p. 250 Modification of Table 12-3 Cause of Reception Error
p. 262 Modification of Figure 13-1 Block Diagram of Serial Interface CSI10
p. 263 Addition of Notes 2 and 3 to Figure 13-2 Format of Serial Operation Mode Register 10
(CSIM10)
p. 264 Modification of Caution 2 and addition of Caution 3 to Figure 13-3 Format of Serial Clock
Selection Register 10 (CSIC10)
p. 266 Modification of description of 13.4.1 Operation stop mode
p. 267 Modification of description of 13.4.2 3-wire serial I/O mode (1) Registers used
p. 274 Addition of (5) SO10 output to 13.4.2 3-wire serial I/O mode
p. 279 Addition of Caution 3 to Figure 14-2 Format of Interrupt Request Flag Register (IF0L, IF0H,
IF1L)
p. 291 Modification of Table 15-1 Relationship Between HALT and STOP Modes and Clock in old
edition to Table 15-1 Relationship Between Operation Clocks in Each Operation Status
p. 293 Addition of Cautions 2 and 3 to Figure 15-1 Format of Oscillation Stabilization Time Counter
Status Register (OSTC)
p. 295 Modification of Table 15-2 Operating Statuses in HALT Mode
p. 303
p. 304
p. 304
p. 305
Modification of figures
• Figure 16-1 Block Diagram of Reset Function
• Figure 16-2 Timing of Reset by RESET Input
• Figure 16-3 Timing of Reset Due to Watchdog Timer Overflow
• Figure 16-4 Timing of Reset in STOP Mode by RESET Input
p. 309 Modification of Figure 17-1 Block Diagram of Clock Monitor
p. 311 Addition of normal operation mode to Table 17-2 Operation Status of Clock Monitor (When
CLME = 1)
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD
432
(4/4)
Page Description
pp. 314, 315 Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software
and (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software to
Figure 17-3 Timing of Clock Monitor
p. 317 Modification of Figure 18-1 Block Diagram of Power-on-Clear Circuit
p. 320 Modification of Figure 19-1 Block Diagram of Low-Voltage Detector
p. 322 Addition of Caution to Figure 19-3 Format of Low-Voltage Detection Level Selection Register
(LVIS)
pp. 324, 326 Modification of Figure 19-4 Timing of Low-Voltage Detector Internal Reset Signal Generation
and Figure 19-5 Timing of Low-Voltage Detector Interrupt Signal Generation
p. 329 Partial modification of description of (2) When used as in terrupt under <Action> in 19.5
Cautions for Low-Volta ge Dete ctor
pp. 333, 334 Addition of Note 2 to Table 21-3 Wiring Between
µ
PD78F0103 and Dedicated Flash
Programmer
p. 340 Addition of Note to Figure 21-7 Environment for Writing Program to Flash Memory
p. 340
p. 341
p. 341
p. 342
p. 342
Modification of figures
• Figure 21-8 Communication with Dedicated Flash Programmer (CSI10)
• Figure 21-9 Communication with Dedicated Flash Programmer (CSI10 + HS)
• Figure 21-10 Communication with Dedicated Flash Programmer (UART0)
• Figure 21-11 Communication with Dedicated Flash Programmer (UART0 + HS)
• Figure 21-12 Communication with Dedicated Flash Programmer (UART6)
p. 345 Partial modification of description of 21.5.2 (2) Malfunction of other device
p. 346 Modification of description of 21.5.4 Port pins
p. 346 Partial modification of Caution to 21.5.6 Power supply
p. 369
p. 376
p. 377
p. 377
Modification of CHAPTER 23 ELECTRICAL SPECIFICATIONS (STAND ARD PRODUCTS, (A)
GRADE PRODUCTS)
• Modification of Note 2 of DC Characteristics
• Addition of Notes 1 and 2 to POC Circuit Characteristics
• Modification of Note 1 of LVI Circuit Characteristics
• Addition of condition for data retention supply voltage and Note to Data Memory STOP Mode
Low Supply Voltage Data Retention Characteristics
p. 383
p. 390
p. 391
p. 392
p. 392
Modification of CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
• Modification of Note 2 of DC Characteristics
• Modification of values for overall error and conversion time in A/D Converter Characteristics
• Addition of Note 2 to POC Circuit Characteristics
• Modification of Note 2 of LVI Circuit Characteristics
• Addition of condition for data retention supply voltage and Note 2 to Data Memory STOP Mode
Low Supply Voltage Data Retention Characteristics
p. 395 Addition of CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
p. 406 Modification of Table 27-1 Surface Mounting Type Soldering Conditions
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD 433
D.2 Revision History of Previous Editions
A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the
revision was applied. (1/5)
Edition Description Applied to:
X1 input clock oscillation stabilization time
212/fX, 214/fX, 215/fX, 216/fX, 217/fX → 211/fX, 213/fX, 214/fX, 215/fX, 216/fX Throughout
Modification of Figure 4-5 Block Diagram of P10
Modification of Table 4-3 Settings of Port Mode Register and Output Latch When
Alternate-Function Is Used
CHAPTER 4
PORT FUNCTIONS
Modification of Figure 5-6 Format of Oscillation Stabilization Time Counter
Status Register (OSTC)
Modification of Figure 5-7 Format of Oscillation Stabilization Time Select
Register (OSTS)
Addition of 5.7 Clock Selection Flowchart and Register Settings
CHAPTER 5
CLOCK GENERATOR
Addition of Remark to 12.1 Functions of Serial Interface UART6 CHAPTER 12
SERIAL INTERFACE UART6
Addition of Reset to Table 14-1 Interrupt Source List CHAPTER 14
INTERRUPT FUNCTI ONS
Modification of Figure 15-2 Format of Oscillation Stabilization Time Counter
Status Register (OSTC)
Modification of Figure 15-3 Format of Oscillation Stabilization Time Select
Register (OSTS)
CHAPTER 15
STANDBY FUNCTION
2nd
Addition of CHAPTER 25 RETRY CHAPTER 25 RETRY
Modification of reset value of the following register in Table 3-5 Special Function
Register List
• Serial I/O shift register 10 (SIO10)
Modification of manipulatable bit unit of the following registers in Table 3-5 Special
Function Register List
• Oscillation stabilization time counter status register (OSTC)
• Interrupt request flag register 1L (IF1L)
• Interrupt mask flag register 1L (MK1L)
• Priority specification flag register 1L (PR1L)
CHAPTER 3 CPU
ARCHITECTURE
Modification of manipulatable bit unit in 5.3 (5) Oscillation stabilization time
counter status register (OSTC)
Modification of Figure 5-11 Status Transition Diagram
Modification of Table 5-3 Relationship Between Operation Clocks in Each
Operation Status
Modification of Table 5-4 Oscillation Control Flags and Clock Oscillation Status
Modification of Table 5-6 Clock and Register Settings
CHAPTER 5 CLOCK
GENERATOR
Modification of reset value in 6.2 (2) 16-bit timer capture/compare register 000
(CR000) and (3) 16-bit timer capture/compare register 010 (CR010)
Modification of manipulatable bit unit in 6.3 (4) Prescaler mode register 00 (PRM00)
CHAPTER 6 16-BIT
TIMER/EVENT COUNTER 00
Modification of Caution in 9.4.2 Watchdog timer operation when “Ring-OSC can
be stopped by software” is selected by mask option
2nd
(corrected
edition)
Modification of 9.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC
can be stopped by software” is selected by mask option)
CHAPTER 9 WATCHDOG
TIMER
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD
434
(2/5)
Edition Description Applied to:
Addition of 9.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can
be stopped by software” is selected by mask option) CHAPTER 9 WATCHDOG
TIMER
Addition of (11) A/D converter sampling time and A/D conversion start delay
time in 10.6 Cautions for A/D Converter CHAPTER 10 A/D
CONVERTER
Modification of reset value in 13.2 (2) Serial I/O shift register 10 (SIO10) CHAPTER 13 SERIAL
INTERFACE CSI10
Modification of manipulatable bit unit in 15.1.2 (1) Oscillation stabilization time
counter status register (OSTC)
Modification of A/D converter item in Table 15-2 Operating Statuses in HALT mode
CHAPTER 15 STANDBY
FUNCTION
Addition of 18.4 Cautions for Power-on-Clear Circuit CHAPTER 18 POWER-ON-
CLEAR CIRCUIT
Modification of Figure 19-3 Format of Low-Voltage Detection Level Selection
Register (LVIS)
Addition of 19.5 Cautions for Low-Voltage Dete ctor
CHAPTER 19 LOW-VOLTAGE
DETECTOR
Modification of the following contents in CHAPTER 23 ELECTRICAL
SPECIFICATIONS (TARGET VALUES)
• Absolute Maximum Ratings
• X1 Oscillator Characteristics
• DC Characteristics
• A/D Converter Characteristics
• POC Circuit Characteristics
• LVI Circuit Characteristics
• Data Memory STOP Mode Low Supply Volta ge Data Retention Characteristics
(deletion of data retention supply current)
• Deletion of Ring-OSC Characteristics
• Flash Memory Programming Characteristics
CHAPTER 23 ELECTRICAL
SPECIFICATIONS (TARGET
VALUES)
2nd
(corrected
edition)
Modification from CHAPTER 25 RETRY to CHAPTER 25 CAUTIONS FOR WAIT CHAPTER 25 CAUTIONS
FOR WAIT
Deletion of following products.
•
µ
PD780101(A2), 780102(A2), 780103(A2)
•
µ
PD78F0103M3MC(A1)-5A4, 78F0103M4MC(A1)-5A4
Modification of supply voltage range of (A1) product and ambient operating
temperature of flash memory version of (A1) product
Modification of reset value of A/D conversion result register (ADCR) (0000H →
undefined)
Throughout
Update of 1.6 78K0/K1 Series Lineup CHAPTER 1 OUTLINE
Modification of Figure 3-12 Data to Be Saved to Stack Memory
Modification of Figure 3-13 Data to Be Restored from Stack Memory
Modification of [Description example] in 3.4.4 Short direct addressing
Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed
addressing, and 3.4.9 Stack addressing
CHAPTER 3 CPU
ARCHITECTURE
Modification of Figure 4-10 Block Diagram of P20 to P23
Addition of Remark to Figure 4-13 Block Diagram of P130
CHAPTER 4 PORT
FUNCTIONS
Addition of condition (set value of MCM0) to Figure 5-2 Format of Processor Clock
Control Register (PCC)
Partial modification of description in 5.5 Clock Generator Operation
3rd
Addition of 5.7 Changing System Clock and CPU Clock Settings
CHAPTER 5 CLOCK
GENERATOR
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD 435
(3/5)
Edition Description Applied to:
Modification of Figure 6-1 Block Diagram of 16-Bit Timer/Event Counter 00
Modification of Cautions 1 and 2 in 6.2 (2) 16-bit timer capture/compare register
000 (CR000), and modification of Caution 1 in (3) 16-bit timer capture/compare
register 010 (CR010)
Addition of Caution 1 to Figure 6-5 Format of Prescaler Mode Register 00
(PRM00)
Addition of Note to Figure 6-8 Interval Timer Configuration Diagram
Modification of Caution 1 of Figure 6-10 Control Register Settings for PPG
Output Operatio n
Addition of Figure 6-11 Configuration of PPG Output and Figure 6-12 PPG
Output Operation Ti min g
Addition of Note to Figure 6-15 Timing of Pulse Width Measurement Operation
with Free-Running Counter and One Capture Register (with Both Edges
Specified), Figure 6-18 Timing of Pulse Width Measurement Operation with
Free-Running Counter (with Both Edges Specified), and Figure 6-20 Timing of
Pulse Width Measurement Operation with Free-Running Counter and Two
Capture Registers (with Rising Edge Specified)
Modification of Figure 6-24 Configuration Diagram of External Event Counter
Addition of 6.4.6 One-shot pulse output operation
Modification of Figure 6-34 Capture Register Data Retention Timing
Addition of description <2> to 6.5 (4) Capture register data retention timing
Deletion of 6.5 (7) Conflicting operations from old edition
CHAPTER 6 16-BIT
TIMER/EVENT COUNTER 00
Modification of Figure 7-1 Block Diagram of 8-Bit Timer/Event Counter 50
Addition of Caution 1 to Figure 7-2 Format of Timer Clock Selection Register 50
(TCL50)
Deletion of Caution 1 of old edition and modification of Caution 2 of Figure 7-3
Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Addition of Remark to Figure 7-8 PWM Output Operation Timing
CHAPTER 7 8-BIT
TIMER/EVENT COUNTER 50
Addition of square-wave output to 8.1 Functions of 8-Bit Timers H0 and H1, and
change of PWM pulse generator mode to PWM output
Modification of Figure 8-1 Block Diagram of 8-Bit Timer H0
Modification of Figure 8-2 Block Diagram of 8-Bit Timer H1
Addition of Note and Caution 1 to Figure 8-3 Format of 8-Bit Timer H Mode
Register 0 (TMHMD0)
Addition of Figure 8-5 Format of Port Mode Register 1 (PM1)
Change of 8.4.1 Operation as interval timer of old edition to 8.4.1 Operation as
interval timer/square-wave output
Modification of (a) Basic operation of Figure 8-7 Timing of Interval Timer/Square-
Wave Output Operation
Modification of description of duty ratio in 8.4.2 (1) Usage
CHAPTER 8 8-BIT TIMERS
H0 AND H1
Addition of description to 10.2 (2) A/D conversion result register (ADCR),
modification of description in (3) Sample & hold circuit and (4) Voltage
comparator, and partial modification of Caution 2 in (6) ANI0 to ANI3 pins
3rd
Modification of Note 1 of Figure 10-4 Forma t of A/D Converter Mode Register
(ADM)
CHAPTER 10 A/D
CONVERTER
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD
436
(4/5)
Edition Description Applied to:
Modification of Figure 10-6 Format of Analog Input Channel Specification
Register (ADS)
Addition of description to 10.3 (3) Power-fail comparison mode register (PFM),
and modification of Figure 10-7 Format of P ower-Fail Comparison Mode Register
(PFM)
Modification of expressions in 10.4.2 Input voltage and conversion results
Partial modification of description in 10.6 (5) ANI0/P20 to ANI3/P23
Addition of description to 10.6 (9) Conversion results just after A/D conversion
start
CHAPTER 10 A/D
CONVERTER
Modification of Caution 3 of 11.1 Functions of Serial Interface UART0
Modification of Figure 11-1 Bloc k Diagram of Serial Interface UART0
Modification of Caution 3 in Figure 11-2 Format of Asynchronous Serial Interface
Operation Mode Register 0 (ASIM0) and 11.4.2 (1) (a) Asynchronous serial
interface operation mode register 0 (ASIM0)
Addition of Note and Caution 1 to Figure 11-4 Format of Baud Rate Generator
Control Register 0 (BRGC0) and 11.4.3 (2) (a) Baud rate generator control
register 0 (BRGC0)
Addition of Figure 11-5 Format of Port Mode Register 1 (PM1) and 11.4.2 (1) (c)
Port mode register 1 (PM1)
Modification of Figure 11-11 Configuration of Baud Rate Generator
Modification of term in 11.4.3 (4) Permissible baud rate range during reception
and 12.4.3 (4) Permissible baud rate range during reception as follows
Transfer rate → Data frame length
Modification of Remark 1 in Table 11-4 Maximum/Mini mum Permissible Baud
Rate Error
CHAPTER 11 SERIAL
INTERFACE UART0
(
µ
PD780102, 780103, 78F0103
ONLY)
Addition of Figure 12-4 Format of Input Switch Control Register (ISC)
Modification of Figure 12-5 Bloc k Diagram of Serial Interface UART6
Addition of Note and Caution 1 to Figure 12-9 Format of Clock Selection Register
6 (CKSR6) and 12.4.3 (2) (a) Clock selection register 6 (CKSR6)
Modification of Figure 12-11 Format of Asynchronous Serial Interface Control
Register 6 (ASICL6) and 12.4.2 (1) (d) Asynchronous serial interface control
register 6 (ASICL6)
Addition of Figure 12-12 Format of Port Mode Register 1 (PM1) and 12.4.2 (1) (e)
Port mode register 1 (PM1)
Modification of description of 12.4.2 (2) (h) SBF transmission and addition of Figure
12-22 Example of Setting Procedure of SBF Transmission (Flowchart)
Modification of Figure 12-25 Configuration of Baud Rate Generator
CHAPTER 12 SERIAL
INTERFACE UART6
Modification of Figure 13-1 Block Diagram of Serial Interface CSI10
Addition of Figure 13-4 Format of Port Mode Register 1 (PM1) and 13.4.2 (1) (c)
Port mode register 1 (PM1)
CHAPTER 13 SERIAL
INTERFACE CSI10
Modification of (C) Software interrupt in Figure 14-1 Basic Configuration of
Interrupt Function
Addition of Note 4 to Table 14-2 Flag Corres ponding to Interru pt Reque st Sou rces
Deletion of Caution 1 from Figure 14-3 Format of Interrupt Mask Flag Register
(MK0L, MK0H, MK1L) of old edition
3rd
Addition of Table 14-3 Ports Corresponding to EGPn and EGNn
CHAPTER 14 INTERRUPT
FUNCTIONS
APPENDIX D REVISION HISTORY
User’s Manual U15836EJ4V0UD 437
(5/5)
Edition Description Applied to:
Addition of items of software interrupt requests to Table 14-5 Interrupt Request
Enabled for Multiple Interrupt Servicing During Interrupt Servicing CHAPTER 14 INTERRUPT
FUNCTIONS
Modification of Table 15-1 Relationship Between HALT and STOP Modes and
Clock
Modification of following items in Table 15-2 Operating Statuses in HALT Mode
and Table 15-4 Operating Statuses in STOP Mode
• System clock
• 16-bit timer/event counter 00 (Table 15-2 only)
• 8-bit timer H0
• Watchdog timer
• Serial interface UART0
• Serial interface UART6
CHAPTER 15 STANDBY
FUNCTION
Modification of Figure 16-1 Block Diagram of Reset Function CHAPTER 16 RESET
FUNCTION
Addition of description to (4) and (5) of Figure 17-3 Timing of Clock Monitor CHAPTER 17 CLOCK
MONITOR
Addition of Note to description of 18.1 Functions of Power-on-Clear Circuit
Modification of Figure 18-1 Block Diagram of Power-on-Clear Circuit
CHAPTER 18 POWER-ON-
CLEAR CIRCUIT
Addition of Note to description of 19.1 Functions of Low-Voltage Detector
Modification of Figure 19-1 Block Diagram of Low-Voltage Detector
Addition of Note 2 to Figure 19-3 Format of Low-Voltage Detection Level
Selection Register (LVIS)
Modification of Figure 19-7 Example of Software Processing of LVI Interrupt
CHAPTER 19 LOW-VOLTAGE
DETECTOR
Addition of Note to description of CHAPTER 20 MASK OPTIONS CHAPTER 20 MASK
OPTIONS
Revision of CHAPTER 21
µ
PD78F0103 (no change to 21.1 Internal Memory Size
Switching Register) CHAPTER 21
µ
PD78F0103
Revision of CHAPTER 23 ELECTRICAL SPECIFICATIONS CHAPTER 23 ELECTRICAL
SPECIFICATIONS
Addition of CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS CHAPTER 25
RECOMMENDED
SOLDERING CONDITIONS
Addition of A.3 Control Software
Deletion of ‘NP-36GS’ and ‘NGS-30’ from A.5 Debugging Tools (Hardware) of old
edition, and addition of in-circuit emulator ‘IE-78K0K1-ET’
Modification of ordering name of RX78K0 in A.7 Embedded Software
APPENDIX A
DEVELOPMENT TOOLS
3rd
Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN APPENDIX B NOTES ON
TARGET SYSTEM DESIGN
