CY7C462A-10JI - Cypress Semiconductor

PRELIMINARY

5420

CY7C460A,CY7C462A

CY7C464A,CY7C466A

Asynchronou s, Casc adable 8K/16K/32K/64K x9 FIFOs

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

September 19

1997

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

• 8K x 9 FIFO (CY7C460A)

• 16K x 9 FIFO (CY7C462A)

• 32K x 9 FIFO (CY7C464A)

• 64K x 9 FIFO (CY7C466A)

• 10 ns access ti m es, 20 ns read/write cycle time s

• High-speed 50 MHz read/write independent of

depth/width

• Low operating power

—ICC= 60 mA

—ISB =2 mA

• Asynchronous read/wr ite

• Empty and Full flags

• Half Full flag (in standalone mode)

• Retransmit (in standalone mode)

• TTL-compatible

• W idth and Depth Expansion Capabi lity

•5V ± 10% supply

• PLCC, LCC, 300-mil and 600-mil DIP packagi ng

• Three-st ate output s

• Pin compatible density upgrade to CY7C42X/46X family

• Pi n compatible and func tionall y equival ent to IDT7205,

IDT7206, IDT7207, IDT7208

Functional Descripti on

The CY7C460A, CY7C462A, CY7C464A, and CY7C466A a re

respectively, 8K, 16K, 32K, and 64K words by 9-bit wide

fir st- i n-f irst - out (F IFO ) mem orie s. E ach FI FO me mory is org a -

nized such that the data is read in the same sequential order

that it w as written . Full a nd Empty fl ags are pro vided to pr event

ov erru n and under run. Thr ee ad diti onal pi ns are also pr o vided

to facilitate unlimited expansion in width, depth, or both. The

depth e xpansion te chnique steer s the control signal s fr om one

device to another by passi ng tokens.

The read and write operations may be asynchronous; each

can occu r at a rate of up to 50 MHz. The wri te opera tion occurs

when the write (W) signal is LOW . Read occurs when read (R) goes

LOW. The nine data outputs go to the high-impedance state when R

is HIG H.

A Half Full (H F) output flag is provi ded that is v alid in the standalone

(single device) and width expansion confi gurati ons. In the depth ex-

pansion configuration, this pin provides the expansion out (XO) inf or-

mation that is used to tell the ne xt FIFO that it will be activ ated.

In the standalone and width expansi on config urations, a LOW

on the retransmit (RT) input causes th e FIFOs to retransmit the

data. Read enable (R) and write enable (W) must both be HIGH dur-

ing a retransmit cycle, and then R is used to access the data.

The CY7C460A, CY7C462A, CY7C4 64A, and CY7C46 6A a re

fa bricat ed using Cy pre ss’s adv anced 0.5 µ RAM3 CMOS tec h-

nology. Input ESD protection is greater than 2000V and

latch-up is prevented by careful layout and the use of guard

rings.

32K x

LogicBlockDiagram Pin Configurations

Top View

DIP

GND

Vcc

FL/RT

XO/HF

PLCC/LCC

Top View

4 3 2 1 32 31 30

14 15 16 17 18 19 20

FL/RT

XO/HF

READ

CONTROL

WRITE

CONTROL

WRITE

POINTER

RESET

LOGIC

EXPANSION

LOGIC

RAM ARRAY

8K x 9

16K x 9

DATAINPUTS

(D0−D8)

THREE–

STATE

BUFFERS

DATAOUTPUTS

(Q0-Q 8)

READ

POINTER

FLAG

LOGIC

XO/HF

FL/RT

GND

C460A–1

C460A–2

C460A–3

7C460A

7C462A

7C464A

7C460A

7C462A

7C464A

64K x 9

7C466A 7C466A

DUAL PORT

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Maximum Ratings

(Abo v e which the useful life ma y be impai red. F or user gui de-

li nes, not tested.)

Sto ra g e Temp e ra tu re .. ..... ... .. ..... .. ..... ... ..... ..–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Volt age to Ground Potent ial ...............–0.5V to +7.0V

DC Voltage Appli ed to Outputs

in High Z State............................................... –0.5V to +7.0V

DC Input Voltage............................................ –0.5V to +7.0V

Power Dissipation ..........................................................1.0W

Output Current, into Outputs (LOW)............................ 20 mA

Static Discharge Voltage ...........................................>2001V

(per MIL- STD-883, Method 3015)

Latch-Up Current......... ............................................>200 mA

Selectio n Gu ide

7C460A-10

7C462A-10

7C464A-10

7C466A-10

7C460A-15

7C462A-15

7C464A-15

7C466A-15

7C460A-25

7C462A-25

7C464A-25

7C466A-25

Frequency (MHz) 50 40 28.5

Maximum Access Time (ns) 10 15 25

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to + 70°C 5V ± 10%

Industrial –40°C to +85°C5V ± 10%

Military[1] –55°C to +125°C 5V ± 10%

Electrica l Characte ristics Over the Oper ating Range[2]

Parameter Description Test Condi tions

7C460A/462A/464A/466A

(-10,-15,-25) UnitMin. Max.

VOH Output HIGH Voltage VCC = Min., IOH = −2.0 mA 2.4 V

VOL Ou tp ut LOW Vo l tag e VCC = Min., IOL = 8.0 mA 0.4 V

VIH Input HIGH Voltage 2.2 Vcc V

VIL Input LOW Voltage −0.5 0.8 V

IIX Input Leakage Current GND < VI < VCC –10 +10 µA

IOZ Output Leakage Current R > VIH, GND < VO < VCC –10 +10 µA

ICC Ope rating Current VCC = Max.,

IOUT = 0 mA, Freq=20MHz 60 mA

ISB Standby Current All Inputs = VCC−.2V, Freq=0MHz 2mA

Capacitance[4]

Parameter Description Test Conditions Max. Unit

CIN Input Capacit ance TA = 25°C, f = 1 MHz,

VCC = 4. 5V 10 pF

COUT Output Capacitance 12 pF

Notes:

1. TA is the “instant on” case temperature.

2. See the last page of this specification for Group A subgroup testing information.

3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.

4. Tested initially and after any design or process changes that ma y affect these parameters.

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

AC Test Loads and Waveforms

3.0V

OUTPUT

R1500Ω

333Ω

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤5ns ≤5ns

OUTPUT

R1500Ω

333Ω

5pF

INCLUDING

JIG AND

SCOPE

OUTPUT 2V

Equivalent to: THÉ VENIN EQUIVALENT

(b)

C460A–4 C460A–5 C460A–6

(a)

ALL INPUT PULSES

200Ω

Swi tch i ng C h aracteri sti cs Ov er the Op erating Range [2,5]

Parameter Description

7C460A-10

7C462A-10

7C464A-10

7C466A-10

7C460A-15

7C462A-15

7C464A-15

7C466A-15

7C460A-25

7C462A-25

7C464A-25

7C466A-25 UnitMin. Max. Min. Max. Min. Max.

tRC Read Cycle Time 20 25 35 ns

tAAccess Time 10 15 25 ns

tRR Read Recovery Time 10 10 10 ns

tPR Rea d P u l s e W idth 10 15 25 ns

tLZR Read LOW to Low Z 3 3 3 ns

tDVR[6] Data V alid After Read HIGH 3 3 3 ns

tHZR[6] Read HIGH to High Z 15 15 18 ns

tWC Write Cycl e Time 20 25 35 ns

tPW Write Pul se Width 10 15 25 ns

tHWZ Write HIGH to Low Z 5 5 5 ns

tWR Write Recovery Time 10 10 10 ns

tSD Data Set-Up Time 9 9 9 ns

tHD Data Hold Time 0 0 0 ns

tMRSC MR Cycle Time 20 25 35 ns

tPMR MR Pulse Width 10 15 25 ns

tRMR MR Recovery Time 10 10 10 ns

tRPW Read HIGH to MR HIGH 10 15 25 ns

tWPW Write HIGH to MR HIGH 10 15 25 ns

tRTC Retransm it Cycle Time 20 25 35 ns

tPRT Retransm it Pulse Width 10 15 25 ns

tRTR Retransm it Recovery Time 10 10 10 ns

tEFL MR to EF LOW 20 25 35 ns

tHFH MR to HF HIGH 20 25 35 ns

tFFH MR to FF HIGH 20 25 35 ns

tREF Read LOW to EF LO W 10 15 25 ns

tRFF Read HIGH to FF HIGH 10 15 25 ns

tWEF Write HIGH to EF HIGH 10 15 25 ns

tWFF Write LOW t o FF LO W 10 15 25 ns

tWHF Write LO W to HF LOW 10 15 35 ns

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

tRHF Read HIGH to HF HIGH 10 15 35 ns

tRAE Effective Read from Write

HIGH 10 15 25 ns

tRPE E f fec tive Re a d P ulse Widt h

After EF HIGH 10 15 25 ns

tWAF Effective Wr ite from Read

HIGH 10 15 25 ns

tWPF Effective Write Pulse

Width After FF HIGH 10 15 25 ns

tXOL Exp ansion Out LOW

Delay from Clock 10 15 25 ns

tXOH Exp ansion Out HIGH

Delay from Clock 10 15 25 ns

Notes:

5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the sp ecified IOL/IOH and 30-pF load

capacitance, as in part (a) of A C Test Load, unless otherwise specified.

6. tHZR and tDVR use capacitance loading as in part (b) of AC Test Load.

Swi tch i ng C h aracteri sti cs Ov er the Op erating Range [2,5] (contin ued)

Parameter Description

7C460A-10

7C462A-10

7C464A-10

7C466A-10

7C460A-15

7C462A-15

7C464A-15

7C466A-15

7C460A-25

7C462A-25

7C464A-25

7C466A-25 UnitMin. Max. Min. Max. Min. Max.

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Switching Waveforms[7]

Notes:

7. A HIGH-to-LO W transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Corr espondingly , a LO W-to-HIGH strobe

transition causes a LOW-to-HIGH flag transition.

8. W and R = VIH around the rising edge of MR.

9. tMSRC = t PMR + t RMR

Asynchronous Read and Write

C460A–7

DATA VALIDDATA VALID

DATA VALID DATA VALID

tSD tHD

tRC tPR

tAtRR tA

tLZR tDVR tHZR

tWC

tPW tWR

Q0−Q8

D0−D8

tSD tHD

tPW

Master Reset

R,W

tMRSC

tPMR

tEFL

tHFH

tFFH

tRPW

tWPW tRMR

C460A–8

[9]

[8]

HALF FULL+1HALF FULL HALF FULL

HF tWHF

tRHF

Half FullFlag

C460A–9

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Notes:

10. tRTC = tPRT + tRTR.

11. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC, except f or the CY7C46x-20

(Military), whose flags will be valid after tRTC + 10 ns.

Switching Waveforms[7] (continued)

Last Write to First ReadFullFlag

C460A–10

LAST WRITE FIRST READ ADDITIONAL

READS FIR ST WRITE

tWFF tRFF

Last READ toFirst WRITE Empty Flag

C460A–11

VALID

LAST READ FI R ST WRIT E ADDITIONAL

WRITES FIRST R EAD

VALID

tREF tWEF

DATA OUT

Retransm it

C460A–12

tRTC

tPRT

tRTR

FL/RT

R,W

tRTC

tRTR

[10,11]

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Switching Waveforms[7] (continued)

Full Flag and WriteData Flow-Through Mode

C460A–13

DATA IN

DATA OUT

D ATA VAL ID

DATA VALID

tWAF tWPF

tWFF

tRFF

tSD

tHD

EmptyFlag and Read Data Flow-Through Mode

C460A–14

DATA IN

DATA OUT DATA VALID

tRAE

tREF

tWEF tHWZ tA

tRPE

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Architecture

Resetti ng the FIFO

Upon power up, the FIFO must be reset with a master reset

(MR) cycle. Th is causes the FI FO to enter t he empty condi tion

sign ifi ed by the Empty flag (EF) being LOW, and both the Half

Full (HF), and Full fl ags (FF) being HIGH. Read ( R) and writ e

(W) must be HIGH tRPW/tWPW be fore and tRMR a fter the risin g

edge of MR for a valid reset cycle. If reading from the FIFO

after a reset cycle is attempted, the outputs will all be in the

high-impedance state.

Writi ng Data to the FIFO

The availabil it y of at least on e em pty location is indicated by a

HIGH FF. The falling edge of W init iate s a w r ite cy cle. D ata

appearing at the inputs (D0 − D8) tSD before and tHD after the

risi ng edge of W wi ll be stored sequentially i n the FIFO.

The EF LOW-to-HIGH transition occurs tWEF after the first

LOW-to-HIGH transition of W for an empty FIFO. HF goes

LOW tWHF after the falling edge of W following the FIFO ac-

tual ly bei ng ha lf full . Ther efo re , the HF i s ac tiv e once t he FI FO

is f illed t o hal f its capaci ty pl us one w ord. HF will remain LOW

whil e less than one half of total memory is av ailable for writing.

The LOW-to- HIGH tran siti on of HF oc curs tRHF after the rising

edge of R whe n the F IFO goes fr om half f ull +1 t o half ful l. HF

is available in standalone and width expansion modes. FF

goes LOW tWFF after the falling edge of W, during the cycle

in which the last available location is filled. Internal l ogic pre-

vent s ov errunning a full FIFO . Writes t o a full FIFO are i gnored

and the write pointer is not increment ed. FF goes HIGH t RFF

after a read from a full FIFO.

Reading Data f rom t he FIFO

The f alling edge of R initi ate s a read cycl e if the EF is not LO W .

Data outputs (Q0 − Q8) are in a high-impedance condition b e-

tween read operat ions (R HIGH), when the FIFO is empty, or

when the FIFO i s not the active devi ce in th e depth expansion

mode .

When one word is in t he FIFO, the fal ling edge of R initiates a

HIGH-to-LOW transition of EF. When the FIFO is empty, the

outputs are in a high-impedance state. Reads to an empty

FIFO are ign ore d and do not increment the re ad pointer . F rom

the empty condition, t he FIFO can be read t WEF af ter a valid

write.

Retransmit

The retransmit feature is benefici al when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. The retransmit

(RT) input is active in the standalone and width expansion

modes. The retransmit feature is intended for use when a

number of wr ites equal-to-or-less-than the depth of the FIFO

Note:

12. Expansion out of device 1 (XO1) is connected to e xpansion in of device 2 (XI2).

Switching Waveforms[7] (continued)

Expansion TimingDiagrams

C460A–15

XO1(XI2)

D0−D8DATA VALID

DATA DATA

VALID VALID

tXOL

tHD

tSD tSD tHD

tXOL

tLZR

tDVR

tHZR

XO1(XI2)

Q0−Q8

C460A–16

tWR

tRR

DATA VALID

tXOH

tXOL

[12]

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

have occurred since the last MR cycle. A LOW pulse on RT

resets the in ternal read poi nter to the first phys ical lo cation of

the FIFO. R and W must both be HIGH while and tRTR after

retransmit is LOW . With every read cycle after retransmit, pre-

viou sly acces sed dat a is read and the read poi nter increm ent-

ed until equal to t he write pointer. Full, Half Full , and Empty

flags are governed by the relative locations of the read and

write poi nters and are upd ated during a retrans mit cycle . Data

written to the FIFO after activation of RT are transm itted also .

The full depth of the FIFO can be repeatedly retransmitted.

Standalone/Width Expansion Modes

Standalone and width expans ion mode s are s et by groun ding

expansio n in (XI) and tying fi rst load (FL) to VCC prior to a MR

cycl e. FIFOs can be e xpanded in width to pro vide word widths

greater than nine in increments of nine. During width expan-

sion mode, all control line inputs are common to all devices,

and flag outputs fr om an y devic e can be monit ored.

Depth Expansion Mode (

see Figure 1

)

Depth expansion mode is entered when, during a MR cycle,

expansion out (XO) of one device is connect ed to expansion

in (XI) of t he nex t de vi ce , with XO of t he last de vice con nect ed

to XI of the first device. In the depth expansion mo de, the first

load (FL) input, when grounded, indicates that this is the first

par t to be loaded. All other devices must have this pin HIGH.

To enabl e the correct FI FO, XO is pulsed LOW when the last

physical location of the previous FIFO is written to and is

pulsed LOW a gain wh en the l ast ph ysica l location is read. Only

one FIFO is enabled for read and one is enabled for wr ite at

any given ti m e. All other de vices are in standby.

FIFOs can also be expanded simultaneously in depth and

width. Consequently, any depth or width FIFO can be created

with word widths in increments of nine. When expanding in

depth, a composite FF is created by ORing the FFs together.

Likewise, a composite EF is created by ORing EFs together.

HF and RT functions are not available in depth expansion

mode.

Figure 1. Depth Expansion

CY7C460A

CY7C462A

CY7C464A

EMPTY

FULL

D0-8 Q0-8

VCC

* FIRSTDEVICE

C460A–17

CY7C460A

CY7C462A

CY7C464A

CY7C460A

CY7C462A

CY7C464A

CY7C466A

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Ordering Information

8K x 9 Asynchronous FI FO

Speed

(ns) Ordering Code Package

Name P ackage Type Operating

Range

10 CY7C460A-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C460A-10PC P15 28-Lead (600-Mil ) M olded DIP

CY7C460A-10PTC P21 28-Lead (300-Mil) Molded DIP

CY7C460A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

15 CY7C460A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C460A-15PC P15 28-Lead (600-Mil ) M olded DIP

CY7C460A-15PTC P21 28-Lead (300-Mil) Molded DIP

CY7C460A-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

CY7C460A-15LMB L55 32-Pin Rectangular Leadle ss Chip Carrier Military

25 CY7C460A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C460A-25PC P15 28-Lead (600-Mil ) M olded DIP

CY7C460A-25PTC P21 28-Lead (300-Mil) Molded DIP

CY7C460A-25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

CY7C460A-25LMB L55 32-Pin Rectangular Leadle ss Chip Carrier Military

16K x 9 Asynchronous FIFO

Speed

(ns) Ordering Code Package

Name P ackage Type Operating

Range

10 CY7C462A-10JC J65 32-Lead Plastic Leaded Chi p Carri er Commercial

CY7C462A-10PC P15 28-Lead (600-Mil) Molded DIP

CY7C462A-10PTC P21 28-Lead (300-Mil) Molded DIP

CY7C462A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

15 CY7C462A-15JC J65 32-Lead Plast ic Leaded Chip Carri er Commercial

CY7C462A-15PC P15 28-Lead (600-Mil) Molded DIP

CY7C462A-15PTC P21 28-Lead (300-Mil) Molded DIP

CY7C462A-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

CY7C462A-15LMB L55 32-Pin Rectangular Leadless Chip Carrier Military

25 CY7C462A-25JC J65 32-Lead Plast ic Leaded Chip Carri er Commercial

CY7C462A-25PC P15 28-Lead (600-Mil) Molded DIP

CY7C462A-25PTC P21 28-Lead (300-Mil) Molded DIP

CY7C462A-25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

CY7C462A-25LMB L55 32-Pin Rectangular Leadless Chip Carrier Military

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Orde ring Information ( c on ti nued )

32K x 9 Asynchronous FIFO

Speed

(ns) Ordering Code Package

Name Pack age Typ e Operating

Range

10 CY7C464A-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C464A-10PC P15 28-Lead (600- Mil) Molded DIP

CY7C464A-10PTC P21 28-Lead (300-Mil) Molded DIP

CY7C464A-10JI J65 32-Lead Plastic Leaded Chi p Carr ier Industrial

15 CY7C464A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C464A-15PC P15 28-Lead (600- Mil) Molded DIP

CY7C464A-15PTC P21 28-Lead (300-Mil) Molded DIP

CY7C464A-15JI J65 32-Lead Plastic Leaded Chi p Carr ier Industrial

CY7C464A-15LMB L55 32-Pin Rectangular Leadless Chip Carrier Military

25 CY7C464A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C464A-25PC P15 28-Lead (600- Mil) Molded DIP

CY7C464A-25PTC P21 28-Lead (300-Mil) Molded DIP

CY7C464A-25JI J65 32-Lead Plastic Leaded Chi p Carr ier Industrial

CY7C464A-25LMB L55 32-Pin Rectangular Leadless Chip Carrier Military

64K x 9 Asynchronous FIFO

Speed

(ns) Or dering Code Package

Name Package Type Operating

Range

10 CY7C466A-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C466A-10PC P15 28-Lead (600-Mil) Molded DI P

CY7C466A-10PTC P21 28-Lead (300-Mil) Molded DIP

CY7C466A-10JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

15 CY7C466A-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C466A-15PC P15 28-Lead (600-Mil) Molded DI P

CY7C466A-15PTC P21 28-Lead (300-Mil) Molded DIP

CY7C466A-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

CY7C466A-15LMB L55 32-Pin Rect angular Leadless Chip Carrier Mi litary

25 CY7C466A-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C466A-25PC P15 28-Lead (600-Mil) Molded DI P

CY7C466A-25PTC P21 28-Lead (300-Mil) Molded DIP

CY7C466A-25JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

CY7C466A-25LMB L55 32-Pin Rect angular Leadless Chip Carrier Mi litary

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

MILITARY SPECIFICATIONS

Group A Subgroup Testing

Documen t #: 38−00627

DC Characteristics

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL Max . 1, 2, 3

IIX 1, 2, 3

ICC 1, 2, 3

ISB1 1, 2, 3

ISB2 1, 2, 3

IOS 1, 2, 3

IOZ 1, 2, 3

Switching Characteristics

Parameter Subgroups

tRC 9, 10, 11

tA9, 10, 11

tRR 9, 10, 11

tPR 9, 10, 11

tLZR 9, 10, 11

tDVR 9, 10, 11

tHZR 9, 10, 11

tWC 9, 10, 11

tPW 9, 10, 11

tHWZ 9, 10, 11

tWR 9, 10, 11

tSD 9, 10, 11

tHD 9, 10, 11

tMRSC 9, 10, 11

tPMR 9, 10, 11

tRMR 9, 10, 11

tRPW 9, 10, 11

tWPW 9, 10, 11

tRTC 9, 10, 11

tPRT 9, 10, 11

tRTR 9, 10, 11

tEFL 9, 10, 11

tHFH 9, 10, 11

tFFH 9, 10, 11

tREF 9, 10, 11

tRFF 9, 10, 11

tWEF 9, 10, 11

tWFF 9, 10, 11

tWHF 9, 10, 11

tRHF 9, 10, 11

tRAE 9, 10, 11

tRPE 9, 10, 11

tWAF 9, 10, 11

tWPF 9, 10, 11

tXOL 9, 10, 11

tXOH 9, 10, 11

PRELIMINARY

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

Package Diagrams

32-Lead PlasticLeadedChipCarrier J65

32-Pin Rectangular Leadless Chip Carrier L55

MIL-STD-1835 C-12

CY 7C460A, CY7C462A

CY7C464A,CY7C466A

PRELIMINARY

of any circui try other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

P ackage Diagrams (c ontinued)

28-Lead (600-Mil) MoldedDIP P15

28-Lead (300-Mil) Molded DIP P21