SBAS314B − APRIL 2004 − REVISED JANUARY 2009

    
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FEATURES
D240SPS Data Rate with 4MHz Clock
D20-Bit Effective Resolution
DInput Multiplexer with Two Differential
Channels
DPin-Selectable, High-Impedance Input Buffer
D±5V Differential Input Range
D0.0003% INL (typ), 0.0015% INL (max)
DSelf-Calibrating
DSimple 2-Wire Serial Interface
DOn-Chip Temperature Sensor
DSingle Conversions with Standby Mode
DLow Current Consumption: 300µA
DAnalog Supply: 2.7V to 5.5V
APPLICATIONS
DHand-Held Instrumentation
DPortable Medical Equipment
DIndustrial Process Control
DWeigh Scales
DESCRIPTION
The ADS1222 is a 2-channel, 24-bit, delta-sigma ana-
log-to-digital (A/D) converter. It offers excellent perfor-
mance and low power in a TSSOP-14 package. The
ADS1222 is well-suited for demanding, high-resolution
measurements, especially in portable systems and oth-
er space-saving and power-constrained applications.
A delta-sigma (∆Σ) modulator and digital filter form the
basis of the A/D converter. The analog modulator has
a ±5V differential input range. An input multiplexer
(MUX) is used to select between two separate
differential input channels. A buffer can be selected to
increase the input impedance of the measurement.
A simple, 2-wire serial interface provides all the
necessary control. Data retrieval, self-calibration, and
Standby mode are handled with a few simple
waveforms. When only single conversions are needed,
the ADS1222 can be quickly shut down (Standby mode)
while idle between measurements to dramatically
reduce the overall power consumption. Multiple
ADS1222s can be connected together to create a
synchronously sampling multichannel measurement
system. The ADS1222 is designed to easily connect to
microcontrollers, such as the MSP430.
The ADS1222 supports 2.7V to 5.5V supplies. Power
is typically less than 1mW in 3V operation and less than
1µW during Standby mode.
Mux Digital Filter
and
Serial Interface
∆Σ
Modulator
VREFP VREFN
Buffer
VDD
GNDMUX
AINP1
AINN1
AINP2
AINN2
CLK
DRDY/DOUT
SCLK
TEMPEN
BUFEN
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Copyright 2004−2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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ORDERING INFORMATION (1)
PRODUCT PACKAGE-LEAD PACKAGE
DESIGNATOR PACKAGE
MARKING ORDERING NUMBER TRANSPORT MEDIA,
QUANTITY
ADS1222
TSSOP-14
PW
ADS1222
ADS1222IPWT Tape and Reel, 250
ADS1222
TSSOP-14
PW
ADS1222
ADS1222IPWR Tape and Reel, 2000
(1) For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over o p e r a t i n g f ree-air temperature range unless otherwise noted(1)
ADS1222 UNIT
VDD to GND −0.3 to +6 V
Input current
100, momentary mA
Input current
10, continuous mA
Analog input voltage to GND −0.3 to VDD + 0.3 V
Digital input voltage to GND −0.3 to VDD + 0.3 V
Maximum Junction Temperature +150 °C
Operating Temperature Range −55 to +125 °C
Storage Temperature Range −60 to +150 °C
Lead Temperature (soldering, 10s) +300 °C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , a nd
functional operation of the device at these or any other conditions
beyond those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
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ELECTRICAL CHARACTERISTICS
All specifications at TA = −40°C to +85°C, VDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Input
Full-scale input voltage AINP − AINN ±2VREF V
Absolute input voltage
Buffer of f; AINP, AINN with respect to GND GND − 0.1 VDD + 0. 1 V
Absolute input voltage
Buffer on; AINP, AINN with respect to GND GND + 0.05 VD D − 1.5 V
Differential input impedance
Buf fer off; fCLK = 2MHz 2.7 MΩ
Differential input impedance
Buffer on; fCLK = 2MHz 1.2 GΩ
Common-mode input impedance Buf fer off; fCLK = 2MHz 5.4 MΩ
System Performance
Resolution No missing codes 24 Bits
Data rate 120 (fCLK/2MHz) SPS(1)
Integral nonlinearity (INL)
Buffer off; Differential input signal, end point fit 0.0003 0.0015 % of F SR(2)
Integral nonlinearity (INL)
Buffer on; Differential input signal, end point fit 0.0006 % of F SR
Offset error
Buf fer off 50 150 µV
Offset error
Buffer on 50 µV
Offset error drift
Buf fer off 0.2 µV/°C
Offset error drift
Buffer on 0.2 µV/°C
Offset error match Between channels 20 100 µV
Gain error
Buf fer off 0.004 0.025 %
Gain error
Buffer on 0.008 %
Gain error drift
Buf fer off 0.00003 % of F SR/°C
Gain error drift
Buffer on 0.00006 % of F SR/°C
Gain error match Between channels 0.0005 %
Common-mode rejection
Buf fer off; at DC 95 dB
Common-mode rejection
Buf fer on; at DC 90 100 dB
Power-supply rejection
Buf fer off; at DC, VDD = 2.7V to 5.5V 90 dB
Power-supply rejection
Buf fer on; at DC, VDD = 2.7V to 5.5V 90 dB
Noise 0.8 ppm of FSR, r ms
Temperature Sensor
Temperature sensor voltage TA = 25°C 106 mV
Temperature sensor coefficient 360 µV/°C
Voltage Reference Input
Reference input voltage VREF = VREFP − VREFN 0.5 2.5 VDD(3) V
Negative reference input Buf fer off GND − 0.1 VREFP − 0.5 V
Positive reference input Buf fer off VREFN + 0.5 VDD + 0.1 V
Negative reference input Buffer on GND + 0.05 VREFP − 0.5 V
Positive reference input Buffer on VREFN + 0.5 VD D − 1 .5 V
Voltage reference impedance fCLK = 2MHz 500 kΩ
(1) SPS = samples per second.
(2) FSR = full-scale range = 4VREF.
(3) It will not be possible to reach the digital output full-scale code when VREF > VDD/2.
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = −40°C to +85°C, VDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted.
PARAMETER UNITMAXTYPMINTEST CONDITIONS
Digital Input/Output
VIH 0.8 VDD VDD + 0.1 V
Logic
VIL GND − 0.1 0.2 VDD V
Logic
levels VOH IOH = 1mA 0.8 VDD V
levels
VOL IOL = 1mA 0.2 VDD V
Input leakage ±10 µA
CLK frequency (fCLK) 8 MHz
CLK duty cycle 30 70 %
Power Supply
VDD 2.7 5.5 V
Standby mode < 1 µA
VDD = 5V, normal mode, buffer off 300 µA
VDD current VDD = 5V, normal mode, buffer on 425 µA
VDD current
VDD = 3V, normal mode, buffer off 275 µA
VDD = 3V, normal mode, buffer on 395 µA
Total power dissipation
VDD = 5V, buf fer off 1.5 2.25 mW
Total power dissipation
VDD = 3V, buf fer off 0.8 mW
Temperature Range
Specified −40 +85 °C
Operating −55 +125 °C
Storage −60 +150 °C
(1) SPS = samples per second.
(2) FSR = full-scale range = 4VREF.
(3) It will not be possible to reach the digital output full-scale code when VREF > VDD/2.
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PIN ASSIGNMENTS
PW PACKAGE
TSSOP-14
(TOP VIEW)
VDD
SCLK
CLK
DRDY/DOUT
MUX
TEMPEN
BUFEN
VREFP
VREFN
GND
AINN1
AINP1
AINN2
AINP2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ADS1222
Terminal Functions
TERMINAL
NAME NO. I/O DESCRIPTION
VDD 1 Analog/Digital Analog and digital power supply
SCLK 2 Digital input Serial clock input
CLK 3 Digital input System clock input
DRDY/DOUT 4 Digital Output Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the rising edge of SCLK.
MUX 5 Digital input Selects analog input of mux
TEMPEN 6 Digital input Selects temperature sensor input from mux
BUFEN 7 Digital input Enables input buffer
AINP2 8 Analog input Analog channel 2 positive input
AINN2 9 Analog input Analog channel 2 negative input
AINP1 10 Analog input Analog channel 1 positive input
AINN1 11 Analog input Analog channel 1 negative input
GND 12 Analog/Digital Analog and digital ground
VREFN 13 Analog input Negative reference input
VREFP 14 Analog input Positive reference input
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TYPICAL CHARACTERISTICS
At TA = −40°C to +85°C, VDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted.
Figure 1
ANALOG CURRENT vs TEMPERATURE
Temperature (_C)
Current (µA)
400
375
350
325
300
275
250
225
200 0
−25 25 50 75 125
−50 100
fCLK =4MHz,VDD=5V
fCLK =2MHz,VDD=3V
fCLK =4MHz,VDD=3V
fCLK =2MHz,VDD=5V
Buffer Off
Figure 2
fCLK =4MHz,VDD=5V
fCLK =2MHz,VDD=3V
fCLK =4MHz,VDD=3V
fCLK =2MHz,VDD=5V
Buffer On
ANALOG CURRENT vs TEMPERATURE
Current (µA)
550
500
450
400
350
300
Temperature (_C)
0
−25 25 50 75 125
−50 100
Figure 3
ANALOG CURRENT vs SUPPLY VOLTAGE
Supply Voltage (V)
Current (µA)
3.53.0 4.0 4.5 5.0 5.52.5
500
450
400
350
300
250
Buffer Off
Buffer On
fCLK =2MHz
fCLK =2MHz
fCLK =4MHz
fCLK =4MHz
Figure 4
TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE
Temperature (_C)
Temperature Sensor Voltage (mV)
5
−25 35 65 95 125
−55
150
140
130
120
110
100
90
80
70
Figure 5
Input Voltage, VIN (V)
−3
−4−2−1012345
−5
10
8
6
4
2
0
−2
−4
−6
−8
−10
INL (ppm of FSR)
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
−40_C
+25_C
+85_C
fCLK =2MHz
Buffer Off
Figure 6
−1.5
−2.5 −0.5 0.5 1.5 2.5 3.5
−3.5
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
Input Voltage, VIN (V)
fCLK =2MHz
Buffer On
10
8
6
4
2
0
−2
−4
−6
−8
−10
INL (ppm of FSR)
−40_C
+25_C
+85_C
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TYPICAL CHARACTERISTICS (continued)
At TA = −40°C to +85°C, VDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted.
Figure 7
Input Voltage, VIN (V)
−3
−4−2−1012345
−5
15
10
5
0
−5
−10
−15
INL (ppm of FSR)
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
fCLK =4MHz
Buffer Off
−40_C
+25_C
+85_C
Figure 8
−1.5
−2.5 −0.5 0.5 1.5 2.5 3.5
−3.5
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
Input Voltage, VIN (V)
fCLK =4MHz
Buffer On
15
10
5
0
−5
−10
−15
INL (ppm of FSR)
−40_C
+25_C
+85_C
Figure 9
NOISE vs INPUT VOLTAGE
Input Voltage, VIN (V)
Noise (ppm of FSR, rms)
−3−1135
−5
2.5
2.0
1.5
1.0
0.5
0
fCLK =2MHz
Buffer Off
Figure 10
NOISE vs INPUT VOLTAGE
Input Voltage, VIN (V)
Noise (ppm of FSR, rms)
0.5 1.5 3.5
−3.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
fCLK =2MHz
Buffer On
−2.5 −1.5 −0.5 2.5
Figure 11
NOISE vs INPUT VOLTAGE
Input Voltage, VIN (V)
Noise (ppm of FSR, rms)
−3−1135
−5
2.5
2.0
1.5
1.0
0.5
0
fCLK =4MHz
Buffer Off
Figure 12
NOISE vs INPUT VOLTAGE
Noise (ppm of FSR, rms)
2.5
2.0
1.5
1.0
0.5
fCLK =4MHz
Buffer On
Input Voltage, VIN (V)
0.5 1.5 3.5
−3.5 −2.5 −1.5 −0.5 2.5
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OVERVIEW
The ADS1222 is an A/D converter comprised of a
delta-sigma modulator followed by a digital filter. A m u x
allows for one of two input channels to be selected. A
buffer can also be selected to increase the input
impedance. The modulator measures the differential
input signal VIN = (AINP – AINN) against the differential
reference V REF = (VREFP – VREFN). Figure 13 shows
a conceptual diagram of the device. The differential
reference is scaled internally so that the full-scale input
range i s ±2VREF. The digital filter receives the modulator
signal and provides a low-noise digital output. A 2-wire
serial interface indicates conversion completion and
provides the user with the output data.
ANALOG INPUTS (AINPx, AINNx)
The input signal to be measured is applied to the input
pins AINPx and AINNx. The positive internal input is
generalized as AINP, and the negative internal input is
generalized a s AINN. The signal is selected though the
input mux, which is controlled by MUX, as shown in
Table 1. The ADS1222 accepts differential input
signals, but can also measure unipolar signals. When
measuring unipolar (or single-ended signals) with
respect to ground, connect the negative input (AINNx)
to ground and connect the input signal to the positive
input (AINPx). Note that when the ADS1222 is
configured this way, only half of the converter full-scale
range is used since only positive digital output codes
are produced. An input buffer can be selected to
increase the input impedance of the A/D converter with
the BUFEN pin.
Table 1. Input Channel Selection with MUX
DIGITAL PIN SELECTED ANALOG INPUTS
MUX POSITIVE INPUT NEGATIVE INPUT
0 AINP1 AINN1
1 AINP2 AINN2
Mux AINP VIN
AINN
Temp
Sensor
Digital
Filter
and
Serial
Interface
∆Σ
Modulator
VREFP
Σ
VREFN
Buffer
AINP1
AINN1
AINP2
AINN2
+−
CLK
DRDY/DOUT
SCLK
TEMPEN
MUX BUFEN
2
VREF
2VREF
Σ
Figure 13. Conceptual Diagram of the ADS1222
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Analog Input Measuremen t without the Input Buffer
With the buffer disabled by setting the BUFEN pin l ow,
the ADS1222 measures the input signal using internal
capacitors that are continuously charged and
discharged. Figure 14 shows a simplified schematic of
the ADS1222 input circuitry, with Figure 15 showing t he
on/off timings of the switches. The S1 switches close
during the input sampling phase. With S1 closed, CA1
charges to AINP, CA2 charges to AINN, and CB charges
to (AINP – AINN). For the discharge phase, S1 opens
first and then S2 closes. CA1 and CA2 discharge to
approximately VDD/2 and CB discharges to 0V. This
two-phase sample/discharge cycle repeats with a
frequency of fCLK/32 (62.5kHz for fCLK = 2MHz).
Mux
VDD
VDD/2
VDD/2
S1
S1
AINN
AINP S2
CA1
3pF
CB
6pF
CA2
3pF
VDD
ESD Protection
AINPx
AINNx
S2
Figure 14. Simplified Input Structure with the
Buffer Turned Off
ON
OFF
ON
S1
S2OFF
tSAMPLE = 32/fCLK
Figure 15. S1 and S2 Switch Timing for Figure 14
The constant charging of the input capacitors presents
a load on the inputs that can be represented by effective
impedances. Figure 16 shows the input circuitry with
the capacitors and switches of Figure 14 replaced by
their effective impedances. These impedances scale
inversely with fCLK frequency. For example, if fCLK
frequency is reduced by a factor of 2, the impedances
will double.
ZeffA=t
SAMPLE/CA1 =6M
Ω(1)
ZeffB=t
SAMPLE/CB=3M
Ω(1)
ZeffA=t
SAMPLE/CA2 =6M
Ω(1)
NOTE: (1) fCLK =2MHz.
AINPx
AINNx
VDD/2
VDD/2
Figure 16. Effective Analog Input Impedances
with the Buffer Off
ESD diodes protect the inputs. To keep these diodes
from turning on, make sure the voltages on the input
pins do not go below GND by more than 100mV, and
likewise do not exceed VDD by 100mV:
GND – 100mV < (AINP, AINN) < VDD + 100mV
Analog Input Measurement with th e Input Buffer
When the buffer is enabled by setting the BUFEN pin
high, a low-drift, chopper-stabilized input buffer is used
to achieve very high input impedance. The buffer
charges the input sampling capacitors, thus removing
the load from the measurement. Because the input
buffer is chopper-stabilized, the charging of parasitic
capacitances causes the charge to be carried away, as
if by resistance. The input impedance can be modeled
by a single resistor, as shown in Figure 17. The
impedance scales inversely with fCLK frequency, as in
the nonbuffered case. Note that during standby mode,
the buffer must be disabled to prevent loading of the
inputs.
AINP
AINN
1.2GΩ(1)
NOTE: (1) fCLK =2MHz.
Figure 17. Effective Analog Input Impedances
with the Buffer On
Note also that the analog inputs (listed in the Electrical
Characteristics table as Absolute Input Range) must
remain between GND + 0.05V to VDD − 1.5V.
Exceeding this range degrades linearity and results in
performance outside the specified limits.
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TEMPERATURE SENSOR
On-chip diodes provide temperature-sensing capabili-
ty. By setting the TEMPEN pin high, the selected analog
inputs are disconnected and the inputs to the A/D
converter are connected to the anodes of two diodes
scaled t o 1 x and 64x in current and size inside the mux,
as shown in Figure 18. By measuring the difference in
voltage of these diodes, temperature changes can be
inferred from a baseline temperature. Typically, the
difference in diode voltages is 106mV at 25°C, with a
temperature coef ficient of 360µV/°C. A similar structure
is used in the MSC1210 for temperature measurement.
For more information, see TI application report
SBAA100, Using the MSC121x as a High-Precision
Intelligent Temperature Sensor , available for download
at www.ti.com.
AINP
AINP1
AINN1
AINP2
AINN2
8I 1I
1X 8X
AINN
TEMPEN
VDD
MUX
Figure 18. Measurement of the Temperature
Sensor in the Input Multiplexer
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference used by the modulator is
generated from the voltage difference between VREFP
and VREFN: VREF = VREFP – VREFN. The reference
inputs use a structure similar to that of the analog
inputs. A simplified diagram of the circuitry on the
reference inputs is shown in Figure 19. The switches
and capacitors can be modeled with an effective
impedance of:
ǒtsample
2Ǔń16pF +500kW
where fCLK = 2MHz.
VDD
Self Gain Cal
AINP
(1) fCLK =2MHz
AINN
VREFP VREFN
VDD
ESD
Protection
16pF Zef f = 500kΩ (1)
Figure 19. Simplified Reference Input Circuitry
ESD diodes protect the reference inputs. To prevent
these diodes from turning on, make sure the voltages
on the reference pins do not go below GND by more
than 100mV, and likewise, do not exceed VDD by
100mV:
GND – 100mV < (VREFP, VREFN) < VDD + 100mV
During self gain calibration, all the switches in the input
multiplexer are opened, VREFN is internally connected
to AINN, and VREFP is connected to AINP. The input
buffer may be disabled or enabled during calibration.
When the buffer is disabled, the reference pins will be
driving the circuitry shown in Figure 9 during self gain
calibration, resulting in increased loading. To prevent
this additional loading from introducing gain errors,
make sure the circuitry driving the reference pins has
adequate drive capability. When the buffer is enabled,
the loading on the reference pins will be much less, but
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11
the buffer will limit the allowable voltage range on
VREFP and VREFN during self or self gain calibration
as the reference pins must remain within the specified
input range of the buf fer in order to establish proper gain
calibration.
For best performance, VREF should be VDD/2, but it can
be raised a s high as VDD. When VREF exceeds VDD/2,
it is not possible to reach the full-scale digital output
value corresponding to ±2VREF, since this requires the
analog inputs to exceed the power supplies. For
example, if VREF = VDD = 5V, the positive full-scale
signal is 10V. The maximum positive input signal that
can be supplied before the ESD diodes turn on is when
AINP = 5.1V and AINN = –0.1V, resulting in VIN = 5.2V.
Therefore, it is not possible to reach the positive (or
negative) full-scale readings in this configuration. The
digital output codes are limited to approximately one
half of the entire range. For best performance, bypass
the voltage reference inputs with a 0.1µF capacitor
between VREFP and VREFN. Place the capacitor as
close as possible to the pins.
CLOCK INPUT (CLK)
This digital input supplies the system clock to the
ADS1222. The CLK frequency can be increased to
speed u p the data rate. CLK must be left running during
normal operation. It may be turned off during Standby
mode to save power , but this is not required. The CLK
input may be driven with 5V logic, regardless of the VD D
voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10Ω to 100Ω) can often help. CLK can be
generated from a number of sources including
standalone crystal oscillators and microcontrollers.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it
indicates when new data is ready by going LOW.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins to
output the conversion data, most significant bit (MSB)
first. Data is shifted out on each subsequent SCLK
rising edge. After all 24 bits have been retrieved, the pin
can be forced high with an additional SCLK. It will then
stay high until new data is ready. This is useful when
polling o n the status of DRDY/DOUT to determine when
to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V
logic regardless of the VDD voltage. There is hysteresis
built into this input, but care should still be taken to
ensure a clean signal. Glitches or slow-rising signals
can cause unwanted additional shifting. For this reason,
it is best to make sure the rise-and-fall times of SCLK
are less than 50ns.
FREQUENCY RESPONSE
The ADS1222 frequency response for fCLK = 2MHz is
shown in Figure 20. The frequency response repeats at
multiples of the modulator sampling frequency of
62.5kHz. The overall response is that of a low-pass filter
with a −3db cutof f frequency of 31.5Hz. As shown, the
ADS1222 does a good job attenuating out to 60kHz. For
the best resolution, limit the input bandwidth to less than
this value to keep higher frequency noise from affecting
performance. Often, a simple RC filter on the ADS1222
analog inputs is all that is needed.
Input Frequency (Hz)
Gain (dB)
0
−20
−40
−60
−80
−100 31250 625000
Figure 20. Frequency Response
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To help see the response at lower frequencies,
Figure 21 illustrates the response out to 1kHz. Notice
that signals at multiples of 120Hz are rejected. The
ADS1222 data rate and frequency response scale
directly with CLK frequency. For example, if fCLK
increases from 2MHz to 4MHz, the data rate increases
from 120SPS to 240SPS, while the notches increase
from 120Hz to 240Hz.
Input Frequency (Hz)
Gain (dB)
0
−20
−40
−60
−80
−100 500 600 700 800 900100 200 300 400 1k0
Figure 21. Frequency Response to 1kHz
Rejecting 50Hz or 60Hz noise is as simple as choosing
the clock frequency. If simultaneous rejection of 50Hz
and 60Hz noise is desired, fCLK = 910kHz can be
chosen. The data rate becomes 54.7SPS and the
frequency response of the ADS1222 rejects the 50Hz
and 60Hz noise to below 60dB. The frequency
response of the ADS1222 near 50Hz and 60Hz with
fCLK = 910kHz is shown in Figure 22.
Input Frequency (Hz)
Gain (dB)
0
−20
−40
−60
−80
−100 8030 40 50 60 70
Figure 22. Frequency Response Near 50Hz and
60Hz with fCLK = 910kHz
SETTLING TIME
After changing the input multiplexer, selecting the input
buffer, or using temperature sensor, the first data is fully
settled. In the ADS1222, the digital filter is allowed to
settle after toggling any of the MUX, BUFEN, or
TEMPEN pins. Toggling of any of these digital pins will
cause the input to switch to the proper channel, start
conversions, and hold the DRDY/DOUT line high until
the digital filter is fully settled. For example, if MUX
changes from low to high, selecting a different input
channel, DRDY/DOUT immediately goes high and the
conversion process restarts. DRDY/DOUT goes low
when fully settled data is ready for retrieval. There is no
need to discard any data. Figure 23 shows the timing of
the DRDY/DOUT line as the input multiplexer changes.
SYMBOL DESCRIPTION MIN MAX UNITS
t1(1) Settling time (DRDY/DOUT held high) after a change in any of the 25.9 26.4 ms
MUX, BUFEN, or TEMPEN pins
(1) Values given for fCLK = 2MHz. For dif ferent fCLK frequencies, scale proportional to CLK period.
Abrupt change in internal VIN due to status change (for example, switch channels, temp sensor, buffer enable)
ADS1222 holds DRDY/DOUT
until digital filter settles
MUX0
VIN t1
DRDY/DOUT
DRDY/DOUT suppressed after status change
Fully settled
data ready
Figure 23. Example of Settling Time After Changing the Input Multiplexer
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The ADS1222 uses a Sinc3 digital filter to improve noise
performance. Therefore, in certain instances, large
changes in input will require settling time. For example,
an external multiplexer in front of the ADS1222 can put
large changes in input voltage by simply switching input
channels. Abrupt changes in the input will require three
data cycles to settle. When continuously converting,
four readings may be necessary to settle the data. If the
change in input occurs in the middle of the first conver-
sion, three more full conversions of the fully settled input
will b e required to get fully settled data. Discard the first
three readings because they will contain only partially-
settled data. Figure 24 illustrates the settling time for
the ADS1222 in Continuous Conversion mode.
If the input is known to change abruptly, the mux can be
quickly switched to an alternate channel and quickly
switched back to the original channel. By toggling the
mux, the ADS1222 resets the digital filter and initiates a
new conversion. During this time, the DRDY/DOUT line
is held high until fully-settled data is available.
DATA FORMAT
The ADS1222 outputs 24 bits of data in binary two’s
complement format. The least significant bit (LSB) has
a weight of (2VREF)/(223 – 1). The positive full-scale
input produces an output code of 7FFFFFh and the
negative full-scale input produces an output code of
800000h. The output clips at these codes for signals
exceeding full-scale. Table 2 summarizes the ideal
output codes for different input signals.
Table 2. Ideal Output Code vs Input Signal
INPUT SIGNAL VIN
(AINP − AINN) IDEAL OUTPUT CODE(1)
w+2VREF 7FFFFFh
+2VREF
223 *1000001h
0 000000h
−2VREF
223 *1FFFFFFh
v−2VREFǒ223
223 *1Ǔ800000h
(1) Excludes effects of noise, INL, of fset, and gain errors.
DATA RETRIEVAL
The ADS1222 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as shown in Figure 25. After this occurs, begin
shifting out the data by applying SCLKs. Data is shifted
out MSB first. It is not required to shift out all 24 bits of
data, but the data must be retrieved before the new data
is updated (see t2) or else it will be overwritten. Avoid
data retrieval during the update period. DRDY/DOUT
remain at the state of the last bit shifted out until it is
taken high (see t6), indicating that new data is being
updated. To avoid having DRDY/DOUT remain in the
state of the last bit, shift a 25th SCLK to force
DRDY/DOUT high (see Figure 26). This technique is
useful when a host controlling the ADS1222 is polling
DRDY/DOUT to determine when data is ready.
Abrupt change in external VIN
VIN
DRDY/DOUT
Start of
conversion First Conversion;
includes
unsettled VIN
Second Conversion;
VIN settled, but
digital filter
unsettled
Third Conversion;
VIN settled, but
digital filter
unsettled
Fourth Conversion;
VIN and digital filter
both settled
Conversion
time
Figure 24. Settling Time in Continuous Conversion Mode
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SYMBOL DESCRIPTION MIN MAX UNITS
t2DRDY/DOUT low to first SCLK rising edge 0 ns
t3SCLK positive or negative pulse width 100 ns
t4SCLK rising edge to new data bit valid: propagation delay 50 ns
t5SCLK rising edge to old data bit valid: hold time 0 ns
t6(1) Data updating; no readback allowed 48 µs
t7(1) Conversion time (1/data rate) 8.32 8.32 ms
(1) Values given for fCLK = 2MHz. For dif ferent fCLK frequencies, scale proportional to CLK period.
DRDY/DOUT 23 22 21
124
0
LSBMSB
Data
Data Ready
SCLK
t2
t7
t3
t3
t6
New Data Ready
t4t5
Figure 25. Data Retrieval Timing
23
12425
22 21 0
Data
25th SCLK to Force DRDY/DOUT High
Data Ready New Data Ready
DRDY/DOUT
SCLK
Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards
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SELF-CALIBRATION
Self-calibration can be initiated at any time, although in
many applications the ADS1222 drift performance is so
good that the self-calibration performed automatically
at power-up is all that is needed. To initiate
self-calibration, apply at least two additional SCLKs
after retrieving 24 bits of data. Figure 27 shows the
timing pattern. The 25th SCLK will send DRDY/DOUT
high. The falling edge of the 26th SCLK will begin the
calibration cycle. Additional SCLK pulses may be sent
after the 26th SCLK; however , activity on SCLK should
be minimized during calibration for best results.
When the calibration is complete, DRDY/DOUT goes
low, indicating that new data is ready. There is no need
to alter the analog input signal applied to the ADS1222
during calibration; the input pins are disconnected
within the A/D converter and the appropriate signals are
applied internally and automatically. The first
conversion after a calibration is fully settled and valid for
use. The time required for a calibration depends on two
independent signals: the falling edge of SCLK and an
internal clock derived from CLK. Variations in the
internal calibration values will change the time required
for calibration (t8) within the range given by the min/max
specs. t11 and t12 described in the next section are
affected likewise.
STANDBY MODE
Standby mode dramatically reduces power
consumption (typically < 1µW with CLK stopped) by
shutting down all of the active circuitry. To enter Standby
mode, simply hold SCLK high after DRDY/DOUT goes
low, as shown in Figure 28. Standby mode can be
initiated a t any time during readback; it is not necessary
to retrieve all 24 bits of data beforehand. Note that
during standby mode, the buffer must be disabled to
prevent loading of the inputs.
When t 11 has p assed with SCLK held h igh, Standby mode
will activate. DRDY/DOUT stays high when Standby
mode begins. SCLK must remain high to s tay in Standby
mode. To exit Standby mode (wakeup), set SCLK low.
The first data after exiting Standby mode is valid. It is not
necessary to stop CLK dur ing Standby mode, but doing
so will fur ther reduce the digital supply current .
Standby Mode With Self-Calibration
Self-calibration can be set to run immediately after
exiting Standby mode. This is useful when the
ADS1222 is put in Standby mode for long periods of
time and self-calibration is desired afterwards to
compensate for temperature or supply voltage
changes.
To force a self-calibration with Standby mode, shift 25
bits out before taking SCLK high to enter Standby
mode. Self-calibration then begins after wakeup.
Figure 29 shows the appropriate timing. Note the extra
time needed after wakeup for calibration before data is
ready. The first data after Standby mode with
self-calibration is fully settled and can be used.
23DRDY/DOUT
SCLK 1 24
t8
25 26
2322 21 0
Data Ready After Calibration
Calibration Begins
SYMBOL DESCRIPTION MIN MAX UNITS
t8(1) First data ready after calibration 77.1 77.9 ms
(1) Values given for fCLK = 2MHz. For dif ferent fCLK frequencies, scale proportional to CLK period.
Figure 27. Self-Calibration Timing
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SYMBOL DESCRIPTION MIN MAX UNITS
t9(1) SCLK high after DRDY/DOUT goes low to activate Standby mode 0 8.272 ms
t10(1) Standby mode activation time 8.272 8.304 ms
t11(1) Data ready after exiting Standby mode 27.7 28.1 ms
(2) Values given for fCLK = 2MHz. For dif ferent fCLK frequencies, scale proportional to CLK period.
DRDY/DOUT 23 22 21
124
023
SCLK
Standby Mode
StartConversion
Data Ready
t9t10 t11
Figure 28. Standby Mode Timing (can be used for single conversions)
SYMBOL DESCRIPTION MIN MAX UNITS
t12(1) Data ready after exiting Standby mode and calibration 78.8 79.7 ms
(1) Values given for fCLK = 2MHz. For dif ferent fCLK frequencies, scale proportional to CLK period.
Standby Mode
Begin Calibration
Data Ready After Calibration
t10 t12
DRDY/DOUT 23
12425
22 21 0 23
SCLK
Figure 29. Standby Mode with Self-Calibration Timing (can be used for single conversions)
SINGLE CONVERSIONS
When only single conversions are needed, Standby
mode can be used to start and stop the ADS1222. To
make a single conversion, first enter the Standby mode
holding SCLK high. Now, when ready to start the
conversion, take SCLK low. The ADS1222 wakes up
and begins the conversion. W ait for DRDY/DOUT to go
low, and then retrieve the data. Afterwards, take SCLK
high to stop the ADS1222 from converting and re-enter
Standby mode. Continue to hold SCLK high until ready
to start the next conversion. Operating in this fashion
greatly reduces power consumption since the
ADS1222 is shut down while idle between conversions.
Self-calibrations can be performed prior to the start of
the single conversions by using the waveform shown in
Figure 29.
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APPLICATIONS INFORMATION
GENERAL RECOMMENDATIONS
The ADS1222 is a high-resolution A/D converter.
Achieving optimal device performance requires careful
attention to the support circuitry and printed circuit
board (PCB) design. Figure 30 shows the basic
connections for the ADS1222. As with any precision
circuit, be sure to use good supply bypassing capacitor
techniques. A smaller value ceramic capacitor in
parallel with a larger value tantalum capacitor works
well. Place the capacitors, in particular the ceramic
ones, close to the supply pins. Use a ground plane and
tie the ADS1222 GND pin and bypass capacitors
directly to it. Avoid ringing on the digital inputs. Small
resistors (≈100Ω) in series with the digital pins can help
by controlling the trace impedance. Place these
resistors at the source end.
Pay special attention to the reference and analog
inputs. These are the most critical circuits. Bypass the
voltage reference using similar techniques to the supply
voltages. The quality of the reference directly affects
the overall accuracy of the device. Make sure to use a
low noise and low drift reference such as the REF1004.
Often, only a simple RC filter is needed on the inputs.
This circuit limits the higher frequency noise. Avoid
low-grade dielectrics for the capacitors and place them
as close as possible to the input pins. Keep the traces
to the input pins short, and carefully watch how they are
routed on the PCB.
After the power supplies and reference voltage have
stabilized, issue a self-calibration command to
minimize offset and gain errors.
ADS1222
VDD
SCLK
CLK
DRDY/DOUT
MUX
TEMPEN
BUFEN
VREFP
VREFN
GND
AINN1
AINP1
AINN2
AINP2
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
Same as shown
for AINP1 and AINN1.
0.1µF
10µF
+5V
0.1µF10µF+2.5V Reference
220pF
0.1µF
220pF
VINP
VINN
301Ω
301Ω
Figure 30. Basic Connections
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18
MULTICHANNEL SYSTEMS
Multiple ADS1222s can be operated in parallel to
measure multiple input signals. Figure 31 shows an
example of a four-channel system. For simplicity, the
supplies and reference circuitry are not shown. The
same CLK signal should be applied to all devices. To
synchronize the ADS1222s, connect the same SCLK
signal to all devices. Then place all the devices in
Standby mode. Afterwards, starting a conversion will
synchronize all the ADS1222s; that is, they will sample
the input signals simultaneously. The DRDY/DOUT
outputs will go low at approximately the same time after
synchronization. When reading data from the devices,
the data appears in parallel on DRDY/DOUT as a result
of the common SCLK connection.
The falling edges of DRDY/DOUT, indicating that new
data is ready, will vary with respect to each other no
more than time t13. This variation is due to possible
differences i n the ADS1222 internal calibration settings.
To account for this, when using multiple devices, either
wait for t13 to pass after seeing one DRDY/DOUT go
low, or wait until all DRDY/DOUTs have gone low before
retrieving data.
Note that changing channels (using the MUX pin), or
using the input buffer (BUFEN) or the temperature
sensor (TEMPEN), may require more care to settle the
digital filter. For example, if the MUX pin is toggled on
one device and not the other , the DRDY /DOUT line will
be held high until the conversion settles on the first
device. The latter device will continue conversions
through this time. See the Settling Time section of this
datasheet for further details.
SYMBOL DESCRIPTION MIN MAX UNITS
t13(1) Difference between DRDY/DOUTs going low in multichannel ±0.8 ms
systems
(1) Values given for fCLK = 2MHz. For dif ferent fCLK frequencies, scale proportional to CLK period.
CLK
SCLK
DRDY/DOUT
AINP1
AINN1
AINP4
AINN4
MUX
ADS1222
MUX Select
Inputs
OUT1
CLK and SCLK
Sources
OUT1
OUT2
t13
…
CLK
SCLK
DRDY/DOUT
AINP1
AINN1
AINP4
AINN4
MUX
ADS1222
MUX Select
Inputs
OUT2
…
Figure 31. Example of Using Multiple ADS1222s in Parallel
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19
SUMMARY OF SERIAL INTERFACE WAVEFORMS
DRDY/DOUT
SCLK
23 22 21 0
MSB LSB
124
DRDY/DOUT
SCLK
23 22 21 0
12425
DRDY/DOUT
SCLK
23 22 21 0
1242526
Begin Calibration
Data Ready
After Calibration
DRDY/DOUT
SCLK
Data Ready
Start
Conversion
Standby Mode
23 22 21 0
124
DRDY/DOUT
SCLK
23 22 21 0
12425
Data Ready
After Calibration
Begin Calibration
(a) Data Retrieval
(b) Data Retrieval with DRDY/DOUT Forced HighAfterwards
(c) Self−Calibration
(d) Standby Mode/Single Conversions
(e) Standby Mode/Single Conversions with Self−Calibration
Standby Mode
Figure 32. Summary of Serial Interface Waveforms
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20
Revision History
DATE REV PAGE SECTION DESCRIPTION
12/2/08 B 9Analog Input
Measurement with the
Input Buffer Added last sentence to fist paragraph describing standby mode.
15 Standby Mode Added last sentence to first paragraph describing standby mode.
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1222IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
ADS1222IPWT TSSOP PW 14 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1222IPWR TSSOP PW 14 2000 367.0 367.0 35.0
ADS1222IPWT TSSOP PW 14 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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