M95128-WMN6TP/P - STMICROELECTRONICS

January 2012 Doc ID 5798 Rev 14 1/45

M95128

M95128-W M95128-R

128 Kbit serial SPI bus EEPROM

with high speed clock

Features

■Compatible with SPI bus serial interface

(positive clock SPI modes)

■Single supply voltage:

– 4.5 to 5.5 V for M95128

– 2.5 to 5.5 V for M95128-W

– 1.8 to 5.5 V for M95128-R

■High speed

– 10 MHz clock rate, 5 ms write time

■Status Register

■Hardware protection of the Status Register

■Byte and Page Write (up to 64 bytes)

■Self-timed programming cycle

■Adjustable size read-only EEPROM area

■Enhanced ESD protection

■More than 1 000 000 write cycles

■More than 40-year data retention

■Packages

–ECOPACK2

® (RoHS compliant and

Halogen-free)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8 (MB, MC)

2 × 3 mm (MLP)

www.st.com

Contents M95128, M95128-W, M95128-R
2/45 Doc ID 5798 Rev 14
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory organization   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Serial Data output (Q)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
3 Serial Clock (C)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4 Chip Select (S)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
6 Write Protect (W)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
7 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
8 Supply voltage (VCC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
8.1 Operating supply voltage VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.2 Device reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.3 Power-up conditions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.4 Power-down  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
3 Data Protection and protocol control  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Write Enable (WREN)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
3 Read Status Register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
3.1 WIP bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 WEL bit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 SRWD bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
5 Read from Memory Array (READ)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20

M95128, M95128-W, M95128-R Contents

Doc ID 5798 Rev 14 3/45

5.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6.1 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . 22

6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

List of tables M95128, M95128-W, M95128-R
4/45 Doc ID 5798 Rev 14
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Write-protected block size  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Status Register format  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Operating conditions (M95128)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Operating conditions (M95128-W)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Operating conditions (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Capacitance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. DC characteristics (M95128, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics (M95128-W, device grade 6)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. DC characteristics (M95128-W, device grade 3)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. DC characteristics (M95128-R)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. AC characteristics (M95128, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. AC characteristics (M95128-W, device grade 6)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. AC characteristics (M95128-W, device grade 3)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. AC characteristics (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 38
Table 22. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24. Available M95128x products (package, voltage range, temperature grade)  . . . . . . . . . . . 41
Table 25. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

M95128, M95128-W, M95128-R List of figures
Doc ID 5798 Rev 14 5/45
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO, UFDFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Write Enable (WREN) sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Page Write (WRITE) sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Hold timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 37
Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline  . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Description M95128, M95128-W, M95128-R

6/45 Doc ID 5798 Rev 14

1 Description

The M95128, M95128-W and M95128-R are electrically erasable programmable memory

(EEPROM) devices accessed by a high speed SPI-compatible bus. The memory array is

organized as 16384 × 8 bits.

Figure 1. Logic diagram

The device is accessed by a simple serial interface that is SPI-compatible. The bus signals

are C, D and Q, as shown in Ta b l e 1 and Figure 1.

The device is selected when Chip Select (S) is taken low. Communications with the device

can be interrupted using Hold (HOLD).

Figure 2. SO, UFDFPN and TSSOP connections

1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.

AI12805

VCC

M95128

HOLD

VSS

DVSS

HOLDQ

AI12806

M95128

M95128, M95128-W, M95128-R Description

Doc ID 5798 Rev 14 7/45

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data input Input

Q Serial Data output Output

SChip Select Input

W Write Protect Input

HOLD Hold Input

VCC Supply voltage

VSS Ground

Memory organization M95128, M95128-W, M95128-R

8/45 Doc ID 5798 Rev 14

2 Memory organization

The memory is organized as shown in Figure 3.

Figure 3. Block diagram

AI01272C

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

1 Page

X Decoder

Y Decoder

Size of the

Read only

EEPROM

area

Status

M95128, M95128-W, M95128-R Signal description

Doc ID 5798 Rev 14 9/45

3 Signal description

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

3.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

3.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

3.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

3.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal write cycle is in progress, the device will be in the Standby

Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power

mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

3.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

Signal description M95128, M95128-W, M95128-R

10/45 Doc ID 5798 Rev 14

3.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against Write instructions (as specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either high or low, and must be stable during all write instructions.

3.7 VSS ground

VSS is the reference for the VCC supply voltage.

3.8 Supply voltage (VCC)

3.8.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [VCC(min), VCC(max)] range must be applied (see Ta b l e 7 , Ta bl e 8 and

Ta bl e 9 ). This voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In

order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with

a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package

pins.

3.8.2 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up, the device does not respond to any instruction until VCC

reaches the internal reset threshold voltage (this threshold is defined in DC tables 12, 13, 14

and 15 as VRES.

When VCC passes over the POR threshold, the device is reset and in the following state:

●in Standby Power mode

●deselected (note that, to be executed, an instruction must be preceded by a falling

edge on Chip Select (S))

●Status register values:

– the Write Enable Latch (WEL) bit is reset to 0

– the Write In Progress (WIP) bit is reset to 0

– the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

When VCC passes over the POR threshold, the device is reset and enters the Standby

Power mode. The device must not be accessed until VCC reaches a valid and stable VCC

voltage within the specified [VCC(min), VCC(max)] range defined in Ta b l e 7 , Ta b le 8 and

Ta bl e 9 .

M95128, M95128-W, M95128-R Signal description

Doc ID 5798 Rev 14 11/45

3.8.3 Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this

time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is

therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see

Figure 12).

In addition, the Chip Select (S) input offers a built-in safety feature, as it is edge-sensitive as

well as level-sensitive: after power-up, the device does not become selected until a falling

edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must

have been high, prior to going low to start the first operation.

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in Ta bl e 7 , Ta b le 8 and Tab l e 9 and the rise time must not vary faster than 1 V/µs.

3.8.4 Power-down

During power-down (continuous decrease in the VCC supply voltage below the minimum

VCC operating voltage defined in Ta bl e 7 , Ta b l e 8 and Ta bl e 9 ), the device must be:

●deselected (Chip Select S should be allowed to follow the voltage applied on VCC)

●in Standby Power mode (there should not be any internal write cycle in progress).

Operating features M95128, M95128-W, M95128-R

12/45 Doc ID 5798 Rev 14

4 Operating features

4.1 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.

The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 4).

The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 4 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

Figure 4. Hold condition activation

AI02029D

HOLD

Hold

Condition

Hold

Condition

M95128, M95128-W, M95128-R Operating features

Doc ID 5798 Rev 14 13/45

4.2 Status Register

Figure 3 shows the position of the Status Register in the control logic of the device. The

Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. For a detailed description of the Status Register bits,

see Section 5.3: Read Status Register (RDSR).

4.3 Data Protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

●Write and Write Status Register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

●All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Write (WRITE) instruction completion

●The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

●The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

●The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

●The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2. Write-protected block size

Status Register bits

Protected block

Array addresses protected

BP1 BP0 M95128, M95128-W, M95128-R

0 0 none none

0 1 Upper quarter 3000h - 3FFFh

1 0 Upper half 2000h - 3FFFh

1 1 Whole memory 0000h - 3FFFh

Instructions M95128, M95128-W, M95128-R

14/45 Doc ID 5798 Rev 14

5 Instructions

Each instruction starts with a single-byte code, as summarized in Ta b l e 3 .

If an invalid instruction is sent (one not contained in Ta b le 3 ), the device automatically

deselects itself.

5.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

high.

Figure 5. Write Enable (WREN) sequence

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100

RDSR Read Status Register 0000 0101

WRSR Write Status Register 0000 0001

READ Read from Memory Array 0000 0011

WRITE Write to Memory Array 0000 0010

AI02281E

21 34567

High Impedance

Instruction

M95128, M95128-W, M95128-R Instructions

Doc ID 5798 Rev 14 15/45

5.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

●Power-up

●WRDI instruction execution

●WRSR instruction completion

●WRITE instruction completion.

Figure 6. Write Disable (WRDI) sequence

AI03750D

21 34567

High Impedance

Instruction

Instructions M95128, M95128-W, M95128-R

16/45 Doc ID 5798 Rev 14

5.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Write or Write Status Register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the Status Register continuously, as shown in Figure 7.

The status and control bits of the Status Register are as follows:

5.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

5.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write or Write Status Register instruction is accepted.

5.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Write instructions. These bits are written with the Write Status

1, the relevant memory area (as defined in Ta bl e 4 ) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

5.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the

non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 4. Status Register format

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

M95128, M95128-W, M95128-R Instructions

Doc ID 5798 Rev 14 17/45

Figure 7. Read Status Register (RDSR) sequence

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

Instructions M95128, M95128-W, M95128-R

18/45 Doc ID 5798 Rev 14

5.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

sending the instruction code followed by the data byte on Serial Data input (D), and driving

the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of

Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge

of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not

executed.

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-

timed write cycle that takes tW to complete (as specified in Ta b l e 1 6 , Ta b l e 1 7 , Ta bl e 1 9 and

Ta bl e 1 9 ). The instruction sequence is shown in Figure 8.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write

cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also

reset at the end of the write cycle tW.

The Write Status Register (WRSR) instruction allows the user to change the values of the

BP1, BP0 and SRWD bits:

●The Block protect (BP1, BP0) bits define the size of the area that is to be treated as

read only, as defined in Ta b l e 5 .

●The SRWD bit (Status register write disable bit), in accordance with the signal read on

the Write protect pin (W), allows the user to set or reset the write protection mode of the

Status Register itself, as shown in Ta bl e 5 . When in the Write-protected mode, the

Write Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the

WRSR instruction, including the tW write cycle.

The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0

bits in the Status Register. Bits b6, b5, b4 are always read as 0.

Table 5. Protection modes

signal

SRWD

bit Mode Write protection of the

Status Register

Memory content

Protected area(1)

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.

Unprotected area(1)

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the BP1

and BP0 bits can be

changed

Write Protected Ready to accept Write

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the BP1

and BP0 bits cannot be

changed

Write Protected Ready to accept Write

instructions

M95128, M95128-W, M95128-R Instructions

Doc ID 5798 Rev 14 19/45

The protection features of the device are summarized in Ta b l e 2 .

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of whether Write Protect (W) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

●If Write Protect (W) is driven high, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

●If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the Write enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution.) As a consequence, all the data bytes in the memory area that are

software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,

are also hardware-protected against data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered:

●by setting the Status register write disable (SRWD) bit after driving Write Protect (W)

low

●or by driving Write Protect (W) low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write

Protect (W) high.

If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can

never be activated, and only the Software-protected mode (SPM), using the Block protect

(BP1, BP0) bits in the Status Register, can be used.

Figure 8. Write Status Register (WRSR) sequence

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

Instructions M95128, M95128-W, M95128-R

20/45 Doc ID 5798 Rev 14

5.5 Read from Memory Array (READ)

As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven low.

The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input

(D). The address is loaded into an internal address register, and the byte of data at that

address is shifted out, on Serial Data Output (Q).

If Chip Select (S) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

Figure 9. Read from Memory Array (READ) sequence

1. The most significant address bits (b15, b14) are Don’t Care.

AI01793D

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28 29 30

76543 1 7

High Impedance Data Out 1

Instruction 16-Bit Address

MSB

Data Out 2

M95128, M95128-W, M95128-R Instructions

Doc ID 5798 Rev 14 21/45

5.6 Write to Memory Array (WRITE)

As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte, address byte, and at least one data byte are then shifted

in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a

byte boundary of the input data. The self-timed write cycle, triggered by the rising edge of

Chip Select (S), continues for a period tWC (as specified in Ta b l e 1 6 to Ta bl e 1 9 .), at the end

of which the Write in Progress (WIP) bit is reset to 0.

In the case of Figure 10, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte. If,

though, Chip Select (S) continues to be driven low, as shown in Figure 11., the next byte of

input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address

counter are incremented. If the number of data bytes sent to the device exceeds the page

boundary, the internal address counter rolls over to the beginning of the page, and the

previous data there are overwritten with the incoming data. (The page size of these devices

is 64 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

●if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

●if a write cycle is already in progress

●if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

●if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is

read as “0” and a programmed bit is read as “1”.

Figure 10. Byte Write (WRITE) sequence

1. The most significant address bits (b15, b14) are Don’t Care.

AI01795D

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28 29 30

High Impedance

Instruction 16-Bit Address

765432 0

Data Byte

Instructions M95128, M95128-W, M95128-R

22/45 Doc ID 5798 Rev 14

Figure 11. Page Write (WRITE) sequence

1. The most significant address bits (b15, b14) are Don’t Care.

5.6.1 ECC (error correction code) and write cycling

Most M95128, M95128-W and M95128-R devices offer an ECC (error correction code) logic

which compares each 4-byte word with 6 EEPROM bits of ECC (the list of concerned

devices is defined in Table 24: Available M95128x products (package, voltage range,

temperature grade)). As a result, if a single bit out of 4 bytes of data happens to be

erroneous during a read operation, the ECC detects it and replaces it by the correct value.

The read reliability is therefore improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes

making up the word. It is therefore recommended to write by packets of 4 bytes in order to

benefit from the larger amount of write cycles.

The maximum number of write cycles is qualified at 1 Million (1 000 000) write cycles, using

a cycling routine that writes to the device by multiples of 4-byte packets.

AI01796D

3433 35 36 37 38 39 40 41 42 44 45 46 4732

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1413 3210

28 29 30

Instruction 16-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3

65432 0

Data Byte N

M95128, M95128-W, M95128-R Delivery state

Doc ID 5798 Rev 14 23/45

6 Delivery state

The device is delivered with the memory array set at all 1s (FFh). The Status Register Write

Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

7 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction

(such as the Read from Memory Array and Read Status Register instructions) have been

clocked into the device.

Figure 12. Bus master and memory devices on the SPI bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

Figure 12 shows an example of three memory devices connected to an MCU, on an SPI

bus. Only one memory device is selected at a time, so only one memory device drives the

Serial Data Output (Q) line at a time, the other memory devices are high impedance.

The pull-up resistor R (represented in Figure 12) ensures that a device is not selected if the

bus master leaves the S line in the high impedance state.

AI12304c

Bus master

SPI memory

device

SDO

SDI

SCK

CQD

SPI memory

device

CQD

SPI memory

device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

RRR

Connecting to the SPI bus M95128, M95128-W, M95128-R

24/45 Doc ID 5798 Rev 14

In applications where the bus master might enter a state where all inputs/outputs SPI bus

would be in high impedance at the same time (for example, if the bus master is reset during

the transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S line is pulled high): this will ensure that S and C do not become high at the

same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

7.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

●CPOL=0, CPHA=0

●CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 13, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

●C remains at 0 for (CPOL=0, CPHA=0)

●C remains at 1 for (CPOL=1, CPHA=1)

Figure 13. SPI modes supported

AI01438B

MSB

CPHA

CPOL

MSB

M95128, M95128-W, M95128-R Maximum rating

Doc ID 5798 Rev 14 25/45

8 Maximum rating

Stressing the device outside the ratings listed in Ta bl e 6 may cause permanent damage to

the device. These are stress ratings only, and operation of the device at these, or any other

conditions outside those indicated in the operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability. Refer also to the STMicroelectronics SURE Program and other relevant

quality documents.

Table 6. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

TAAmbient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering See note (1)

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU

°C

VOOutput voltage –0.50 VCC+0.6 V

VIInput voltage –0.50 6.5 V

IOL DC output current (Q = 0) 5 mA

IOH DC output current (Q = 1) –5 mA

VCC Supply voltage –0.50 6.5 V

VESD Electrostatic discharge voltage (human body model)(2)

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 p F, R1 = 1500 Ω, R2 = 500 Ω).

–4000 4000 V

DC and AC parameters M95128, M95128-W, M95128-R

26/45 Doc ID 5798 Rev 14

9 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Table 7. Operating conditions (M95128)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 4.5 5.5 V

TAAmbient operating temperature (device grade 3) –40 125 °C

Table 8. Operating conditions (M95128-W)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

Ambient operating temperature (device grade 6) –40 85 °C

Ambient operating temperature (device grade 3) –40 125 °C

Table 9. Operating conditions (M95128-R)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TAAmbient operating temperature –40 85 °C

M95128, M95128-W, M95128-R DC and AC parameters

Doc ID 5798 Rev 14 27/45

Figure 14. AC measurement I/O waveform

Table 10. AC measurement conditions

Symbol Parameter Min. Max. Unit

CLLoad capacitance 100 pF

Input rise and fall times 50 ns

Input pulse voltages 0.2VCC to 0.8VCC V

Input and output(1) timing reference voltages

1. Output Hi-Z is defined as the point where data out is no longer driven.

0.3VCC to 0.7VCC V

Table 11. Capacitance(1)

1. Sampled only, not 100% tested, at TA =25 °C and a frequency of 5 MHz.

Symbol Parameter Test condition Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

CIN

Input capacitance (D) VIN = 0 V 8 pF

Input capacitance (other pins) VIN = 0 V 6 pF

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

DC and AC parameters M95128, M95128-W, M95128-R

28/45 Doc ID 5798 Rev 14

Table 12. DC characteristics (M95128, device grade 3)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 2 µA

ICC Supply current

C = 0.1VCC/0.9VCC at 5 MHz,

VCC = 5 V, Q = open 4mA

C = 0.1VCC/0.9VCC at 10 MHz,

VCC = 5 V, Q = open 8mA

ICC1

Supply current

(Standby Power mode)

S = VCC, VCC = 5 V,

VIN = VSS or VCC

5µA

VIL Input low voltage –0.45 0.3 VCC V

VIH Input high voltage 0.7 VCC VCC+1 V

VOL(1)

1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

Output low voltage IOL = 2 mA, VCC = 5 V 0.4 V

VOH(1) Output high voltage IOH = –2 mA, VCC = 5V 0.8V

CC V

VRES(2)

2. Characterized only, not 100% tested.

Internal reset threshold

voltage 2.5 4.0 V

Table 13. DC characteristics (M95128-W, device grade 6)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 2 µA

ICC Supply current (Read)

C = 0.1VCC/0.9VCC at 5 MHz,

VCC = 2.5 V, Q = open 3mA

C = 0.1VCC/0.9VCC at 5 MHz,

VCC = 5 V, Q = open 5mA

ICC0(1)

1. Characterized value, not tested in production.

Supply current (Write) During tW, S = VCC, 2.5 V < VCC < 5.5 V 5 mA

ICC1

Supply current

(Standby Power mode)

S = VCC, VIN = VSS or VCC,

2.5 V < VCC < 5.5 V 5µA

VIL Input low voltage –0.45 0.3 VCC V

VIH Input high voltage 0.7 VCC VCC+1 V

VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA or

VCC = 5 V and IOL = 2 mA 0.4 V

VOH Output high voltage VCC = 2.5 V and IOH = –0.4 mA or VCC

= 5 V and IOH = –2 mA 0.8 VCC V

VRES(2)

2. Characterized only, not 100% tested.

Internal reset threshold

voltage 1.0 1.65 V

M95128, M95128-W, M95128-R DC and AC parameters

Doc ID 5798 Rev 14 29/45

Table 14. DC characteristics (M95128-W, device grade 3)

Symbol Parameter Test condition Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ± 2 µA

ICC Supply current (Read) C = 0.1VCC/0.9VCC at 5 MHz,

VCC = 2.5 V, Q = open 3mA

ICC0(1)

1. Characterized value, not tested in production.

Supply current (Write) During tW, S = VCC,

2.5 V < VCC < 5.5 V 6mA

ICC1

Supply current

(Standby Power mode)

S = VCC, VIN = VSS or VCC

2.5 V < VCC < 5.5 V, 5µA

VIL Input low voltage –0.45 0.3 VCC V

VIH Input high voltage 0.7 VCC VCC+1 V

VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA or

VCC = 5 V and IOL = 2 mA 0.4 V

VOH Output high voltage VCC = 2.5 V and IOH = –0.4 mA or

VCC = 5 V and IOH = –2 mA 0.8 VCC V

VRES(2)

2. Characterized only, not 100% tested.

Internal reset threshold

voltage 1.0 1.65 V

DC and AC parameters M95128, M95128-W, M95128-R

30/45 Doc ID 5798 Rev 14

Table 15. DC characteristics (M95128-R)

Symbol Parameter Test condition(1)

1. If the application uses the M95128-R device with 2.5 V < VCC < 5.5 V and –40 °C < TA < +85 °C, please

refer to Table 17: AC characteristics (M95128-W, device grade 6) instead of the above table.

Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ± 2 µA

ILO

Output leakage

current

S = VCC, voltage applied on Q = VSS

or VCC

± 2 µA

ICCR Supply current (Read)

VCC = 1.8 V, C = 0.1 VCC or 0.9VCC,

fC=2 MHz, Q = open 1mA

VCC = 2.5 V, C = 0.1 VCC or 0.9VCC,

fC=2 MHz, Q = open 3mA

ICC1

Supply current

(Standby)

VCC = 5.0 V, S = VCC, VIN = VSS or

VCC

5µA

VCC = 2.5 V, S = VCC, VIN = VSS or

VCC

3µA

VCC = 1.8 V, S = VCC, VIN = VSS or

VCC

3µA

VIL Input low voltage 2.5V < VCC < 5.5V –0.45 0.3VCC V

1.8V < VCC < 2.5V –0.45 0.25VCC V

VIH Input high voltage 2.5V < VCC < 5.5V 0.7VCC VCC+1 V

1.8V < VCC < 2.5V 0.75VCC VCC+1 V

VOL Output low voltage

VCC = 2.5 V, IOL = 1.5 mA or

VCC = 5.5 V, IOL = 2 mA 0.2VCC V

VCC = 1.8 V, IOL = 0.15 mA 0.3 V

VOH Output high voltage

VCC = 2.5 V, IOH = –0.4 mA, or

VCC = 5.5 V, IOH = –2 mA, or

VCC = 1.8 V, IOH = –0.1 mA

0.8VCC V

VRES(2)

2. Characterized only, not 100% tested.

Internal reset

threshold voltage 1.0 1.65 V

M95128, M95128-W, M95128-R DC and AC parameters

Doc ID 5798 Rev 14 31/45

Table 16. AC characteristics (M95128, device grade 3)

Test conditions specified in Table 1 0 and Table 7

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 10 MHz

tSLCH tCSS1 S active setup time 30 ns

tSHCH tCSS2 S not active setup time 30 ns

tSHSL tCS S deselect time 40 ns

tCHSH tCSH S active hold time 30 ns

tCHSL S not active hold time 30 ns

tCH (1)

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)

tCLH Clock high time 45 ns

tCL (1) tCLL Clock low time 45 ns

tCLCH (2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 2 µs

tCHCL (2) tFC Clock fall time 2 µs

tDVCH tDSU Data in setup time 10 ns

tCHDX tDH Data in hold time 10 ns

tHHCH Clock low hold time after HOLD not active 30 ns

tHLCH Clock low hold time after HOLD active 30 ns

tCLHL Clock low setup time before HOLD active 0 ns

tCLHH Clock low setup time before HOLD not active 0 ns

tSHQZ (2) tDIS Output disable time 40 ns

tCLQV tVClock low to output valid 40 ns

tCLQX tHO Output hold time 0 ns

tQLQH (2) tRO Output rise time 40 ns

tQHQL (2) tFO Output fall time 40 ns

tHHQV tLZ HOLD high to output valid 40 ns

tHLQZ (2) tHZ HOLD low to output high-Z 40 ns

tWtWC Write time 5 ms

DC and AC parameters M95128, M95128-W, M95128-R

32/45 Doc ID 5798 Rev 14

Table 17. AC characteristics (M95128-W, device grade 6)

Test conditions specified in Table 10 and Ta b le 8

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 90 ns

tSHCH tCSS2 S not active setup time 90 ns

tSHSL tCS S deselect time 100 ns

tCHSH tCSH S active hold time 90 ns

tCHSL S not active hold time 90 ns

tCH (1)

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)

tCLH Clock high time 90 ns

tCL (1) tCLL Clock low time 90 ns

tCLCH (2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 1 µs

tCHCL (2) tFC Clock fall time 1 µs

tDVCH tDSU Data in setup time 20 ns

tCHDX tDH Data in hold time 30 ns

tHHCH Clock low hold time after HOLD not active 70 ns

tHLCH Clock low hold time after HOLD active 40 ns

tCLHL Clock low setup time before HOLD active 0 ns

tCLHH Clock low setup time before HOLD not active 0 ns

tSHQZ (2) tDIS Output disable time 100 ns

tCLQV tVClock low to output valid 60 ns

tCLQX tHO Output hold time 0 ns

tQLQH (2) tRO Output rise time 50 ns

tQHQL (2) tFO Output fall time 50 ns

tHHQV tLZ HOLD high to output valid 50 ns

tHLQZ (2) tHZ HOLD low to output high-Z 100 ns

tWtWC Write time 5 ms

M95128, M95128-W, M95128-R DC and AC parameters

Doc ID 5798 Rev 14 33/45

Table 18. AC characteristics (M95128-W, device grade 3)

Test conditions specified in Ta ble 10 and Table 8

Symbol Alt. Parameter Min. Max. Unit

fCfSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 90 ns

tSHCH tCSS2 S not active setup time 90 ns

tSHSL tCS S deselect time 100 ns

tCHSH tCSH S active hold time 90 ns

tCHSL S not active hold time 90 ns

tCH (1)

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)

tCLH Clock high time 90 ns

tCL (1) tCLL Clock low time 90 ns

tCLCH (2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 1 µs

tCHCL (2) tFC Clock fall time 1 µs

tDVCH tDSU Data in setup time 20 ns

tCHDX tDH Data in hold time 30 ns

tHHCH Clock low hold time after HOLD not active 70 ns

tHLCH Clock low hold time after HOLD active 40 ns

tCLHL Clock low setup time before HOLD active 0 ns

tCLHH Clock low setup time before HOLD not active 0 ns

tSHQZ (2) tDIS Output disable time 100 ns

tCLQV tVClock low to output valid 60 ns

tCLQX tHO Output hold time 0 ns

tQLQH (2) tRO Output rise time 50 ns

tQHQL (2) tFO Output fall time 50 ns

tHHQV tLZ HOLD high to output valid 50 ns

tHLQZ (2) tHZ HOLD low to output high-Z 100 ns

tWtWC Write time 5 ms

DC and AC parameters M95128, M95128-W, M95128-R

34/45 Doc ID 5798 Rev 14

Table 19. AC characteristics (M95128-R)

Test conditions specified in Tab l e 10 and Table 9(1)

1. If the application uses the M95128-R at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer to

Table 17 instead of the above table.

Symbol Alt. Parameter Min.(2)

2. This is preliminary data.

Max.(2) Unit

fCfSCK Clock frequency D.C. 2 MHz

tSLCH tCSS1 S active setup time 200 ns

tSHCH tCSS2 S not active setup time 200 ns

tSHSL tCS S deselect time 200 ns

tCHSH tCSH S active hold time 200 ns

tCHSL S not active hold time 200 ns

tCH (3)

3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)

tCLH Clock high time 200 ns

tCL (3) tCLL Clock low time 200 ns

tCLCH (4)

4. Value guaranteed by characterization, not 100% tested in production.

tRC Clock rise time 1 µs

tCHCL (4) tFC Clock fall time 1 µs

tDVCH tDSU Data in setup time 40 ns

tCHDX tDH Data in hold time 50 ns

tHHCH Clock low hold time after HOLD not active 140 ns

tHLCH Clock low hold time after HOLD active 90 ns

tCLHL Clock low setup time before HOLD active 0 ns

tCLHH Clock low setup time before HOLD not active 0 ns

tSHQZ (4) tDIS Output disable time 250 ns

tCLQV tVClock low to output valid 150 ns

tCLQX tHO Output hold time 0 ns

tQLQH (4) tRO Output rise time 100 ns

tQHQL (4) tFO Output fall time 100 ns

tHHQV tLZ HOLD high to output valid 100 ns

tHLQZ (4) tHZ HOLD low to output high-Z 250 ns

tWtWC Write time 5 ms

M95128, M95128-W, M95128-R DC and AC parameters

Doc ID 5798 Rev 14 35/45

Figure 15. Serial input timing

Figure 16. Hold timing

AI01447d

MSB IN

tDVCH

High impedance

LSB IN

tSLCH

tCHDX

tCLCH

tSHCH

tSHSL

tCHSHtCHSL tCH

tCL

tCHCL

AI01448c

HOLD

tCLHL

tHLCH

tHHCH

tCLHH

tHHQVtHLQZ

DC and AC parameters M95128, M95128-W, M95128-R

36/45 Doc ID 5798 Rev 14

Figure 17. Serial output timing

AI01449f

ADDR

LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCHCL

tCLQX

tCLQV

tSHSL

tCLCH

M95128, M95128-W, M95128-R Package mechanical data

Doc ID 5798 Rev 14 37/45

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

1. Drawing is not to scale.

Table 20. SO8N – 8-lead plastic small outline, 150 mils body width, package

mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ Min Max Typ Min Max

A 1.75 0.0689

A1 0.10 0.25 0.0039 0.0098

A2 1.25 0.0492

b 0.28 0.48 0.011 0.0189

c 0.17 0.23 0.0067 0.0091

ccc 0.10 0.0039

D 4.90 4.80 5.00 0.1929 0.189 0.1969

E 6.00 5.80 6.20 0.2362 0.2283 0.2441

E1 3.90 3.80 4.00 0.1535 0.1496 0.1575

e1.27– –0.05- -

h 0.25 0.50 0.0098 0.0197

k 0°8° 0°8°

L 0.40 1.27 0.0157 0.05

L1 1.04 0.0409

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

Package mechanical data M95128, M95128-W, M95128-R

38/45 Doc ID 5798 Rev 14

Figure 19. TSSOP8 – 8-lead thin shrink small outline, package outline

1. Drawing is not to scale.

Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

N (number of leads) 8 8

TSSOP8AM

EE1

A2A

M95128, M95128-W, M95128-R Package mechanical data

Doc ID 5798 Rev 14 39/45

Figure 20. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

outline

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be

connected to any other voltage or signal line on the PCB, for example during the soldering process.

Table 22. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data

Symbol

millimeters inches(1)

1. Values in inches are converted from mm and rounded to four decimal digits.

Typ Min Max Typ Min Max

A 0.550 0.450 0.600 0.0217 0.0177 0.0236

A1 0.020 0.000 0.050 0.0008 0.0000 0.0020

b 0.250 0.200 0.300 0.0098 0.0079 0.0118

D 2.000 1.900 2.100 0.0787 0.0748 0.0827

D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669

D2 (rev MC) 1.200 1.600 0.0472 0.0630

E 3.000 2.900 3.100 0.1181 0.1142 0.1220

E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118

E2 (rev MC) 1.200 1.600 0.0472 0.0630

e 0.500 0.0197

K (rev MB) 0.800 0.0315

K (rev MC) 0.300 0.0118

L 0.300 0.500 0.0118 0.0197

L1 0.150 0.0059

L3 0.300 0.0118

eee(2)

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measuring.

0.080 0.0031

:7?-%E

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EEE

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Part numbering M95128, M95128-W, M95128-R

40/45 Doc ID 5798 Rev 14

11 Part numbering

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

Table 23. Ordering information scheme

Example: M95128 – W MN 6 T P /P

Device type

M95 = SPI serial access EEPROM

Device function

128 = 128 Kbit (16384 x 8)

Operating voltage

blank = VCC = 4.5 to 5.5 V

W = VCC = 2.5 to 5.5 V

R = VCC = 1.8 to 5.5 V

Package

MN = SO8 (150 mils width)

DW = TSSOP8 (169 mils width)

MB or MC = UFDFPN8 (MLP8 2 × 3 mm)

Device grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3 = Device tested with high reliability certified flow(1)

Automotive temperature range (–40 to 125 °C)

1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your

nearest ST sales office for a co.

Option

blank = Standard packing

T = Tape and reel packing

Plating technology

P or G = ECOPACK2® (RoHs compliant and Halogen-free)

Process(2)

2. The Process letter /P applies only to Grade 3 devices.

/P or /PC = DP26% Chartered

M95128, M95128-W, M95128-R Part numbering

Doc ID 5798 Rev 14 41/45

Table 24. Available M95128x products (package, voltage range, temperature grade)

Package M95128-R

(1.8 V to 5.5 V)

M95128-W

(2.5 V to 5.5 V)

M95128

(4.5 V to 5.5 V)

SO8N (MN) Grade 6 Grade 6

Grade 3(1)

1. Grade 3 products (without ECC) are codified as /P and /PC in Table 23: Ordering information scheme).

Grade 3(1)

UFDFPN8 (MLP8)

2 × 3 mm (MB) Grade 6 - -

TSSOP (DW) Grade 6 Grade 3(1) -

Revision history M95128, M95128-W, M95128-R

42/45 Doc ID 5798 Rev 14

12 Revision history

Table 25. Document revision history

Date Revision Changes

17-Nov-1999 2.1 New -V voltage range added (including the tables for DC characteristics,

AC characteristics, and ordering information).

07-Feb-2000 2.2 New -V voltage range extended to M95256 (including AC characteristics,

and ordering information).

22-Feb-2000 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 1μs to 100ns

15-Mar-2000 2.4 -V voltage range changed to 2.7-3.6V

29-Jan-2001 2.5

Lead Soldering Temperature in the Absolute Maximum Ratings table

amended

Illustrations and Package Mechanical data updated

12-Jun-2001 2.6

Correction to header of Table 12B

TSSOP14 Illustrations and Package Mechanical data updated

Document promoted from Preliminary Data to Full Data Sheet

08-Feb-2002 2.7 Announcement made of planned upgrade to 10 MHz clock for the 5V, –40

to 85°C, range.

09-Aug-2002 2.8 M95128 split off to its own datasheet. Data added for new and forthcoming

products, including availability of the SO8 narrow package.

24-Feb-2003 2.9 Omission of SO8 narrow package mechanical data remedied

26-Jun-2003 2.10 -V voltage range removed

21-Nov-2003 3.0 Table of contents, and Pb-free options added. -S voltage range extended

to -R. VIL(min) improved to –0.45V

17-Mar-2004 4.0

Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering

temperature information clarified for RoHS compliant devices. Device

grade information clarified

21-Oct-2004 5.0

M95128 datasheet merged back in. Product List summary table added.

AEC-Q100-002 compliance. Device Grade information clarified. tHHQX

corrected to tHHQV. 10MHz product becomes standard

M95128, M95128-W, M95128-R Revision history
Doc ID 5798 Rev 14 43/45
13-Apr-2006 6
New M95128 datasheet extracted from the M95128/256 datasheet. Order 
of sections modified. 
ECC (error correction code) and Write cycling paragraph added.
Section 3.8: Supply voltage (VCC) added and information removed below 
Section 4: Operating features.
Power up state removed below Section 6: Delivery state.
Figure 13: SPI modes supported modified and Note 2 added.
ICC1 specified over the whole VCC range and ICC0 added to Ta b l e 1 3 , 
Ta b l e 1 4  and Ta b l e 1 5 .
ICC specified over the whole VCC range in Ta b l e 1 3 . 
tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively.
Figure 16: Hold timing modified.
Process letter and Note 1 added to Table 23: Ordering information 
scheme. 
“AC Characteristics (M95128, Device Grade 6)” Table (for 10MHz 
frequency) removed.
Note 1 removed from Table 19: AC characteristics (M95128-R).
TA added to Table 6: Absolute maximum ratings.
PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and 
M95128-R are no longer under development.
Test conditions changed for VOL and VOH in Section Table 14.: DC 
characteristics (M95128-W, device grade 3).
27-Jun-2006 7
Figure 12: Bus master and memory devices on the SPI bus modified.
SO8N package specifications updated (see Ta b le 2 0  and Figure 18).
V Process specified and A Process replaced by P in Table 23: Ordering 
information scheme.
04-Oct-2007 8
Section 3.8: Supply voltage (VCC), Section 4.3: Data Protection and 
protocol control, Section 5.4: Write Status Register (WRSR), Section 5.6: 
Write to Memory Array (WRITE) and Section 5.6.1: ECC (error correction 
code) and Write cycling updated.
Note removed below Figure 12: Bus master and memory devices on the 
SPI bus, replaced by paragraph.
Test conditions modified for ICC1 and ICC0 in Table 15: DC characteristics 
(M95128-R). AC characteristics values added for fC frequency = 10 MHz in 
Table 16: AC characteristics (M95128, device grade 3).
tW modified in Table 19: AC characteristics (M95128-R).
Section 10: Package mechanical data:
– UFDFPN8 package added 
– Package mechanical inch values calculated from mm and rounded to 4 
decimal digits
Table 24: Available M95128x products (package, voltage range, 
temperature grade) added.
Blank removed below Plating technology, first note removed, process A 
added and process V removed in Table 23: Ordering information scheme.
15-Jan-2008 9
Section 3.7: VSS ground added. Section 3.8.2: Device reset, 
Section 3.8.4: Power-down and Section 5.6.1: ECC (error correction code) 
and Write cycling modified.
VIL and VIH modified in Table 15: DC characteristics (M95128-R).
Table 24: Available M95128x products (package, voltage range, 
temperature grade) updated.
Table 25. Document revision history (continued)
Date Revision Changes

Revision history M95128, M95128-W, M95128-R
44/45 Doc ID 5798 Rev 14
11-Jul-2008 10
M95128, device grade 3 devices is now offered at 10 MHz frequency.
Section 3.8: Supply voltage (VCC) on page 10 and Section 5.4: Write 
Status Register (WRSR) on page 18 updated.
Table 15: DC characteristics (M95128-R) on page 30 modified.
tCH and tCL modified in Table 16: AC characteristics (M95128, device 
grade 3) on page 31.
Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial 
output timing modified.
Process A removed from Table 23: Ordering information scheme.
Small text changes.
17-Feb-2009 11
Section 3.8: Supply voltage (VCC) and Section 5.4: Write Status Register 
(WRSR) updated.
Note added to Section 5.6: Write to Memory Array (WRITE).
ICC modified in Table 12: DC characteristics (M95128, device grade 3).
VRES added to DC characteristics tables 12, 13, 14 and 15.
Note added to Table 19: AC characteristics (M95128-R).
Note added below Figure : .
Small text changes.
12-Jan-2010 12
Section 5.6.1: ECC (error correction code) and write cycling modified 
(applies to all devices).
TLEAD, IOL and IOH added to Table 6: Absolute maximum ratings.
Note added to Table 15: DC characteristics (M95128-R).
Process modified in Table 23: Ordering information scheme.
All packages are ECOPACK2 compliant.
02-Mar-2010 13
Section 5.6.1: ECC (error correction code) and write cycling and Table 24: 
Available M95128x products (package, voltage range, temperature grade) 
updated.
04-Jan-2012 14 Updated UFDFPN8 package data.
Table 25. Document revision history (continued)
Date Revision Changes

M95128, M95128-W, M95128-R

Doc ID 5798 Rev 14 45/45

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