Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller SS SSS sess DESCRIPTION The Philips 8031AH/8051AH is a high-performance microcontroller fabricated with Philips high-density highly reliable +5V, Gepletion-load, N-channel, silicon-gate, N500 MOS process technology. It provides the hardware features, architectural enhancements and instructions that are necessary to make it a powerful and cost-effective controller for applications requiring up to 64k bytes of program memory and/or up to 64k bytes of data storage. The 8051AH contains a 4k x 8 read-only program memory, a 128 x 8 read-only data memory, 32 |/O lines, two 16-bit counterAimers, a five-source, two-priority level nested interrupt Structure, a serial /O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock Circuits. The 8031 AH is identical, except that it lacks the program memory. For systems that require extra Capability, the 8051AH can be expanded using standard TTL compatible memories and byte oriented peripheral controllers. The 8051AH microcontroller, like its 8048 predecessor, is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12MHz crystal, 58% of the instructions execute in 1 HS, 40% in 2us and multiply and divide require only 4us. LOGIC SYMBOL FEATURES Reduced supply current 4k x 8 ROM (8051AH) @ 128 x 8 RAM Four 8-bit ports, 32 I/O lines Two 16-bit timer/event counters High-performance full-duplex serial channel External memory expandable to 128k Boolean processor Industry standard 8051 architecture: ~ Non-paged jumps Direct addressing Four 8-register banks ~ Stack depth up to 128-bytes Multiply, divide, subtract, compare Most instructions execute in ips 4s multiply and divide 8031AH/8051AH PIN CONFIGURATIONS P1.0f 7] al cl Voc P1.1[2] [39] Po.wADo Pr2[3) [38] Po.1/AD1 P1.s[4) 37| Po.2/AD2 pra[5] [36] Po.a/aD3 P1s[6 [35] PO.a/aDa P1.6[7] [34] Po.s/ADS P17[8) [33] Po.@/ADe rsT[9] [32} PO.7/AD7 [ai] EX [30] ALE [29] PSEN [28] P2.7/A15 27] P2.e/A14 [26] P2.5/A13 25] P2.4/A12 24) P2.QA11 [23] P2.2/A10 [22] P2.1/A9 [21] P2ovas Pin Function Pin Function Pin Function 1 NC 18 INTIP33 30 P2E/Al4 2 Pto 16 TWP3.4 31 P2.7/A15 3 P14 17 T1P3.5 32 4 P12 18 WRP36 33 ALE 5 P13 19 ROP3.7 34 NC 6 Pt.4 20 XTAL2 35 EX 7 PS 21 XTAL1 36 = PO.7/AD7 6 P16 22 Vss 37 ~PO.G/AD6 @ PL7 23 NC 38 PO.S/ADS 10 RST 24 =P2.0/A8 39 PO.4/ADS 11 AxOD/P3.0 25 P2.1/A9 40 PO.YAD3 12 NC 26 P2.2/A10 4'1 PO.2/AD2 13 TxD/P3.1 27 P23/A11 42 ~PO.1/AD1 14 3.2 28 P2Z4/A12 43 PO.Q@/ADO 29 P2S/AI3 44 Voge <_> <> <__. |_ADDRESS AND 5 </ DATABUS <*> . +> E EK PSEN PxO> TxD < > IRTS vy InTT> > & 10> 5 5 ADDRESS BUS a Ti > S WR<e > Fro< _. B December 29, 1992 1257 853-0096 08603"Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller 8031AH/8051AH PART NUMBER SELECTION PHILIPS PHILIPS NORTH AMERICA ROMiess (MARKING NUMBER) ROMiess (ORDER NUMBER) ROM ROMless ROM TEMPERATURE C AND PACKAGE FREQ. MHz DRAWING NUMBER MAF8031AH-2-12P MAF8031A-2 N MAF8051AH-2P SCN8031HACN40 SCN8051HACN40 40 to +85, Plastic Dual In-Line Package 12 0415C MAB8031AH-2-12P MAB8031A-2 N MAB8051AH-2P SCN8031HCCN40 SCN8051HCCN40 0 to +70, Plastic Dual In-Line Package 12 0415C SCN8031HCFN40 SCN8051HCFN40 0 to +70, Plastic Dual In-Line Package 15 0415C SCN8031HAFN40 SCN8051HAFN40 40 to +85, Plastic Dual In-Line Package 15 0415C MAB8031AH-2-12WP MAB8031A-2 A MAB8051AH-2WP SCN8031HCCA44 SCN8051HCCA44 0 to +70, Plastic Leaded Chip Carrier 12 0403G MAF8031 AH-2-12WP MAF8031A-2A MAF8051AH-2WP SCN8031HACA44 SCN8051HACA44 40 to +85, Plastic Leaded Chip Carrier 12 0403G SCN8031HCFA44 SCN8051HCFA44 0 to +70, Plastic Leaded Chip Carrier 15 0403G SCN8031HAFA44 SCN805 1HAFA44 40 to +85, Plastic Leaded Chip Carrier 15 0403G December 29, 1992 1258 Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller 8031AH/8051AH BLOCK DIAGRAM P0.0-PO.7 P2.0-P2.7 ~------------- a | "PORTO PORT 2 | | DRIVERS DRIVERS | Vocl 1 t 4 i | - | Vss| : | RAM ADDR PORT 0 ti] ReaisTeR p> 4 ORAM LATCH taro ROM kK, 44> | Us U Y Y | Zz | | i a ft | B nce STACK ! | REGISTER POINTER i | | agoness K | Ture rw Aeeien ! ! Vv | ! ALU PCON | SCON| TMOD| TCON >] berreR KD | THO | TLO | TH1 | I ah TU | | Psw SBUF! IE Ip INESE- iy | | INTERRUPT, SERIAL MENTER PORT AND TIMER BLOCKS | 4s | | PROGRAM ! COUNTER c= | | PSEN ++] asele TIMING # A ~S] -OPTR | L AND 2 aN v EK controx | E & ft ft | rst Lol z2* ee ! PD PORT 1 PORT 3 | LATCH LATCH | | | | OSCILLATOR it it | | PORT 1 RT | _ DRIVERS Lo _ DRIVERS | TAN TA Ht a ia LL J Ot P1.0-P1.7 P3.0-P3.7 December 29, 1992 1259Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller 8031AH/8051AH PIN DESCRIPTIONS PIN NO. MNEMONIC | DIP Lec | TYPE NAME AND FUNCTION Vss 20 22 1 Ground: OV reference. Voc 40 44 | Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0-0.7 39-32 | 43-36 | VO | Port 0: Port 0 is an open-drain, bidirectional /O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. ; P1.0-P1.7 1-8 2-9 VO | Port 1: Port 1 is an 8-bit bidirectional /O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: 1j,). P2.0-P2.7 21-28 | 24-31 VO | Port 2: Port 2 is an 8-bit bidirectional I/O port with intemal! pull-ups. Port 2 pins that have 1s written to them are pulled high by the intemal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the intemal pull-ups. (See DC Electrical Characteristics: lj_). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong intemal pull-ups when emitting 1s. During accesses to externa! data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0-P3.7 10-17 | 11, YO | Port 3: Port 3 is an 8-bit bidirectional /O port with intemal pull-ups. Port 3 pins that have 1s written 13-19 to them are pulled high by the intemal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: lj_). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 I RxD (P3.0): Serial input port 1 13 Le) TxD (P3.1): Serial output port 12 14 I INTO (P3.2): External interrupt 13 15 I INTT (P3.3): External interrupt 14 16 | TO (P3.4): Timer 0 external input 15 17 ! T1 (P3.5): Timer 1 external input 16 18 O | WR (P3.6): Extemal data memory write strobe 17 19 O | RD (P3.7): External data memory read strobe RST 9 10 t Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to Vgg permits a power-on reset using only an extemal capacitor to Vec. ALE 30 33 VO | Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 32 | Program Store Enable: The read strobe to external program memory. When the device Is executing code from the extemal program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to extemal data memory. is not activated during fetches from internal program memory. EA 31 35 ! External Access Enable: EA must be externally held low to enable the device to fetch code from extemal program memory locations OOOOH to OFFFH. If EA is held high, the device executes from : internal program memory unless the program counter contains an address greater than OFFFH. XTAL1 19 21 ! Crystal 1: Input to the inverting oscillator amplifier. XTAL2 18 20 oO Crystal 2: Output from the inverting oscillator amplifier and input to the internal clock generator circuits. OSCILLATOR To drive the device from an external clock high and low times specified in the data sheet CHARACTERISTICS source, XTAL2 should be driven while XTAL1 must be observed. XTAL1 and XTAL2 are the input and output, is connected to ground. There are no respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. December 29, 1992 requirements on the duty cycle of the external clock signal, because the input to the intemal DESIGN CONSIDERATIONS clock circuitry is through a divide-by-two At power-on, the voltage on Vec and RST flip-flop. However, minimum and maximum pon come up at the same time for a proper start-up. 1260Philips Semiconductors Microcontroller Products . Product specification Single-chip 8-bit microcontroller 8031AH/8051AH ABSOLUTE MAXIMUM RATINGS? 2.3 PARAMETER RATING UNIT Storage temperature range 65 to +150 c Voltage on any other pin to Vss 0.5 to +7.0 Vv Input, output current on any single pin 10 mA Power dissipation 1.0 w a DC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C, Voc = 5V 410%, Vgg = 0V4: TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vit Input low voltage ~0.5 0.8 Vv Vin Input high voltage; except XTAL2, RST 2.0 Vect+0.5 Vv Vint Input high voltage to RST for reset, XTAL2 XTAL1 to Vsg 2.5 Voec+0.5 Vv Vor Output low voltage; ports 1, 2, 36 lo. = 1.6mA 0.45 V Vou Output low voltage; port 0, ALE, PSEN lo = 3.2mA 0.45 Vv Von Output high voltage; ports 1, 2, 3 lon = -80UA 2.4 Vv Vou Output high voltage; port 0, ALE, PSENS lon = -400UA 2.4 Vv Mie Logical 0 input current; ports 1, 2, 3 Vin = 0.45V -500 pA Sida Input high current to RST for reset Vin < Voc -1.5V 500 pA lu Input leakage current; port 0, EA 0.45<Vin<Vec +10 pA Ine Logical 0 input current for XTAL2 XTAL1 = Vgs, Vin = 0.45V 3.2 mA loc Power supply current All outputs disconnected 125 mA and EA = Voc Cio Pin capacitance 10 pF Tamp = 40C to +85C, Voc = SV 10%, Vgs = OV TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vin Input high voltage; except XTAL2, RST 2.1 Voect0.5 Vv Viet Input high voltage to RST and XTAL2 XTAL1I = Vsg 2.6 Vec+0.5 Vv lit Logical 0 input current for XTAL2 XTAL1 = Vgs, Vin = 0.45V ~4.0 mA loc Power supply current All outputs disconnected 135 mA and EA = Voc NOTES: 1. a fF ON Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vgg unless otherwise noted. All voltage measurements are referenced to ground. For testing, all input signals swing between 0.45V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and at output voltages of 0.8V and 2.0V as appropriate. . Voz is derated when the device rapidly discharges extemal capacitance. This AC noise is most pronounced during emission of address data. When using external memory, locate the latch or buffer as close as possible to the device. Emitting Degraded Datum Ports VO Lines Vor (Peak Max) Address P2, PO P1, P3 0.8V Write Data PO P1, p3, ALE 0.8V . CL = 100pF for port 0, ALE and PSEN outputs: C, = 80pF for all other ports. December 29, 1992 1261Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller 8031AH/8051AH AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or 40C to +85C, Voc = 5V 420%, Veg = OV1:2 12MHz CLOCK VARIABLE CLOCK SYMBOL } FIGURE PARAMETER MIN MAX MIN MAX UNIT TAciet Oscillator frequency: Speed Versions SCN8051/31 c 3.5 12 + MHz MAB805 1/31 -2 3.5 12 =? MHz MAF805 1/31 ~2 3.5 12 MHz SCN8051/31 F 3.5 15 MHz tude 1 ALE pulse width 127 2teic_-40 ns taviL 1 Address valid to ALE low 43 tere. 40 ns tax 1 Address hold after ALE low 48 tere. -35 ns tut 1 ALE low to valid instruction in 233 4terci-100 ns tiLPL 1 ALE low to PSEN low 58 teieL-25 ns tpLpH 1 PSEN pulse width 215 Stcrer-35 ns tev 1 PSEN low to valid instruction in 125 3teLcL-125 ns texix 1 input instruction hold after PSEN 0 0 ns texiz 1 Input instruction float after PSEN 63 terci-20 ns taviv 1 Address to valid instruction in 302 Sterer-115 ns tpLaz 1 PSEN tow to address float 20 20 ns tpxay 1 PSEN to address valid 75 tercr -8 ns Data Memory tRLRH 2,3 RD pulse width 400 6teicL-100 ns twuwH 2,3 WR pulse width 400 6teLcL-100 ns taLov 2,3 RD low to valid data in 252 Steric. -165 ns taHDx 2,3 Data hold after RD 0 0 ns taHpz 2,3 Data float after AD 97 2teier-70 ns tLipv 2,3 ALE low to valid data in 517 BteLoL-150 ns tavov 2,3 Address to valid data in 585 Sterci-165 ns tuwe 2,3 | ALE low to RD or WR low 200 300 3teicL-50 Stoic. +50 ns tavwe 2,3 Address valid to WR low or RD low 203 4toic_-130 ns tavwx 2,3 Data valid to WR transition 23 terc_-60 ns tovwu 2,3 Data valid to WR high 433 Ttore, -150 ns twHox .+2,3 Data hold after WR 33 tere.-50 ns taLaz 2,3 RD low to address float 20 20 ns tWHLH 2,3. | RD or WRhigh to ALE high 43 123 toic.40 tocL +40 ns External Clock toHcox 5 High time 20 20 ns toicx 5 Low time 20 20 ns toLcH 5 Rise time 20 20 ns toHeL 5 Fall time 20 20 ns NOTES: 1, Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. December 29, 1992 1262Philips Semiconductors Microcontroller Products Single-chip 8-bit microcontroller Product specification 8031AH/8051AH EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always t (= time). The other characters, depending on their positions, indicate the name of a signal or the logical Status of that signal. The designations are: A Address C - Clock ~ Input data ~ Logic level high r ~ Instruction (program memory contents) L = Logic level low, or ALE P - PSEN Q - Output data R - FD signal t - Time V - Valid W- WR signal X ~- No longer a valid logic level Z Float Examples: tayviL= Time for address valid to ALE low. tup_= Time for ALE low to PSEN Iow. PORT 2 }# taviv PN a L INSTR IN = XX Figure 1. External Program Memory Read Cycle AS-A15 VK tWHLH tupv tuiw, ><_____ talky -> . aN y * NA tavi [> . tax [* tarpvy > taHpz tao >| taLaz RHDX PORT 0 A0-A7 Jy oN FROM RIOR DPL {DATAIN A0-A7 FROM PCL INSTR IN }+ tayvw_ > tavov > Y _ P2.0-P2.7 OR A8-A15 FROM DPH KX A0-A15 FROM PCH Figure 2. External Data Memory Read Cycle December 29, 1992 1263Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller 8031AH/8051AH YS NO f[ ~~ = NY e th yy, Pe- twuwH NY tuLax tev. | tavwx | [= twrax < favwH > / nT v N PORTO _ > | FROM RIOR Vy DATA OUT A0-A7 FROM PCL INSTR IN <t_ taywL _> Y PORT 2 >- P2.0-P2.7 OR AB-A15 FROM DPH XK A0-A15 FROM PCH Figure 3. External Data Memory Write Cycle INSTRUCTION | 0 | 1 | 2 | 3 | 4 | 5 | 6 | ? | 8 | cLo%K LILI LI LILI LI LI LI toven al | NK KKK ~_/ WRITE TO SBUF >| ' | XHDX txnpv r act qT y i D D INPUT DATA + OUTPUT DATA CLEAR Ri Figure 4. Shift Register Mode Timing December 29, 1992 1264Philips Semiconductors Microcontroller Products Single-chip 8-bit microcontroller Product specification 8031AH/8051AH Figure 5. External Clock Drive 24v 2.0V 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V fora logic "1" and 0.45V for a logic 0. Timing measurements are made at 2.0V min for a logic '1" and 0.8V for a logic '0. Figure 6. AC Testing Input/Output 2.4 0.45V NOTE: <+__ FLoaT | 2.0V 2.0V 2.4V 0.8V 0.8V 0.45V For timing purposes, the float state is defined as the point at which @ PO pin sinks 2.4mA or sources 400A at the voltage test levels. Figure 7. Float Waveform Vv fl Voc Veco Voc | EX (NC) -| XTAL2 g CLOCK SIGNAL -m4 XTAL1 re Figure 8. Ico Test Condition, Active Mode All other pins are disconnected Voc-05 ---- 0.48V Figure 9. Clock Signal Waveform for icc Tests In Active and Idle Modes tercu = toner = Sns December 29, 1992 1265