JANUARY 2010
DSC-5279/05
1
©2010 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆3.3V I/O
◆◆
◆◆
◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP)
Description
The IDT71V3576/78 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V3578.
A
0
-A
17
A d dre s s Inp uts Inp ut S ync hro no us
CE Chip Enable Inp ut Synchrono us
CS
0
, CS
1
Chip Sele cts Inp ut Synchrono us
OE Outp ut Enab le Input A sy nchro no us
GW Glo b al Wri te Enab le Input Sy nchro no us
BWE Byte Write Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
(1)
Indiv idual Byte Write Se le cts Inp ut Synchrono us
CLK Clock Input N/A
ADV B urs t Ad dress Ad vance Inp ut Synchrono us
ADSC A d d re ss S tatus (Cache Co ntro lle r) Input Sy nchro no us
ADSP A dd re ss Status (Pro ce sso r) Inp ut Synchrono us
LBO Line ar / Inte rle aved B urst Ord e r Input DC
TMS Test Mode Select Input Synchronous
TDI Te st Data Inp ut Inp ut S ync hro no us
TCK Test Clock Input N/A
TDO Te st Data Outp ut Outp ut Sync hro no us
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/O S ync hro no us
V
DD
, V
DDQ
Co re Po wer, I/O Po wer Supp ly N/A
V
SS
Ground Supply N/A
5279 tb l 01
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V3576S/YS
IDT71V3578S/YS
6.42
2
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
17
Address Inputs I N/A Synchro nous Address inputs. The address re gister is triggere d by a combination of the rising edg e
o f CLK and ADSC Low o r ADSP Lo w and CE Lo w.
ADSC Address Status
(Cache Control ler) ILOW
Synchro nous Add re ss Status from Cache Controlle r. ADSC is an ac ti v e LO W inp ut tha t is us e d to l o ad
the address registers with new addresses.
ADSP Address Status
(Processor) ILOW
Synchro nous Address Status from Processor. ADSP is an activ e LOW i np ut that is us e d to lo ad the
address registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance ILOW
Synchronous Address Advance. ADV is an ac ti ve LOW inp ut tha t is u se d to adv anc e the inte rn al
b urst c ounte r, co ntrolling burst acces s after the initial add res s is load ed. When the inp ut is HIGH the
burs t c o unter is no t i nc re m e n te d ; that i s , the re i s no ad d re s s ad v anc e .
BWE B y te Wr ite E na b l e I LOW Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the ris ing
edge of CLK then BWx in p uts are p as s e d to the nex t s tag e i n the c i rc ui t. If BWE is HIGH then the
byte write inputs are blocked and only GW c an i nitiate a write c y c le .
BW
1
-BW
4
Individual Byte
Wr i te Ena ble s ILOW
Synchronous byte write enables. BW
1
co ntrols I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc. Any
active byte write causes all outp uts to b e disabled.
CE Chip Enab le I LOW Synchro no us chip enab le. CE is used with CS
0
and CS
1
to e nab l e the IDT71V 3576/ 78 . CE als o g ate s
ADSP.
CLK Clo c k I N/ A Thi s i s the c l o c k i np u t. A ll tim in g refere n ce s for the d e v i c e are m ad e with re s p ec t to th is i np u t.
CS
0
Chip Selec t 0 I HIGH Synchro no us activ e HIGH chip se lec t. CS
0
is used with CE and CS
1
to e n ab l e th e chip .
CS
1
Chip Selec t 1 I LOW Synchronous activ e LOW chip se lect. CS
1
is used with CE and CS
0
to enab le the c h ip .
GW Glob al Write
Enable ILOW
Synchro nous global write enable. This input will write all four 9-bit data byte s whe n LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Inp ut/ Ou tp ut I/ O N/ A S y nc hro no us d ata input/ o u tp ut (I/ O) p i ns . B o th the d ata inp ut p ath a nd d ata o utp u t p ath are re gi s te red
and trigge re d by the rising edge of CLK.
LBO Li ne ar B urs t Ord e r I LOW Asynchrono us burst o rd er sele ction inp ut. When LBO is HIGH, the interleaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a s tati c input and mu st
not change state while the device is op erating.
OE Output E nab le I L OW As ync hro no us o utput e nabl e . Whe n OE is LOW the data o utput d rivers are enabled on the I/O pins if
the chip is also se le cte d. When OE is HIGH the I/O pins are in a high-impe danc e state .
TM S Tes t M odeS el ect I N / A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal
pullup.
TDI Tes t Data Input I N/ A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has
an inte rnal pullup.
TC K Test Cl oc k I N / A Clo ck inp ut of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO Te s t Da taO utp u t O N /A Se rial output of registe rs placed between TDI and TDO. This output is active depending on the state
of the TAP contro ller.
ZZ Sleep Mode I HIGH Asynchrono us sle ep mo de inp ut. ZZ HIGH will g ate the CLK inte rnally and po we r do wn the
IDT71V3576/78 to its lo we st p ower co nsumption le ve l. Data retention is g uarantee d i n Sl ee p
Mo de .This p in has an inte rnal pull do wn.
V
DD
Power S up ply N/A N/ A 3. 3V c o re p o wer s up p l y.
V
DDQ
Po we r Supp ly N/A N/A 3.3V I/O Sup ply.
V
SS
Ground N/A N/A Ground.
NC No Co n nec t N/ A N/ A NC p i ns are not el e c tri c al l y c o nn e c te d to th e d e vi c e .
5279 tbl 02
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
A
0-
A
16/17
ADDRESS
REGISTER
CLR
A1*
A0*
17/18
2
17/18
A
2
–A
17
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
36/18 36/18
ADSP
ADV
CLK
ADSC
CS
0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BWE
LBO
I/O
0
— I/O
31
I/O
P1
—I/O
P4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
OUTPUT
REGISTER
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
5279 drw 01
ZZ
Powerdown
,
JTAG
(SA Version)
TMS
TDI
TCK
TRST
(Optional)
TDO
6.42
4
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6 . This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
Symbol Rating Comm erci al &
Industrial Unit
V
TERM
(2)
Terminal Vo ltage with
Re s p e ct to GND -0.5 to +4.6 V
V
TERM
(3,6)
Terminal Vo ltage with
Re s p e ct to GND -0.5 to V
DD
V
V
TERM
(4,6)
Terminal Vo ltage with
Re s p e ct to GND -0.5 to V
DD
+0.5 V
V
TERM
(5,6)
Terminal Vo ltage with
Re s p e ct to GND -0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature -0 to +70
o
C
Industrial
Operating Temperature -40 to +85
o
C
T
BIAS
Temperature
Under Bias -55 to + 125
o
C
T
STG
Storage
Temperature -55 to +125
o
C
P
T
Po we r Dissip ation 2.0 W
I
OUT
DC Outp ut Curre nt 50 mA
5279 tbl 03
Grade Temperature
(1)
V
SS
V
DD
V
DDQ
Co mme rc ial 0°C to +70°C 0V 3. 3V ±5% 3.3V±5%
Ind ustrial -40°C to +85°C 0V 3.3V±5% 3.3V±5%
52 79 t b l 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Co re Supp ly Voltage 3. 135 3.3 3.4 65 V
V
DDQ
I/O Supply Voltage 3.135 3.3 3.465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
I nput High Volta ge - Inpu ts 2. 0
____
V
DD
+0.3 V
V
IH
I nput High Volta ge - I/O 2. 0
____
V
DDQ
+0.3
(1)
V
V
IL
I nput Low Voltage -0.3
(2)
____
0.8 V
5279 tbl 06
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 5 pF
C
I/O
I/ O Cap aci tanc e V
OUT
= 3dV 7 pF
5279 tbl 07
NOTES:
1. TA is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
5
Pin Configuration – 128K x 36
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5279 drw 02
V
DD
/NC
(1)
I/O
15
I/O
P3
NC
I/O
P4
A
15
A
16
I/O
P1
NC
I/O
P2
ZZ
(2)
,
6.42
6
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 18
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5279 drw 03
V
DD
/NC
(1)
NC
NC
NC
NC
A
16
A
17
NC
NC
A
10
ZZ
(2)
,
TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
7
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to V SS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5279 drw 06
,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5279 drw 07
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Inp ut Le akag e Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LZZ
|ZZ, LBO and JTAG Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Low Vo ltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Voltag e I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5279 tbl 08
Symbol Parameter Test Conditions
150MHz 133MHz
UnitCom'l Ind Com'l Ind
I
DD
Operating Power Supply
Current Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
295 305 250 260 mA
I
SB1
CMOS Standby Power
Supply Current Devic e Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
30 35 30 35 mA
I
SB2
Clo ck Running Po wer
Supply Current Devic e Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
105 115 100 110 mA
I
ZZ
Full Sleep Mode Supply
Current ZZ > V
HD,
V
DD
= Max. 30 35 30 35 mA
5279 tbl 09
Inp ut P uls e L e ve ls
Inp ut Ris e /Fal l Time s
Inp ut Tim ing Re fe re nc e Le v e ls
Output Timi ng Re fe rence Leve ls
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
52 79 t b l 10
6.42
8
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,3)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation Address
Used
CE CS
0
CS
1
ADSP ADSC ADV GW BWE BWxOE
(2) CLK I/O
Deselected Cycle, Power Down None HXXX LXXXXX -HI-Z
Deselected Cycle, Power Down None L XHL XXXXXX-HI-Z
Deselected Cycle, Power Down None LL XL XXXXXX-HI-Z
Deselected Cycle, Power Down None L XH X LXXXXX -HI-Z
Deselected Cycle, Power Down None LL XX LXXXXX-HI-Z
Re ad Cyc le , Be gin Burst Exte rnal L H L L X X X X X L - D
OUT
Re ad Cyc le , Be gin Burst Exte rnal L H L L X X X X X H - HI-Z
Re ad Cyc le , Be gin Burst Exte rnal L H L H L X H H X L - D
OUT
Re ad Cyc le , Be gin Burst Exte rnal L H L H L X H L H L - D
OUT
Re ad Cyc le , Be gin Burst Exte rnal L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - D
IN
Write Cycle, Begin Burst External L H L H L X L X X X - D
IN
Re ad Cyc le , Co ntinue Burst Ne xt X X X H H L H H X L - D
OUT
Re ad Cyc le , Co ntinue Burst Ne xt X X X H H L H H X H - HI-Z
Re ad Cyc le , Co ntinue Burst Ne xt X X X H H L H X H L - D
OUT
Re ad Cyc le , Co ntinue Burst Ne xt X X X H H L H X H H - HI-Z
Re ad Cyc le , Co ntinue Burst Ne xt H X X X H L H H X L - D
OUT
Re ad Cyc le , Co ntinue Burst Ne xt H X X X H L H H X H - HI-Z
Re ad Cyc le , Co ntinue Burst Ne xt H X X X H L H X H L - D
OUT
Re ad Cyc le , Co ntinue Burst Ne xt H X X X H L H X H H - HI-Z
Write Cyc le, Co ntinue Burst Ne xt X X X H H L H L L X - D
IN
Write Cyc le, Co ntinue Burst Ne xt X X X H H L L X X X - D
IN
Write Cyc le, Co ntinue Burst Ne xt H X X X H L H L L X - D
IN
Write Cyc le, Co ntinue Burst Ne xt H X X X H L L X X X - D
IN
Re ad Cyc le , Sus p end Burs t Curre nt X X X H H H H H X L - D
OUT
Re ad Cyc le , Su sp e nd Burs t Curre nt X X X H H H H H X H - HI-Z
Re ad Cyc le , Sus p end Burs t Curre nt X X X H H H H X H L - D
OUT
Re ad Cyc le , Su sp e nd Burs t Curre nt X X X H H H H X H H - HI-Z
Re ad Cyc le , Sus p end Burs t Curre nt H X X X H H H H X L - D
OUT
Re ad Cyc le , Su sp e nd Burs t Curre nt H X X X H H H H X H - HI-Z
Re ad Cyc le , Sus p end Burs t Curre nt H X X X H H H X H L - D
OUT
Re ad Cyc le , Su sp e nd Burs t Curre nt H X X X H H H X H H - HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X - D
IN
Write Cycle, Suspend Burst CurrentXXXH H HLXXX-D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X - D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X - D
IN
5279 tbl 11
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
9
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table(1, 2)
Asynchronous Truth Table(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V3578.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Byte s L X X X X X
Write all Byte s H L L L L L
Writ e B y te 1
(3)
HLLHHH
Writ e B y te 2
(3)
HLHLHH
Writ e B y te 3
(3)
HLHHLH
Writ e B y te 4
(3)
HLHHHL
5279 tbl 12
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5279 tbl 15
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
5279 tbl 14
Operation
(2)
OE ZZ I/O Status Power
Re ad L L Data Out Active
Read H L High-Z Active
Write X L Hig h-Z – Data In Ac ti ve
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sle ep
5279 tbl 13
6.42
10
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
150MHz 133MHz
Symbol Parameter Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time 6.7
____
7.5
____
ns
t
CH
(1)
Clo ck Hig h Puls e Wid th 2. 6
____
3
____
ns
t
CL
(1)
Clock Low Pulse Width 2.6
____
3
____
ns
Output Parameters
t
CD
Clock Hig h to Val id Data
____
3.8
____
4.2 ns
t
CDC
Clo c k Hig h to Data Chang e 1. 5
____
1.5
____
ns
t
CLZ
(2)
Clo c k Hig h to Outp ut Acti ve 0
____
0
____
ns
t
CHZ
(2)
Clo c k Hi gh to Data Hig h-Z 1. 5 3. 8 1. 5 4. 2 ns
t
OE
Outp ut Enab le Ac ce ss Time
____
3.8
____
4.2 ns
t
OLZ
(2)
Output Enab le Low to Outp ut Active 0
____
0
____
ns
t
OHZ
(2)
Output Enab le Hig h to Output Hig h-Z
____
3.8
____
4.2 ns
Set Up Times
t
SA
Address Setup Time 1.5
____
1.5
____
ns
t
SS
Address Status Setup Time 1.5
____
1.5
____
ns
t
SD
Data In S e tup Time 1. 5
____
1.5
____
ns
t
SW
Write Setup Time 1.5
____
1.5
____
ns
t
SAV
Address Advance Setup Time 1.5
____
1.5
____
ns
t
SC
Chip Enab le/Select Setup Time 1.5
____
1.5
____
ns
Hold T imes
t
HA
Address Hold Time 0.5
____
0.5
____
ns
t
HS
Ad d ress Status Hold Time 0.5
____
0.5
____
ns
t
HD
Data In Ho l d Ti me 0.5
____
0.5
____
ns
t
HW
Write Ho ld Time 0. 5
____
0.5
____
ns
t
HAV
Address Advance Hold Time 0.5
____
0.5
____
ns
t
HC
Chip Enab le/Se lect Hold Time 0.5
____
0.5
____
ns
S leep Mode an d Co nfigurati on Pa rameters
t
ZZPW
ZZ Pulse Width 100
____
100
____
ns
t
ZZR
(3)
ZZ Re c ov e ry Tim e 100
____
100
____
ns
t
CFG
(4)
Config uration Se t-up Time 27
____
30
____
ns
5279 tbl 16
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
11
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Pipelined Read Cycle(1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O3(Ay)O2(Ay)
O2(Ay)
t
CLZ
ADV
CE,CS
1
(Note3)
Pipelined
ReadBurstPipelinedRead
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burstwrapsaround
toitsinitialstate)
O4(Ay)
5279drw08
ADSP
ADVHIGHsuspends
burst
,
6.42
12
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
CLK
ADSP
ADDRESS
GW
ADV
OE
DAT
A
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DAT
A
IN
(2)
t
OE
O1(Az)
O1(Az)
SingleReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
5279drw09
t
CD
,
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
13
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Wa vef orm of Write Cyc le No. 1 - GW Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DAT
A
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
t
HW
GW
t
SW
(Note3)
I2(Az)
BurstWrite
BurstReadBurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVHIGHsuspendsburst)
I1(Ay)
GWisignoredwhenADSPinitiatesacycleandissampledonthenextclockrisingedge
t
SC
5279drw10
,
6.42
14
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa ve form of Write Cyc le No. 2 - Byte Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DAT
A
OUT
OE
t
HC
t
SD
Single
WriteBurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
t
HW
BWE
t
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)I4(Ay)
I3(Ay)
t
SC
BWEisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge
BWxisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge
I3(Az)
O3(Aw)
5279drw11
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
15
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
SingleReadSnoozeMode
tZZPW
5279drw12
O1(Ax)
Ax
(Note4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
16
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW,BWE,BWx
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5279 drw 14
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5279 drw 15
,
6.42
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
17
Ordering Information
Package Information
100-Pin Thin Quad Plastic Flatpack (TQFP)
Information available on the IDT website
6.42
18
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
7/26/99 Updated to new format
9/17/99 Pg. 8 Revised ISB1 and IZZ for speeds 100–200MHz
Pg. 11 Revised tCDC (min.) at 166MHz
Pg. 18 Added 119 BGA package diagram
Pg. 20 Added Datasheet Document History
12/31/99 Pg. 1, 8, 11, 19 Removed 166, 183, and 200MHz speed grade offerings
(see IDT71V35761 and IDT71V35781)
Pg. 1, 4, 8, 11, 19 Added Industrial Temperature range offerings
04/04/00 Pg.18 Added 100TQFP Package Diagram Outline
Pg. 4 Add capacitancce table for the BGA package; Add Industrial temperature to table;
Insert note to Absolute Max Rating and Recommended Operating Temperature tables
Pg. 7 Add note to BGA pin configurations; corrected typo in pinout
06/01/00 Add new package offering, 13 x 15mm fBGA
Pg. 20 Correct BG119 Package Diagram Outline
07/15/00 Pg. 7 Add note reference to BG119 pinout
Pg. 8 Add DNU reference note to BQ165 pinout
Pg. 20 Update BG119 Package Diagram Outline Dimensions
10/25/00 Remove Preliminary Status
Pg. 8 Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
04/22/03 Pg. 4 Updated 165 BGA table information from TBD to 7
06/30/03 Pg. 1,2,3,5-9 Updated datasheet with JTAG information
Pg. 5-8 Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiring NC or connection to Vss.
Pg. 19,20 Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions
Pg. 21-23 Removed old package information from the datasheet
Pg. 24 Updated ordering information with JTAG and Y stepping information. Added information
regarding packages available IDT website.
01/01/04 Pg.21 Added "Restricted hazardous substance device" to ordering information.
01/20/10 Pg.1,2,4,7,8 Combined S and YS datasheet into one datasheet. Deleted JTAG and packages BGA, fBGA.
Pg.19,20,21 Removed "IDT" from orderable part number.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
