SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Features Applications Frequency range from 1 MHz to 110 MHz Printers LVCMOS/LVTTL compatible output Flat panel drivers Standby current as low as 0.4 A PCI Fast resume time of 3 ms (Typ) Microprocessors <30 ps cycle-to-cycle jitter Spread options (contact SiTime for other spread options) * Center spread: 0.50%, 0.25% * Down spread: -1%, -0.5% Standby, output enable, or spread disable mode Industry-standard packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm x mm Outstanding mechanical robustness for portable applications All-silicon device with outstanding reliability of 2 FIT (10x improvement over quartz-based devices), enhancing system mean-time-to-failure (MTBF) Pb-free, RoHS and REACH compliant DC Electrical Characteristics Parameters Output Frequency Range Frequency Tolerance Aging Operating Temperature Range Supply Voltage Current Consumption Standby Current Duty Cycle Rise/Fall Time Output Voltage High Symbol Min. Typ. Max. Unit f 1 - 110 MHz F_tol Ag T_use Vdd Idd I_std DC Tr, Tf VOH -50 - +50 PPM -100 - +100 PPM -1 - 1 PPM Condition Inclusive of: Initial stability, operating temperature, rated power, supply voltage change, load change, shock and vibration Spread Off 1st year at 25C -20 - +70 C Extended Commercial -40 - +85 C Industrial 1.71 1.8 1.89 V 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.97 3.3 3.63 V - 3.7 4.1 mA No load condition, f = 20 MHz, Vdd = 2.5 V, 2.8 V or 3.3 V - 3.2 3.5 mA No load condition, f = 20 MHz, Vdd = 1.8 V - 2.4 4.3 A ST = GND, Vdd = 3.3 V, Output is Weakly Pulled Down - 1.2 2.2 A ST = GND, Vdd = 2.5 or 2.8 V, Output is Weakly Pulled Down - 0.4 0.8 A ST = GND, Vdd = 1.8 V, Output is Weakly Pulled Down 45 - 55 % All Vdds. f <= 70 MHz 40 - 60 % All Vdds. f >70 MHz - 1 2 ns 20% - 80% Vdd=2.5 V, 2.8 V or 3.3 V, 15 pf load - 1.3 2.5 ns 20% - 80% Vdd=1.8 V, 15 pf load 90% - - Vdd IOH = -4 mA (Vdd = 3.3 V) IOH = -3 mA (Vdd = 2.8 V and 2.5 V) IOH = -2 mA (Vdd = 1.8 V) Output Voltage Low - - 10 %Vdd VOL IOL = -4 mA (Vdd = 3.3 V) IOL = -3 mA (Vdd = 2.8 V and 2.5 V) IOL = -2 mA (Vdd = 1.8 V) Output Load Ld - - Input Voltage High VIH 70% Input Voltage Low VIL - Startup Time T_start Resume Time Cycle-to-Cycle Jitter SiTime Corporation Rev. 1.7 15 pF - - Vdd - 30% Vdd Pin 1, OE or ST or SD - - 10 ms Measured from the time Vdd reaches its rated minimum value T_resume - 3.0 3.8 ms Measured from the time ST pin crosses 50% threshold T_cyc - - 26 ps f = 50 MHz, Spread = ON - - 26 ps f = 50 MHz, Spread = OFF 990 Almanor Avenue, Sunnyvale, CA 94085 At maximum frequency and supply voltage. Contact SiTime for higher output load option Pin 1, OE or ST or SD (408) 328-4400 www.sitime.com Revised November 18, 2013 SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Spread Spectrum Modes[1] Center Spread Code Percentage Down Spread B D O Q 0.25% 0.50%[2] -0.5% -1.0%[2] Notes: 1. In both center spread and down spread modes, triangle modulation is employed with a frequency of ~32 kHz. 2. 0.5% and -1.0% are available ONLY for <75 MHz in extended commercial temperature range. Pin Configuration Pin Symbol [3] H or Open : specified frequency output L: output is low (weak pull down). Oscillator stops Standby (ST) 1 ST/OE/SD 2 Top View Functionality Output Enable (OE) H or Open[3]: specified frequency output L: output is high impedance. Spread Disable (SD) H or Open: Spread = ON L: Spread =OFF GND Ground Connect to Ground Clock Output 3 CLK Output 4 VDD Power Supply ST/OE/SD 1 4 VDD GND 2 3 CLK Note: 3. In 1.8 V mode, a resistor of <10 k between OE pin and VDD is recommended. Absolute Maximum Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Min. Max. Unit Storage Temperature Parameters -65 150 C VDD -0.5 4 V Electrostatic Discharge - 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) - 260 C Number of Program Writes - 1 NA Program Retention over -40 to 125C, Process, VDD (0 to 3.65V) - 1,000+ years Thermal Considerations Package Lead Count Center Pad 4 Layer Board[5] 2 Layer Board[4] Junction-to-Case[6] (bottom) Thermal Resistance (C/W) 7050 4 Soldered down 43.6 229 2.6 7050 4 Not soldered down 191 263 2.6 7050 4 No center pad 142 273 29.8 5032 4 No center pad 96.8 199 24 3225 4 No center pad 109 212 27 2520 4 No center pad 117 222 26 Junction-to-Ambient Thermal Resistance (C/W) Notes: 4. Test boards compliant with JESD51-3. 5. Test boards compliant with JESD51-7. 6. Referenced to bottom of case. Rev. 1.7 Page 2 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Environmental Compliance Parameter Condition/Test Method Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensibility Level MSL1 Startup and Resume Timing Diagram 90% Vdd: 2.5/2.8/3.3V parts 95% Vdd: 1.8V parts Vdd Vdd Pin 4 Voltage T_resume T_start CLK Output CLK Output T_resume: Time to resume from ST (ST Mode Only) T_start: Time to start from power-off (ST/OE Mode) Rev. 1.7 ST Voltage 50% Vdd Page 3 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Programmable Drive Strength The SiT9003 includes a programmable drive strength feature to provide a simple, flexible tool to optimize the clock rise/fall time for specific applications. Benefits from the programmable drive strength feature are: * Improves system radiated electromagnetic interference (EMI) by slowing down the clock rise/fall time * Improves the downstream clock receiver's (RX) jitter by decreasing (speeding up) the clock rise/fall time. * Ability to drive large capacitive loads while maintaining full swing with sharp edge rates. For more detailed information about rise/fall time control and drive strength selection, see the SiTime Applications Note section; http://www.sitime.com/support/application-notes. EMI Reduction by Slowing Rise/Fall Time Figure 1 shows the harmonic power reduction as the rise/fall times are increased (slowed down). The rise/fall times are expressed as a ratio of the clock period. For the ratio of 0.05, the signal is very close to a square wave. For the ratio of 0.45, the rise/fall times are very close to near-triangular waveform. These results, for example, show that the 11th clock harmonic can be reduced by 35 dB if the rise/fall edge is increased from 5% of the period to 45% of the period. trise=0.05 trise=0.1 trise=0.15 trise=0.2 10 Harmonic amplitude (dB) 0 -20 The SiT9003 can support up to 60 pF or higher in maximum capacitive loads with up to 3 additional drive strength settings. Refer to the Rise/Tall Time Tables to determine the proper drive strength for the desired combination of output load vs. rise/fall time SiT9003 Drive Strength Selection Tables 1 through 4 define the rise/fall time for a given capacitive load and supply voltage. 1. Select the table that matches the SiT9003 nominal supply voltage (1.8V, 2.5V, 2.8V, 3.3V). 2. Select the capacitive load column that matches the application requirement (15 pF to 60 pF) 3. Under the capacitive load column, select the desired rise/fall times. 4. The left-most column represents the part number code for the corresponding drive strength. 5. Add the drive strength code to the part number for ordering purposes. Calculating Maximum Frequency trise=0.25 trise=0.3 trise=0.35 trise=0.4 trise=0.45 -10 increases. As an example, for a 3.3V SiT9003 device with default drive strength setting, the typical rise/fall time is 1.1ns for 15 pF output load. The typical rise/fall time slows down to 2.9ns when the output load increases to 45 pF. One can choose to speed up the rise/fall time to 1.9ns by then increasing the drive strength setting on the SiT9003. Based on the rise and fall time data given in Tables 1 through 4, the maximum frequency the oscillator can operate with guaranteed full swing of the output voltage over temperature as follows: -30 -40 -50 M a x F re q u e n c y = -60 -70 -80 1 3 5 7 9 11 Harm onic num ber Figure 1. Harmonic EMI reduction as a Function of Slower Rise/Fall Time Jitter Reduction with Faster Rise/Fall Time Power supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to increase rise/fall time (edge rate) of the input clock. Some chipsets would require faster rise/fall time in order to reduce their sensitivity to this type of jitter. The SiT9003 provides up to 3 additional high drive strength settings for very fast rise/fall time. Refer to the Rise/Fall Time Tables to determine the proper drive strength. 1 5 x T rf_ 2 0 /8 0 Where Trf_20/80 is the typical rise/fall time at 20% to 80% Vdd Example 1 Calculate fMAX for the following condition: * Vdd = 3.3V (Table 1) * Capacitive Load: 30 pF * Desired Tr/f time = 1.6ns (rise/fall time part number code = Z) Part number for the above example: SiT9003AIZ14-33EB-105.12345 High Output Load Capability The rise/fall time of the input clock varies as a function of the actual capacitive load the clock drives. At any given drive strength, the rise/fall time becomes slower as the output load Rev. 1.7 Drive strength code is inserted here. Default setting is "-" Page 4 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Rise and Fall Time Tables Table 1. Rise/Fall Times, VDD = 3.3V 10%, T = 40C to 85C Table 3. Rise/Fall Times, VDD = 2.5V 10%, T = 40C to 85C Load (pF) Drive Strength U x or "-": Default Z H Load (pF) Unit 15 30 45 60 Max. ns 2.4 3.5 5.5 6.4 Typ. ns 1.7 2.8 4.3 5.4 Max. ns 2.0 2.5 3.9 4.8 Typ. ns 1.1 2.0 2.9 3.8 Max. ns 1.2 2.0 3.0 3.7 Typ. ns 0.8 1.6 2.2 2.9 Max. ns 0.9 1.7 2.5 3.0 Typ. ns 0.6 1.3 1.9 2.3 Table 2. Rise/Fall Times, VDD = 2.8V 10%, T = 40C to 85C Drive Strength U X x or "-": Default H Unit 15 30 45 60 Max. ns 2.8 4.6 6.8 8.3 Typ. ns 2.1 3.6 5.2 6.4 Max. ns 2.3 3.3 5.0 5.9 Typ. ns 1.4 2.5 3.7 4.7 Max. ns 2.0 2.6 3.4 4.8 Typ. ns 1.1 1.9 2.8 3.6 Max. ns 1.3 2.2 3.3 4.0 Typ. ns 0.9 1.6 2.3 2.9 Table 4. Rise/Fall Times, VDD = 1.8V 5%, T = 40C to 85C Load (pF) Drive Strength U X x or "-": Default H Load (pF) Unit 15 30 45 60 Max. ns 2.5 4.1 6.0 7.3 Typ. ns 2.0 3.2 4.8 5.9 Max. ns 2.2 3.0 4.5 5.4 Typ. ns 1.3 2.2 3.3 4.3 Max. ns 2.0 2.4 3.5 4.3 Typ. ns 1.0 1.7 2.5 3.2 Max. ns 1.2 1.9 2.9 3.6 Typ. ns 0.7 1.5 2.0 2.6 Drive Strength U X Z x or "-": Default Unit 15 30 45 60 Max. ns 4.2 6.8 9.4 12.1 Typ. ns 3.1 5.1 7.3 9.2 Max. ns 3.2 4.9 6.9 8.7 Typ. ns 2.3 3.7 5.3 6.5 Max. ns 2.7 3.9 5.5 6.7 Typ. ns 1.7 2.9 4.2 5.2 Max. ns 2.5 3.3 4.6 5.7 Typ. ns 1.4 2.4 3.4 4.3 Note: 7. All rise/fall times are measured for the thresholds of 20% to 80% of VDD. Rev. 1.7 Page 5 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Dimensions and Patterns Package Size - Dimensions (Unit: mm)[8] Recommended Land Pattern (Unit: mm)[9] 2.5 x 2.0 x 0.75 mm 1.9 2.5 0.05 #3 #3 1.5 #2 #2 1.0 0.5 YXXXX #1 #4 1.1 2.0 0.05 #4 1.00 #1 0.75 0.05 0.75 1.1 3.2 x 2.5 x 0.75 mm 3.2 0.05 #3 #4 0.7 1.9 0.9 #2 #1 0.9 0.75 0.05 #2 1.2 YXXXX #1 2.2 2.1 #3 2.5 0.05 #4 1.4 5.0 x 3.2 x 0.75 mm 2.54 5.0 0.05 #2 #1 2.2 1.6 #2 0.75 0.05 #1 #4 1.1 YXXXX #3 0.8 #3 3.2 0.05 #4 2.39 1.15 1.5 7.0 x 5.0 x 0.90 mm 5.08 3.81 2.6 5.08 0.90 0.10 Rev. 1.7 2.0 1.1 YXXXX 5.0 0.05 7.0 0.05 1.4 2.2 Page 6 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Dimensions and Patterns Package Size - Dimensions (Unit: mm)[8] Recommended Land Pattern (Unit: mm)[9] 7.0 x 5.0 x 0.90 mm (with Center-Pad) 5.08 2.0 3.81 YXXXX 0.900.10 Do not Connect the center pad or Connect it to Device's GND 2.2 Notes: 8. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of "Y" will depend on the assembly location of the device. 9. A capacitor of value 0.1 F between Vdd and GND is required. Rev. 1.7 Page 7 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Ordering Information The Part No. Guide is for reference only. To customize and build an exact part number, use the SiTime Part Number Generator. SiT9003AC -14-18EB-66. 6 6 6 0 0 T Packaging "T" and "Y" ordering codes for appropriate T&R. Please refer to the table below. Leave Blank for Bulk Part Family "SiT9003" Revision Letter "A" is the revision Frequency 1.00000 to 110.00000 MHz Temperature Range "C" Commercial, -20 to 70C "I" Industrial, -40 to 85C Spread Spectrum Percentage "B" for 0.25% "D" for 0.50% "O" for -0.50% "Q" for -1.0% Output Drive Strength "-" Default (datasheet limits) See "Drive Strength Settings" "U" "X" "Z" "H" Feature Pin "E" for Output Enable "S" for Standby "D" for Spread Disable Package Size "1" 2.5 x 2.0 mm "2" 3.2 x 2.5 mm "3" 5.0 x 3.2 mm "4" 7.0 x 5.0 mm (With Center Pad) "8" 7.0 x 5.0 mm (Without Center Pad) Supply Voltage "18" "25" "28" "33" for for for for 1.8V 2.5V 2.8V 3.3V Frequency Stability "3" for 50 PPM "4" for 100 PPM Available Spread Options vs. Temperature and Frequency Temperature Range Spread Percentage C = -20 to 70C I = -40 to 85C B = 0.25% 1-110 MHz D = 0.50% 1-75 MHz - O = -0.50% 1-110 MHz Q = -1.0% 1-75 MHz - Ordering Codes for Supported Tape & Reel Packing Method Device Size 12 mm T&R (3ku) 12 mm T&R (1ku) 16 mm T&R (3ku) 16 mm T&R (1ku) 2.5 x 2.0 mm T Y - - 3.2 x 2.5 mm T Y - - 5.0 x 3.2 mm T Y - - 7.0 x 5.0 mm - - T Y Rev. 1.7 Page 8 of 9 www.sitime.com SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Revision History Version Release Date 1.62 8/20/13 Added drive strength settings Change Summary 1.7 11/18/13 Revised rise and fall time tables, added 7050 package diagram with center pad, add thermal considerations. (c) SiTime Corporation 2013. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress. 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CRITICAL USE EXCLUSION POLICY BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE. SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. Rev. 1.7 Page 9 of 9 www.sitime.com