A3PN250-1VQ100 - Actel Corporation

January 2010 I

ProASIC®3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)†

•FlashLock

® to Secure FPGA Contents

Low Power

• Low-Power ProASIC3 nano Products

• 1.5 V Core Voltage for Low Power

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate† and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†

• True Dual-Port SRAM (except ×18 organization)†

Enhanced Commercial Temperature Range

• –20°C to +70°C

† A3PN030 and smaller devices do not support this feature.

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices A3PN010 A3PN015 A3PN020 A3PN030 1A3PN060 A3PN125 A3PN250

System Gates 10 k 15 k 20 k 30 k 60 k 125 k 250 k

Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048

VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144

RAM kbits (1,024 bits)2– – – – 18 36 36

4,608-Bit Blocks2– – – – 488

FlashROM Bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k

Secure (AES) ISP2– – – – Yes Yes Yes

Integrated PLL in CCCs2– – – – 111

VersaNet Globals 4 4 4 6 18 18 18

I/O Banks 2 3 3 2 224

Maximum User I/Os (packaged device) 34 49 49 77 71 71 68

Maximum User I/Os (Known Good Die) 34 – 52 83 717168

Package Pins

QFN

VQFP

QN48 QN68 QN68 QN48, QN68

VQ100 VQ100 VQ100 VQ100

Notes:

1. A3PN030 is available in the Z feature grade only.

2. A3PN030 and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E handbooks.

Advance v0.6

ProASIC3 nano Flash FPGAs

II Advance v0.6

I/Os Per Package

ProASIC3 nano Devices A3PN010 A3PN015 A3PN020 A3PN030 1A3PN060 A3PN125 A3PN250

Known Good Die 34 – 52 83 71 71 68

QN48 34 34

QN68 49 49 49

VQ100 77 71 71 68

Notes:

1. A3PN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices.

Refer to "ProASIC3 nano Ordering Information" on page III.

2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 Handbook to ensure

compliance with design and board migration requirements.

3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of

the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant

versions. All other packages are RoHS-compliant only.

Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions

Packages QN48 QN68 VQ100

Length × Width (mm\mm) 6 x 6 8 x 8 14 x 14

Nominal Area (mm2)36 64 196

Pitch (mm) 0.4 0.4 0.5

Height (mm) 0.90 0.90 1.20

ProASIC3 nano Flash FPGAs

Advance v0.6 III

ProASIC3 nano Ordering Information

Device Marking

Actel normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some

of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited.

Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages,

a subset of the device marking will be used that includes the required legal information and as much of the part number as

allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the

applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples.

Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of

Schmitt trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt

trigger input. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not

marked on the device.

A3PN010 = 10,000 System Gates

A3PN015 = 15,000 System Gates

A3PN020 = 20,000 System Gates

A3PN030 = 30,000 System Gates

A3PN060 = 60,000 System Gates

A3PN125 = 125,000 System Gates

A3PN250 = 250,000 System Gates

Speed Grade

Blank = Standard

Feature Grade

Z = nano devices without enhanced features

A3PN250 Z 1 VQ

Part Number

ProASIC3 nano Devices

Package Type

VQ =Very Thin Quad Flat Pack (0.5 mm pitch)

DIELOT =Known Good Die

QN =Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)

100 I

Package Lead Count

Lead-Free Packaging

Application (Temperature Range)

Blank = Commercial (–20°C to +70°C Ambient Temperature)

I= Industrial (–40°C to +85°C Ambient Temperature)

Blank = Standard Packaging

G= RoHS-Compliant Packaging

PP = Pre-Production

ES=Engineering Sample (Room Temperature Only)

1 = 15% Faster than Standard

2 = 25% Faster than Standard

ProASIC3 nano Flash FPGAs

IV Advance v0.6

Figure 1 shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the

device/package combination ordered.

ProASIC3 nano Product Available in the Z Feature Grade

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.

Figure 1 • Example of Device Marking for Small Form Factor Packages

Devices A3PN030 A3PN060 A3PN125 A3PN250

Packages QN48 – – –

QN68 – – –

VQ100 VQ100 VQ100 VQ100

ProASIC3 nano Devices A3PN010 A3PN015 A3PN020 A3PN030 A3PN060 A3PN125 A3PN250

QN48 C, I – – C, I – – –

QN68 – C, I C, I C, I – – –

VQ100 – – – C, I C, I C, I C, I

Notes:

1. C = Commercial temperature range: –20°C to 70°C ambient temperature

2. I = Industrial temperature range: –40°C to 85°C ambient temperature

Temperature Grade Std.

C1✓

I2✓

Notes:

1. C = Commercial temperature range: –20°C to 70°C ambient temperature.

2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

ACTELXXX

AGL030YWW

UCG81XXXX

XXXXXXXX

Country of Origin

Date Code

Customer Mark

(if applicable)

Device Name

(six characters)

Package

Wafer Lot #

Advance v0.6 1-1

1 – ProASIC3 nano Device Overview

General Description

ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3

nano devices the advantage of being a secure, low-power, single-chip solution that is live at power-

up (LAPU). ProASIC3 nano devices are reprogrammable and offer time-to-market benefits at an

ASIC-level unit cost. These features enable designers to create high-density systems using existing

ASIC or FPGA design flows and tools.

ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as

well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and

smaller devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system

gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features

and packages for greater customer value in high volume consumer, portable, and battery-backed

markets. Added features include smaller footprint packages designed with two-layer PCBs in mind,

low power, hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-

sensitive applications.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be live at power-

up; no external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3

nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes

the ProASIC3 nano device a cost-effective ASIC replacement solution, especially for applications in

the consumer, networking/communications, computing, and avionics markets.

With a variety of devices under $1, Actel ProASIC3 nano FPGAs enable cost-effective

implementation of programmable logic and quick time to market.

Security

Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3 nano devices incorporate

FlashLock, which provides a unique combination of reprogrammability and design security without

external overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to secure

programmed intellectual property and configuration data. In addition, all FlashROM data in

ProASIC3 nano devices can be encrypted prior to loading, using the industry-leading AES-128

(FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National

Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3

nano devices have a built-in AES decryption engine and a flash-based AES key that make them the

most comprehensive programmable logic device security solution available today. ProASIC3 nano

devices with AES-based security allow for secure, remote field updates over public networks such as

the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system

cloners, and IP thieves. The contents of a programmed ProASIC3 nano device cannot be read back,

although secure design verification is possible.

ProASIC3 nano Device Overview

1-2 Advance v0.6

Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have

been used to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and

AES security, are unique in being highly resistant to both invasive and noninvasive attacks. Your

valuable IP is protected and secure, making remote ISP possible. A ProASIC3 nano device provides

the most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

ProASIC3 nano FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

Actel flash-based ProASIC3 nano devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based ProASIC3 nano devices greatly simplifies total

system design and reduces total system cost, often eliminating the need for CPLDs and clock

generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in

system power will not corrupt the ProASIC3 nano device's flash configuration, and unlike SRAM-

based FPGAs, the device will not have to be reloaded when system power is restored. This enables

the reduction or complete removal of the configuration PROM, expensive voltage monitor,

brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 nano

devices simplify total system design and reduce cost and design risk while increasing system

reliability and improving system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano

flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano

FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable

(or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by

using error detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an

ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited

power-on current surge and no high-current transition period, both of which occur on many

FPGAs.

ProASIC3 nano devices also have low dynamic power consumption to further maximize power

savings.

ProASIC3 nano Device Overview

Advance v0.6 1-3

Advanced Flash Technology

ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through

an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine

granularity, enhanced flexible routing resources, and abundant flash switches allows for very high

logic utilization without compromising device routability or performance. Logic functions within

the device are interconnected through a four-level routing hierarchy.

Advanced Architecture

The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell

ASICs. The ProASIC3 nano device consists of five distinct and programmable architectural features

(Figure 1-3 to Figure 1-4 on page 1-5):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Advanced I/O structure

Note: *Bank 0 for the A3PN030 device

Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM

(A3PN010 and A3PN030)

VersaTile

I/Os

User Nonvolatile FlashROM Charge Pumps

Bank 1*

Bank 1

Bank 0

Bank 1

CCC-GL

ProASIC3 nano Device Overview

1-4 Advance v0.6

Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and A3PN020)

Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125)

VersaTile

I/Os

User Nonvolatile FlashROM Charge Pumps

Bank 1

Bank 2

Bank 0

Bank 1

CCC-GL

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 1Bank 1

Bank 0Bank 0

Bank 1

ProASIC3 nano Device Overview

Advance v0.6 1-5

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the ProASIC3 nano core tile as either a three-input

lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC3 family of third-generation

architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of ProASIC3 nano devices via an IEEE 1532 JTAG interface.

VersaTiles

The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The ProASIC3 nano VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-5 for VersaTile configurations.

Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250)

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

VersaTile

CCC

I/Os

ISP AES

Decryption

User Nonvolatile

FlashROM Charge Pumps

Bank 0

Bank 3Bank 3

Bank 1Bank 1

Bank 2

Figure 1-5 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3 nano Device Overview

1-6 Advance v0.6

User Nonvolatile FlashROM

Actel ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The

FlashROM can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface.

The core can be individually programmed (erased and written), and on-chip AES decryption can be

used selectively to securely load data over public networks (except in the A3PN030 and smaller

devices), as in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel ProASIC3 nano development software solutions, Libero® Integrated Design Environment

(IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation

of sequential programming files for applications requiring a unique serial number in each part.

Another feature enables the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks

along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size.

Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual

blocks have independent read and write ports that can be configured with different bit widths on

each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The

embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using

the UJTAG macro (except in A3PN030 and smaller devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures

provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and

A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices

use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any

PLLs or programmable delays.

For devices using the six CCC block architecture, these six CCC blocks are located at the four corners

and the centers of the east and west sides.

ProASIC3 nano Device Overview

Advance v0.6 1-7

All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay

operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the

FPGA core or from dedicated connections to the CCC block, which are located near the CCC.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis (for PLL only)

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration (for PLL only).

• Output duty cycle = 50% ± 1.5% or better (for PLL only)

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used (for PLL only)

• Maximum acquisition time = 300 µs (for PLL only)

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL

only)

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC) (for PLL only)

Global Clocking

ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the

CCC and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high fanout nets.

I/Os with Advanced I/O Standards

ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V,

2.5 V, and 3.3 V).

The I/Os are organized into banks, with two, three, or four banks per device. The configuration of

these banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of various single-data-rate applications for all versions of nano devices and

double-data-rate applications for the A3PN060, A3PN125, and A3PN250 devices.

ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support

cold-sparing and Schmitt trigger.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of

a card in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data

undisturbed when the system is powered up, while the component itself is powered down, or

when power supplies are floating.

ProASIC3 nano Device Overview

1-8 Advance v0.6

Wide Range I/O Support

Actel nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the

JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of

2.7 V to 3.6 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components

from the board or move to less costly components with greater tolerances. Wide range eases I/O

bank management and provides enhanced protection from system voltage spikes, while providing

the flexibility to easily run custom voltage applications.

Part Number and Revision Date

Part Number 51700111-001-5

Revised January 2010

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (Advance v0.6) Page

Advance v0.5

(August 2009)

The note for A3PN030 in the "ProASIC3 nano Devices" table was revised. It states

A3PN030 is available in the Z feature grade only.

Advance v0.4

(January 2009)

All references to speed grade –F were removed from this document. N/A

The"I/Os with Advanced I/O Standards" section was revised to add definitions of

hot-swap and cold-sparing.

1-7

Advance v0.3

(November 2008)

Table 1 · ProASIC3 nano Devices was revised to change the maximum user I/Os for

A3PN020 and A3PN030. The following table note was removed: "Six chip (main)

and three quadrant global networks are available for A3PN060 and above."

The QN100 package was removed for all devices. N/A

The "Device Marking" section is new. III

Advance v0.2

(October 2008)

The A3PN030 device was added to product tables and replaces A3P030 entries

that were formerly in the tables.

I to IV

The "Wide Range I/O Support" section is new. 1-8

Advance v0.1

(October 2008)

The "I/Os Per Package" table was updated to add the following information to

table note 4: "For nano devices, the VQ100 package is offered in both leaded and

RoHS-compliant versions. All other packages are RoHS-compliant only."

The "ProASIC3 nano Product Available in the Z Feature Grade" section was

updated to remove QN100 for A3PN250.

The "General Description" section was updated to give correct information

about number of gates and dual-port RAM for ProASIC3 nano devices.

1-1

The device architecture figures, Figure 1-3 · ProASIC3 nano Device Architecture

Overview with Two I/O Banks (A3PN060 and A3PN125) through

Figure1-4·ProASIC3 nano Device Architecture Overview with Four I/O Banks

(A3PN250), were revised. Figure 1-1 · ProASIC3 Device Architecture Overview

with Two I/O Banks and No RAM (A3PN010 and A3PN030) is new.

1-3

through

1-5

The "PLL and CCC" section was revised to include information about CCC-GLs in

A3PN020 and smaller devices.

1-6

ProASIC3 nano Device Overview

Advance v0.6 1-9

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

Advance v0.2 2-1

2 – ProASIC3 nano DC and Switching

Characteristics

General Specifications

The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-

sparing, and hot-swap I/O capability. Refer to the ordering information in the ProASIC3 nano

Product Brief for more information.

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V V

TSTG 1Storage temperature –65 to +150 °C

TJ1Junction temperature +125 °C

Notes:

1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

2. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

ProASIC3 nano DC and Switching Characteristics

2-2 Advance v0.2

Table 2-2 • Recommended Operating Conditions 1, 2

Symbol Parameter

Extended

Commercial Industrial Units

TAAmbient temperature –20 to +70 2–40 to +85 2°C

TJJunction temperature –20 to +85 –40 to +100 °C

VCC 31.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.425 to 3.6 1.425 to 3.6 V

VPUMP 4Programming voltage Programming Mode 0 to 3.45 0 to 3.45 V

Operation 40 to 3.6 0 to 3.6 V

VCCPLL 5Analog power supply

(PLL)

1.5 V DC core supply voltage 31.425 to 1.575 1.425 to 1.575 V

VCCI and VMV 71.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

3.3 V Wide Range supply voltage 62.7 to 3.6 2.7 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-14 on page 2-15. VMV and VCCI should be at the same voltage within a

given I/O bank.

4. VPUMP can be left floating during operation (not programming mode).

5. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.

6. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

7. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating

Junction Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout

activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4

for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle 2Maximum Overshoot/

Undershoot 2

2.7 V or less 10%1.4 V

5%1.49 V

3 V 10%1.1 V

5%1.19 V

3.3 V 10%0.79 V

5%0.88 V

3.6 V 10%0.45 V

5%0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

ProASIC3 nano DC and Switching Characteristics

2-4 Advance v0.2

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-5

Thermal Characteristics

Introduction

The temperature variable in the Actel Designer software refers to the junction temperature, not

the ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute

maximum junction temperature is 100°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Temperature and Voltage Derating Factors

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 100°C70°C–

20.5°C/W

------------------------------------ 1 . 4 6 3 W

===

Table 2-5 • Package Thermal Resistivities

Package Type Device Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Quad Flat No Lead (QFN) All devices 48 TBD TBD TBD TBD C/W

68 TBD TBD TBD TBD C/W

100 TBD TBD TBD TBD C/W

Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.425 V)

Array Voltage VCC (V)

Junction Temperature (°C)

–40°C –20°C 0°C 25°C 70°C 85°C 110°C

1.425 0.968 0.973 0.979 0.991 1.000 1.006 1.013

1.500 0.888 0.894 0.899 0.910 0.919 0.924 0.930

1.575 0.836 0.841 0.845 0.856 0.864 0.870 0.875

ProASIC3 nano DC and Switching Characteristics

2-6 Advance v0.2

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 2-7 • Quiescent Supply Current Characteristics

A3PN010 A3PN015 A3PN020 A3PN060 A3PN125 A3PN250

Typical (25°C) 1 mA 1 mA 1 mA 2 mA 2 mA 3 mA

Max. (Commercial) 5 mA 5 mA 5 mA 10 mA 10 mA 20 mA

Max. (Industrial) 8 mA 8 mA 8 mA 15 mA 15 mA 30 mA

Notes:

1. IDD Includes VCC, VPUMP, and VCCI, currents. Values do not include I/O static contribution, which

is shown in Table 2-9.

2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD

and higher I/O leakage.

Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

VCCI (V)

Dynamic Power

PAC9 (µW/MHz)*

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.26

3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.95

2.5 V LVCMOS 2.5 4.59

2.5 V LVCMOS – Schmitt Trigger 2.5 6.01

1.8 V LVCMOS 1.8 1.61

1.8 V LVCMOS – Schmitt Trigger 1.8 1.70

1.5 V LVCMOS (JESD8-11) 1.5 0.96

1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.90

Note: *PAC9 is the total dynamic power measured on VCCI.

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

CLOAD (pF) 2VCCI (V)

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 162.43

2.5 V LVCMOS 10 2.5 92.49

1.8 V LVCMOS 10 1.8 47.48

1.5 V LVCMOS (JESD8-11) 10 1.5 32.75

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. Values are for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 have a

default loading of 35 pF.

3. PAC10 is the total dynamic power measured on VCCI.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-7

Power Consumption of Various Internal Resources

Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices

Parameter Definition

Device Specific Dynamic Contributions

(µW/MHz)

A3PN250

A3PN125

A3PN060

A3PN020

A3PN015

A3PN010

PAC1 Clock contribution of a Global Rib 11.03 11.03 9.3 TBD TBD TBD

PAC2 Clock contribution of a Global Spine 1.58 0.81 0.81 TBD TBD TBD

PAC3 Clock contribution of a VersaTile row 0.81

PAC4 Clock contribution of a VersaTile used as a

sequential module

0.12

PAC5 First contribution of a VersaTile used as a

sequential module

0.07

PAC6 Second contribution of a VersaTile used as a

sequential module

0.29

PAC7 Contribution of a VersaTile used as a

combinatorial Module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin

(standard-dependent)

See Table 2-8 on page 2-6.

PAC10 Contribution of an I/O output pin

(standard-dependent)

See Table 2-9 on page 2-6.

PAC11 Average contribution of a RAM block during a

read operation

25.00 N/A

PAC12 Average contribution of a RAM block during a

write operation

30.00 N/A

PAC13 Dynamic contribution for PLL 2.60 N/A

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power

spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE) software.

Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices

Parameter Definition

Device Specific Static Power (mW)

A3PN250

A3PN125

A3PN060

A3PN020

A3PN015

A3PN010

PDC1 Array static power in Active mode See Table 2-7 on page 2-6.

PDC4 Static PLL contribution 12.55 N/A

PDC5 Bank quiescent power (VCCI-dependent) See Table 2-7 on page 2-6.

Notes:

1. Minimum contribution of the PLL when running at lowest frequency.

2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power

spreadsheet calculator or SmartPower tool in Libero IDE.

ProASIC3 nano DC and Switching Characteristics

2-8 Advance v0.2

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on

page 2-10.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-13 on page 2-10.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-13 on page 2-10. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in

Table 2-12 on page 2-10.

NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-12

on page 2-10.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-10.

FCLK is the global clock signal frequency.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-9

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-10.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-10.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-10.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-10.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-10.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on

page 2-10.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 *FCLKOUT

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated

by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include

each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL

contribution.

ProASIC3 nano DC and Switching Characteristics

2-10 Advance v0.2

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at

half of the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-11

User I/O Characteristics

Timing Model

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case

VCC = 1.425 V, with Default Loading at 10 pF

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVCMOS 2.5V Output Drive

Strength = 8 mA High Slew Rate

Input LVCMOS 2.5 V

LVCMOS 1.5 V

LVTTL 3.3 V Output drive

strength = 8 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTL Output drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 2 mA

High slew rate

LVTTL Output drive strength = 4 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

tPD = 0.56 ns tPD = 0.49 ns

tDP = 2.25 ns

tPD = 0.87 ns tDP = 2.87 ns

tPD = 0.51 ns

tDP = 2.21 ns

tPD = 0.47 ns tDP = 3.02 ns

tPD = 0.47 ns

tPY = 0.84 ns

tCLKQ = 0.55 ns tOCLKQ = 0.59 ns

tSUD = 0.43 ns tOSUD = 0.31 ns

tDP = 2.21 ns

tPY = 0.84 ns

tPY = 1.14 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 0.84 ns

tICLKQ = 0.24 ns

tISUD = 0.26 ns

tPY = 1.04 ns

ProASIC3 nano DC and Switching Characteristics

2-12 Advance v0.2

Figure 2-3 • Input Buffer Timing Model and Delays (example)

tPY

(R)

PAD

Vtrip

GND tPY

(F)

Vtrip

50%

VIH

VCC

VIL

tDOUT

(R)

DIN

GND tDOUT

(F)

50%50%

VCC

PAD Y

tPY

CLK

I/O Interface

DIN

tDIN

To Array

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-13

Figure 2-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50%50%

VCC

0 V

DOUT 50%50%0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3 nano DC and Switching Characteristics

2-14 Advance v0.2

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50%50%t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50%50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-15

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions—Software Default Settings

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL 1IOH 1

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

3.3 V LVCMOS

Wide Range

Any 2High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100

µA

100

µA

2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V LVCMOS 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4

1.5 V LVCMOS 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 22

Notes:

1. Currents are measured at 85°C junction temperature.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B

specification.

Table 2-15 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial 1Industrial 2

IIL 3IIH 4IIL 3IIH 4

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

Notes:

1. Commercial range (–20°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <

VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

ProASIC3 nano DC and Switching Characteristics

2-16 Advance v0.2

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-16 • Summary of AC Measuring Points

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

3.3 V LVCMOS Wide Range 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

Table 2-17 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-17

Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF)

STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

For A3PN060, A3PN125, and A3PN250

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

3.3 V LVTTL / 3.3 V LVCMOS 8 High 35 0.60 4.85 0.04 1.12 TBD 0.43 4.17 3.40 2.69 3.14

3.3 V LVCMOS Wide Range Any 1High 35 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

2.5 V LVCMOS 8 High 35 0.60 5.11 0.04 1.39 TBD 0.43 4.24 4.16 2.69 2.97

1.8 V LVCMOS 4 High 35 0.60 6.75 0.04 1.31 TBD 0.43 4.96 5.40 2.74 2.84

1.5 V LVCMOS 2 High 35 0.60 8.10 0.04 1.52 TBD 0.43 5.78 6.45 2.80 2.79

Notes:

1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B

specification.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF)

STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

For A3PN020, A3PN015, and A3PN010

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

3.3 V LVTTL / 3.3 V LVCMOS 8 High 10 0.60 2.97 0.04 1.12 1.51 0.43 2.60 2.02 2.69 3.14

3.3 V LVCMOS Wide Range Any 1High 10 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

2.5 V LVCMOS 8 High 10 0.603.010.041.391.610.432.642.252.692.97

1.8 V LVCMOS 4 High 10 0.603.490.041.311.890.433.042.702.742.84

1.5 V LVCMOS 2 High 10 0.604.040.041.522.140.433.503.112.802.79

Notes:

1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B

specification.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-18 Advance v0.2

Detailed I/O DC Characteristics

Table 2-20 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-21 • I/O Output Buffer Maximum Resistances 1

Standard Drive Strength

RPULL-DOWN

(Ω)2RPULL-UP

(Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

3.3 V LVCMOS Wide Range 100 µA TBD TBD

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

1.5 V LVCMOS 2 mA 200 224

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on VCCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R(WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-19

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-23 • I/O Short Currents IOSH/IOSL

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27

4 mA 25 27

6 mA 51 54

8 mA 51 54

3.3 V LVCMOS Wide Range 100 µA TBD TBD

2.5 V LVCMOS 2 mA 16 18

4 mA 16 18

6 mA 32 37

8 mA 32 37

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

1.5 V LVCMOS 2 mA 13 16

*TJ = 100°C

Table 2-24 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

–20°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 2-25 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL / LVCMOS (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS No requirement 10 ns *20 years (110°C)

*The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity

evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

ProASIC3 nano DC and Switching Characteristics

2-20 Advance v0.2

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-27 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL

HIOSL IOSH

IIL

1IIH

Drive Strength

Min.,

Max.,

Min.,

Max.,

Min.,

AMax., mA

3Max., mA3µA

4µA

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <

VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-6 • AC Loading

Table 2-28 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

03.31.410

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-16 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-21

Timing Characteristics

Table 2-29 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 10.48 0.04 1.12 TBD 0.43 8.86 7.41 2.40 2.47 ns

–1 0.51 8.91 0.04 0.95 TBD 0.36 7.54 6.30 2.04 2.10 ns

–2 0.45 7.83 0.03 0.84 TBD 0.32 6.62 5.53 1.79 1.84 ns

4 mA Std. 0.60 10.48 0.04 1.12 TBD 0.43 8.86 7.41 2.40 2.47 ns

–1 0.51 8.91 0.04 0.95 TBD 0.36 7.54 6.30 2.04 2.10 ns

–2 0.45 7.83 0.03 0.84 TBD 0.32 6.62 5.53 1.79 1.84 ns

6 mA Std. 0.60 7.45 0.04 1.12 TBD 0.43 6.48 5.53 2.69 3.00 ns

–1 0.51 6.33 0.04 0.95 TBD 0.36 5.51 4.70 2.29 2.55 ns

–2 0.45 5.56 0.03 0.84 TBD 0.32 4.84 4.13 2.01 2.24 ns

8 mA Std. 0.60 7.45 0.04 1.12 TBD 0.43 6.48 5.53 2.69 3.00 ns

–1 0.51 6.33 0.04 0.95 TBD 0.36 5.51 4.70 2.29 2.55 ns

–2 0.45 5.56 0.03 0.84 TBD 0.32 4.84 4.13 2.01 2.24 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 7.53 0.04 1.12 TBD 0.43 6.15 5.18 2.39 2.61 ns

–1 0.51 6.41 0.04 0.95 TBD 0.36 5.23 4.41 2.04 2.22 ns

–2 0.45 5.63 0.03 0.84 TBD 0.32 4.60 3.87 1.79 1.95 ns

4 mA Std. 0.60 7.53 0.04 1.12 TBD 0.43 6.15 5.18 2.39 2.61 ns

–1 0.51 6.41 0.04 0.95 TBD 0.36 5.23 4.41 2.04 2.22 ns

–2 0.45 5.63 0.03 0.84 TBD 0.32 4.60 3.87 1.79 1.95 ns

6 mA Std. 0.60 4.85 0.04 1.12 TBD 0.43 4.17 3.40 2.69 3.14 ns

–1 0.51 4.13 0.04 0.95 TBD 0.36 3.55 2.89 2.29 2.67 ns

–2 0.45 3.63 0.03 0.84 TBD 0.32 3.11 2.54 2.01 2.34 ns

8 mA Std. 0.60 4.85 0.04 1.12 TBD 0.43 4.17 3.40 2.69 3.14 ns

–1 0.51 4.13 0.04 0.95 TBD 0.36 3.55 2.89 2.29 2.67 ns

–2 0.45 3.63 0.03 0.84 TBD 0.32 3.11 2.54 2.01 2.34 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-22 Advance v0.2

Table 2-31 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 6.08 0.04 1.12 1.51 0.43 5.20 4.48 2.40 2.47 ns

–1 0.51 5.17 0.04 0.95 1.28 0.36 4.43 3.81 2.04 2.10 ns

–2 0.45 4.54 0.03 0.84 1.13 0.32 3.88 3.35 1.79 1.84 ns

4 mA Std. 0.60 6.08 0.04 1.12 1.51 0.43 5.20 4.48 2.40 2.47 ns

–1 0.51 5.17 0.04 0.95 1.28 0.36 4.43 3.81 2.04 2.10 ns

–2 0.45 4.54 0.03 0.84 1.13 0.32 3.88 3.35 1.79 1.84 ns

6 mA Std. 0.60 4.76 0.04 1.12 1.51 0.43 4.25 3.83 2.69 3.00 ns

–1 0.51 4.05 0.04 0.95 1.28 0.36 3.61 3.26 2.29 2.55 ns

–2 0.45 3.56 0.03 0.84 1.13 0.32 3.17 2.86 2.01 2.24 ns

8 mA Std. 0.60 4.76 0.04 1.12 1.51 0.43 4.25 3.83 2.69 3.00 ns

–1 0.51 4.05 0.04 0.95 1.28 0.36 3.61 3.26 2.29 2.55 ns

–2 0.45 3.56 0.03 0.84 1.13 0.32 3.17 2.86 2.01 2.24 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-32 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 3.84 0.04 1.12 1.51 0.43 3.09 2.44 2.39 2.61 ns

–1 0.51 3.27 0.04 0.95 1.28 0.36 2.63 2.07 2.04 2.22 ns

–2 0.45 2.87 0.03 0.84 1.13 0.32 2.31 1.82 1.79 1.95 ns

4 mA Std. 0.60 3.84 0.04 1.12 1.51 0.43 3.09 2.44 2.39 2.61 ns

–1 0.51 3.27 0.04 0.95 1.28 0.36 2.63 2.07 2.04 2.22 ns

–2 0.45 2.87 0.03 0.84 1.13 0.32 2.31 1.82 1.79 1.95 ns

6 mA Std. 0.60 2.97 0.04 1.12 1.51 0.43 2.60 2.02 2.69 3.14 ns

–1 0.51 2.52 0.04 0.95 1.28 0.36 2.21 1.72 2.29 2.67 ns

–2 0.45 2.21 0.03 0.84 1.13 0.32 1.94 1.51 2.01 2.34 ns

8 mA Std. 0.60 2.97 0.04 1.12 1.51 0.43 2.60 2.02 2.69 3.14 ns

–1 0.51 2.52 0.04 0.95 1.28 0.36 2.21 1.72 2.29 2.67 ns

–2 0.45 2.21 0.03 0.84 1.13 0.32 1.94 1.51 2.01 2.34 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-23

3.3 V LVCMOS Wide Range

Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range

3.3 V LVCMOS

Wide Range VIL VIH VOL VOH IOL IOH IIL 1IIH 2

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA µA4µA4

Any 3 –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <

VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B

specification.

4. Currents are measured at 85°C junction temperature.

ProASIC3 nano DC and Switching Characteristics

2-24 Advance v0.2

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-34 • Minimum and Maximum DC Input and Output Levels

2.5 V LVCMOS VIL VIH VOL VOH IOL

HIOSL IOSH

IIL

1IIH

Drive Strength

Min.,

Max.,

Min.,

Max.,

Min.,

AMax., mA

3Max., mA3µA

4µA

2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10

6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <

VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-35 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

02.51.210

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-16 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-25

Timing Characteristics

Table 2-36 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 11.40 0.04 1.39 TBD 0.43 9.71 9.33 2.37 2.25 ns

–1 0.51 9.70 0.04 1.19 TBD 0.36 8.26 7.94 2.02 1.91 ns

–2 0.45 8.51 0.03 1.04 TBD 0.32 7.25 6.97 1.77 1.68 ns

4 mA Std. 0.60 11.40 0.04 1.39 TBD 0.43 9.71 9.33 2.37 2.25 ns

–1 0.51 9.70 0.04 1.19 TBD 0.36 8.26 7.94 2.02 1.91 ns

–2 0.45 8.51 0.03 1.04 TBD 0.32 7.25 6.97 1.77 1.68 ns

6 mA Std. 0.60 8.24 0.04 1.39 TBD 0.43 7.20 6.77 2.70 2.87 ns

–1 0.51 7.01 0.04 1.19 TBD 0.36 6.13 5.76 2.30 2.44 ns

–2 0.45 6.15 0.03 1.04 TBD 0.32 5.38 5.05 2.01 2.14 ns

8 mA Std. 0.60 8.24 0.04 1.39 TBD 0.43 7.20 6.77 2.70 2.87 ns

–1 0.51 7.01 0.04 1.19 TBD 0.36 6.13 5.76 2.30 2.44 ns

–2 0.45 6.15 0.03 1.04 TBD 0.32 5.38 5.05 2.01 2.14 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-37 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.54 0.04 1.39 0.43 6.25 6.65 2.37 2.34 ns

–1 0.51 7.26 0.04 1.19 0.36 5.31 5.66 2.01 1.99 ns

–2 0.45 6.38 0.03 1.04 0.32 4.66 4.97 1.77 1.75 ns

4 mA Std. 0.60 8.54 0.04 1.39 0.43 6.25 6.65 2.37 2.34 ns

–1 0.51 7.26 0.04 1.19 0.36 5.31 5.66 2.01 1.99 ns

–2 0.45 6.38 0.03 1.04 0.32 4.66 4.97 1.77 1.75 ns

6 mA Std. 0.60 5.11 0.04 1.39 0.43 4.24 4.16 2.69 2.97 ns

–1 0.51 4.35 0.04 1.19 0.36 3.61 3.54 2.29 2.53 ns

–2 0.45 3.82 0.03 1.04 0.32 3.17 3.11 2.01 2.22 ns

8 mA Std. 0.60 5.11 0.04 1.39 0.43 4.24 4.16 2.69 2.97 ns

–1 0.51 4.35 0.04 1.19 0.36 3.61 3.54 2.29 2.53 ns

–2 0.45 3.82 0.03 1.04 0.32 3.17 3.11 2.01 2.22 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-26 Advance v0.2

Table 2-38 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 6.79 0.04 1.39 1.61 0.43 5.87 5.37 2.37 2.25 ns

–1 0.51 5.77 0.04 1.19 1.37 0.36 5.00 4.56 2.02 1.91 ns

–2 0.45 5.07 0.03 1.04 1.20 0.32 4.39 4.01 1.77 1.68 ns

4 mA Std. 0.60 6.79 0.04 1.39 1.61 0.43 5.87 5.37 2.37 2.25 ns

–1 0.51 5.77 0.04 1.19 1.37 0.36 5.00 4.56 2.02 1.91 ns

–2 0.45 5.07 0.03 1.04 1.20 0.32 4.39 4.01 1.77 1.68 ns

6 mA Std. 0.60 5.34 0.04 1.39 1.61 0.43 4.79 4.55 2.70 2.87 ns

–1 0.51 4.55 0.04 1.19 1.37 0.36 4.08 3.87 2.30 2.44 ns

–2 0.45 3.99 0.03 1.04 1.20 0.32 3.58 3.40 2.01 2.14 ns

8 mA Std. 0.60 5.34 0.04 1.39 1.61 0.43 4.79 4.55 2.70 2.87 ns

–1 0.51 4.55 0.04 1.19 1.37 0.36 4.08 3.87 2.30 2.44 ns

–2 0.45 3.99 0.03 1.04 1.20 0.32 3.58 3.40 2.01 2.14 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-39 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 3.93 0.04 1.39 1.61 0.43 3.17 2.84 2.37 2.34 ns

–1 0.51 3.34 0.04 1.19 1.37 0.36 2.69 2.41 2.01 1.99 ns

–2 0.45 2.93 0.03 1.04 1.20 0.32 2.36 2.12 1.77 1.75 ns

4 mA Std. 0.60 3.93 0.04 1.39 1.61 0.43 3.17 2.84 2.37 2.34 ns

–1 0.51 3.34 0.04 1.19 1.37 0.36 2.69 2.41 2.01 1.99 ns

–2 0.45 2.93 0.03 1.04 1.20 0.32 2.36 2.12 1.77 1.75 ns

6 mA Std. 0.60 3.01 0.04 1.39 1.61 0.43 2.64 2.25 2.69 2.97 ns

–1 0.51 2.56 0.04 1.19 1.37 0.36 2.25 1.92 2.29 2.53 ns

–2 0.45 2.25 0.03 1.04 1.20 0.32 1.97 1.68 2.01 2.22 ns

8 mA Std. 0.60 3.01 0.04 1.39 1.61 0.43 2.64 2.25 2.69 2.97 ns

–1 0.51 2.56 0.04 1.19 1.37 0.36 2.25 1.92 2.29 2.53 ns

–2 0.45 2.25 0.03 1.04 1.20 0.32 1.97 1.68 2.01 2.22 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-27

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-40 • Minimum and Maximum DC Input and Output Levels

1.8 V LVCMOS VIL VIH VOL VOH IOL

HIOSL IOSH

IIL

1IIH

Drive Strength

Min.

, V Max., V Min., V

Max.,

V Min., V

Max.,

mA3Max.,

mA3µA

4µA

2 mA –0.3 0.35 * VCCI 0.65 *

VCCI

3.6 0.45 VCCI –

0.45

2 2 9 11 10 10

4 mA –0.3 0.35 *

VCCI

0.65 *

VCCI

3.6 0.45 VCCI –

0.45

4 4 17 22 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <

VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-41 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

01.80.910

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-16 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 nano DC and Switching Characteristics

2-28 Advance v0.2

Timing Characteristics

Table 2-42 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 15.34 0.04 1.31 TBD 0.43 12.49 12.58 2.35 1.72 ns

–1 0.51 13.05 0.04 1.12 TBD 0.36 10.63 10.70 2.00 1.46 ns

–2 0.45 11.45 0.03 0.98 TBD 0.32 9.33 9.40 1.76 1.28 ns

4 mA Std. 0.60 10.68 0.04 1.31 TBD 0.43 9.39 8.98 2.75 2.74 ns

–1 0.51 9.09 0.04 1.12 TBD 0.36 7.99 7.64 2.34 2.33 ns

–2 0.45 7.98 0.03 0.98 TBD 0.32 7.01 6.70 2.05 2.04 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-43 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 11.61 0.04 1.31 0.43 7.36 8.94 2.35 1.78 ns

–1 0.51 9.88 0.04 1.12 0.36 6.26 7.60 2.00 1.51 ns

–2 0.45 8.67 0.03 0.98 0.32 5.49 6.67 1.75 1.33 ns

4 mA Std. 0.60 6.75 0.04 1.31 0.43 4.96 5.40 2.74 2.84 ns

–1 0.51 5.74 0.04 1.12 0.36 4.22 4.60 2.33 2.42 ns

–2 0.45 5.04 0.03 0.98 0.32 3.70 4.04 2.05 2.12 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-29

Table 2-44 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.90 0.04 1.31 1.89 0.43 7.80 7.02 2.35 1.72 ns

–1 0.51 7.57 0.04 1.12 1.60 0.36 6.64 5.97 2.00 1.46 ns

–2 0.45 6.65 0.03 0.98 1.41 0.32 5.82 5.24 1.76 1.28 ns

4 mA Std. 0.60 7.08 0.04 1.31 1.89 0.43 6.40 5.93 2.75 2.74 ns

–1 0.51 6.02 0.04 1.12 1.60 0.36 5.44 5.05 2.34 2.33 ns

–2 0.45 5.29 0.03 0.98 1.41 0.32 4.78 4.43 2.05 2.04 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-45 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 4.99 0.04 1.31 1.89 0.43 3.70 3.53 2.35 1.78 ns

–1 0.51 4.24 0.04 1.12 1.60 0.36 3.15 3.01 2.00 1.51 ns

–2 0.45 3.72 0.03 0.98 1.41 0.32 2.77 2.64 1.75 1.33 ns

4 mA Std. 0.60 3.49 0.04 1.31 1.89 0.43 3.04 2.70 2.74 2.84 ns

–1 0.51 2.97 0.04 1.12 1.60 0.36 2.58 2.30 2.33 2.42 ns

–2 0.45 2.61 0.03 0.98 1.41 0.32 2.27 2.02 2.05 2.12 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-30 Advance v0.2

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-46 • Minimum and Maximum DC Input and Output Levels

1.5 V LVCMOS VIL VIH VOL VOH IOL

HIOSL IOSH

IIL

1IIH

Drive Strength

Min.

, V Max., V Min., V

Max.,

V Max., V Min., V

Max.,

mA3Max.,

mA3µA

4µA

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 *

VCCI

0.75 *

VCCI

2 2 13 16 10 10

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-47 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF)

0 1.5 0.75 10

Notes:

1. Measuring point = Vtrip. See Table 2-16 on page 2-16 for a complete table of trip points.

2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-31

Timing Characteristics

Table 2-48 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 13.17 0.04 1.52 TBD 0.43 11.64 10.91 2.81 2.67 ns

–1 0.51 11.20 0.04 1.29 TBD 0.36 9.90 9.28 2.39 2.27 ns

–2 0.45 9.83 0.03 1.14 TBD 0.32 8.69 8.15 2.10 1.99 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-49 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.10 0.04 1.52 TBD 0.43 5.78 6.45 2.80 2.79 ns

–1 0.51 6.89 0.04 1.29 TBD 0.36 4.92 5.48 2.39 2.37 ns

–2 0.45 6.05 0.03 1.14 TBD 0.32 4.32 4.81 2.09 2.08 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-50 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 8.87 0.04 1.52 2.14 0.43 8.06 7.19 2.81 2.67 ns

–1 0.51 7.54 0.04 1.29 1.82 0.36 6.86 6.12 2.39 2.27 ns

–2 0.45 6.62 0.03 1.14 1.60 0.32 6.02 5.37 2.10 1.99 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-51 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.60 4.04 0.04 1.52 2.14 0.43 3.50 3.11 2.80 2.79 ns

–1 0.51 3.44 0.04 1.29 1.82 0.36 2.98 2.65 2.39 2.37 ns

–2 0.45 3.02 0.03 1.14 1.60 0.32 2.62 2.32 2.09 2.08 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-32 Advance v0.2

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

Figure 2-10 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-33

Table 2-52 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-10 on page 2-32 for more information.

ProASIC3 nano DC and Switching Characteristics

2-34 Advance v0.2

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

Figure 2-11 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-35

Table 2-53 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-11 on page 2-34 for more information.

ProASIC3 nano DC and Switching Characteristics

2-36 Advance v0.2

Input Register

Timing Characteristics

Figure 2-12 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

tISUE

50%

tISUD

tIHD

50%50%

tICLKQ

tIHE

tIRECPRE tIREMPRE

tIRECCLR tIREMCLR

tIWCLR

tIWPRE

tIPRE2Q

tICLR2Q

tICKMPWH tICKMPWL

50%50%

50%50%50%

50%50%

50%50%50%50%50%50%

50%

Table 2-54 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns

tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-37

Output Register

Timing Characteristics

Figure 2-13 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

OSUE

50%

OSUD

OHD

50%50%

OCLKQ

OHE

ORECPRE

OREMPRE

ORECCLR

OREMCLR

OWCLR

OWPRE

OPRE2Q

OCLR2Q

OCKMPWH

OCKMPWL

50%50%

50%50%50%

50%50%

50%50%50%50%50%50%

50%

Table 2-55 • Output Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns

tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns

tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 ns

tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-38 Advance v0.2

Output Enable Register

Timing Characteristics

Figure 2-14 • Output Enable Register Timing Diagram

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

tOESUE

50%

tOESUD tOEHD

50%50%

tOECLKQ

tOEHE

tOERECPRE

tOEREMPRE

tOERECCLR tOEREMCLR

tOEWCLR

tOEWPRE

tOEPRE2Q tOECLR2Q

tOECKMPWH tOECKMPWL

50%50%

50%50%50%

50%50%

50%50%50%50%50%50%

50%

Table 2-56 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.44 0.51 0.59 ns

tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns

tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 ns

tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-39

DDR Module Specifications

Input DDR Module

Figure 2-15 • Input DDR Timing Model

Table 2-57 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC3 nano DC and Switching Characteristics

2-40 Advance v0.2

Timing Characteristics

Figure 2-16 • Input DDR Timing Diagram

tDDRICLR2Q2

tDDRIREMCLR

tDDRIRECCLR

tDDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

tDDRICLKQ1

246

357

tDDRIHD

tDDRISUD

tDDRICLKQ2

Table 2-58 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

Parameter Description –2–1Std. Units

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 ns

tDDRISUD Data Setup for Input DDR (Fall) 0.25 0.28 0.33 ns

Data Setup for Input DDR (Rise) 0.25 0.28 0.33 ns

tDDRIHD Data Hold for Input DDR (Fall) 0.00 0.00 0.00 ns

Data Hold for Input DDR (Rise) 0.00 0.00 0.00 ns

tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 ns

tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns

tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 ns

tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 ns

FDDRIMAX Maximum Frequency for Input DDR MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-41

Output DDR Module

Figure 2-17 • Output DDR Timing Model

Table 2-59 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC3 nano DC and Switching Characteristics

2-42 Advance v0.2

Timing Characteristics

Figure 2-18 • Output DDR Timing Diagram

116

910

28 3 9

tDDROREMCLR

tDDROHD1

tDDROREMCLR

tDDROHD2

tDDROSUD2

tDDROCLKQ

tDDRORECCLR

CLK

Data_R

Data_F

CLR

Out

tDDROCLR2Q

7104

Table 2-60 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns

tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 ns

tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 ns

FDDOMAX Maximum Frequency for the Output DDR TBD TBD TBD MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-43

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section,

timing characteristics are presented for a sample of the library. For more details, refer to the

Fusion, IGLOO®/e, and ProASIC3/E Macro Library Guide.

Figure 2-19 • Sample of Combinatorial Cells

MAJ3

MUX2

AXOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3

NAND2

ProASIC3 nano DC and Switching Characteristics

2-44 Advance v0.2

Figure 2-20 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF),

tPD(FF), tPD(FR)) where edges are

applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50%50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-45

Timing Characteristics

VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each

has a data input and optional enable, clear, or preset. In this section, timing characteristics are

presented for a representative sample from the library. For more details, refer to the Fusion,

IGLOO/e, and ProASIC3/E Macro Library Guide.

Table 2-61 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –2 –1 Std. Units

INV Y = !A tPD 0.40 0.46 0.54 ns

AND2 Y = A · B tPD 0.47 0.54 0.63 ns

NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 ns

OR2 Y = A + B tPD 0.49 0.55 0.65 ns

NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 ns

XOR2 Y = A ⊕ Bt

PD 0.74 0.84 0.99 ns

MAJ3 Y = MAJ(A, B, C) tPD 0.70 0.79 0.93 ns

XOR3 Y = A ⊕ B ⊕ Ct

PD 0.87 1.00 1.17 ns

MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 ns

AND3 Y = A · B · C tPD 0.56 0.64 0.75 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5

for derating values.

Figure 2-21 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

ProASIC3 nano DC and Switching Characteristics

2-46 Advance v0.2

Timing Characteristics

Figure 2-22 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

tSUE

50%

tSUD

tHD

50%50%

tCLKQ

tHE

tRECPRE tREMPRE

tRECCLR tREMCLRtWCLR

tWPRE

tPRE2Q tCLR2Q

tCKMPWH tCKMPWL

50%50%

50%50%50%

50%50%

50%50%50%50%50%50%

50%

Table 2-62 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 ns

tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 ns

tHD Data Hold Time for the Core Register 0.00 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns

tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.36 0.41 0.48 ns

tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.32 0.37 0.43 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-47

Global Resource Characteristics

A3PN250 Clock Tree Topology

Clock delays are device-specific. Figure 2-23 is an example of a global tree used for clock routing.

The global tree presented in Figure 2-23 is driven by a CCC located on the west side of the A3PN250

device. It is used to drive all D-flip-flops in the device.

Figure 2-23 • Example of Global Tree Use in an A3PN250 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

ProASIC3 nano DC and Switching Characteristics

2-48 Advance v0.2

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be

driven and conditioned internally by the CCC module. For more details on clock conditioning

capabilities, refer to the "Clock Conditioning Circuits" section on page 2-51. Table 2-63 to

Table 2-68 on page 2-50 present minimum and maximum global clock delays within each device.

Minimum and maximum delays are measured with minimum and maximum loading.

Timing Characteristics

Table 2-63 • A3PN010 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2 Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.56 0.75 0.64 0.85 0.75 1.00 ns

tRCKH Input HIGH Delay for Global Clock 0.57 0.79 0.65 0.90 0.76 1.05 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.22 0.25 0.29 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-64 • A3PN015 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.61 0.86 0.70 0.98 0.82 1.15 ns

tRCKH Input HIGH Delay for Global Clock 0.62 0.91 0.71 1.03 0.83 1.21 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.28 0.32 0.38 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-49

Table 2-65 • A3PN020 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.61 0.86 0.70 0.98 0.82 1.15 ns

tRCKH Input HIGH Delay for Global Clock 0.62 0.91 0.71 1.03 0.83 1.21 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.28 0.32 0.38 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-66 • A3PN060 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.72 0.95 0.82 1.08 0.96 1.26 ns

tRCKH Input HIGH Delay for Global Clock 0.71 0.96 0.81 1.11 0.96 1.30 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.25 0.30 0.35 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-50 Advance v0.2

Table 2-67 • A3PN125 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.76 0.99 0.87 1.12 1.02 1.32 ns

tRCKH Input HIGH Delay for Global Clock 0.76 1.02 0.87 1.17 1.02 1.37 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Table 2-68 • A3PN250 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std.

UnitsMin. 1Max. 2Min. 1Max. 2Min. 1Max. 2

tRCKL Input LOW Delay for Global Clock 0.79 1.02 0.90 1.16 1.06 1.36 ns

tRCKH Input HIGH Delay for Global Clock 0.78 1.04 0.88 1.18 1.04 1.39 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-51

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-69 • ProASIC3 nano CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz

Delay Increments in Programmable Delay Blocks 1,2 200 ps

Number of Programmable Values in Each Programmable

Delay Block

Serial Clock (SCLK) for Dynamic PLL 3125 MHz

Input Cycle-to-Cycle Jitter (peak magnitude) 1.5 ns

CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

Network

Used

External

FB Used

3 Global

Networks

Used

0.75 MHz to 24 MHz 0.50%0.70%

24 MHz to 100 MHz 1.00%1.20%

100 MHz to 250 MHz 1.75%2.00%

250 MHz to 350 MHz 2.50%5.60%

Acquisition Time

LockControl = 0

LockControl = 1

300 µs

6.0 ms

Tracking Jitter 5

LockControl = 0

LockControl = 1

1.6 ns

0.8 ns

Output Duty Cycle 48.5 51.5 %

Delay Range in Block: Programmable Delay 1 1,2 1.25 15.65 ns

Delay Range in Block: Programmable Delay 2 1,2 0.025 15.65 ns

Delay Range in Block: Fixed Delay 1,2 2.2 ns

Notes:

1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings.

2. TJ = 25°C, VCC = 1.5 V

3. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific

junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

4. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL

input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by

the period jitter parameter.

ProASIC3 nano DC and Switching Characteristics

2-52 Advance v0.2

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.

Figure 2-24 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-53

Embedded SRAM and FIFO Characteristics

SRAM

Figure 2-25 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC3 nano DC and Switching Characteristics

2-54 Advance v0.2

Timing Waveforms

Figure 2-26 • RAM Read for Pass-Through Output

Figure 2-27 • RAM Read for Pipelined Output

CLK

ADD

BLK_B

WEN_B

CYC

CKH

CKL

BKS

ENS

ENH

DOH1

BKH

CKQ1

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-55

Figure 2-28 • RAM Write, Output Retained (WMODE = 0)

Figure 2-29 • RAM Write, Output as Write Data (WMODE = 1)

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS tENH

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

(pass-through) DI1

DnDI0

(pipelined) DI0DI1

DI2

ProASIC3 nano DC and Switching Characteristics

2-56 Advance v0.2

Figure 2-30 • RAM Reset

CLK

RESET_B

DO D

CYC

CKH

CKL

RSTBQ

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-57

Timing Characteristics

Table 2-70 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tAS Address Setup time 0.25 0.28 0.33 ns

tAH Address Hold time 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup time 0.14 0.16 0.19 ns

tENH REN_B, WEN_B Hold time 0.10 0.11 0.13 ns

tBKS BLK_B Setup time 0.23 0.27 0.31 ns

tBKH BLK_B Hold time 0.02 0.02 0.02 ns

tDS Input data (DI) Setup time 0.18 0.21 0.25 ns

tDH Input data (DI) Hold time 0.00 0.00 0.00 ns

tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 1.79 2.03 2.39 ns

Clock High to New Data Valid on DO (flow-through, WMODE = 1) 2.36 2.68 3.15 ns

tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.89 1.02 1.20 ns

tC2CWWL Address collision clk-to-clk delay for reliable write after write on same

address; applicable to closing edge

0.33 0.28 0.25 ns

tC2CWWH Address collision clk-to-clk delay for reliable write after write on same

address; applicable to rising edge

0.30 0.26 0.23 ns

tC2CRWH Address collision clk-to-clk delay for reliable read access after write on

same address; applicable to opening edge

0.45 0.38 0.34 ns

tC2CWRH Address collision clk-to-clk delay for reliable write access after read on

same address; applicable to opening edge

0.49 0.42 0.37 ns

tRSTBQ RESET_B Low to Data Out Low on DO (flow through) 0.92 1.05 1.23 ns

RESET_B Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 ns

tCYC Clock Cycle time 3.23 3.68 4.32 ns

FMAX Maximum Frequency 310 272 231 MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating

values.

ProASIC3 nano DC and Switching Characteristics

2-58 Advance v0.2

Table 2-71 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tAS Address setup time 0.25 0.28 0.33 ns

tAH Address hold time 0.00 0.00 0.00 ns

tENS REN_B, WEN_B setup time 0.09 0.10 0.12 ns

tENH REN_B, WEN_B hold time 0.06 0.07 0.08 ns

tDS Input data (DI) setup time 0.18 0.21 0.25 ns

tDH Input data (DI) hold time 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 ns

tCKQ2 Clock HIGH to new data valid on DO (pipelined) 0.90 1.02 1.20 ns

tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same

address; applicable to opening edge

0.50 0.43 0.38 ns

tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same

address; applicable to opening edge

0.59 0.50 0.44 ns

tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 0.92 1.05 1.23 ns

RESET_B LOW to data out LOW on DO (pipelined) 0.92 1.05 1.23 ns

tREMRSTB RESET_B removal 0.29 0.33 0.38 ns

tRECRSTB RESET_B recovery 1.50 1.71 2.01 ns

tMPWRSTB RESET_B minimum pulse width 0.21 0.24 0.29 ns

tCYC Clock cycle time 3.23 3.68 4.32 ns

FMAX Maximum frequency 310 272 231 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for

derating values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-59

FIFO

Figure 2-31 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ProASIC3 nano DC and Switching Characteristics

2-60 Advance v0.2

Timing Waveforms

Figure 2-32 • FIFO Reset

Figure 2-33 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A

)

MPWRSTB

RSTFG

RSTCK

RSTAF

RCLK/

WCLK

RESET_B

EMPTY

AEMPTY

WA/RA

(Address Counter)

RSTFG

RSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

tCKAF

tRCKEF

EMPTY

AEMPTY

tCYC

WA/RA

(Address Counter)

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-61

Figure 2-34 • FIFO FULL Flag and AFULL Flag Assertion

Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 2-36 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

tRCKEF

tCKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

tWCKF

tCKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

ProASIC3 nano DC and Switching Characteristics

2-62 Advance v0.2

Timing Characteristics

Table 2-72 • FIFO

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tENS REN_B, WEN_B Setup Time 1.38 1.57 1.84 ns

tENH REN_B, WEN_B Hold Time 0.02 0.02 0.02 ns

tBKS BLK_B Setup Time 0.22 0.25 0.30 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 2.36 2.68 3.15 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 0.92 1.05 1.23 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 ns

FMAX Maximum Frequency for FIFO 310 272 231 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-63

Embedded FlashROM Characteristics

Timing Characteristics

Figure 2-37 • Timing Diagram

HOLD

CKQ2

CLK

Address

Data D

Table 2-73 • Embedded FlashROM Access Time

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tSU Address Setup Time 0.53 0.61 0.71 ns

tHOLD Address Hold Time 0.00 0.00 0.00 ns

tCK2Q Clock to Out 16.23 18.48 21.73 ns

FMAX Maximum Clock Frequency 15.00 15.00 15.00 MHz

ProASIC3 nano DC and Switching Characteristics

2-64 Advance v0.2

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays

to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-11 for more details.

Timing Characteristics

Table 2-74 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDISU Test Data Input Setup Time 0.53 0.60 0.71 ns

tDIHD Test Data Input Hold Time 1.07 1.21 1.42 ns

tTMSSU Test Mode Select Setup Time 0.53 0.60 0.71 ns

tTMDHD Test Mode Select Hold Time 1.07 1.21 1.42 ns

tTCK2Q Clock to Q (data out) 6.39 7.24 8.52 ns

tRSTB2Q Reset to Q (data out) 21.31 24.15 28.41 ns

FTCKMAX TCK Maximum Frequency 23.00 20.00 17.00 MHz

tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns

tTRSTREC ResetB Recovery Time 0.21 0.24 0.28 ns

tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5

for derating values.

ProASIC3 nano DC and Switching Characteristics

Advance v0.2 2-65

Part Number and Revision Date

Part Number 51700111-002-1

Revised November 2008

List of Changes

The following table lists critical changes that were made in the current version of the chapter.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status datasheet may not have completed Actel’s