DMILL - Atmel Corporation - Datasheet.Directory

Rev. B – 24-Aug-01

Atmel is ma nufacturi ng the DMILL techno logy in i ts Nantes’ factor y. Pri marily devel-

oped to serve the High Energy Physics market, the technology offers versatile

components suitable for any advanced mixed or pure digital conception. Taking

advantage of SOI use and trench in sulat ors, the SCR structur es inherently pr esent in

std CMOS technology and responsible for LATCH-UP is totally eliminated. Moreover,

in association with outstanding radiation proper ties, product designed and fabricated

with DMILL offers total security for use in highly energetic particle environments.

DMILL Process

Introduction DMILL is a BiCMOS technology fabricated using Silic on

On Insulator (SOI) substrate. The decision to develop

new equi pment for High Energy Phy sics ( HEP) res earch

has lead to the n eed of ultra har d te ch nol ogy. T he dete c-

tor electronics adjacent to the collision areas can

accumul ate rad ia tio n dos es above 10Mrad . Fu rt hermo re ,

the low level of the detector signals imposes very high

signal to noise ratios. To meet these new requirements,

the French Commissariat à l’Ener gi e Ato miq ue (CE A) , an

organization highly involved in almost all advanced

nuclear Physics research, has, by taking advantage of its

extensive experience in SOI hardened technologies,

developed the DMILL technology, a mixed analog/digital

technology ha rdened to t olerate more than 10Mra d and

1014 neutrons/cm².

DMILL Performance

Active and passive

devices The DMILL process offers a designer the possibility to

use 4 di fferent ac tive devic es, i.e. NMO S, PMOS, NPN

Bipolar and PJFET. With regards to advanced analog

needs, several passive elements are also available, such

as resisto rs and capacito rs. For interconnec t, 1 low-rho

polysilicon and 2 AlSi layers can be used. Table 1 lists

the electrical performance of DMILL.

Integration For Radiation hardness reasons, DMILL uses several

features, which ar e silicon con suming. Howeve r, trench

is effic ie nt to reduc e th e c riti cal dimen si on , whi ch is co m-

mon in BULK CMOS technologies. Thus, the overall

layout-inflating factor is limited to 30% compared to a

similar 0.8µm BiCMOS technology. Today, mixed com-

plex designs have achieved 1Million transistors/cm².

Speed Thanks to SOI, parasitic capacitors are reduced. There-

fore, the intrinsic speed of the devices is increased

compared to similar BULK technology:

•- Propagation dela y = 150pS @ ambient temperature

(180pS @ 150°C) (1)

•- Bipolar Ft = 5.0GHz at ambient temperature

1. inverter made of NMOS (4.0x0.8) and PMOS (8.0/0.8)

Rad Hard

Mixed Signal

Technology

DMILL

Rev. B – 24-Aug-01

Table 1. DMILL basic parameters

Parameter Typ value Unit Description

MOS transistors

Leff N 0.72 µm Electrical length of a 0.8µm N channel transistor

Leff P 0.70 µm Electrical length of a 0.8µm N channel transistor

VTN 0.93 VThreshold v oltage of a 0.8µm N channel transistor

VTP -0.80 VThreshold voltage of a 0.8µm P channel transistor

IDSN (0.8µm) 8.30 mA Drain current for a 25/0.8µm N transistor with

VGS=VDS=5.0V

IDSP (0.8µm) 4.60 mA Drain current for a 25/0.8µm P transistor with VGS=VDS=-

5.0V

BVDSS (1µA) >8.00 VDrain / Source breakdown voltage at ID = 1.0µA

VTN Field >10.0 V

VTP Fie ld >10.0 V

NPN bipolar

Beta (1.2x1.2) 250 NU NPN 1.2x1.2 ideal forward beta

VEARLY 96 VNPN Forward early voltage

BVCE0 5.70 VBreakdown of collector/emitter with base open

BVCB0 17.0 VBreakdown of collector/base with emitter open

P-JFET

VPPJ (1.2µm) 1.20 VPinch-off voltage of a 100/1.2 P-JFET

GDPJ (1.2µm) 1.135 µS/µm Drain transconducatnce of a 100/1.2 PJFET (VGS=0V;

VDS=-3V)

Oxides

Eox 17.5 nm Gate oxide thickness

EField 470 nm Gate oxide thickness

Ecapa 42.0 nm Gate oxide thickness

Resistors

RP+ 118 Ω/square P+ resistivity

RP- 3550 Ω/square P- resistivity

Rextrins 1650 Ω/square Extrinsi c base r esistivi t y

R POL 2.35 Ω/square Poly gate resistivity

R M1 0.050 Ω/square Metal 1 resistivity

R M2 0.040 Ω/square Metal2 resistivity

3DMILL Rev. B – 24-Aug-01

Cross sections Techno log y cr oss - se ct ion in Fig u re 1 giv es an i ndi ca tio n of how the dev i ce s are bu il t on

top of the insulator layer of the SOI substrate.

Figure 1. DMILL Technology Cross Section

No Latch-Up The use of combined S OI substrate and lateral isolation by trench rem oves the u sual

three-dimensional SRC parasitic structure inherent to CMOS/Bulk technologies. Thus,

no Latch- up can be trigge red, either by elec trical injec tion or prom pt charges dep osited

by heavy particles during their travel across silicon.

Radiation properties The proxim ity of the electronics from the area the protons collide in HEP experiments

makes the radiation requirements ex tremely high. Some of the circuits will suffer from

30Mrad combi ned wi th a fluen ce of 6.0 E14 ne utrons/cm ² after 1 0 yea rs lifeti me! There-

fore, particular attention is paid to make all devices radiation hard. Characterizations are

conducted using various ionizing particles because of HEP bombarding cocktails. Of

particula r i nte re st , X and Ga mma ray s a s w ell as pr oto n a nd n eutr on . Cum ul ated dos es

up to 30Mrad are regularly deposited to measure post radiation parameter’s variation.

Hardness demonstration up to 350Mrad was done with a 16bit sliced µprocessor. The

following figures give some indication on the r epeatability of the radiation hardness of

the DMILL p rocess. Not ice that Ra diation i nduced drifts are conti nuously verified an d

Statistical Process Control is in force, as for any other technological param eter (thick-

ness, electrical, dimension…).

PMOS

N+

TRENCH

P+ P+

LOCOS

N+

N+ N-

SIMOX BURR IED OXIDE

SUBSTRAT ( BACK SILICON)

TRENCH

P+N+N+ LOCOS

P-

NMOS

N+N+ LOCOS

NMOSPMOS

P-

N+N+

P-

TRENCH

P-

NMOS

lost area lost area

SIMOX BURRIED OX IDE

SUBSTRAT (BACK SILICON)

PJFET (HALF)

N+ P+

LOCOS

N+ collector

N + P- C hannel

N+

P+

NPN BJT

N+ P+

LOCOS

N+ collector

N+ N- DRIFT

N+

P-

TRENCH P-

TRENCH

High Value RES

P- N+

Capacitor

Bi as e d ‘ lost’

area

P-

DMILL

Rev. B – 24-Aug-01

Figure 2. NMOS transistor thrshold voltage with dose over production

Figure 3. PMOS transistor thrshold voltage with dose over production

Figure 4. NPN gain versus batch numberft

200

400

600

800

1000

1200

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Ba tch number

Vt (mV)

0 rad

10 Mrad

-1200

-1000

-800

-600

-400

-200

1234567891011121314

Batch num ber

Vt (mV)

0 rad

10 Mrad

100

150

200

250

300

350

400

batch number

0 rad

10 Mrad

Final Process

Process under opti mizati on

USL@0rad

LSL@0rad

LSL@10Mrad

5DMILL Rev. B – 24-Aug-01

Figure 5. NPN gain ver s us 1MeV equivalent neutron fluence

Figure 6. PJFET ∆Vp versus 1MeV equivalent neutron fluence

Post 10Mrad parameter drifts To allow designer to assess design robustness, Atmel offers, in the design kit, a set of

10Mrad post irradiation drifts. Therefore, sensitive parameters drift is injected in the sim-

ulation. It is rec om men ded to us e thes e n umb er s i n co mbi nat ion with typi cal te chnology

parameters to avoid over-pessimistic simulation.

Since no significant degradation is observed before 1Mrad accumulated dose, most of

the space design will not require any post-rad simulation.

Radiation Hardness

Assurance In order to verify the process stability over the production period, Atmel has installed a

Radiation Hardness Assurance (RHA) program. Each and every DMILL production run

is irradiated up to 10Mrad with 10keV X-rays. This is a non-destructive test performed at

wafer level on process control monitors located in the street line (scribe lines) of the

wafers. Irradiation is collimated so that customer’s circuits are not damaged. Wafers are

delivered with a Radiati on Certif icate of Confor manc e (Co C) to post radi ation spe cific a-

tions th at are sche duled in th e El ectric al Desi gn Rul es. The pos sibili ty ex ists to rem ove

this control when not necessary.

SEU characteristics Single Event Upset is a tempor ary event that ca n occur in storing elem ents by highly

energetic particles crossing over the silicon layer. If the quantity of charges deposited by

this particle is higher than the stored charge, then, the information contained in the stor-

ing element is corrupted. This error is not permanent and can be restored.

100

120

1.E+12 1.E+13 1.E+14 1.E+15 1.E+16

Neutron (p/cm ²)

β/β0 ( 100µA)

b/b0 for

Ic=1E-4A

-1

-0.8

-0.6

-0.4

-0.2

1.E+12 1.E+13 1.E+14 1.E+15 1.E+16

Neutron (p/cm ²)

Ic=100µA

DMILL

Rev. B – 24-Aug-01

DMILL is intrinsically hardened against SEU because the silicon layer on top of the insu-

lator is very thin (1.2µm). So, deposited charge is very small. Thus, compared to

standard Bulk CMOS technology, DMILL offers improved SEU figures:

Note: (*) By comparison to standard BULK CMOS technology with similar lithography.

Most impo rtantly for this mixed a nalog/digita l application , Atmel offe rs SEU har dened

cells (DF Fs , S RAM) by use of a ddi tio nal lo gic . Demonst ra tio n of the appl icability of t his

technique to various technologies has been done by irradiating cells up to 115

MeV/(mg/cm2) without any SEU detection.

SEU must be evaluated on a case-by-case basis. From a digital standpoint, the process

provides for lat chup- free opera tion up to the spec ified radiat ion limits. If Custom er

requires performance beyond the radiation parameters, either in Total Dose, or in flux, a

fault-tolerant design approach can be adopted.

From an ana log standp oint, SE U is a mor e comp lex iss ue. SEU depends on a num ber

of variables such as the amount and duration of transients on signal lines, charge stored

on (or dissipated from) capacitors, etc. Essentially, this becomes a tradeoff issue

where, f or i nstance, capa citors can be ma de la rger s o tha t SEU’s have a pr opor tional ly

smaller effect. Similar tradeoffs exist in almost every type of analog circuit.

Storing element SEU threshold

(MeV/(mg/cm²)) Reduction factor (*)

Memory Cell 15 200

DFF cell 70 130

Combinatorial 70 40

7DMILL Rev. B – 24-Aug-01

Noise Characteristics DMILL devices have particularly low nois e properties. This is il lustrated in the figures

below . Even afte r 10Mrad ac cumula ted dose, noise figu res remai n lower th an a few

nV/√Hz. This prop erty i s of v ery h igh i mpor tance for an alog desi gner s de aling with low

input signals as well as harsh environments.

In addition, substrate partitioning is possible with DMILL technology. The use of a lat-

eral trench is a way to reduce noise and parasitic coupling between analog and digital

portions of a mixed design. A specific “User’s Guide” (RDER2402) is available to give

designers techniques to reduce spurious effects and to take into account parasitic ele-

ments in complex designs.

Figure 7. Noise properties of NMOS transistors up to 10 Mrad

Figure 8. Noise properties of PMOS transistors up to 10 Mrad

100

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Fre quency (Hz)

nV/sqrt(Hz)

Ic=100µA ; Vb= -3V

13 batches

100

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Fre quency (Hz )

nV/sqrt(Hz)

Ic=100µ A ; Vb=3V

11 batches

DMILL

Rev. B – 24-Aug-01

Figure 9. Noise properties of PJFET transistors up to 10 Mrad

Figure 10. Noise properties of NPN transistors up to 10 Mrad

100

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Fre quency (Hz)

nV/sqrt(Hz)

PJ FET 2000/1.2

Ic = 100µA

9 batches

100

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Fre que ncy (Hz)

nV/sqrt(Hz)

NPN 1.2/1.2 ; Ic = 100µA

13 batches

9DMILL Rev. B – 24-Aug-01

Development Tools Atmel offers, for free, a DMILL design kit. This set of tools allows the designer to

develop ad vanced and highly in tegrated circui ts for mixed analog/d igital applications .

The desi gn kit, whi ch is bein g dist ributed to Cu st omer under the signe d Non Dis closur e

Agreeme nt (ND A), i s c omprise d o f sever al fi les a nd pap er do cumen ts tha t are incl uded

in the Cadence 9502 environment. Part of the content is described in 18.4.1.

List of specifications and files Topological design rules (RDTR2401)

–Design rules for layout

–Specific rules for ESD protection

–Mask gen eration for drawn layers

Electrical design rules (RDER2401)

–Electrical parameters (resistance, capacitance, currents, etc.)

–Electrical models for simulation including –55 to +150°C and 250°C

–MOS transistors: BSIM3v3 for ELDO

–NPN Bipolar: Gummel & Poon

–PJFET: Spice

–Corner files (typN / typP; f a stN / fastP; slowN / slowP; slowN / fastP; f astN /

slowP)

–Reliability characteristics (Electromigration, Hot Carrier Injection, etc.)

–DMILL specific characteristics (noise, radiation, etc.)

SOI/DMILL design users guide (RDER2402)

Included is a s et of des ign rule s and te ch niques to get a f irst pas s yield desig n with

particular focus on parasitic and cross talk effects.

Cadence library (v9502)

The Cadence library is composed of several files including:

DDK Cadence library root directory

DDK.lib Cadence library file

DDK.drc DMILL technology Cadence file DRC format

Parameters ELDO BSIM3v3 parameters for DMILL in Cadence format

Basic Framework independent basic DMILL information

ESD Protection

DMILL design kit offers several types of ESD protection depending on I/O structure:

ASSEMBLY rules

Bonding Pads are defined and verified by DRC. However, specific rules can be adapted

for modern assembly techniques.

Scribe lines are defined according to Atmel HIgh RELiability rules. No waiver is

accepted since Process Control Monitors must be inserted in those lines.

Type Description / test

Digital Input Protection Diode & resistor / Specific Poly-contact spacing / > 4000V

Analog Input Protection Grounded gate NMOS transistors / Specific Poly-contact spacing / > 4000V

Output Buffer NMOS & PMOS / Specific Poly-contact spacing / > 4000V

Pow er Supply protection Grounded gate NMOS transistors / Specific Poly-contact spacing / > 4000V

DMILL

Rev. B – 24-Aug-01

Digital library In the frame of one CERN funding, a digital std-cell library for automatic place and route

has been de ve loped. The c on ten t of the li br ary is l ist ed in Tabl e 2 . V ERI LO G and S YN-

OPSYS libraries are provided.

Table 2. Digital Library

Cell function Symbol

Inverter Jiv1

Power inverter (double drive) Jiv2

Power inverter (triple drive) Jiv3

Pow er inverter (f our-time drive) Jiv4

2-Input AND Jan2

3-Input AND Jan3

2-Input NAND Jnd2

3-Input NAND Jnd3

4-Input NAND Jnd4

6-Input NAND Jnd6

8-Input NAND Jnd8

2-Input OR Jor2

3-Input OR Jor3

2-Input NOR Jnr2

3-Input NOR Jnr3

4-Input NOR Jnr4

2- Input exclusive OR Jxo2

2- Input exclusive NOR Jxn2

2 x 2 input AND into 2 input NOR Jaoi1

2 input AND into 3 input NOR Jaoi2

2 input OR into 3 input NAND Joai1

2 x 2 input OR into 2 input NAND Joai2

Fulladder Jfuadd

2 to 1 multiplexer Jmx2

4 to 1 multiplexer Jmx4

8 to 1 multiplexer Jmx8

1 to 2 decoder with active low enable Jdec2e

2 to 4 decoder with active low enable Jdec4e

Tristate buffer Jtbuf

Non inver ting buffer Jbuf

D latch with active low reset Jldrl

11 DMILL Rev. B – 24-Aug-01

D latch with active high set Jldsh

D Flip-Flop Jfd

Scan D Flip-Flop Jfd1s

D Flip-Flop with active high reset Jfdrh

D Flip-Flop with active lo w set Jfdsl

D Flip-Flop with active low set & active high reset Jfdslrh

JK Flip-Flop with active high reset Jfjkrh

JK Flip-Flop with active low set Jfjksl

Schmitt trigger Jbis1

TTL input Jbit1

TTL input with pull-up resistor Jbit2

CMOS input Jbic1

CMOS input with pull-up resistor Jbic2

CMOS input with pull-down resistor Jbic3

TTL output Jbot1

CMOS output Jboc1

Open drain with pull-up resistor Jbo2

Open drain with pull-down resistor Jbo3

Tri-state output Jbto1

Bidirection: Tri-state out + Schmitt trigger in Jbtbs1

Bidirection: Tri-state out + Schmitt trigger In + pull-up Jbtbs2

Bidirection: Tri-state out + TTL in Jbtb1

Bidirection: Tri-state out + TTL in + pull-up Jbtb2

Bidirection: Tri-state out + CMOS in Jbcb1

Analog signal pad with ESD Jbia1

Analog signal pad Jboa1

Digital VDD pad Jpdd1

Analog VDD pad Jpdda1

Digital VSS pad Jpss1

Analog VSS pad Jpssa1

Cell function Symbol

DMILL

Rev. B – 24-Aug-01

Analog library To answer im med iate need s, Atme l gives acce ss to a limite d set of analog cel ls. 9 cells

are available and described in the Table 3.

Table 3. Analog library

Note: This list is not ex ha ust ive.

Program Management Atmel will designate a pro gram man ager, with necessar y author ity for planning and

management of financial resources. A program manager will provide Customer with one

overall schedule. The schedule will be maintained throughout the life of the contract.

Monthly reports, teleconferences, or other reports will be generated as mutually agreed.

Any particular event will be immediately reported to Customer when a schedule is

affect ed.

Prototyping Mix ed analog /digit al develop ment often requires prototypi ng for fun ction or arc hitectur e

validat ion . It is als o ac ce pte d th at analog de bug r equ ires s ev er al l oop s to refin e design.

The prototyping phase allows assessing yield figures before larger scale production.

Consider ing the h igh Non Re curren t Expen ses (NRE) nece ssar y to acces s ASI C proto-

typing, Atmel is offering the Multi-Project Wafer (MPW) service. The objective of this

approach is to group circuits fr om different cus tomers together on one single reticule.

Thus, sets of masks and numbers of wafers are minimized.

MPW organizatio n The MPW serv ice is organized for DMILL either at Atmel or through IMEC, a Belgi um

company in the frame of the Europractice projects context. Starting 4 times a year,

MPW runs co llec t DMILL des igns. Un der Atm el respon sibi lity, IM EC will recei ve tape or

FTP files. Then, DRC verification will be done on the net-lists and reticule physical

placeme nt wi ll be done prior to sen di ng th e GD SI I tape to A tme l fo r fu rther ma sk ma nu-

facturing and wafer proces sing. The lead-time is genera lly 14 weeks from submi ssion

date to die delivery. In addition to pure foundry, additional test and assembly services

are possible. More information can be gathered at:

www.imec.be/europractice/

More wafer runs can also be organized when requested.

Debug / extended

characterization In case the design of the chip is sub-contracted, the design house can handle several

design validation and prototype evaluation. First silicon will be used to verify and charac-

terize the basic functionality as well as electrical performances. Extended verifications

Cell function Symbol

Trimable Band-gap Voltage Reference BGP01

Band-Gap Voltage Reference BGP02

40nA Current generator IG01

50µA Current Generator IG02

Low Power, Low Voltage High DC Gain Operational Amplifier OPA01

High DC Gain Folded Cascade Operational Amplifier OPA02

CMOS Operational Amplifier with class AB output stage OPA03

Low Noise Charge preamplifier PRE01

13 DMILL Rev. B – 24-Aug-01

can als o b e cond uc ted ov er the Mili tar y (-5 5°C; +125°C) tem perature and p ower sup ply

ranges. A detailed report will be furnished to Customer with available functional and per-

formance margins.

When necessary, specific radiation tests such as heavy ion induced Single Event Upset

(SEU) sensitivity will be tested on several parts according to the existing standards.

When a non-q ualified assemb ly technique or packa ge is used, extended the rmal and

mech anical ch arac terizati on can be perfo rmed to gi ve Custo mer proof of suitabl e qual-

ity and reliability.

Price and delivery for

prototyping Basic MPW offer:

–Fixed price of $800 per mm².

–Minimum dimension of 10mm²

–No maximum dimension but maximal edge dimension will be limited to

10mm

–20 prototypes (non-tested or packaged) will be sent to the customer

–Quality level is Engineering thus Atmel in-house specifications are in force

Several options are possible and must be clearly identified in the Purchase order, based

on prior negotiation with Atmel:

–Maximum quantity up to 500 parts

–Inspection level can be done according to the MIL-std 883, tm 2010 cond.B.

–Parts can be packaged in either hermetic or plastic

–W afer can be sent to any subcontractor for any modern assembly technique

–Wafer can be tested provided positive answer to prior test feasibility study is

given

–etc…

DMILL

Rev. B – 24-Aug-01

Large scale production If the MPW a pproach is no t acceptable (confidentiality , quantity, e tc.), dedica ted runs

can be or dered dire ctly wit h Atmel. T he netlist is transf erred to the At mel desi gn center

for DRC verification. A GDSII tape is made available for mask generation. The Quantity

of wafers n ecessar y to de liver the reque sted qua ntity of final pr oduc ts is calcu lated ta k-

ing into account manufacturing, test, visual inspection and assembly yields. DMILL

maximum production is 150 wafers per week.

DMILL production Different possibilities exist to produce DMILL circuits:

–Pure foundry: Wafers are manufactured according to in-house procedures

and delivered with a CoC.

–Tested wafers: Provided a test program is validated, Atmel can either test or

sub-contract test of the wafers to sort Good dice.

–Tested dice: Probed wafers are diced to extract and deliver only good dice.

–P ackaged dice: Provided bonding diagram and prior feasibility study is

concluded positively, Atmel can make or can sub-contract assembly of good

die to a quality gr ade selected by Customer.

–Screened parts: Atmel can conduct or subcontract part screening from

commercial up to highest quality level required for space applications.

–Any combination of the above possibilities

Test The test pr ogram is developed acc ording to the requirements of the Sour ce Control

Drawing (customer specification). Prototypes coming from previous MPW runs are used

to debug both test program and hardware. The final test program will use the frame

develop ed during the pro totyping p hase wi th a possi ble extens ion acc ording to the fina l

specification. A review of the test program content will be done with Customer represen-

tatives prior to production release.

Customer Source Inspection Customer may require a Customer Source Inspection (CSI) at any step of the fabrica-

tion. Notification to Customer representative will be made at least 15 days prior to the

CSI.

15 DMILL Rev. B – 24-Aug-01

Design background Atmel cu sto mer s wid ely use the DMILL technology for va ri ous fi nal app lic at ion s. To day ,

more than 20cm² of different designs have been fabricated for High Energy Physics and

Nuclear Industry applications. The application breakdown is roughly 70% HEP, 15%

nuclear and 15% misc.

Examples of DMILL

designs 1. Advanced Synthesizer Local oscillator: It realizes a PLL Frequency synthesizer

based on fraction al div isi on, inc lu ding spu rious can cell ati on tec hnique (Sigma-

Delta). RF input frequency up to 400MHz.

2. Low noise charge Preamplifier with DC coupling for Large Hadron Collider

Experiment

3. Mixed-signal data receiver/clock synchronizer ASIC f or analog front end

4. Analog readout for position sensitive radiation detectors

5. Four-channel rad-hard delay generator with 1ns minimum time step

6. 80MHz clock and data recovery circuit

7. Analog signal processor for a calorimeter with a multi-gain preamplifier

8. Sample and hold multiplexer

9. Clock and Digital logic for front end rad-hard electronics

10. Analog memory

11. 12-bit, 5 MHz ADC

12. 4-chann el tri-ga in sh aper

13. 128 channel analog pipeline for MSGC detectors

14. 128 channel preamplifier, shaper, and buffer

15. Analog pulse shape processor

16. 128 x 1 multiplexer

17. Bias generator/pulse generator

18. 128 channel binary readout

19. Bipolar front end preamplifier and comparator

20. Dynamic FIFO

21. De-randomizer and data comp re ssor

22. Charge sensitive preamplifier and shaper

23. 12-bit 40 MHz ADC

24. Satellite thermal controller/multiplexer

25. Bus driver for satellite on-board systems

26. Sun sensor system using Silicon photodiodes

27. Front-end for astrophysics experiment

28. Angular coder for nuclear industry (10Mrad)

29. Nuclear robotics component

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the inform ation contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted

by the Company in connection with the sale of Atmel produc ts, expressly or by implication. Atmel’s products are not authorized for use as crit ical

components in life suppor t devices or systems.

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Tel: 441344707 300

Fax: 441344427 371

USA

2325 Orchard Parkway

San Jose

California 95131

USA-California

Tel: 1408441 0311

Fax: 1408436 4200

1465 Route 31, 5th Floor

Annandale

New Jersey 08801

USA-New Jersey

Tel: 1908848 5208

Fax: 1908848 5232

Hong Kong

77 Mody Rd., Tsimshatsui East,

Rm.1219

East Kowloon

Hong Kong

Tel: 85223789 789

Fax: 85223755 733

Korea

Ste.605,Singsong Bldg. Young-

deungpo-ku

150-010 Seoul

Korea

Tel: 8227851136

Fax: 8227851137

Singapore

25 Tampines Street 92

Singapore 528877

Rep. of Singapore

Tel: 65260 8223

Fax: 65787 9819

Taiwan

Wen Hwa 2 Road, Lin Kou

Hsiang

244 T aipei Hsie n 244

Taiwan, R .O.C.

Tel: 88622609 5581

Fax: 88622600 2735

Japan

1-24-8 Shinkawa, Chuo-Ku

104-0033 Tokyo

Japan

Tel : 8133523 3551

Fax: 8133523 7581

Web site

http://www.atmel-wm.com

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