Document Number: MMA26xxNKW Rev. 4, 03/2012 Freescale Semiconductor Data Sheet: Technical Data DSI Inertial Sensor The MMA26xxNKW family, a SafeAssure solution, includes DSI2.5 compatible overdamped X-axis satellite accelerometers. MMA26xxNKW Features * * * * * * * 25g to 312.5g Nominal Full-Scale Range Selectable 180 Hz, 2-pole, 400 Hz, 4-pole, or 800 Hz, 4-pole LPF DSI2.5 Compatible with full support of Mandatory Commands 16 s internal sample rate, with interpolation to 1 ms -40C to 125C Operating Temperature Range Pb-Free 16-Pin QFN, 6 by 6 Package Qualified AECQ100, Revision G, Grade 1 (-40C to +125C) (http://www.aecouncil.com/) Bottom View 16-PIN QFN CASE 2086-01 Typical Applications * Airbag Front and Side Crash Detection TEST5 TEST6 ORDERING INFORMATION TEST7 VSS Top View 16 15 14 13 Device Axis Range Package Shipping MMA2602NKW X 25g 2086-01 Tubes TEST2 1 MMA2605NKW X 50g 2086-01 Tubes TEST3 2 11 CREGA MMA2606NKW X 62.5g 2086-01 Tubes TEST1 3 10 TEST4 MMA2612NKW X 125g 2086-01 Tubes BUSRTN 4 MMA2618NKW X 187g 2086-01 Tubes MMA2631NKW X 312g 2086-01 Tubes MMA2602NKWR2 X 25g 2086-01 Tape & Reel MMA2605NKWR2 X 50g 2086-01 Tape & Reel MMA2606NKWR2 X 62.5g 2086-01 Tape & Reel MMA2612NKWR2 X 125g 2086-01 Tape & Reel MMA2618NKWR2 X 187g 2086-01 Tape & Reel MMA2631NKWR2 X 312g 2086-01 Tape & Reel For user register array programming, please consult your Freescale representative. (c) 2010-2012 Freescale Semiconductor, Inc. All rights reserved. 12 VSSA 17 5 6 7 8 PCM BUSOUT BUSIN HCAP 9 CREG PIN CONNECTIONS Application Diagram TEST2 BUSIN BUSIN VCC TEST1 TEST3 MMA26xxN C1 TEST4 TEST5 BUSRTN BUSRTN VSS TEST6 TEST7 CREG BUSOUT CREGA HCAP C4 C5 C3 VSSA PCM VSS Figure 1. Application Diagram External Component Recommendations Ref Des Type Description Purpose C1 Ceramic C3 Ceramic, Tantalum 1 F C3 100 F, 10%, 50V, X7R C4 Ceramic 1 F, 10%, 10V, X7R Voltage Regulator Output Capacitor (CREG) C5 Ceramic 1 F, 10%, 10V, X7R Voltage Regulator Output Capacitor (CREGA) 100 pF C1 1000 pF 10%, 50V, X7R BUSIN Power Supply Decoupling, ESD Reservoir Capacitor for Keep Alive during Signaling xxxxxxx xxxxxxx X: 0 g X: +1 g xxxxxxx xxxxxxx xxxxxxx xxxxxxx Device Orientation X: 0 g xxxxxxx xxxxxxx X: -1 g X: 0 g X: 0 g EARTH GROUND Figure 2. Device Orientation Diagram MMA26xxNKW 2 Sensors Freescale Semiconductor, Inc. Internal Block Diagram HCAP BUSIN HCAP VDSI_REF ANALOG VREGA VOLTAGE REGULATOR CREGA VREF VSSA LOW-VOLTAGE RESET BUSRTN TEST3 CONTROL LOGIC SERIAL ENCODER VSS CREG REFERENCE VOLTAGE VDSI_REF VSSB DIGITAL VREG VOLTAGE REGULATOR TEST OTP FUSE ARRAY OSCILLATOR TEST4 TEST5 TEST6 VREG SELF-TEST INTERFACE g-CELL VREGA CONTROL IN VREG DSP SINC Filter CONVERTER STATUS OUT 3 1 - z-D --------------------------------- 1 D x (1 - z ) IIR Low-Pass Filter Compensation PCM Encoder PCM Figure 3. Block Diagram MMA26xxNKW Sensors Freescale Semiconductor, Inc. 3 TEST5 TEST6 TEST7 Pin Connections VSS 1 16 15 14 13 TEST2 1 12 VSSA 17 TEST3 2 11 CREGA TEST1 3 10 TEST4 5 6 7 8 BUSIN HCAP 9 CREG VSSB 4 PCM BUSRTN Figure 4. Block Diagram Table 1. Pin Description Pin Pin Name Formal Name 1 TEST2 Test Pin This pin must be left unconnected in the application. 2 TEST3 Test Pin This pin must be grounded in the application. 3 TEST1 Test Pin This pin must be grounded in the application. 4 BUSRTN Ground This pin is the common return for power and signalling. 5 PCM PCM Output This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled or disabled via OTP. If unused, this pin must be left unconnected in the application. Reference Section 3.5.3.6. 6 VSSB Ground This pin must be grounded in the application. 7 BUSIN Supply / Comm This pin is connected to the DSI positive bus node and provides the power supply and communication to the system master. An external capacitor must be connected to between this pin and the BUSRTN pin. Reference Figure 1. 8 HCAP Hold Capacitor This pin rectifies the supply voltage on the BUSIN pin to create the supply voltage for the device. An external capacitor must be connected between this pin and the BUSRTN pin to store energy for operation during master communication signalling. Reference Figure 1. 9 CREG Digital Supply This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 10 TEST4 Test Pin This pin must be grounded in the application. 11 CREGA Analog Supply This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. 12 VSSA Analog GND 13 TEST5 Test Pin This pin enables test mode, and provides the SPI programming voltage in test mode. This pin is must be grounded in the application. 14 TEST6 Test Pin This pin must be grounded in the application. 15 TEST7 Test Pin This pin must be grounded in the application. 16 VSS Digital GND 17 PAD Die Attach Pad Corner Pads Corner Pads Definition This pin is the power supply return node for analog circuitry. This pin is the power supply return node for the digital circuitry. This pin is the die attach flag, and should be connected to VSS in the application. Reference Section 5. The corner pads are internally connected to VSS. MMA26xxNKW 4 Sensors Freescale Semiconductor, Inc. 2 Electrical Characteristics 2.1 Maximum Ratings Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. Do not apply voltages higher than those shown in the table below. # Rating Symbol Value Unit VCC VCC -0.3 to +30.0 -0.3 to +34.0 V V (3) (3) -0.3 to +3.0 V (3) IIN IIN 400 75 mA mA (3) (3) Powered Shock (six sides, 0.5 ms duration) gpms 2000 g (5) Unpowered Shock (six sides, 0.5 ms duration) gshock 2000 g (5) Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation) hDROP 1.2 m (5) 9 10 11 Electrostatic Discharge (per AECQ100) HBM (100 pF, 1.5 k) CDM (R = 0) MM (200 pF, 0) VESD VESD VESD 2000 500 200 V V V (5) (5) (5) 12 13 Temperature Range Storage Junction Tstg TJ -40 to +125 -40 to +150 C C (3) (3) 14 Thermal Resistance JC 2.5 C/W (11) 1 2 Supply Voltage (continuous) (BUSIN, HCAP) Supply Voltage (pulsed < 400 ms, repetition rate 60s) (BUSIN, HCAP) 3 CREG, CREGA, PCM, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 4 5 BUSIN, BUSRTN and HCAP Current Maximum duration 1 s Continuous 6 7 8 2.2 Operating Range The operating ratings are the limits normally expected in the application. VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units VHCAP VBUS VL 6.3 -0.3 VH 30 30 V V (1,12) (1,12) 30.0 V (3) 15 16 Supply Voltage VHCAP BUSIN 17 Programming Voltage Applied to BUSIN (DSI) VPP 14.0 18 Programming Current BUSIN IPP 85 mA (3) TA TA TL -40 -40 TH +105 +125 C C (1) (3) 19 20 Operating Temperature Range MMA26xxNKW Sensors Freescale Semiconductor, Inc. 5 2.3 Electrical Characteristics - Supply and I/O VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic 21 Quiescent Supply Current * Symbol Min Typ Max Units IDD 8.0 mA (1) 22 Inrush Current (excluding HCAP Capacitor charge current) Power On until VREG Stable IINRUSH 20 mA (3) 23 24 Internally Regulated Voltages VREG VREGA VREG VREGA 2.425 2.425 2.50 2.50 2.575 2.575 V V (1) (1) 25 26 27 VHCAP Under-Voltage Detection (See Figure 5) Under-Voltage Detection Threshold VHCAP Recovery Threshold Hysteresis (VPORHCAP_r - VPORHCAP_f) VPORHCAP_f VPORHCAP_r VHYST_HCAP 5.8 70 6.0 100 6.2 6.3 140 V V mV (3,6) (3,6) (3) VPORVREG_f VPORVREGA_f 2.15 2.15 2.25 2.25 2.40 2.40 V V (3.6) (3.6) VHYST_VREG VHYST_VREGA 0.05 0.05 0.10 0.10 0.15 0.15 V V (3) (3) CREG, CREGA RCREGESR, RCREGAESR 500 1000 1500 200 nF m (9) (9) Output High Voltage (PCM) 34 ILoad = 100 A VOH VREG - 0.1 V (9) Output Low Voltage (PCM) 35 ILoad = 100 A VOL 0.1 V (9) TUNDER TOVER 155 -55 C C (9) (9) Internal Regulator Low Voltage Detection Threshold VREG Falling VREGA Falling Hysteresis VREG 30 VREGA 31 28 29 32 33 External Capacitor (CREG, CREGA) Capacitance ESR (including interconnect resistance) Temperature Monitoring 36 Under-Temperature Monitor Threshold 37 Over-Temperature Monitor Threshold 2.4 Electrical Characteristics - DSI VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified # Characteristic HCAP Rectifier Leakage Current 38 VBUSIN = 0V, VHCAP = 9.0V Symbol Min Typ Max Units * IRLKG 100 A (1) 39 40 BUSIN to HCAP Rectifier Voltage Drop (VBUSIN = 7V) IHCAP = -15 mA IHCAP = -100 mA * * VRECT VRECT 0.75 0.9 1.0 1.2 V V (1) (1) 41 42 BUSIN Bias Current VBUSIN = 8.0V, VHCAP = 9.0V VBUSIN = 4.5V, VHCAP = 24V, No Response Current * IBUSIN_BIAS IBUSIN_BIAS -100 -100 100 100 A A (1) (1) 43 BUSIN Response Current VBUSIN = 4.0V * IRESP 9.9 11 12.1 mA (1) BUSIN Logic Thresholds 44 Signal Threshold 45 Frame Threshold * * VTHS VTHF 2.8 5.5 3.0 6.0 3.2 6.5 V V (1) (1) BUSIN Logic Hysteresis Signal Frame * * VHYSS VHYSF 30 100 90 300 mV mV (3) (3) 46 47 MMA26xxNKW 6 Sensors Freescale Semiconductor, Inc. 2.5 Electrical Characteristics - Signal Chain VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic Sensitivity (10-bit @ 100 Hz referenced to 0 Hz) 25g Range 50g Range 62.5g Range 125g Range 187g Range 312g Range Total Sensitivity Error (including non-linearity) 54 TA = 25C TL T A TH 55 48 49 50 51 52 53 56 Digital Offset 10-bit output 57 58 Range of Output (10-Bit Mode) Acceleration Internal Error 59 60 Cross-Axis Sensitivity Z-axis to X-axis Y-axis to X-axis 61 ADC Output Noise Peak (1 Hz - 1 kHz, 10-Bit) 62 System Output Noise (10-Bit, RMS, All Ranges) 63 64 Non-linearity (all ranges) 10-bit output, Range < 50g 10-bit output, 50g Range 312.5g Symbol Min Typ Max Units * SENS SENS SENS SENS SENS SENS 20.48 10.24 8.192 4.096 2.731 1.638 LSB/g LSB/g LSB/g LSB/g LSB/g LSB/g (1,14) (1,14) (1,14) (1,14) (1,14) (1,14) * * SENS_25 SENS -5 -7 +5 +7 % % (1) (1) * OFF10Bit 460 512 564 LSB (1) RANGEACC RANGEERR 1 0 1023 LSB LSB (3) (3) VZX VYX -5 -5 -- -- +5 +5 % % (3) (3) * * * * * nSD -4 -- +4 LSB (3) nRMS +1.2 LSB (3) NLOUT_sub50g NLOUT_sub250g -2 -2 +2 +2 % % (3) (3) MMA26xxNKW Sensors Freescale Semiconductor, Inc. 7 2.6 Electrical Characteristics - Self-Test and Overload VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Symbol Min Typ Max Units Acceleration (without hitting internal g-cell stops) 65 25g, 50g, 62.5g, 125g Characteristic gg-cell_Clip60X 400 456 500 g (9) 66 Acceleration (without hitting internal g-cell stops) 187g, 312g gg-cell_Clip240X 1750 2065 2300 g (9) 67 and Sinc Filter Clipping Limit 25g gADC_Clip60X 98 108 121 g (9) 68 and Sinc Filter Clipping Limit 50g gADC_Clip60X 191 210 232 g (9) and Sinc Filter Clipping Limit 69 62.5g gADC_Clip60X 191 210 232 g (9) 70 and Sinc Filter Clipping Limit 125g gADC_Clip120X 353 379 409 g (9) 71 and Sinc Filter Clipping Limit 187g gADC_Clip240X 1690 1876 2106 g (9) 72 and Sinc Filter Clipping Limit 312g gADC_Clip480X 1690 1876 2106 g (9) 73 74 75 76 77 78 Deflection, 10-Bit, Self-Test - Offset, 30 sample ave, TA = 25C) 25g Range 50g Range 62.5g Range 125g Range 187g Range 312g Range DFLCT_X25 DFLCT_X50 DFLCT_X62 DFLCT_X125 DFLCT_X187 DFLCT_X312 246 123 98 49 82 49 LSB LSB LSB LSB LSB LSB (1) (1) (1) (1) (1) (1)) 79 Self-test deflection range, TA = 25 C DFLCT -10 +10 % (1) 80 Self-test deflection range, TL TA TH DFLCT -20 +20 % (1) * * * * * * MMA26xxNKW 8 Sensors Freescale Semiconductor, Inc. 2.7 Dynamic Electrical Characteristics - DSI VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Symbol Min Typ Max Units tDSI_INIT tDSP_INIT tDSI_INIT tDSP_INIT 400 / fOSC 400 / fOSC 10000 / fOSC 10000 / fOSC s s s s (7) (7) (7) (7) HCAP Under-Voltage Reset Delay (See Figure 5) 85 VHCAP < VPORHCAP_f to POR assertion tHCAP_POR 880 / fOSC s (7) VREG Under-Voltage Reset Delay (See Figure 6) 86 VREG < VPORVREG_f to POR assertion tVREG_POR 5 s (3) VREGA Under-Voltage Reset Delay (See Figure 7) 87 VREGA < VPORVREGA_f to POR assertion tVREGA_POR 5 s (3) tPOR_CAPTEST tCAPTEST_TIME tCAPTEST_RATE 12000 / fOSC 6 / fOSC 256 / fOSC s s s (7) (7) (7) DRATE 100 200 kbps (7) 81 82 83 84 Characteristic Reset Recovery (See Figure 20) POR negated to 1st DSI Command (Initialization Command) POR negated to Acceleration Data Valid (Including LPF Init) DSI Clear Command to 1st DSI Command (Initialization Command) DSI Clear Command to Acceleration Data Valid (Including LPF Init) VREG, VREGA Capacitor Monitor 88 POR to first Capacitor Test Disconnect 89 Disconnect Time () 90 Disconnect Rate () 91 Communication Data Rate 92 Loss of Signal Reset Time Maximum time below frame threshold tTO 2.00 4.00 ms (7) 93 BUSIN Response Current Slew Rate 1.0 mA to 9.0 mA, 9.0 to 1.0 mA tITR 0.33 10.0 mA/s (3) tRSP_R tRSP_F 2.50 2.50 s s (7) (7) DCL DCH 10 60 33 67 40 90 % % (7) (7) tIFS tIFS tIFS 2 20 20 ms s s (7) (7) (7) tLAT_DSI 4 / fOSC 5 / fOSC s (7) tPROG_BIT 64 256 s (7) tST_ACT_180 tST_DEACT_180 tST_ACT_400 tST_DEACT_400 tST_ACT_800 tST_DEACT_800 2.00 2.00 1.00 1.00 0.50 0.50 5.00 5.00 2.50 2.50 1.75 1.75 ms ms ms ms ms ms (7) (7) (7) (7) (7) (7) tCRC_Err 75 / fOSC s (7) BUSIN Timing to Response Current 94 BUSIN Negative Voltage Transition =3.0V to IRSP = 7.0 mA rise 95 BUSIN Negative Voltage Transition =3.0V to IRSP = 5.0 mA fall 96 97 98 99 100 DSI BUSIN Signal Duty Cycle Logic `0' Logic `1' Inter-frame Separation Time (See Figure 8) Following Read Write NVM Command Following Initialization Following other DSI bus commands 101 DSI Data Latency OTP Program Timing 102 Time to program one OTP bit 103 104 105 106 107 108 Self-Test Response Time Self-Test Activation time (EOFSlave to 90% DFLCT_xxx, 180 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% DFLCT_xxx, 180 Hz LPF) Self-Test Activation time (EOFSlave to 90% DFLCT_xxx, 400 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% DFLCT_xxx, 400 Hz LPF) Self-Test Activation time (EOFSlave to 90% DFLCT_xxx, 800 Hz LPF) Self-Test Deactivation time (EOFSlave to 10% DFLCT_xxx, 800 Hz LPF) 109 Error Detection Response Time Mirror Register CRC Error to Status Flag (S) set (Factory or User Array) * * MMA26xxNKW Sensors Freescale Semiconductor, Inc. 9 2.8 Dynamic Electrical Characteristics - Signal Chain VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units fOSC 3.80 4 4.20 MHz (1) tLAT_INTERP 64 / fOSC 65 / fOSC s (7) fC_LPF0 OLPF0 fC_LPF1 OLPF1 fC_LPF2 OLPF2 171 380 760 180 2 400 4 800 4 189 420 840 Hz 1 Hz 1 Hz 1 (7) (7) (7) (7) (7) (7) fgcell_3dB_xlo fgcell_3dB_xhi 938 3952 2592 14370 Hz Hz (9) (9) Sensing Element Natural Frequency 25g, 50g, 62.5g, 125g 187g, 312g fgcell_xlo fgcell_xhii 12651 26000 13871 28700 Hz Hz (9) (9) 122 123 Sensing Element Damping Ratio 25g, 50g, 62.5g, 125g 187g, 312g gcell_xlo gcell_xhi 2.760 1.260 6.770 3.602 (9) (9) 124 125 Sensing Element Delay (@100 Hz) 25g, 50g, 62.5g, 125g 187g, 312g fgcell_delay100_xlo fgcell_delay100_xhi 63 13 170 40 s s (9) (9) 126 Package Resonance Frequency fPackage 100 kHz (9) 110 Internal Oscillator Frequency 111 Data Interpolation Latency 112 113 114 115 116 117 DSP Low-Pass Filter Cutoff frequency LPF0 (referenced to 0 Hz) Filter Order LPF0 Cutoff frequency LPF1 (referenced to 0 Hz) Filter Order LPF1 Cutoff frequency LPF2 (referenced to 0 Hz) Filter Order LPF2 118 119 Sensing Element Rolloff Frequency (-3 db) 25g, 50g, 62.5g, 125g 187g, 312g 120 121 * Notes: 1. Parameters tested 100% at final test at -40C, 25C, and 105C. 2. Parameters tested 100% at probe. 3. Verified by characterization. 4. * Indicates critical characteristic. 5. Verified by qualification testing, not tested in production. 6. Parameters verified by pass/fail testing in production. 7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is determined by internal system clock frequency. 8. Verified by user system level characterization, not tested in production, or at component level. 9. Verified by Simulation. 10.Measured at final test. Self-test activation occurs under control of the test program. 11.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 12.Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24V at final test. 13.N/A. 14.Sensitivity, and overload capability specifications will be reduced when 80Hz filter is selected. 15.Filter cutoff frequencies are directly dependent upon the internal oscillator frequency. 16.Target values. Actual values to be determined during device characterization. MMA26xxNKW 10 Sensors Freescale Semiconductor, Inc. UV: UNDER-VOLTAGE CONDITION EXISTS VPORHCAP_r VPORHCAP_f VHCAP VHYST_HCAP UV UV tHCAP_POR POR Figure 5. VHCAP Under-Voltage Detection VREG VPORVREG_r VPORVREG_f VHYST_VREG tVREG_POR POR Figure 6. VREG Under-Voltage Detection VREGA VPORVREGA_r VPORVREGA_f VHYST_VREGA tVREGA_POR POR Figure 7. VREGA Under-Voltage Detection MMA26xxNKW Sensors Freescale Semiconductor, Inc. 11 tSTART_master VTHF VTHS BUSIN' tIFS_master tIFS_slave LOGIC `1' LOGIC `0' tSTART_slave 9mA EOFslave 1mA IRESPONSE tITR tRSP_F tITR tRSP_R tLAT_DSI tLAT_INTERP DSP_OUT Figure 8. DSI Bus Inter-frame Timing MMA26xxNKW 12 Sensors Freescale Semiconductor, Inc. 3 Functional Description 3.1 User Accessible Data Array A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable array, an OTP user programmable array, and read only registers for device status. The OTP arrays incorporate independent CRC circuitry for fault detection (reference Section 3.2). Portions of the factory programmable array are reserved for factory-programmed trim values. The user accessible data is shown in the table below. Table 2. User Accessible Data Byte Addr RA[3:0] Register $00 SN0 SN[7] SN[6] SN[5] SN[4] $01 SN1 SN[15] SN[14] SN[13] SN[12] $02 SN2 SN[23] SN[22] SN[21] SN[20] SN[19] $03 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24] $04 TYPE LPF[1] LPF[0] 1 0 RNG[3] RNG[2] RNG[1] RNG[0] CRC_U[1] CRC_U[0] Nibble Addr WA[3:0] Bit Function 7 6 5 Bit Function Nibble Addr (WA[3:0]) 4 3 2 1 0 SN[3] SN[2] SN[1] SN[0] SN[11] SN[10] SN[9] SN[8] SN[18] SN[17] SN[16] $05 DEVCFG DEVID UNUSED UNUSED UNUSED UNUSED CRC_U[2] $06 DEVCFG1 UD00[5] UD00[4] UD00[3] UD00[2] UD00[1] UD00[0] $07 DEVCFG2 LOCK_U UNUSED PCM RESERVED ADDR[3] ADDR[2] ADDR[1] ADDR[0] $08 UD01 UD01[7] UD01[6] UD01[5] UD01[4] UD01[3] UD01[2] UD01[1] UD01[0] $09 UD02 UD02[7] UD02[6] UD02[5] UD02[4] UD02[3] UD02[2] UD02[1] UD02[0] $0A UD03 UD03[7] UD03[6] UD03[5] UD03[4] UD03[3] UD03[2] UD03[1] UD03[0] Reference Table 39 Reference Table 39 Type F AT_OTP[1] AT_OTP[0] $0B UD04 UD04[7] UD04[6] UD04[5] UD04[4] UD04[3] UD04[2] UD04[1] UD04[0] $0C UD05 UD05[7] UD05[6] UD05[5] UD05[4] UD05[3] UD05[2] UD05[1] UD05[0] $0D UD06 UD06[7] UD06[6] UD06[5] UD06[4] UD06[3] UD06[2] UD06[1] UD06[0] $0E UD07 UD07[7] UD07[6] UD07[5] UD07[4] UD07[3] UD07[2] UD07[1] UD07[0] $0F UD08 UD08[7] UD08[6] UD08[5] UD08[4] UD08[3] UD08[2] UD08[1] UD08[0] U/F Type codes F: Freescale programmed OTP locationU/F:User and/or Freescale programmed OTP location. R: Read-only registerU:User Programmed OTP location. Note: Unused and Unprogrammed Spare bits always read `0'. 3.1.1 Device Serial Number Registers A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial number is composed of the following information: Bit Range Content SN[12:0] SN[31:13] Serial Number Lot Number Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2.1 for details regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or performance, and are only used for traceability purposes. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 13 3.1.2 Device Type Register (TYPE) The Device Type Register is an OTP configuration register which contains device configuration information. Bit 5 - Bit 0 are factory programmed and are included in the factory programmed OTP CRC verification. These bits are read only to the user. Bit 7 - Bit 6 are user programmable OTP bits and are included in the user programmable OTP CRC verification. Table 3. Factory Configuration Register Location RA[3:0] Register $04 TYPE 7 6 5 4 3 2 1 0 Bnk0 $08 LPF[1] LPF[0] 1 0 RNG[3] RNG[2] RNG[1] RNG[0] 0 0 1 0 0 0 0 0 Factory Default 3.1.2.1 Bit WA[3:0] WA[3:0] Low-Pass Filter Selection Bits (LPF[1:0]) (TYPE[7:6]) The Low-Pass Filter selection bit selects between one of three low-pass filter options. These bits can be factory or user programmed. LPF[1] LPF[0] Low-Pass Filter Selected 0 0 400 Hz, 4-Pole 0 1 Not Enabled1 1 0 180 Hz, 2-Pole 1 1 800 Hz, 4-Pole This filter option is not implemented. LPF[1:0] must not be set to this value to guarantee proper operation and performance. 3.1.2.2 Range Selection Bits (RNG[3:0]) (TYPE[3:0]) The Range Selection Bits indicate the full-scale range of the device, as shown below. These bits are factory programmed. g-Cell Design RNG[3] RNG[2] RNG[1] RNG[0] Full-Scale Range 0 0 0 0 N/A N/A 0 0 0 1 25g Medium-g 0 0 1 0 50g Medium-g 0 0 1 1 62g Medium-g 0 1 0 0 125g Medium-g 0 1 0 1 187g High-g 0 1 1 0 312g High-g 0 1 1 1 N/A N/A 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 Reserved N/A 1 1 0 1 1 1 1 0 1 1 1 1 MMA26xxNKW 14 Sensors Freescale Semiconductor, Inc. 3.1.3 Device Configuration Register (DEVCFG) The Device configuration register is a user programmable OTP register which contains device configuration information. This register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programmable OTP array. Table 4. Device Control Register Location RA[3:0] Register $05 DEVCFG WA[3:0] 7 6 5 4 Bnk0 $0A 1 0 0 0 1 0 0 0 Factory Default 3.1.3.1 Bit WA[3:0] Bnk0 $09 3 0 0 2 1 0 CRC_U[2] CRC_U[1] CRC_U[0] 0 0 0 Device ID Bit (DEVCFG[7]) The Device ID Bit is a user programmable bit which allows the user to select between 2 device IDs. The Device ID is transmitted in response to the Request ID DSI command. Reference Section 4.2.1.5 for more information regarding the Request ID DSI command. This bit can be factory or user programmed. 3.1.3.2 DEVID Device ID 0 `00110' 1 `00100' User Configuration CRC (CRC_U[2:0], DEVCFG[2:0]) The User Configuration CRC bits contain the 3-bit CRC used for verification of the user programmable OTP array. Reference Section 3.2.2 for details regarding the CRC for the user programmable OTP array. These bits can be factory or user programmed. 3.1.4 Device Configuration Register 1 (DEVCFG1) The Device configuration register is a user programmable OTP register which contains device configuration information. This register is included in the user register CRC check. Refer to Section 3.2.2 for details. Table 5. Device Control Register 1 Location RA[3:0] Register $06 DEVCFG1 WA[3:0] 7 6 5 4 Bnk2 $06 UD00[5] UD00[4] UD00[3] UD00[2] 0 0 0 0 Factory Default 3.1.4.1 Bit WA[3:0] Bnk1 $06 3 2 UD00[1] UD00[0] 0 0 1 0 AT_OTP[1] AT_OTP[0] 0 0 User Specific Data 00 Bits (UD00[5:0], DEVCFG1[7:2]) The User Specific Data bits have no impact on the device function or performance. The bits can be programmed with user or assembly specific information. These bits can be factory or user programmed. 3.1.4.2 Attribute Bits (AT_OTP[1:0], DEVCFG1[1:0]) The Attribute Bits are user defined bits which are transmitted in response to the Request Status, Disable Self-Test Stimulus or Enable Self-Test Stimulus DSI commands. The transmitted values are qualified by the LOCK_U bit as shown in the table below. These bits can be factory or user programmed. LOCK_U 0 1 DEVCFG1 Values AT_OTP[1] AT_OTP[0] DSI Transmitted Values AT[1] AT[0] X X 1 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 MMA26xxNKW Sensors Freescale Semiconductor, Inc. 15 3.1.5 Device Configuration 2 Register (DEVCFG2) Device configuration register 2 is a user programmable OTP register which contains device configuration information. This register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programmable OTP array. Table 6. Device Control Register Location RA[3:0] Register $07 DEVCFG2 7 6 5 4 Bnk0 $07 Bnk2 $07 Bnk3 $07 Bnk3 $0F LOCK_U UNUSED PCM RESERVED 0 0 0 0 Factory Default 3.1.5.1 Bit WA[3:0] WA[3:0] Bnk1 $07 3 2 1 0 ADDR[3] ADDR[2] ADDR[1] ADDR[0] 0 0 0 0 User Configuration Lock Bit (LOCK_U, DEVCFG2[7]) The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active. Reference Section 3.2.2 for details regarding the LOCK_U bit and CRC verification. 3.1.5.2 PCM Bit (DEVCFG2[5]) The PCM Bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code Modulated signal proportional to the acceleration response. Reference Section 3.5.3.6 for more information regarding the PCM output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed. 3.1.5.3 Device Address (ADDR[3:0], DEVCFG2[3:0]) The Device Address bits define the preprogrammed DSI Bus device address. If the Device Address bits are programmed to `0000', there is not preprogrammed address, and the address must be assigned via the Initialization DSI command. Reference Section 4.2.1.1 for more details regarding the Initialization DSI command. These bits can be factory or user programmed. 3.1.6 User Data Registers (UDx) The User Data Registers are user programmable OTP register which can be programmed with user or assembly specific information. These registers have no impact on the device performance, but are included in the user register CRC check. Refer to Section 3.2.2 for details regarding the user register CRC check. These registers can be factory or user programmed. Location RA[3:0] Register $08 UD01 Bit WA[3:0] WA[3:0] 7 6 5 4 Bnk2 $08 UD01[7] UD01[6] UD01[5] UD01[4] Bnk1 $08 3 2 1 0 UD01[3] UD01[2] UD01[1] UD01[0] $09 UD02 Bnk2 $09 UD02[7] UD02[6] UD02[5] UD02[4] Bnk1 $09 UD02[3] UD02[2] UD02[1] UD02[0] $0A UD03 Bnk2 $0A UD03[7] UD03[6] UD03[5] UD03[4] Bnk1 $0A UD03[3] UD03[2] UD03[1] UD03[0] $0B UD04 Bnk2 $0B UD04[7] UD04[6] UD04[5] UD04[4] Bnk1 $0B UD04[3] UD04[2] UD04[1] UD04[0] $0C UD05 Bnk2 $0C UD05[7] UD05[6] UD05[5] UD05[4] Bnk1 $0C UD05[3] UD05[2] UD05[1] UD05[0] $0D UD06 Bnk2 $0D UD06[7] UD06[6] UD06[5] UD06[4] Bnk1 $0D UD06[3] UD06[2] UD06[1] UD06[0] $0E UD07 Bnk2 $0E UD07[7] UD07[6] UD07[5] UD07[4] Bnk1 $0E UD07[3] UD07[2] UD07[1] UD07[0] $0F UD08 Bnk2 $0F UD08[7] UD08[6] UD08[5] UD08[4] Bnk1 $0F UD08[3] UD08[2] UD08[1] UD08[0] 0 0 0 0 0 0 0 0 Factory Default MMA26xxNKW 16 Sensors Freescale Semiconductor, Inc. 3.2 OTP Array Lock and CRC Verification 3.2.1 Factory Programmed OTP Array Lock and CRC Verification The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the Factory programmed OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which the internal lock bit is read as `1'. Automatic OTP readouts occur only after POR or a DSI Clear Command is received. Factory Lock Bit Value in Fuse Array Lock Bit Value in Mirror Register After Automatic Readout 0 N/A NO NO 1 0 NO NO 1 1 YES YES Lock Bit Active? CRC Verification Enabled? The Factory programmed OTP array is locked by Freescale and will always be active after POR. The CRC is continuously calculated on the factory programmed OTP array, which includes the registers listed below: Register Name Register Addresses Serial Number Registers SN0, SN1, SN2, SN3 Included in Factory CRC? Yes Type Register TYPE[5:0] Yes Factory Programmable Device Configuration Bits Internal Register Map Yes Factory OTP Array CRC CRC_F[2:0] No Factory OTP Array Lock Bit LOCK_F No Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification uses a generator polynomial of g(x) = X3 + X +1, with a seed value = `111'. The calculated CRC is compared against the CRC_F[2:0] bits. If a CRC mismatch is detected, an internal data error is set and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values. 3.2.2 User Programmable OTP Array Lock and CRC Verification The User Programmable OTP array is independently verified for errors with a 3-bit CRC. The CRC verification is enabled only when the User Programmable OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which the LOCK_U bit is read as `1'. Automatic OTP readouts occur only after POR or a DSI Clear Command is received. Factory Lock Bit Value in Fuse Array Lock Bit Value in Mirror Register After Automatic Readout 0 N/A NO NO 1 0 NO NO 1 1 YES YES Lock Bit Active? CRC Verification Enabled? Once the LOCK_U bit is active, the CRC is continuously calculated on the user programmable OTP Array, which includes the registers listed below: Register Name Register Addresses Type Register TYPE[7:6] Included in User CRC? Yes Device ID Bit DEVCFG[7]: 1 Yes User Data Register 0 DEVCFG1[7:2]: UD00[5:0] Yes Attribute Bits DEVCFG1[1:0]: AT_OTP[1:0] Yes PCM Bit DEVCFG2[5]: PCM Yes RESERVED Bit DEVCFG2[4] Yes Device Address DEVCFG2[3:0]: ADDR[3:0] Yes User Data Registers 1 - 8 UD01 - UD08 Yes User Programmable OTP Array CRC DEVCFG[2:0]: CRC_U[2:0] No User Programmable OTP Array Lock Bit DEVCFG2[7]: LOCK_U No Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification uses a generator polynomial of g(x) = X3 + X+ 1, with a seed value = `111'. The calculated CRC is compared against the user programmed CRC, CRC_U[2:0], which is also included in the user programmable array. If a CRC mismatch is detected, an internal data error is set, and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values. Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regardless of the state of the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 17 3.3 Voltage Regulators The device derives its internal supply voltage from the HCAP supply voltage. The device includes separate internal voltage regulators for the analog (VREGA) and digital circuitry (VREG). External filter capacitors are required, as shown in Figure 1. The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the HCAP and internal voltages have stabilized sufficiently for proper operation. The voltage monitor asserts internal reset when the HCAP supply or internally regulated voltages fall below predetermined levels. A reference generator provides a stable voltage which is used by the converter. VOLTAGE VBUF REGULATOR HCAP VREGA = 2.50 V VOLTAGE REGULATOR BIAS GENERATOR BANDGAP REFERENCE VREF TRIM REFERENCE VREF_MOD = 1.250 V GENERATOR VBUF VREGA VOLTAGE REGULATOR CREGA OSCILLATOR TRIM CONVERTER OTP ARRAY VREG = 2.50 V CREG DIGITAL LOGIC DSP HCAP VREG VREGA VREF COMPARATOR Digital Delay tHCAP_POR COMPARATOR Analog Filter Delay tVREG_POR COMPARATOR Analog Filter Delay tVREG_POR POR Figure 9. Voltage Regulation and Monitoring 3.3.1 CREG and CREGA Regulator Capacitor The internal regulator requires an external capacitor between the CREG pin and VSS pin, and the CREGA pin and VSSA pin for stability. Figure 1 shows the recommended types and values for each of these capacitors. 3.3.2 VHCAP Voltage Monitor The device includes a circuit to monitor the voltage on the HCAP pin. If the voltage falls below the specified threshold in Section 2, the device will be reset within the reset delay time (tHCAP_POR) specified in Section 2.7. MMA26xxNKW 18 Sensors Freescale Semiconductor, Inc. 3.3.3 VREG, and VREGA Under-Voltage Monitor The device includes a circuit to monitor the internally regulated voltages (VREG and VREGA). If either of the internal regulator voltages fall below the specified thresholds in Section 2, the device will be reset within the reset delay time (tVREG_POR, tVREGA_POR) specified in Section 2.7. 3.3.4 VREG and VREGA Capacitance Monitor A monitor circuit is incorporated to ensure predictable operation if the connection to the external CREG or CREGA capacitor becomes open. At a continuous rate specified in Section 2.7 (tCAPTEST_RATE), both regulators are simultaneously disabled for a short duration (tCAPTEST_TIME). If either of the external capacitors are not present, the associated regulator voltage will fall below the internal reset threshold, forcing a device reset. tCAPTEST_RATE tCAPTEST_TIME CAP_Test VREG Capacitor Present Capacitor Open VPORVREG_f POR Time Figure 10. VREG Capacitor Monitor tCAPTEST_RATE tCAPTEST_TIME CAP_Test VREGA Capacitor Present Capacitor Open VPORREGA_f POR Time Figure 11. VREGA Capacitor Monitor 3.4 Internal Oscillator The device includes a factory trimmed oscillator as specified in Section 2.8. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 19 3.5 Acceleration Signal Path 3.5.1 Transducer The device transducer is an overdamped mass-spring-damper system described by the following transfer function: where: 2 n H ( s ) = -----------------------------------------------------2 2 s + 2 n s + n = Damping Ratio n = Natural Frequency = 2fn Reference Section 2.8 for transducer parameters. 3.5.2 Converter The sigma delta converter provides the interface between the g-cell and the DSP block. The output of the converter is a data stream at a nominal frequency of 1 MHz. g-cell 1= CTOP VX FIRST INTEGRATOR CINT1 z-1 2 z-1 1 - z-1 CBOT 1-BIT QUANTIZER SECOND INTEGRATOR _OUT 1 - z-1 V = C x VX / CINT1 C = CTOP - CBOT ADC 1 2 DAC V = 2 x VREF Figure 12. Converter Block Diagram 3.5.3 Digital Signal Processing Block A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating the signal processing flow within the DSP block is shown in Figure 13. _OUT A Sinc Filter 3 1 - z -D --------------------------------- 1 D x (1 - z ) B Low-Pass Filter n + ( n z -1 ) + ( n z -2 ) n + ( n z -1 ) + ( n z -2 ) 11 12 13 21 22 23 a ----------------------------------------------------------------------------- ----------------------------------------------------------------------------0 d + ( d z -1 ) + ( d z -2 ) d + ( d z -1 ) + ( d z -2 ) 11 12 13 21 22 23 D C Compensation Output Scaling E F Interpolation OUTPUT Figure 13. Signal Chain Diagram MMA26xxNKW 20 Sensors Freescale Semiconductor, Inc. Table 7. Signal Chain Characteristics Description Sample Time (s) Data Width (Bits) A 1 1 1 B SINC Filter 16 20 12 C D E F Over Range (Bits Signal Width (Bits) Signal Noise Signal Margin (Bits) (Bits) Typical Block Latency 112/fosc 4 Reference Section 3.5.2 Section 3.5.3.1 Low-Pass Filter 16 26 1 12 4 9 Reference Section 3.5.3.2 Compensation 16 26 4 10 3 9 24/fosc Section 3.5.3.3 DSP Sampling 10-Bit Output Scaling Interpolation 3.5.3.1 Section 3.5.3.2 16 10 4/fosc Section 3.5.3.5 1 10 64/fosc Section 3.5.3.5 Decimation Sinc Filter The serial data stream produced by the converters is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 16. 3 1 - z - 16 H ( z ) = ----------------------------------16 x ( 1 - z - 1 ) Figure 14. Sinc Filter Response, tS = 16 s MMA26xxNKW Sensors Freescale Semiconductor, Inc. 21 3.5.3.2 Low-Pass Filter Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter. ( n 11 z 0 ) + ( n 12 z - 1 ) + ( n 13 z - 2 ) ( n 21 z 0 ) + ( n 22 z - 1 ) + ( n 23 z - 2 ) H ( z ) = a 0 -------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------( d 11 z 0 ) + ( d 12 z - 1 ) + ( d 13 z - 2 ) ( d 11 z 0 ) + ( d 22 z - 1 ) + ( d 23 z - 2 ) The device provides the option for one of three low-pass filters. The filter is selected with the LPF[1:0] bits in the TYPE register. The filter selection options are listed in Section 3.1.2.1, Table 8. Response parameters for the low-pass filter are specified in Section 2.8. Filter characteristics are illustrated in the figures below. Table 8. Low-Pass Filter Coefficients Description Filter Coefficients a0 180 Hz LPF 400 Hz LPF 800 Hz LPF Group Delay 0.000534069200512 n11 0.25 n12 0.499999985098839 d11 1 d12 -1.959839582443237 n13 0.25 d13 0.960373640060425 n21 1 d21 1 n22 0 d22 0 n23 0 d23 0 a0 0.003135988372378 1.0 n11 0.000999420881271 d11 n12 0.001998946070671 d12 -1.892452478408814 n13 0.000999405980110 d13 0.89558845758438 n21 0.250004753470421 d21 1.0 n22 0.499986037611961 d22 -1.919075012207031 n23 0.250009194016457 d23 0.923072755336761 a0 0.011904109735042 1.0 n11 0.003841564059258 d11 n12 0.007683292031288 d12 -1.790004611015320 n13 0.003841534256935 d13 0.801908731460571 n21 0.250001862645149 d21 1.0 n22 0.499994158744812 d22 -1.836849451065064 n23 0.250003993511200 d23 4608/fosc 3392/fosc 1728/fosc 0.852215826511383 Note: Low-Pass Filter Figures do not include g-cell frequency response. MMA26xxNKW 22 Sensors Freescale Semiconductor, Inc. Figure 15. Low-Pass Filter Characteristics: fC = 180 Hz, 2-Pole, tS = 16 s MMA26xxNKW Sensors Freescale Semiconductor, Inc. 23 Figure 16. Low-Pass Filter Characteristics: fC = 400 Hz, 4-Pole, tS = 16 s MMA26xxNKW 24 Sensors Freescale Semiconductor, Inc. Figure 17. Low-Pass Filter Characteristics: fC = 800 Hz, 4-Pole, tS = 16 s MMA26xxNKW Sensors Freescale Semiconductor, Inc. 25 3.5.3.3 Compensation The device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-linearity. 3.5.3.4 Data Interpolation The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital signal processing chain is delayed one sample time. On reception of an acceleration data request, the transmitted data is interpolated from the 2 previous samples, resulting in a latency of one sample time, and a maximum signal jitter of 1/16 of a sample time. Reference Figure 8 for more information regarding interpolation and data latency. 3.5.3.5 Output Scaling The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-Bit word which covers the acceleration range of the device. Figure 18 shows the method used to establish the acceleration data word from the 26-bit DSP output. Over Range Signal Noise D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 10 Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 9 Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 8 Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 Margin D9 D8 ... D2 D1 D0 Using Truncation Using Truncation Using Truncation Figure 18. Output Scaling Diagram 3.5.3.6 PCM Output Function The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2 register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the acceleration response is output onto the PCM pin. The PCM output is intended for test use only. A block diagram of the PCM output is shown in Figure 19. Output Scaling D_x[9:1] A CARRY PCM 9 9 Bit ADDER 9 Sample updated every 16S B SUM fCLK = 4 MHz 9 DD QQ DD QQ DD QQ DDFF QQ DFF Q FF FF FF FF FF FF FF CLK QQ CLK CLK QQ CLK CLK QQ CLK CLK QQ CLK CLK Q Figure 19. PCM Output Function Block Diagram MMA26xxNKW 26 Sensors Freescale Semiconductor, Inc. 3.6 Device Initialization Following powerup, under-voltage reset or reception of a DSI Clear Command, the device proceeds through an initialization process as described in the following tables: Table 9. Powerup or Under-Voltage Reset Initialization Process # Description Time 1 Power up to a Known State 0 3 Read Fuse Array and Copy to Memory Array (Mirror Registers) S Flag ST Flag DSI Response N/A N/A 1 0 No Response No Response 4 Initialize DSI State Machine (the device is ready for DSI Messages) tDSI_INIT 1 0 DSI Read Acceleration Data Short response = zero. DSI Read Acceleration Data Long response = invalid data. 5 Initialize the DSP (Acceleration Data is Valid) tDSP_INIT 0 0 Normal Table 10. DSI Clear Command Initialization Process # Description Time 1 the device logic comes out of reset 0 3 Read Fuse Array and Copy to Memory Array (Mirror Registers) S Flag ST Flag DSI Response 1 0 1 0 No Response No Response 4 Initialize DSI State Machine (the device is ready for DSI Messages) tDSI_INIT 1 0 DSI Read Acceleration Data Short response = zero. DSI Read Acceleration Data Long response = invalid data. 5 Initialize the DSP (Acceleration Data is Valid) tDSP_INIT 0 0 Normal BUSIN' VPORHCAP_r VHCAP VPORVREG_r VREG VPORVREGA_r VREGA POR Internal Delay tINT_INIT DSI Ready DSP_OUT tDSI_INIT tDSP_INIT Figure 20. Initialization Timing MMA26xxNKW Sensors Freescale Semiconductor, Inc. 27 3.7 Overload Response 3.7.1 Overload Performance The device is designed to operate within a specified range. However, acceleration beyond that range (overload) impacts the operating range output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon the overload frequency and amplitude. The device g-cell is overdamped, providing the optimal design for overload performance. However, the performance of the device during an overload condition is affected by many other parameters, including: * g-cell damping * Non-linearity * Clipping limits * Symmetry Figure 21 shows the g-cell, Sigma Delta, and output clipping of the device over frequency. The relevant parameters are specified in Section 2. Acceleration (g) g-cellRolloff Region Clipped by Output LPFRolloff io Reg nC ed b lipp y g- cell Determined by g-cell roll-off and ADC clipping to due ADC ion nearity t y r b o t is Li ped al D NonClip Sign y and io n f g o e R etr io n Reg Asymm gg-cell_Clip gADC_Clip Determined by g-cell roll-off and full-scale range gRange_Norm Region of Interest fLPF Region of No Signal Distortion Beyond Specification fg-Cell 5kHz 10kHz Frequency (kHz) Figure 21. Output Clipping Vs. Frequency 3.7.2 Sigma Delta Overrange Response Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. The converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates predictably under all cases of overrange, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. MMA26xxNKW 28 Sensors Freescale Semiconductor, Inc. 4 DSI Protocol Layer 4.1 Communication Interface Overview The device is compatible with the DSI Bus Standard V2.5. 4.1.1 DSI Physical Layer Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer. 4.1.2 DSI Data Link Layer Reference DSI Bus Standard,V2.5, Section 4 for information regarding the DSI data link layer. The sections below describe the DSI data link layer features supported. 4.2 DSI Protocol 4.2.1 DSI Bus Commands DSI Bus Commands are summarized in Table 11. The device supports only the command formats specified in Section 4.2.1. The device will ignore commands of any other format. If a CRC error is detected, or a reserved or un-implemented command is received, the device will not respond. Following all messages, the device requires a minimum inter-frame separation (tIFS). As long as the minimum inter-frame separation times defined in Section 4.2.1 are met, all supported commands are guaranteed to be executed, and the device will be ready for the next message. The device will respond as appropriate during the subsequent DSI transfer. Exactly one response is attempted. Table 11. DSI Bus Command Summary Command Command Format Description Data C3 C2 C1 C0 Hex 0 0 0 0 $0 Initialization D7 D6 D5 D4 D3 D2 D1 D0 Standard Long Only NV BS Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] 0 0 0 1 $1 0 0 1 0 $2 Request Status Standard/Enhanced L/S Read Acceleration Data Standard/Enhanced L/S 0 0 1 1 $3 Not Implemented 0 1 0 0 $4 Request ID Information 0 1 0 1 $5 Not Implemented 0 1 1 0 $6 Not Implemented 0 1 1 1 $7 Clear 1 0 0 0 $8 Not Implemented 1 0 0 1 $9 Read Write NVM Standard/Enhanced L WA[3] WA[2] WA[1] WA[0] 1 0 1 0 $A Format Control Standard/Enhanced L R/W FA[2] FA[1] FA[0] RD[3] RD[2] RD[1] RD[0] FD[3] FD[2] FD[1] 1 0 1 1 $B Read Register Data Standard/Enhanced L 0 0 0 FD[0] 0 RA[3] RA[2] RA[1] RA[0] 1 1 0 0 $C Disable Self-Test Standard/Enhanced L/S 1 1 0 1 $D Activate Self-Test Standard/Enhanced L/S 1 1 1 0 $E Not Implemented Not Implemented Not Implemented 1 1 1 1 $F Reverse Initialization Not Implemented Not Implemented Not Implemented Standard/Enhanced L/S Not Implemented Not Implemented Not Implemented Standard/Enhanced L/S Not Implemented Not Implemented Not Implemented Not Implemented MMA26xxNKW Sensors Freescale Semiconductor, Inc. 29 4.2.1.1 Initialization Command The initialization command conforms to the description provided in Section 6.1.1 of the DSI Bus Standard V2.5. The initialization command is only supported as a standard long command. No other commands are recognized by the device until a valid standard long initialization command is received. Table 12. Initialization Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] NV BS Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] A[3] A[2] A[1] A[0] 0 0 0 0 CRC 4 bits Table 13. Initialization Command Bit Definitions Bit Field Definition C[3:0] Initialization Command = `0000' A[3:0] DSI device address. This address is set to the preprogrammed device address following reset, or to `0000' if no preprogrammed address has been assigned. PA[3:0] DSI Address to be programmed. Bnk[1:0] These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation. Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for further details regarding register programming and bank selection. BS No bus switch is included in the device: 1 - the device is Reset. 0 - Normal Operation NV NVM Program Enable. This bit enables programming of the user-programmed OTP locations. Data to be programmed is transferred to the device during subsequent Read Write NVM commands. 1 - Enable OTP programming 0 - Disable OTP programming If the BS bit is set in the initialization command, the device will be reset within tBSOPEN. If the device has been preprogrammed, PA[3:0] and A[3:0] must match the preprogrammed address. If no device address has been previously programmed into the OTP array, PA[3:0] contains the device address, and A[3:0] must be zero. If either addressing condition is not met, the device address is not assigned, and the device will not respond to the Initialization command. If the addressing conditions are met, the new device address is assigned to A[3:0]. Once the device address is assigned, the new address (A[3:0]) is not protected by the User Programmable OTP Array CRC Verification. The User Programmable OTP array CRC is calculated and verified using the OTP programmed values of A[3:0] = `0000'. Once initialized, the device will no longer recognize or respond to Initialization commands. Table 14. Initialization Command Response Response D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] PA[3] PA[2] PA[1] PA[0] 0 0 0 BF NV 0 Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] CRC 4 bits Table 15. Initialization Response Bit Definitions Bit Field Definition PA[3:0] DSI device address. This field contains the device address. If the device is unprogrammed when the initialization command is issued, the device address is assigned. This field contains the programmed address. An Initialization command which attempts to assign a device address of zero is ignored. Bnk[1:0] These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation. Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for further details regarding register programming and bank selection. NV NVM Program Enable. This bit indicates if programming of the user-accessible OTP is enabled. 1 - OTP programming Enabled 0 - OTP programming Disabled BF This bit indicates the success or failure of the bus test performed as part of the Initialization command. 1 - Bus fault detected 0 - Bus test passed MMA26xxNKW 30 Sensors Freescale Semiconductor, Inc. 4.2.1.2 Request Status Command The Request Status command is supported in the following command formats: * Standard Long Command * Standard Short Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) * Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11) The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of `0000'. The data bits D[7:0] in the command are only used in the CRC calculation. Table 16. Request Status Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] A[3] A[2] A[1] A[0] 0 0 0 1 CRC 0 to 8 bits Table 17. Request Status Command Bit Definitions Bit Field Definition C[3:0] Request Status Command = `0001' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. D[7:0] Used for CRC calculation only Table 18. Short Response - Request Status Command Response D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 0 0 0 0 0 0 NV U ST 0 AT[1] AT[0] S 0 CRC 0 to 8 bits Table 19. Long Response - Request Status Command Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 0 0 0 NV U ST 0 AT[1] AT[0] S 0 CRC 0 to 8 bits Table 20. Request Status Response Bit Definitions Bit Field S AT[1:0] Definition This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. 0 - No Internal Error detected Reference Table 59 for conditions that set the S bit. Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2) ST This bit indicates whether internal self-test circuitry is active 1 - Self-test active 0 - Self-test disabled U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details. NV NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled. 1 - OTP programming Enabled 0 - OTP programming Disabled A[3:0] DSI device address. This field contains the device address. Shaded bits are transmitted to meet the response message length of the received message MMA26xxNKW Sensors Freescale Semiconductor, Inc. 31 4.2.1.3 Read Acceleration Data Command The Read Acceleration Data command is supported in the following command formats: * Standard Long Command * Standard Short Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) * Enhanced Short Command as configured by the Form at Control Command (Reference Section 4.2.1.11) The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of `0000'. The data bits D[7:0] in the command are only used in the CRC calculation. Table 21. Read Acceleration Data Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] A[3] A[2] A[1] A[0] 0 0 1 0 CRC 0 to 8 bits Table 22. Read Acceleration Data Command Bit Definitions Bit Field Definition C[3:0] Read Acceleration Data Command = `0010' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. D[7:0] Used for CRC calculation only Table 23. Short Response - Read Acceleration Data Command Response Response Length D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] AD[9] AD[9] AD[8] AD[8] AD[7] 8 9 D[5] D[4] D[3] D[2] AD[8] AD[7] AD[7] AD[6] AD[6] AD[5] D[1] D[0] AD[6] AD[5] AD[5] AD[4] AD[4] AD[3] AD[2] AD[3] AD[2] AD[1] AD[4] AD[3] AD[2] AD[1] AD[0] CRC 10 11 0 to 8 bits 12 13 14 15 AT_OTP[1] AT_OTP[0] ST 0 S AD[9] Table 24. Long Response - Read Acceleration Data Command Response D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 S AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] CRC 0 to 8 bits Table 25. Read Acceleration Response Bit Definitions Bit Field AD[9:0] S Definition 10-bit acceleration result produced by the device. This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. 0 - No Internal Error detected Reference Table 59 for conditions that set the S bit. ST This bit indicates whether internal self-test circuitry is active 1 - Self-test active 0 - Self-test disabled A[3:0] DSI device address. This field contains the device address. AT_OTP[1:0] Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2) Shaded bits are transmitted to meet the response message length of the received message The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the minimum acceleration value is transmitted as defined in Table 26. MMA26xxNKW 32 Sensors Freescale Semiconductor, Inc. Table 26. Acceleration Data Values 8-Bit Data Value 9-Bit Data Value 10-Bit Data Value Decimal Hex Decimal Hex Decimal Hex 255 0xFF 511 0x1FF 1023 0x3FF * * * * * * * * * * * * * * * * * * 131 0x83 259 0x103 515 0x203 130 0x82 258 0x102 514 0x202 129 0x81 257 0x101 513 0x201 128 0x80 256 0x100 512 0x200 127 0x7F 127 0x0FF 511 0x1FF 126 0x7E 126 0x0FE 510 0x1FE 125 0x7D 125 0x0FD 509 0x1FD * * * * * * * * * * * * * * * * * * Description Maximum positive acceleration value Positive acceleration values Typical 0 g level Negative acceleration values 1 1 1 1 1 1 Maximum negative acceleration value 0 0 0 0 0 0 Sensor Error 4.2.1.4 DSI Command #3 DSI Command `0011' is not implemented. The device ignores all command formats with a command ID of `0011'. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 33 4.2.1.5 Request ID Information Command The Request ID Information command is supported in the following command formats: * Standard Long Command * Standard Short Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) * Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11) The device ignores the Request ID Information command if the DSI device address is set to the DSI Global Device Address of `0000'. The data bits D[7:0] in the command are only used in the CRC calculation. Table 27. Request ID Information Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] A[3] A[2] A[1] A[0] 0 1 0 0 CRC 0 to 8 bits Table 28. Request ID Information Command Bit Definitions Bit Field Definition C[3:0] Request ID Information Data Command = `0100' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. D[7:0] Used for CRC calculation only Table 29. Short Response - Request ID Information Command Response D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 0 0 0 0 0 0 V2 V1 V0 0 1 1 1 0 CRC 0 to 8 bits Table 30. Long Response - Request ID Information Command Response D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 0 0 0 V[2] V[1] V[0] 0 DEVID 1 0 0 CRC 0 to 8 bits Table 31. Request ID Response Bit Definitions Bit Field D[4:0] = {1'b0,DEVID, 3'b100} Definition Device Identifier:`00100', or `01100' DEVID: Bit 7 of the DEVCFG regIster V[2:0] Version ID. This field indicates the device / silicon revision of the device. A[3:0] DSI device address. This field contains the device address. Shaded bits are transmitted to meet the response message length of the received message 4.2.1.6 DSI Command #5 DSI Command `0101' is not implemented. The device ignores all command formats with a command ID of `0101'. 4.2.1.7 DSI Command #6 DSI Command `0110' is not implemented. The device ignores all command formats with a command ID of `0110'. MMA26xxNKW 34 Sensors Freescale Semiconductor, Inc. 4.2.1.8 Clear Command The Clear command is supported in the following command formats: * Standard Long Command * Standard Short Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) * Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11) When the device successfully decodes a Clear Command, and the address field matches either the assigned device address (PA[3:0]) or the DSI Global address of `0000' the device logic is reset. Reference Section 3.6 for the initialization sequence following a Clear Command. The data bits D[7:0] in the command are only used in the CRC calculation. There is no response to the Clear Command. Table 32. Clear Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] A[3] A[2] A[1] A[0] 0 1 1 1 CRC 0 to 8 bits Table 33. Clear Command Bit Definitions Bit Field Definition C[3:0] Clear Command = `0111'. When a Clear Command is successfully decoded and the address field matches either the assigned device address or the DSI Global Device Address of `0000' the device logic is reset. Reference Section 3.6 for the initialization sequence following a Clear Command. A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field or the Global Device Address of `0000'. Otherwise, the command is ignored. D[7:0] Used for CRC calculation only 4.2.1.9 DSI Command #8 DSI Command `1000' is not implemented. The device ignores all command formats with a command ID of `1000'. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 35 4.2.1.10 Write NVM Command The Write NVM command is supported in the following command formats: * Standard Long Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the DSI Global Device Address of `0000'. The Write NVM command uses the nibble address definitions in Table 2 and summarized in Table 39. Table 34. Write NVM Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] WA[3] WA[2] WA[1] WA[0] RD[3] RD[2] RD[1] RD[0] A[3] A[2] A[1] A[0] 1 0 0 1 CRC 0 to 8 bits Table 35. Write NVM Command Bit Definitions Bit Field Definition C[3:0] Write NVM Command = `1001' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. RD[3:0] RD[3:0] contains the data to be written to the OTP location addressed by WA[3:0] when the NV bit is set. WA[3:0] WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set. Table 36. Long Response - Write NVM Command (NV = 1) Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] WA[3] WA[2] WA[1] WA[0] 1 1 Bnk[1] Bnk[0] RD[3] RD[2] RD[1] RD[0] CRC 0 to 8 bits Table 37. Long Response - Write NVM Command (NV = 0) Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 0 0 0 1 1 1 1 A[3] A[2] A[1] A[0] CRC 0 to 8 bits Table 38. Write NVM Response Bit Definitions Bit Field Bnk[1:0] A[3:0] Definition These bits provide the bank address selected in the Initialization command. DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. RD[3:0] RD[3:0] contains the contents of the registers addressed by WA[3:0] after the execution of the NVM write. WA[3:0] WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set. Writes to OTP occur only if the NV bit is set. The NV bit is set by the Initialization Command (reference Section 4.2.1.1). If the NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to change the Device Address, the new Device Address is returned. The DSI Bus idle voltage must exceed the minimum VPP voltage when programming the OTP array. No internal verification of the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back after writes to verify proper contents. The total Execution time for the Write NVM command is tPROG_BIT times the number of bits being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must accommodate this timing. Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regardless of the state of the NV bit and the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active (reference Section 3.2.2). MMA26xxNKW 36 Sensors Freescale Semiconductor, Inc. Table 39. OTP Register Nibble Address Assignments Bank Address Bnk[1] Bnk[0] Register Address (Nibble) WA[3] WA[2] WA[1] WA[0] x x 0 0 0 0 x x 0 0 0 1 x x 0 0 1 0 x x 0 0 1 1 x x 0 1 0 0 Register Description UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] x x 0 1 0 1 0 0 0 1 1 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 0 0 1 1 1 DEVCFG2[7] Only RD[3] is written to the LOCK_U bit 0 0 1 0 0 0 TYPE[7:6] Only RD[3:2] is written to LPF[1:0] 0 0 1 0 0 1 DEVCFG[3:0] RD[3] is written to DEVCFG[3] - UNUSED, RD[2:0] is written to CRC_U[2:0] 0 0 1 0 1 0 DEVCFG[7:4] RD[3:0] is written to DEVCFG[7:4] - UNUSED 0 0 1 0 1 1 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 0 1 1 0 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 0 1 1 0 1 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 0 1 1 1 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 0 1 1 1 1 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 1 0 1 1 0 DEVCFG1[3:0] RD[3:2] is written to UD00[1:0], RD[1:0] is written to AT[1:0] 0 1 0 1 1 1 DEVCFG2[3:0] RD[3:0] is written to ADDR[3:0] 0 1 1 0 0 0 UD01[3:0] RD[3:0] is written to UD01[3:0] 0 1 1 0 0 1 UD02[3:0] RD[3:0] is written to UD02[3:0] 0 1 1 0 1 0 UD03[3:0] RD[3:0] is written to UD03[3:0] 0 1 1 0 1 1 UD04[3:0] RD[3:0] is written to UD04[3:0] 0 1 1 1 0 0 UD05[3:0] RD[3:0] is written to UD05[3:0] 0 1 1 1 0 1 UD06[3:0] RD[3:0] is written to UD06[3:0] 0 1 1 1 1 0 UD07[3:0] RD[3:0] is written to UD07[3:0] 0 1 1 1 1 1 UD08[3:0] RD[3:0] is written to UD08[3:0] 1 0 0 1 1 0 DEVCFG1[7:4] RD[3:0] is written to UD00[5:2] 1 0 0 1 1 1 DEVCFG2[5] Only RD[1] is written to the PCM bit 1 0 1 0 0 0 UD01[7:4] RD[3:0] is written to UD01[7:4] 1 0 1 0 0 1 UD02[7:4] RD[3:0] is written to UD02[7:4] 1 0 1 0 1 0 UD03[7:4] RD[3:0] is written to UD03[7:4] 1 0 1 0 1 1 UD04[7:4] RD[3:0] is written to UD04[7:4] 1 0 1 1 0 0 UD05[7:4] RD[3:0] is written to UD05[7:4] 1 0 1 1 0 1 UD06[7:4] RD[3:0] is written to UD06[7:4] 1 0 1 1 1 0 UD07[7:4] RD[3:0] is written to UD07[7:4] 1 0 1 1 1 1 UD08[7:4] RD[3:0] is written to UD08[7:4] 1 1 0 1 1 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 0 1 1 1 DEVCFG2[6] Only RD[2] is written to the DEVCFG2[6] bit (UNUSED) 1 1 1 0 0 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 0 0 1 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 0 1 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 0 1 1 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 1 0 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 1 0 1 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 1 1 0 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 1 1 1 1 1 DEVCFG2[4] Only RD[0] is written to DEVCFG2[4] MMA26xxNKW Sensors Freescale Semiconductor, Inc. 37 4.2.1.11 Format Control Command The Format Control command is supported in the following command formats: * Standard Long Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) The device ignores the Format Control command if the command is in any other format. The device supports the Format Control command with the DSI Global Address of `0000', but does not provide a response. Table 40. Format Control Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] R/W FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] A[3] A[2] A[1] A[0] 1 0 1 0 CRC 0 to 8 bits Table 41. Format Control Command Bit Definitions Bit Field Definition C[3:0] Format Control Command = `1010' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. FD[3:0] Data to be written to the Format Control Register addressed by FA[2:0] if the R/W bit is set to `1'. FA[2:0] The Address of the Format Control Register to read or written. Read/Write determines if the register at address FA[2:0] is to be read or written. 1 - Write FD[3:0] to the Format Control Register addressed by FA[2:0] 0 - Read the Format Control Register addressed by FA[2:0] R/W Table 42. Long Response - Format Control Command Response D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 1 1 0 R/W FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] CRC 0 to 8 bits Table 43. Format Control Response Bit Definitions Bit Field FD[3:0] FA[2:0] Definition The contents of the Format Control Register addressed by FA[2:0]. The Address of the Format Control Register that was read or written. Read/Write indicates if the register at address FA[2:0] was read or written. 1 - FD[3:0] contains the data written to the Format Control Register addressed by FA[2:0] 0 - FD[3:0] contains the contents for the Format Control Register addressed by FA[2:0] R/W A[3:0] DSI device address. This field contains the device address. The format control registers defined in the DSI Bus Standard V2.5 are shown in Table 44. The reset values assigned to each register are also indicated. Table 44. Format Control Register Values Format Control Register Register Address Reset Values DSI Standard Values FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] FD[3] FD[2] FD[1] FD[0] CRC Polynomial - Low Nibble 0 0 0 0 0 0 1 0 0 0 1 CRC Polynomial - High Nibble 0 0 1 0 0 0 1 0 0 0 1 Definition CRC Polynomial = X4 + 1 Seed - Low Nibble 0 1 0 1 0 1 0 1 0 1 0 Seed - High Nibble 0 1 1 0 0 0 0 0 0 0 0 CRC Length (0 to 8) 1 0 0 0 1 0 0 0 1 0 0 CRC Length = 4 Short Word Data Length (8 to 15) 1 0 1 1 0 0 0 1 0 0 0 Short Command Length = 8 Seed = `1010' Reserved 1 1 0 0 0 0 0 0 0 0 0 N/A Format Selection 1 1 1 0 0 0 0 0 0 0 0 N/A MMA26xxNKW 38 Sensors Freescale Semiconductor, Inc. The following restrictions apply to format control register operations: * Writes to the CRC Length Register of values greater than 8 are ignored. The contents of the register are unchanged. * Writes to the Short Word Data Length register of values less than 8 are ignored. The contents of the register are unchanged. The contents of the Format Selection register determine whether the standard DSI values or the values in the format control registers are used. If the Format Selection register contains `1111', the Format Control register values are active. Any write to the Format Control registers will become active upon completion of the write. In this case, the response to a Format Control Command will maintain the format of the previous command resulting in an invalid response. A write of `0000' to the Format Selection register activates the standard DSI values. A write to the Format Selection register of any other value is ignored. 4.2.1.12 Read Register Data Command The Read Register Data command is supported in the following command formats: * Standard Long Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) The device ignores the Register Data command if the command is in any other format, or if the DSI device address is set to the DSI Global Device Address of `0000'. The read register command uses the byte address definitions shown in Table 2. Readable registers along with their Byte addresses are shown in Table 2. Table 45. Read Register Data Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] 0 0 0 0 RA[3] RA[2] RA[1] RA[0] A[3] A[2] A[1] A[0] 1 0 1 1 CRC 0 to 8 bits Table 46. Read Register Data Command Bit Definitions Bit Field Definition C[3:0] Read Register Data Command = `1011' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. RA[3:0] RA[3:0] contains the byte address of the register to be read. Table 47. Long Response - Read Register Data Command Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] RA[3] RA[2] RA[1] RA[0] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] CRC 0 to 8 bits Table 48. Read Register Data Response Bit Definitions Bit Field Definition RD7:0] RD[7:0] contains the data of the register addressed by RA[3:0]. RA[3:0] RA[3:0] contains the byte address of the register to be read. A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 39 4.2.1.13 Disable Self-Test Command The Disable Self-Test command is supported in the following command formats: * Standard Long Command * Standard Short Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) * Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11) The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self-Test command with the DSI Global Address of `0000', but does not provide a response. The Disable Self-Test Command removes the voltage from the self-test plate of the transducer which results in the acceleration output value returning to the 0g offset value within tST_DEACT_xxx, as specified in Section 2. Table 49. Disable Self-Test Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] A[3] A[2] A[1] A[0] 1 1 0 0 CRC 0 to 8 bits Table 50. Disable Self-Test Command Bit Definitions Bit Field Definition C[3:0] Disable Self-Test Command = `1100' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. D[7:0] Used for CRC calculation only Table 51. Short Response - Disable Self-Test Command Response D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 0 0 0 0 0 0 NV U ST 0 AT[1] AT[0] S 0 CRC 0 to 8 bits Table 52. Long Response - Disable Self-Test Command Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 0 0 0 NV U ST 0 AT[1] AT[0] S 0 CRC 0 to 8 bits Table 53. Disable Self-Test Response Bit Definitions Bit Field S AT[1:0] Definition This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. 0 - No Internal Error detected Reference Table 59 for conditions that set the S bit. Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2) ST This bit indicates whether internal self-test circuitry is active 1 - Self-test active 0 - Self-test disabled U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details. NV NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled. 1 - OTP programming Enabled 0 - OTP programming Disabled A[3:0] DSI device address. This field contains the device address. A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout is activated, the internal self-test circuitry is disabled until one of the following conditions occurs: * HCAP under-voltage * A Clear command is received * Internal regulator under-voltage resulting in a reset * A Frame Timeout resulting in a reset MMA26xxNKW 40 Sensors Freescale Semiconductor, Inc. 4.2.1.14 Enable Self-Test Command The Enable Self-Test command is supported in the following command formats: * Standard Long Command * Standard Short Command * Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11) * Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11) The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self-Test command when it is sent to the DSI Global Address of `0000'. The Enable Self-Test Command applies a voltage to the self-test plate of the transducer which results in a delta in the acceleration output value of DFLCT_xxx within tST_ACT_xxx, as specified in Section 2. This remains present until the Disable Self-Test command is received. Activation of the self-test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal self-test circuitry remains disabled, and the ST bit is cleared in the response. Self-test locking is described in Section 4.2.1.13. Table 54. Enable Self-Test Command Data Address Command D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0] A[3] A[2] A[1] A[0] 1 1 0 1 CRC 4 bits Table 55. Enable Self-Test Command Bit Definitions Bit Field Definition C[3:0] Enable Self-Test Command = `1101' A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is ignored. D[7:0] Used for CRC calculation only Table 56. Short Response - Enable Self-Test Command Response D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 0 0 0 0 0 0 NV U ST 0 AT[1] AT[0] S 0 CRC 4 bits Table 57. Long Response - Enable Self-Test Command Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] 0 0 0 0 NV U ST 0 AT[1] AT[0] S 0 CRC 4 bits Table 58. Enable Self-Test Response Bit Definitions Bit Field S AT[1:0] Definition This bit indicates whether the device has detected an internal device error. 1 - Internal Error detected. 0 - No Internal Error detected Reference Table 59 for conditions that set the S bit. Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2) ST This bit indicates whether internal self-test circuitry is active 1 - Self-test active 0 - Self-test disabled U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details. NV NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled. 1 - OTP programming Enabled 0 - OTP programming Disabled A[3:0] DSI device address. This field contains the device address. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 41 4.2.1.15 DSI Command #14 DSI Command `1110' is not implemented. The device ignores all command formats with a command ID of `1110'. 4.2.1.16 Reverse Initialization Command The Reverse Initialization Command is not implemented. The device ignores all command formats with a command ID of `1111'. 4.3 Exception Handling Table 59 summarizes the exception conditions detected by the device and the response for each exception. Table 59. Exception Handling Condition Description S ST U Response Exception Self-Test Request Power On Reset N/A Power Applied Clear Command VREG Under-Voltage N/A VREG < VPORCREG_f - Device held in Reset. - No response to DSI commands. - Device must be re-initialized when VREG returns above VPORCREG_r VREGA Under-Voltage N/A VREGA < VPORCREG_f - Device held in Reset. - No response to DSI commands. - Device must be re-initialized when VREGA returns above VPORCREGA_r 1 1 0 - Reference Section 3.6 Disabled VHCAP < VPORCREG_f for less than tHCAP_POR, ST Disabled 0 0 1 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = normal. - Device does not need to be re-initialized if VHCAP returns above VPORHCAP_r before tHCAP_POR Enabled VHCAP < VPORCREG_f for less than tHCAP_POR, ST Enabled 0 1 1 - DSI Read Acceleration Data Short response = self-test data. - DSI Read Acceleration Data Long response = self-test data. - Device does not need to be re-initialized if VHCAP returns above VPORHCAP_r before tHCAP_POR VHCAP Under-Voltage Transient VHCAP Under-Voltage N/A Capacitor Test Failure N/A DSI Frame Timeout N/A - Device is Reset and will continue to Reset every tHCAP_POR until VHCAP returns above VPORHCAP_r, or an internal supply under-voltage condition occurs. - No response to DSI commands. - Device must be re-initialized when VHCAP returns above VPORHCAP_r VHCAP < VPORCREG_f for longer than tHCAP_POR - Device is Reset and will continue to be reset every tPOR_CAPTEST until the capacitor failure is removed. - No response to DSI commands. - Device must be re-initialized when capacitor failure is removed. - Device is Reset and will continue to be reset every tTO until the BUSIN voltage returns above VTHF or a supply under-voltage condition occurs. - No response to DSI commands. - Device must be re-initialized when VBUSIN returns above VTHF VBUSIN < VTHF for longer than tTO Disabled CRC failure detected in factory programmed OTP array and the LOCK_F bit is set. ST Disabled 1 0 0 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = normal. Enabled CRC failure detected in factory programmed OTP array and the LOCK_F bit is set. ST Enabled 1 1 0 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = self-test data. Disabled CRC failure detected in User programmed OTP array and the 1 LOCK_U bit is set. ST Disabled 0 0 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = normal. Enabled CRC failure detected in User programmed OTP array and the 1 LOCK_U bit is set. ST Enabled 1 0 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = self-test data. Disabled Temperature out of range, ST Disabled. 1 0 0 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = normal. Enabled Temperature out of range, ST Enabled. 1 1 0 - DSI Read Acceleration Data Short response = zero. - DSI Read Acceleration Data Long response = self-test data. Self-Test Enabled Enabled ST Enabled 1 1 0 - Internal self-test circuitry enabled. - DSI Read Acceleration Data Short response = self-test data. - DSI Read Acceleration Data Long response = self-test data. Self-Test Lockout Disabled 2 consecutive Disable Self-Test DSI commands received. 0 0 0 - Internal self-test circuitry disabled. - Enable Self-Test DSI command does not enable Self-Test. Normal response to Enable Self-Test DSI command except the ST bit is not set. - DSI Clear command or Reset disables lockout. Fuse CRC Fault (Factory Array) Fuse CRC Fault (User Array) Temperature Out of Range MMA26xxNKW 42 Sensors Freescale Semiconductor, Inc. 5 Package 5.1 Case Outline Drawing Reference Freescale Case Outline Drawing # 98ASA00090D http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf 5.2 Recommended Footprint Reference Freescale Application Note AN3111, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf Table 60. Revision History Revision number Revision date 4 03/2012 Description of changes * Added SafeAssure logo, changed first paragraph and disclaimer to include trademark information. MMA26xxNKW Sensors Freescale Semiconductor, Inc. 43 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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