© Semiconductor Components Industries, LLC, 2008
October, 2008 − Rev. 25
1Publication Order Number:
NCV8509/D
NCV8509 Series
Sequenced Linear
Dual-Voltage Regulator
The NCV8509 Series are dual voltage regulators whose output
voltages power up in such a manner as to protect the integrity of
modern day microcontroller I/O and ESD input structures. Newer
generation microcontrollers require two power supplies. One voltage
is used for powering the core, while the other powers the I/O.
Features
•Power−Up Sequence
•Output Voltage Options:
♦VOUT1 5 V (±2%) 115 mA, VOUT2 2.6 V (2%) 100 mA
♦VOUT1 5 V (±2%) 115 mA, VOUT2 2.5 V (2%) 100 mA
♦VOUT1 3.3 V (±2%) 115 mA, VOUT2 1.8 V (2%) 100 mA
•Low 175 mA Quiescent Current
•Power Shunt
•Programmable RESET Time
•Dual Drive RESET Valid
•Programmable SLEW Rate Control
•Thermal Shutdown
•16 Lead SOW Exposed Pad
•NCV Prefix, for Automotive and Other Applications Requiring Site
and Change Control
•AEC Qualified
•PPAP Capable
•These are Pb−Free Devices
Typical Applications
•Automotive Powertrain
•Telematics
VIN1
VIN2
GND
VOUT1
VOUT2
SLEW
RESET
Delay
Microprocessor
NCV8509
VBAT
Figure 1. Application Diagram
REX
138 Ω
CSLEW
33 nF
CIN1
10 μF
CIN2
0.1 μF
CVOUT1
10 μF
CVOUT2
10 μF
CDelay
33 nF
RRESET
10 k
MRA4004T3
http://onsemi.com
PIN CONNECTIONS
MARKING DIAGRAM
xx = Voltage Ratings as Indicated
Below:
26 = 5 V/2.6 V
25 = 5 V/2.5 V
18 = 3.3 V/1.8 V
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Device
SOIC 16 LEAD
WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751AG
1
16
1
16
NCNC
116
VOUT2
NC
NCRESET
VIN2
NC
VIN1
NC
NCGND
VOUT1
Delay
NCSLEW
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
NCV8509xx
AWLYYWWG
http://onsemi.com
NCV8509 Series
http://onsemi.com
2
MAXIMUM RATINGS
Rating Value Unit
VIN1 (dc) −0.3 to 50 V
VIN1 Peak Transient Voltage 50 V
VIN2 (dc) 50 V
VIN2 (Current out of pin) 10 mA
Operating Voltage 50 V
Input Voltage Range (SLEW, RESET, Delay) −0.3 to 10 V
VOUT1 10 V
VOUT2 10 V
Electrostatic Discharge (Human Body Model)
(Machine Model)
4.0
400
kV
V
Package Thermal Resistance, SOW−16 E Pad: Junction−to−Case, RθJC
Junction−to−Ambient, RθJA
16
57
°C/W
°C/W
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 240 peak (Note 2) °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
2. −5°C/+0°C allowable conditions.
ELECTRICAL CHARACTERISTICS (6.0 V < VIN1 < 18 V, IVOUT1 = 5.0 mA, IVOUT2 = 5.0 mA, −40°C < TJ < 125°C,
CVOUT1 = CVOUT2 = 10 mF; unless otherwise noted.)
Characteristic Test Conditions Min Typ Max Unit
VOUT1
Output Voltage
5 V Option
3.3 V Option
1.0 mA < IVOUT1 < 100 mA
1.0 mA < IVOUT1 < 100 mA
4.9
3.234
5.0
3.3
5.1
3.366
V
V
Dropout Voltage (VIN1 − VOUT1) IOUT = 100 mA
IOUT = 100 μA
−
−
400
100
600
200
mV
mV
Load Regulation 1.0 mA < IVOUT1 < 100 mA −10 50 mV
Line Regulation 6.0 V < VIN1 < 18 V −10 50 mV
Current Limit VOUT1 = VOUT1 (typ) − 500 mV
VOUT1 = 0 V
115
−
305
105
610
300
mA
mA
VOUT2
Output Voltage
2.6 V Option
2.5 V Option
1.8 V Option
1.0 mA < IVOUT2 < 100 mA
1.0 mA < IVOUT2 < 100 mA
1.0 mA < IVOUT2 < 100 mA
2.548
2.450
1.764
2.6
2.5
1.8
2.652
2.550
1.836
V
V
V
Load Regulation 1.0 mA < IVOUT2 < 100 mA −5.0 50 mV
Line Regulation 6.0 V < VIN1 = VIN2 < 18 V −10 50 mV
Current Limit VOUT2 = VOUT2 (typ) − 500 mV
VOUT2 = 0 V
105
−
305
105
610
300
mA
mA
General
Quiescent Current IOUT1 = IOUT2 = 100 μA, VIN1 = 12 V
IOUT1 = IOUT2 = 50 mA, VIN1 = 14 V
−
−
125
5.0
175
10
μA
mA
Thermal Shutdown (Note 3) (Guaranteed by Design) 150 180 210 °C
3. Both outputs will turn off.
NCV8509 Series
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued) (6.0 V < VIN1 < 18 V, IVOUT1 = 5.0 mA, IVOUT2 = 5.0 mA, −40°C < TJ < 125°C,
CVOUT1 = CVOUT2 = 10 mF; unless otherwise noted.)
Characteristic Test Conditions Min Typ Max Unit
SLEW
SLEW Charging Current SLEW = 1.0 V 4.0 6.0 8.0 μA
VOUT1 SLEW Rate (Note 4)
5 V Option
3.3 V Option
CSLEW = 33 nF
−
−
710
469
−
−
V/s
V/s
VOUT2 SLEW Rate
2.6 V Option
2.5 V Option
1.8 V Option
CSLEW = 33 nF
−
−
−
370
355
256
−
−
−
V/s
V/s
V/s
SLEW Control Threshold (See Figure 53) 1.5 1.8 2.1 V
RESET
RESET Threshold Increasing
(Note 5)
−94.5 96.5 98.5 %
RESET Threshold Decreasing
5 V Option
3.3 V Option
2.6 V Option
2.5 V Option
1.8 V Option
−
4.5
2.97
2.34
2.25
1.62
4.73
3.12
2.46
2.36
1.70
0.965 × VOUT
0.965 × VOUT
0.965 × VOUT
0.965 × VOUT
0.965 × VOUT
V
V
V
V
V
RESET Output Low IRESET = 1.0 mA −0.1 0.4 V
RESET Output Peak Power Down (See Figure 41) −0.6 1.0 V
RESET Threshold Hysteresis
5 V Option
3.3 V Option
2.6 V Option
2.5 V Option
1.8 V Option
−
50
33
26
25
18
100
66
52
50
36
150
99
78
75
54
mV
mV
mV
mV
mV
Delay
Delay Switching Threshold −1.125 1.5 1.875 V
Delay Charge Current Delay = 1.0 V 4.0 6.0 8.0 μA
Delay Saturation Voltage VOUT1 Out of Regulation − − 0.1 V
Delay Discharge Current Delay = 5.0 V VOUT1 out of Regulation 10 − − mA
Output Tracking
Delta 1 [VOUT1 − VOUT2]
5 V Option
3.3 V Option
COUT1 = COUT2 , IOUT1 = IOUT2
COUT1 = COUT2 , IOUT1 = IOUT2
−
−
−
−
3.2
2.8
V
V
Delta 2 [VOUT2 − VOUT1] COUT1 = COUT2 , IOUT1 = IOUT2 − − 100 mV
Power Shunt
Shunt Voltage 1 (VIN2) VIN1 = 6.0 V, IOUT2 = 100 mA, No REX 3.3 −4.6 V
Shunt Voltage 2 (VIN2) VIN1 = 12 V, 1.0 mA < IOUT2 < 100 mA, No REX 3.25 4.5 5.75 V
4. Not a tested parameter.
5. RESET signal sensitive to VOUT1 and VOUT2.
NCV8509 Series
http://onsemi.com
4
PIN DESCRIPTION
Pin No. Symbol Description
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
SLEW
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Control for output rise time during power up. Requires capacitor to ground.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
2
ÁÁÁÁÁ
ÁÁÁÁÁ
Delay
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Timing capacitor for RESET function.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
4, 5, 7−9, 11, 14, 16
ÁÁÁÁÁ
ÁÁÁÁÁ
NC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
No connection.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
6
ÁÁÁÁÁ
ÁÁÁÁÁ
RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Active reset (accurate to VOUT > 1.0 V).
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
10
ÁÁÁÁÁ
ÁÁÁÁÁ
VOUT2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
100 mA output (±2% output voltage) for powering microprocessor core.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
12
ÁÁÁÁÁ
ÁÁÁÁÁ
VIN2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input voltage for VOUT2.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
13
ÁÁÁÁÁ
ÁÁÁÁÁ
VIN1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input voltage for VOUT1, and internal circuitry.
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
15
ÁÁÁÁÁ
ÁÁÁÁÁ
VOUT1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
100 mA output (±2% output voltage) for powering microprocessor I/O.
VOUT1
VIN1
+
+
+
−
VIN1
VIN2
CIN2
CIN1
Power Shunt
Bandgap
& Bias
GND
RESET
VOUT1
−
+
RESET Comp
VBG
VREF
CDelay
Delay
Delay
Discharge
Latch
+
−
−
+
SLEW
CSLEW
VREF
VOUT1
COUT1
VBG
VREF
VIN1
Error Amp
Thermal
Shutdown
+
+
+
−Error Amp
VOUT2
COUT2
VIN2
VREF
Start−Up
Current
Figure 2. Block Diagram
SLEW
Control
REX
VREF
Start−Up
Current
NCV8509 Series
http://onsemi.com
5
TYPICAL PERFORMANCE CHARACTERISTICS
−40
Voltage (V)
2.55
Temperature (°C)
2.59
2.60
2.61
2.62
2.63
2.64
2.65
−20
2.57
2.58
2.56
0 20 40 60 80 100 120 140
Figure 3. 2.6 V Output Voltage
−40
Voltage (V)
3.23
Temperature (°C)
3.31
3.32
3.33
3.34
3.35
3.36
3.37
−20
3.29
3.30
3.28
0 20 40 60 80 100 120 140
3.27
3.25
3.26
3.24
Figure 4. 3.3 V Output Voltage
−40
Voltage (V)
2.45
Temperature (°C)
2.49
2.50
2.51
2.52
2.53
2.54
2.55
−20
2.47
2.48
2.46
0 20 40 60 80 100 120 140
Figure 5. 2.5 V Output Voltage
−40
Voltage (V)
1.76
Temperature (°C)
1.81
1.82
1.83
1.84
−20
1.79
1.80
1.78
0 20 40 60 80 100 120 140
1.77
Figure 6. 1.8 V Output Voltage
−40
Voltage (V)
4.90
Temperature (°C)
4.98
5.00
5.02
5.04
5.06
5.08
5.10
−20
4.94
4.96
4.92
0 20 40 60 80 100 120 140
Figure 7. 5.0 V Output Voltage
IVOUT1 = 5 mA
IVOUT2 = 5 mA
IVOUT1 = 5 mA
IVOUT2 = 5 mA
IVOUT1 = 5 mA
IVOUT2 = 5 mA
IVOUT1 = 5 mA
IVOUT2 = 5 mA
IVOUT1 = 5 mA
IVOUT2 = 5 mA 1.8 V
0
VIN2 (VOLTS)
0
VIN1 (VOLTS)
2 4 6 8 10 12 14 16
Figure 8. VIN2 versus VIN1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Rex = ∞
2.5 V
2.6 V
NCV8509 Series
http://onsemi.com
6
TYPICAL PERFORMANCE CHARACTERISTICS
−40°C
0
IQ (mA)
0
IOUT1 (mA)
5101520 0
IQ (mA)
0
IOUT1 (mA)
10 20 30 40 50 60 70 80 90
Figure 9. IQ versus IOUT1 Figure 10. IQ versus IOUT1
25
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
125°C
25°C
100
2
4
6
8
10
12
−40°C
125°C
25°C
−40°C
0
IQ (mA)
0
IOUT2 (mA)
5101520 0
IQ (mA)
0
IOUT2 (mA)
10 20 30 40 50 60 70 80 90
Figure 11. IQ versus IOUT2 Figure 12. IQ versus IOUT2
25
0.2
0.4
0.6
0.8
1.0
1.2
125°C
25°C
100
0.5
1.0
1.5
2.0
2.5
3.0
−40°C
125°C
25°C
−40°C
0
IQ (mA)
0
IOUT1, IOUT2 (mA)
5101520 0
IQ (mA)
0
IOUT1, IOUT2 (mA)
10 20 30 40 50 60 70 80 90
Figure 13. IQ versus IOUT
(VOUT1 & VOUT2)
Figure 14. IQ versus IOUT
(VOUT1 & VOUT2)
25
0.5
1.0
1.5
2.0
2.5
125°C25°C
100
2
4
6
8
12
−40°C
125°C
25°C
10
14
NCV8509 Series
http://onsemi.com
7
TYPICAL PERFORMANCE CHARACTERISTICS
−40°C
0
VOUT1 (V)
0
VIN1 (V)
2468 0
VOUT1 (V)
0
VIN1 (V)
123456789
Figure 15. VOUT1 (5 V) versus VIN1 Figure 16. VOUT1 (3.3 V) versus VIN1
10
1
2
3
4
5
6
125°C 25°C
10
0.5
1.0
2.0
2.5
3.0
4.0
−40°C
125°C25°C
−40°C
0
VOUT2 (V)
0
VIN1 (V)
2468 0
VOUT2 (V)
0
VIN1 (V)
123456789
Figure 17. VOUT2 (2.6 V) versus VIN1 Figure 18. VOUT2 (2.5 V) versus VIN1
10
0.5
1.0
1.5
2.0
2.5
3.0
125°C25°C
10
0.5
1.0
1.5
2.0
2.5
3.0
−40°C
125°C25°C
−40°C
0
VOUT2 (V)
0
VIN1 (V)
2468
Figure 19. VOUT2 (1.8 V) versus VIN1
10
0.2
0.6
0.8
1.0
2.0
125°C 25°C
13579
1.5
3.5
13579
0.4
1.4
1.6
1.8
1.2
13579
NCV8509 Series
http://onsemi.com
8
TYPICAL PERFORMANCE CHARACTERISTICS
−40
RESET DELAY TIME (mS)
7.5
TEMPERATURE (°C)
−20 20 40 60 0
TIME (mS)
0
CDelay (nF)
20 40 60 80 100 120 140
Figure 20. Reset Delay Time versus
Temperature
Figure 21. Reset Delay Time versus CDelay
120
8.0
8.5
9.0
9.5
10
160
5
15
20
25
10
40
0
VOLTS/SEC
0
CSLEW (nF)
10 40 50 60
VOLTS/SEC
0
CSlew (nF)
30 40 50 60 70 80 90
Figure 22. Slew Rate versus CSlew Figure 23. Slew Rate versus CSlew
100
500
1000
1500
2000
2500
5 V
100
100
200
300
500
700
800
0 80 100
30
35
20 30 70 80 90
3.3 V
2.6 V
2.5 V
1.8 V
400
600
5 V
3.3 V
2.6 V
2.5 V
1.8 V
0
DROPOUT VOLTAGE (mV)
0
OUTPUT CURRENT (mA)
150
300
450
12525 50 75
3.3 V/1.8 V
5 V/2.6 V
0
QUIESCENT CURRENT (mA)
0
OUTPUT CURRENT (mA)
8
16
24 6 8 1012141618
Figure 24. VOUT1 Dropout Voltage Figure 25. Quiescent Current vs. VIN1
100
250
400
50
200
350
100
5 V/2.5 V
6
14
4
12
2
10
3.3 V/1.8 V
5 V/2.6 V
5 V/2.5 V
Iout1 = Iout2 = 50 mA
NCV8509 Series
http://onsemi.com
9
TYPICAL PERFORMANCE CHARACTERISTICS
STABLE REGION
0
ESR (W)
0.01
OUTPUT CURRENT (mA)
10
100
1000
10 10020 30 40 50 60 70 80 90
UNSTABLE
REGION
STABLE
REGION
CVOUT1 = 10 mF
3.3 V
5.0 V
0
ESR (W)
0.01
OUTPUT CURRENT (mA)
10
100
10 100
20 30 40 50 60 70 80 90
UNSTABLE
REGION
STABLE
REGION
CVOUT2 = 10 mF
2.5 V
2.6 V
1.8 V
Figure 26. VOUT1 Output Capacitor ESR (10 mF) Figure 27. VOUT2 Output Capacitor ESR (10 mF)
0.1
1
1
0.1
0
ESR (W)
0.01
OUTPUT CURRENT (mA)
10
100
1000
10 10020 30 40 50 60 70 80 90
STABLE
REGION
0
ESR (W)
0.01
OUTPUT CURRENT (mA)
10
100
10 10020 30 40 50 60 70 80 90
UNSTABLE
REGION
Figure 28. VOUT1 Output Capacitor ESR (0.1 mF / 1 mF) Figure 29. VOUT2 (2.6 V) Output Capacitor
ESR (0.1 mF / 1 mF)
0.1
1
1
0.1
0
ESR (W)
0.01
OUTPUT CURRENT (mA)
10
100
10 10020 30 40 50 60 70 80 90
Figure 30. VOUT2 (2.5 V) Output Capacitor
ESR (0.1 mF / 1 mF)
1
0.1
0
ESR (W)
0.01
OUTPUT CURRENT (mA)
10
100
10 10020 30 40 50 60 70 80 90
UNSTABLE
REGION
Figure 31. VOUT2 (1.8 V) Output Capacitor
ESR (0.1 mF / 1 mF)
1
0.1
3.3 V, 0.1 mF
UNSTABLE
REGION
3.3 V, 1.0 mF
5.0 V, 1.0 mF
5.0 V, 0.1 mF
UNSTABLE
REGION
1 mF
0.1 mF
1 mF
STABLE REGION
UNSTABLE
REGION
UNSTABLE
REGION
1 mF
0.1 mF
1 mF
UNSTABLE
REGION
STABLE
REGION 1 mF
1 mF
0.1 mF
0.1 mF
NCV8509 Series
http://onsemi.com
10
TYPICAL PERFORMANCE CHARACTERISTICS
(Load Transient waveforms shown were measured on the 5 V/2.6 V device)
Figure 32. VOUT1 Load Transient Response
100 mA to No Load & No Load to 100 mA
Figure 33. VOUT2 Load Transient Response
100 mA to No Load & No Load to 100 mA
Figure 34. VOUT1 Load Transient Response
100 mA to No Load
Figure 35. VOUT2 Load Transient Response
100 mA to No Load
Figure 36. VOUT1 Load Transient Response
No Load to 100 mA
Figure 37. VOUT2 Load Transient Response
No Load to 100 mA
NCV8509 Series
http://onsemi.com
11
TIMING DIAGRAMS
VIN1
VOUT1
VOUT2
Outputs are not actively discharged.
Figure 38. Response to Impulse
Figure 39. Output Decay vs. Load Impedance
VIN1
VOUT1
VOUT2
VIN1
VOUT1
VOUT2
VIN1
VOUT1
VOUT2
Z(VOUT1) << Z(VOUT2) Z(VOUT1) >> Z(VOUT2)
Figure 40. VIN Power Shunt
Max VIN Delta
I(VIN2) × REX
Power Shunt Off
Power Shunt On
VIN2
VIN1
4.5 V
NCV8509 Series
http://onsemi.com
12
CIRCUIT DESCRIPTION
Figure 41. Dual Drive RESET Valid
VIN
VOUT1
RESET
Power Up Short on
VOUT1
VIN1 Fast
Turn Off
RESET
Output Peak
Reset Delay Reset Delay Reset Delay
RESET
The RESET function gets its drive from both the input
(VIN1) and the output (VOUT1). Because of this, it is able to
maintain a more reliable reset valid signal. Most regulators
maintain a valid reset signal down to 1 V on the output
voltage. The reset on the NCV8509 is valid down to 0 V on
the output voltage VOUT1 (power is provided via VIN1) and
the reset on the NCV8509 is valid down to 0 V on the input
voltage VIN1 (power is provided via VOUT1). Refer to
Figure 41 for operation timing diagrams.
Delay Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The delay lead provides source current (typically 6.0 μA)
to the external delay capacitor during the following
proceedings:
1. During power up (once the regulation threshold
has been verified);
2. After a reset event has occurred and the device is
back in regulation.
The delay capacitor is discharged when the regulation
(RESET threshold) has been violated. This is a latched
incident. The capacitor will fully discharge and wait for the
device to regulate before going through the delay time event
again.
Power Shunt
REX routes some of the current used in the VOUT2 to a
second input pin (VIN2). This is accomplished by using an
internal shunt. A simplified version of this shunt is shown in
Figure 42. This has the effect of reducing the amount of
power dissipated on chip. The effects of choosing the
external resistor value are shown in Figure 43.
Selection of the optimum Rex resistor value can be done
using the following equation:
(Vin(max) *4.5)
Iout2(max)
When not using the power shunt, short VIN1 to VIN2.
NCV8509 Series
http://onsemi.com
13
Figure 42. Power Shunt
REX
VIN1
VIN2
VOUT2
Voltage
Regulator
Figure 43. Power On Chip
0
0
VIN
0.2
0.4
0.6
0.8
1.0
1.2
1.8
Watts
5 10152025
1.4
1.6
REX > 138
REX = 138
REX < 138
IOUT2 = 100 mA
Figure 44.
135 Ω
VIN1
18 V
VIN2
4.5 V
RLOAD
VOUT2
2.5 V
100 mA
135 Ω
VIN1
6.0 V
VIN2
3.1 V
RLOAD
VOUT2
2.5 V
21.5 mA
135 Ω
VIN1
6.0 V
VIN2
4.5 V
RLOAD
VOUT2
2.5 V
100 mA
78.5 mA
+
600 mV
−
Figure 45. Figure 46.
21.5 mA100 mA 21.5 mA
Why Use a Power Shunt?
The power shunt circuitry helps manage and optimize
power dissipation on the integrated circuit.
Figure 44 shows a 100 mA load. A 135 Ω resistor
dissipates 1.35 W as shown.
Without the power shunt, the 135 Ω resistor would run
into head room issues at 6.0 V and would only be able to
drive 21.5 mA as shown in Figure 45 before causing the
2.5 V output to collapse.
Figure 46 shows the power shunt circuitry adding the
current back in at low voltage operation. So the power is
moved off chip at high voltage where it is needed most.
To further clarify, Figure 47 shows the maximum allowed
resistor value (29 Ω) without the power shunt for 6.0 V
operation.
Figure 48 shows the scenario at high voltage. Only 290 mW
of power is dissipated off chip compared to Figure 44 with
1.35 W.
Figure 47.
29 Ω
VIN1
18 V
VIN2
15.1 V
RLOAD
VOUT2
2.5 V
100 mA
Figure 48.
29 Ω
VIN1
6.0 V
VIN2
3.1 V
RLOAD
VOUT2
2.5 V
100 mA
+
600 mV
−
100 mA 100 mA
NCV8509 Series
http://onsemi.com
14
Power Dissipation
NCV8509 has a power shunt circuit which reduces the
power on chip by utilizing an external resistor, REX. Thus
the power on chip, PIC, is equal to the total power, PT, minus
the power dissipated in the resistor PREX. Refer to Figure 49.
PIC +PTOTAL *PREX (1)
where
(2)
PTOTAL +(VIN1 *VOUT1) IOUT1
)(VIN1 *VOUT2)I
OUT2 )(VIN1 Iq)
and
PREX +(VIN1 *VIN2)I
OUT2 (3)
Figure 49.
NCV8509
Control
Circuitry
IOUT2 IOUT1
Iq
VOUT1
GND
VOUT2
Q3Q2
Q1
REX
VZ
VIN2
VIN1
Shunt
VSAT
+
−
ȧ
ȧ
ȥ
ȡ
Ȣ
IN1 SAT
VREF
VIN1 *(IOUT2 REX)
(4)
VIN2 +
for VIN1 t(VREF )VSAT)
for (VREF )VSAT)tVIN1 t(VREF )(IOUT2 REX))
for (VREF )(IOUT2 IOUT)) tVIN1
where VREF = VZ − VBE when Q1 is normally conducting.
Based on equation 3, the power in REX is dependent on
VIN2. (Increasing REX may require an increase in CIN2. A
careful system validation should be performed for stability).
The voltage on VIN2 is controlled by the shunt circuit, which
has three modes of operation, as seen in Figure 50.
Mode 1. At low battery VIN2 is equal to VIN1 minus the
saturation voltage of the shunt output NPN.
Mode 2. Once VIN1 rises above the reference voltage of
the shunt circuit, VIN2 will regulate at the VREF.
Mode 3. VIN2 would continue to regulate at VREF, but
since IOUT2 is not infinite, when VIN1 rises higher than the
reference voltage plus the voltage drop across the external
resistor REX, it will force VIN2 to be VIN1 − (IOUT2 × REX).
Equation 4 provides a summary for VIN2.
Combining equations 3 and 4 gives three different
equations for power across REX.
PMODE1 +(VSAT IOUT2)(5)
PMODE2 +(VIN1 *VREF) IOUT2 (6)
PMODE3 +IOUT22 REX (7)
NCV8509 Series
http://onsemi.com
15
Figure 50. VIN Shunt
Max VIN Delta
I(VIN2) × REX
Shunt Off
Shunt On
VIN2
VIN1
4.5 V
Mode 1
Mode 2
Mode 3
VIN1 tVREF )VSAT
VIN2 +VIN1 *VSAT
VREF )VSAT tVIN1 tVREF )(IOUT2 REX)
VIN2 +VREF
VIN1 uVREF )(IOUT2 REX)
VIN2 +VIN1 *(IOUT2 REX)
Figure 51. 16 Lead SOW (Exposed Pad), qJA as a
Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625, G−10/R−4
40
70
90
100
Thermal Resistance,
Junction to Ambient, RqJA, (°C/W)
0
Copper Area (mm2)
200 400 800
80
60
50
600
Once the value of PIC(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA +150C*TA
PIC
(8)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA
’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
RqJA +RqJC )RqCS )RqSA (9)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
NCV8509 Series
http://onsemi.com
16
VOUT1
VOUT2
Short On
VOUT1
Short On
VOUT2
≈ 10 μs
≈ 10 μs
Fast SLEW Rate >> Soft Start
Figure 52. Fault Response. Note the High SLEW Rate Coming Out of Fault Conditions.
Soft Start Only Applies to a Power Up Sequence.
Fast SLEW Rate >> Soft Start
Decay Time Dependent
on External Load
Decay Time Dependent
on External Load
Disable Time Disable Time
Slew Rate Control
Figure 53 shows the circuitry associated with Slew Rate
Control. The diagram highlights the control of one output for
simplicity. VOUT1 and VOUT2 are both controlled on the IC.
The slew rate capacitor (CSLEW) is charged with an
on−chip current source runing at 6.0 mA (typ.). Charging a
capacitor with a current source creates a linear voltage ramp
as shown in Figure 54.
The lowest voltage to the positive terminals of the
comparator (Error Amp) dominates the output voltage
(VOUT). Consequently, when CSLEW is fully discharged on
power up, it is the dominant factor on the positive terminal
and disables the output. The output (VOUT) follows the
linear ramp on the SLEW pin (after being gained up with R1
and R2) until VBG becomes the dominant voltage. This
occurs when SLEW = VBG + VD1 or approximately 1.8 V.
R1
+
+
−
VOUT
R2
Error Amp
SLEW
CSLEW
6.0 μA
Internal
Voltage
Rail ≈ 3.8 V
D2
VIN1
D1
VBG
Figure 53. Slew Control Circuitry
Slew time can be calculated using the standard capacitor
equation.
I+Cdv
dt ,t+C(DV)
I
Using a 33 nF capacitor, the slew time is:
t+(33 nF)(1.8 V)
6mA+9.9 ms
The corresponding slew rate for this is 1.8 V/9.9 ms =
182 V/s ON THE SLEW PIN.
To calculate the slew rate on outputs, you must multiply
by the gain set up by R1 and R2.
Av+VOUT
1.28 V
For a 5 V output, the gain would be:
Av+5V
1.28 V +3.9 VńV
assuming VBG = 1.28 V.
The resultant slew rate on the output is the slew rate on the
SLEW pin multiplied by the gain, or:
(182 Vńs) (3.9 VńV) +710 Vńs
Outputs in Regulation
Figure 54.
Time (ms)
SLEW Pin Voltage (V)
3.8
1.8
tSLEW
NCV8509 Series
http://onsemi.com
17
ORDERING INFORMATION
Device Output Voltage Package Shipping†
NCV8509PDW18G
3.3 V/1.8 V
SOIC 16 Lead
(Pb−Free)
47 Units/Rail
NCV8509PDW18R2G SOIC 16 Lead
(Pb−Free)
1000 Tape & Reel
NCV8509PDW25G
5 V/2.5 V
SOIC 16 Lead
(Pb−Free)
47 Units/Rail
NCV8509PDW25R2G SOIC 16 Lead
(Pb−Free)
1000 Tape & Reel
NCV8509PDW26G
5 V/2.6 V
SOIC 16 Lead
(Pb−Free)
47 Units/Rail
NCV8509PDW26R2G SOIC 16 Lead
(Pb−Free)
1000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV8509 Series
http://onsemi.com
18
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751AG−01
ISSUE A
G
−W−
−U−
P
M
0.25 (0.010) W
−T−
SEATING
PLANE
K
D16 PL
C
M
0.25 (0.010) TUW
S S
M
F
DETAIL E
DETAIL E
R x 45_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
J
M
14 PL
PIN 1 I.D.
8
1
16 9
TOP SIDE
0.10 (0.004) T
16
EXPOSED PAD 18
BACK SIDE
L
H
DIM
A
MIN MAX MIN MAX
INCHES
10.15 10.45 0.400 0.411
MILLIMETERS
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
H3.45 3.66 0.136 0.144
J0.25 0.32 0.010 0.012
K0.00 0.10 0.000 0.004
L4.72 4.93 0.186 0.194
M0 7 0 7
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
____
A
B
9
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.350
0.175
0.050
0.376
0.188
0.200
0.074
DIMENSIONS: INCHES
0.024 0.150
Exposed
Pad
C
L
C
L
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NCV8509/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
