ACPL-7970
Optically Isolated Sigma-Delta Modulator
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Description
The ACPL-7970 is a 1-bit, second-order sigma-delta (∑-)
modulator converts an analog input signal into a high-
speed data stream with galvanic isolation based on optical
coupling technology. The ACPL-7970 operates from a 5 V
power supply with dynamic range of 78 dB with an appro-
priate digital  lter. The di erential inputs of ±200 mV (full
scale ±320 mV) are ideal for direct connection to shunt
resistors or other low-level signal sources in applications
such as motor phase current measurement.
The analog input is continuously sampled by a means of
sigma-delta over-sampling using an on-board clock. The
signal information is contained in the modulator data, as a
density of ones with data rate of 10 MHz, and the data are
encoded and transmitted across the isolation boundary
where they are recovered and decoded into high-speed
data stream of digital ones and zeros. The original signal
information can be reconstructed with a digital  lter. The
serial interface for data and clock has a wide supply range
of 3 V to 5.5 V.
Combined with superior optical coupling technology,
the modulator delivers high noise margins and excellent
immunity against isolation-mode transients. With 0.5 mm
minimum distance through insulation (DTI), the ACPL-7970
provides reliable reinforced insulation and high working
insulation voltage, which is suitable for fail-safe designs.
This outstanding isolation performance is superior to
alternatives including devices based on capacitive- or
magnetic-coupling with DTI in micro-meter range. O ered
in a DIP-8 package, the isolated ADC delivers the reliabil-
ity, small size, superior isolation and over-temperature
performance motor drive designers need to accurately
measure current at much lower price compared to tradi-
tional current transducers.
The external clock version modulator ACPL-796J (SO-16
package) is also available.
Features
 10 MHz internal clock
 1-bit, second-order sigma-delta modulator
 16 bits resolution no missing codes (12 bits ENOB)
 78 dB SNR
 6 V/°C maximum o set drift
 ±1% maximum gain error
 Internal reference voltage
 ±200 mV linear range with single 5 V supply (±320 mV
full scale)
 3 V to 5.5 V wide supply range for digital interface
 -40° C to +105° C operating temperature range
 25 kV/s common-mode transient immunity
 Safety and regulatory approvals:
– IEC/EN/DIN EN 60747-5-5: 891 Vpeak working
insulation voltage
– UL 1577: 5000 Vrms/1min isolation voltage
– CSA: Component Acceptance Notice #5
Applications
 Motor phase and rail current sensing
 Power inverter current and voltage sensing
 Industrial process control
 Data acquisition systems
 General purpose current and voltage sensing
 Traditional current transducer replacements
Functional Block Diagram
3-$
MODULATOR/
ENCODER
VIN+
SHIELD
VIN–
BUF
VREF
LED
DRIVER
CLK
DECODER
GND1
VDD1
MDAT
MCLK
VDD2
GND2
2
Pin Con guration and Descriptions
Figure 1. Pin con guration.
VDD1 1
2
3
4
8
7
6
5
VIN+
VIN–
GND1
VDD2
MCLK
MDAT
GND2
ACPL-7970
Table 1. Pin descriptions.
Pin No. Symbol Description
1V
DD1 Supply voltage for signal input side (analog side), relative to GND1
2V
IN+ Positive analog input, recommended input range ±200 mV
3V
IN– Negative analog input, recommended input range ±200 mV (normally connected to GND1)
4 GND1 Supply ground for signal input side
5 GND2 Supply ground for data/clock output side (digital side)
6 MDAT Modulator data output
7 MCLK Modulator clock output
8V
DD2 Supply voltage for data output side, relative to GND2
Table 2. Ordering Information
ACPL-7970 is UL recognized with 5000 Vrms/1 minute rating per UL 1577.
Part number
Option (RoHS
Compliant) Package
Surface
Mount Gull Wing Tape & Reel
IEC/EN/DIN EN
60747-5-5 Quantity
ACPL-7970 -000E 300 mil
DIP-8
X 50 per tube
-300E X X X 50 per tube
-500E X X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-7970-500E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval and RoHS compliance.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawings
Standard DIP Package
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A 7970
YYWW
DATE CODE
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
Dimensions in millimeters and (inches).
Note:
Floating lead protrusion is 0.5 mm (20 mils) max.
5678
4321
5˚ TYP.
0.20 (0.008)
0.33 (0.013)
6.35 ± 0.25
(0.250 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
Note: Initial or continued variation in the color of the white mold compound is normal and does not a ect device performance or reliability.
Figure 2.
4
Gull Wing Surface Mount Option 300
Dimensions in millimeters (inches).
Tolerances (unless otherwise specified): xx.xx = 0.01 Lead coplanarity
xx.xxx = 0.005 Maximum: 0.102 (0.004)
Note: Foating lead protrusion is 0.5 mm (20 mils) max.
5
6
7
8
4
3
2
1
A 7970
YYWW
6.350 ± 0.25
(0.025 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010) 1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
12° NOM.
0.20 (0.008)
0.33 (0.013)
0.635 ± 0.25
(0.025 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
Figure 3.
Regulatory Information
The ACPL-7970 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
Approved with Maximum Working Insulation Voltage
VIORM = 891 Vpeak.
UL
Approval under UL 1577, component recognition program
up to VISO = 5000 Vrms/1min. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
Recommended Pb-Free IR Pro le
Recommended re ow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
5
Table 3. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics [1]
Description Symbol Value Units
Installation classi cation per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 V rms
for rated mains voltage ≤ 600 Vrms
I-IV
I-IV
I-IV
I-IV
Climatic Classi cation 55/105/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 891 Vpeak
Input to Output Test Voltage, Method b
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR 1671 Vpeak
Input to Output Test Voltage, Method a
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR 1426 Vpeak
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 Vpeak
Safety-limiting values
(Maximum values allowed in the event of a failure)
Case Temperature
Input Current [2]
Output Power [2]
TS
IS,INPUT
PS,OUTPUT
175
400
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS≥ 109
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.
2. Safety-limiting parameters are dependent on ambient temperature. The Input Current, IS,INPUT, derates linearly above 25° C free-air temperature at
a rate of 2.67 mA/°C; the Output Power, PS,OUTPUT, derates linearly above 25° C free-air temperature at a rate of 4 mW/°C.
Table 4. Insulation and Safety Related Speci cations
Parameter Symbol Value Units Conditions
Minimum External Air Gap
(External Clearance)
L(101) 7.4 mm Measured from input terminals to output terminals, shortest
distance through air
Minimum External Tracking
(External Creepage)
L(102) 8.0 mm Measured from input terminals to output terminals, shortest
distance path along body
Minimum Internal Plastic Gap
(Internal Clearance)
0.5 mm Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter and
photodetector inside the optocoupler cavity
Tracking Resistance
(Comparative Tracking Index)
CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
6
Table 5. Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS-55 +125 °C
Ambient Operating Temperature TA-40 +105 °C
Supply Voltage VDD1, VDD2 -0.5 6.0 V
Steady-State Input Voltage [1, 3] VIN+, VIN– -2 VDD1 + 0.5 V
Two-Second Transient Input Voltage [2] VIN+, VIN– -6 VDD1 + 0.5 V
Digital Output Voltages MCLK, MDAT -0.5 VDD2 + 0.5 V
Lead Solder Temperature 260° C for 10 sec., 1.6 mm below seating plane
Notes:
1. DC voltage of up to -2 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
2. Transient voltage of 2 seconds up to -6 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.
Table 6. Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Ambient Operating Temperature TA-40 +105 °C
VDD1 Supply Voltage VDD1 4.5 5.5 V
VDD2 Supply Voltage VDD2 3 5.5 V
Input Voltage Range [1] VIN+, VIN– -200 +200 mV
Notes:
1. Full scale input range ±320 mV.
7
Table 7. Electrical Speci cations
Unless otherwise noted, TA = -40° C to +105° C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = -200 mV to +200 mV, and
VIN– = 0 V (single-ended connection); tested with Sinc3 lter, 256 decimation ratio.
Parameter Symbol Min. Typ.[1] Max. Units Test Conditions/Notes Fig.
STATIC CHARACTERISTICS
Resolution 16 Bits Decimation  lter output set to 16 bits
Integral Nonlinearity INL -15 3 15 LSB TA = -40° C to +85° C; see De nitions
section
-25 3 25 LSB TA = 85° C to 105° C
Di erential Nonlinearity DNL -0.9 0.9 LSB No missing codes, guaranteed by
design; see De nitions section
O set Error VOS -2 0.4 2 mV TA = -40° C to +105° C;
see De nitions section
5
O set Drift vs. Temperature TCVOS 26V/°C VDD1 = 5 V
O set Drift vs. VDD1 220 V/V
Internal Reference Voltage VREF 320 mV
Reference Voltage Tolerance GE-1 1 % TA = 25° C, VIN+ = -320 to +320 mV;
see De nitions section
-2 2 % TA = -40° C to +105° C,
VIN+ = -320 to +320 mV
6
VREF Drift vs. Temperature TCGE60 ppm/°C
VREF Drift vs. VDD1 -1.3 mV/V Note 4
ANALOG INPUTS
Full-Scale Di erential Voltage
Input Range
FSR 320 mV VIN = VIN+ – VIN–; Note 2
Average Input Bias Current IINA -0.3 AVDD1 = 5V, VDD2 = 5V, VIN+ = 0 V;
Note 3
7
Average Input Resistance RIN 24 kAcross VIN+ or VIN– to GND1; Note 3
Input Capacitance CINA 8 pF Across VIN+ or VIN– to GND1
DYNAMIC CHARACTERISTICS VIN+ = 400 mVpp, 1 kHz sine wave
Signal-to-Noise Ratio SNR 68 78 dB TA = -40° C to +105° C;
see De nitions section
8
Signal-to-(Noise + Distortion)
Ratio
SNDR 65 75 dB TA = -40° C to +105° C;
see De nitions section
9
E ective Number of Bits ENOB 12 Bits see De nitions section
Isolation Transient Immunity CMR 25 kV/sVCM = 1 kV; See De nitions section
Common-Mode Rejection Ratio CMRR 74 dB
DIGITAL OUTPUTS
Output High Voltage VOH VDD2 –
0.2
VDD2 –
0.1
VIOUT = -200 A
Output Low Voltage VOL 0.6 V IOUT = +1.6 mA
POWER SUPPLY
VDD1 Supply Current IDD1 914mA V
IN+ = –320 mV to +320 mV 10
VDD2 Supply Current IDD2 5.2 8 mA VDD2 = 5 V supply 11
4.6 7 mA VDD2 = 3.3 V supply 12
Notes:
1. All Typical values are at TA = 25° C, VDD1 = 5 V, VDD2 = 5 V.
2. Beyond the full-scale input range the data output is either all zeroes or all ones.
3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
4. VREF Drift vs. VDD1 can be expressed as –0.4%/V with reference to VREF.
8
Table 8. Timing Speci cations
Unless otherwise noted, TA = -40° C to +105° C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions/Notes Fig.
Modulator Clock Output Frequency fMCLK 9 10 11 MHz Clock duty cycle 40% to 60% 13
Data Access Time After MCLK Rising Edge tA40 ns CL = 15 pF 4
Data Hold Time After MCLK Rising Edge tH10 ns CL = 15 pF 4
Figure 4. Data timing.
Table 9. Package Characteristics
Parameter Symbol Min. Typ. Max. Unit Test Condition Note
Input-Output Momentary Withstand
Voltage
VISO 5000 Vrms RH < 50%, t = 1 min; TA = 25° C 1, 2
Input-Output Resistance RI-O 1012 1013 VI-O = 500 VDC 3
1011 TA = 100° C 3
Input-Output Capacitance CI-O 1.4 pF f = 1 MHz 3
Notes:
1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 A). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-
5-5 Insulation Characteristic Table.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 insulation characteristics table and your equipment level
safety speci cation.
3. This is a two-terminal measurement: pins 1–4 are shorted together and pins 5–8 are shorted together.
tA
MCLK
MDAT
tH
9
Typical Performance Plots
Unless otherwise noted, TA = 25° C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = –200 mV to +200 mV, and VIN– = 0 V, with Sinc3 lter,
256 decimation ratio.
Figure 5. O set change vs. temperature. Figure 6. VREF change vs. temperature
Figure 7. Input current vs. input voltage. Figure 8. SNR vs. temperature.
Figure 9. SNDR vs. temperature. Figure 10. IDD1 vs. VIN DC input at various temperatures.
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)
VOS (mV)
305
310
315
320
325
330
335
-55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)
VREF (mV)
-30
-20
-10
0
10
20
30
-400 -320 -240 -160 -80 0 80 160 240 320 400
VIN+ (mV)
IIN+ (MA)
66
68
70
72
74
76
78
80
82
84
86
-55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)
SNR (dB)
66
68
70
72
74
76
78
80
82
84
86
-55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)
SNDR (dB)
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
-400 -300 -200 -100 0 100 200 300 400
VIN (mV)
IDD1 (mA)
25° C
-40° C
105° C
10
Figure 13. Clock frequency vs. temperature for various VDD1.
Figure 11. IDD2 (VDD2 = 5 V) vs. VIN DC input at various temperatures. Figure 12. IDD2 (VDD2 = 3.3V) vs. VIN DC input at various temperatures.
2.0
3.0
4.0
5.0
6.0
7.0
8.0
-400 -300 -200 -100 0 100 200 300 400
VIN (mV)
IDD2 (mA)
25° C
-40° C
105° C
VDD2 = 5 V
2.0
3.0
4.0
5.0
6.0
7.0
8.0
-400 -300 -200 -100 0 100 200 300 400
25°C
-40°C
105°C
VIN (mV)
IDD2 (mA)
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
-55 -35 -15 5 25 45 65 85 105 125
4.5V
5V
5.5V
Temperature (°C)
Clock Frequency (MHz)
VDD2 = 3.3 V
11
De nitions
Integral Nonlinearity (INL)
INL is the maximum deviation of a transfer curve from a
straight line passing through the endpoints of the ADC
transfer function, with o set and gain errors adjusted
out.
Di erential Nonlinearity (DNL)
DNL is the deviation of an actual code width from the ideal
value of 1 LSB between any two adjacent codes in the ADC
transfer curve. DNL is a critical speci cation in closed-loop
applications. A DNL error of less than ±1 LSB guarantees
no missing codes and a monotonic transfer function.
O set Error
O set error is the deviation of the actual input voltage
corresponding to the mid-scale code (32,768 for a 16-bit
system with an unsigned decimation  lter) from 0 V. O set
error can be corrected by software or hardware.
Gain Error (Full-Scale Error)
Gain error includes positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error
is the deviation of the actual input voltage correspond-
ing to positive full-scale code (65,535 for a 16-bit system)
from the ideal di erential input voltage (VIN+ – VIN– =
+320 mV), with o set error adjusted out. Negative full-
scale gain error is the deviation of the actual input voltage
corresponding to negative full-scale code (0 for a 16-bit
system) from the ideal di erential input voltage (VIN+ –
VIN– = -320 mV), with o set error adjusted out. Gain error
includes reference error. Gain error can be corrected by
software or hardware.
Signal-to-Noise Ratio (SNR)
The SNR is the measured ratio of AC signal power to noise
power below half of the sampling frequency. The noise
power excludes harmonic signals and DC.
Signal-to-(Noise + Distortion) Ratio (SNDR)
The SNDR is the measured ratio of AC signal power to
noise plus distortion power at the output of the ADC. The
signal power is the rms amplitude of the fundamental
input signal. Noise plus distortion power is the rms sum
of all non-fundamental signals up to half the sampling
frequency (excluding DC).
E ective Number of Bits (ENOB)
The ENOB determines the e ective resolution of an ADC,
expressed in bits, de ned by ENOB = (SNDR − 1.76)/6.02
Isolation Transient Immunity (CMR)
The isolation transient immunity (also known as Common-
Mode Rejection or CMR) speci es the minimum rate-of-
rise/fall of a common-mode signal applied across the
isolation boundary beyond which the modulator clock or
data is corrupted.
Product Overview
Description
The ACPL-7970 isolated sigma-delta (∑-) modulator
converts an analog input signal into a high-speed (10
MHz typical) single-bit data stream by means of a sigma-
delta over-sampling modulator. The time average of the
modulator data is directly proportional to the input signal
voltage. The modulator uses internal clock of 10 MHz. The
modulator data are encoded and transmitted across the
isolation boundary where they are recovered and decoded
into high-speed data stream of digital ones and zeros. The
original signal information is represented by the density
of ones in the data output.
The other main function of the modulator (optocoupler)
is to provide galvanic isolation between the analog signal
input and the digital data output. It provides high noise
margins and excellent immunity against isolation-mode
transients that allows direct measurement of low-level
signals in highly noisy environments, for example mea-
surement of motor phase currents in power inverters.
With 0.5 mm minimum DTI, the ACPL-7970 provides
reliable double protection and high working insulation
voltage, which is suitable for fail-safe designs. This out-
standing isolation performance is superior to alternatives
including devices based on capacitive- or magnetic-
coupling with DTI in micro-meter range. O ered in an
DIP-8 package, the isolated ADC delivers the reliability,
small size, superior isolation and over-temperature perfor-
mance motor drive designers need to accurately measure
current at much lower price compared to traditional
current transducers.
12
Analog Input
The di erential analog inputs of the ACPL-7970 are im-
plemented with a fully-di erential, switched-capacitor
circuit. The ACPL-7970 accepts signal of ±200 mV (full
scale ±320 mV), which is ideal for direct connection to
shunt based current sensing or other low-level signal
sources applications such as motor phase current mea-
surement. An internal voltage reference determines the
full-scale analog input range of the modulator (±320 mV);
an input range of ±200 mV is recommended to achieve
optimal performance. Users are able to use higher input
range, for example ±250 mV, as long as within full-scale
range, for purpose of over-current or overload detection.
Figure 14 shows the simpli ed equivalent circuit of the
analog input.
In the typical application circuit (Figure 19), the ACPL-7970
is connected in a single-ended input mode. Given the
fully di erential input structure, a di erential input con-
nection method (balanced input mode as shown in Figure
15) is recommended to achieve better performance. The
input currents created by the switching actions on both of
the pins are balanced on the  lter resistors and cancelled
out each other. Any noise induced on one pin will be
coupled to the other pin by the capacitor C and creates
only common mode noise which is rejected by the device.
Typical values for Ra (= Rb) and C are 22 and 10 nF re-
spectively.
Latch-up Consideration
Latch-up risk of CMOS devices needs careful consider-
ation, especially in applications with direct connection to
signal source that is subject to frequent transient noise.
The analog input structure of the ACPL-7970 is designed
to be resilient to transients and surges, which are often
encountered in highly noisy application environments
such as motor drive and other power inverter systems.
Other situations could cause transient voltages to the
inputs include short circuit and overload conditions. The
ACPL-7970 is tested with DC voltage of up to -2 V and
2-second transient voltage of up to -6 V to the analog
inputs with no latch-up or damage to the device.
Modulator Data Output
Input signal information is contained in the modulator
output data stream, represented by the density of ones
and zeros. The density of ones is proportional to the input
signal voltage, as shown in Figure 16. A di erential input
signal of 0 V ideally produces a data stream of ones and
zeros in equal densities. A di erential input of -200 mV
corresponds to 18.75% density of ones, and a di eren-
tial input of +200 mV is represented by 81.25% density of
ones in the data stream. A di erential input of +320 mV or
higher results in ideally all ones in the data stream, while
input of -320 mV or lower will result in all zeros ideally.
Table 5 shows this relationship.
Figure 14. Analog input equivalent circuit. Figure 15. Simpli ed di erential input connection diagram.
200 7(TYP)
3 pF (TYP)
3 pF (TYP)
fSWITCH
= MCLK
VIN+
VIN–
200 7(TYP)
1.5 pF
1.5 pF
COMMON MODE
VOLTAGE
fSWITCH
= MCLK
ANALOG
GROUND ACPL-7970
5 V
+Analog Input
–Analog Input
Ra
Rb C
VIN+
VIN–
VDD1
GND1
–FS (ANALOG INPUT)
+FS (ANALOG INPUT)
0 V (ANALOG INPUT)
TIME
MODULATOR OUTPUT
ANALOG INPUT
Figure 16. Modulator output vs. analog input.
13
Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input Voltage Input Density of 1s ADC Code (16-bit unsigned decimation)
Full-Scale Range 640 mV
+Full-Scale +320 mV 100% 65,535
+Recommended Input Range +200 mV 81.25% 53,248
Zero 0 mV 50% 32,768
–Recommended Input Range -200 mV 18.75% 12,288
–Full-Scale -320 mV 0% 0
Notes:
1. With bipolar o set binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation  lter.
ACPL-7970
3-WIRE
SERIAL
INTERFACE
INPUT
CURRENT
RSHUNT
VIN+
VIN–
VDD1
GND1
ISOLATED
5 V
0.1 MF
MCLK
MDAT
VDD2
GND2
NON-
ISOLATED
5 V/3.3 V
1 MF
SINC3 FILTER
CLOCK
DATA
GND
VDD
SCLK
SDAT
CS
ISOLATION
BARRIER
GND1 GND2
1 MF
0.1
MF
Digital Filter
A digital  lter converts the single-bit data stream from
the modulator into a multi-bit output word similar to
the digital output of a conventional A/D converter. With
this conversion, the data rate of the word output is also
reduced (decimation). A Sinc3 lter is recommended to
Note: In applications, 1 F/0.1 F bypass capacitors are recommended to connect between pins VDD1 and GND1,
and between pins VDD2 and GND2 of the ACPL-7970.
Figure 17. Typical application circuit with a Sinc3 lter.
work together with the ACPL-7970. With 256 decimation
ratio and 16-bit word settings, the output data rate is 39
kHz (= 10 MHz/256). This  lter can be implemented in an
ASIC, an FPGA or a DSP. Some of the ADC codes with cor-
responding input voltages are shown in Table 5.
14
Figure 18. Typical application circuit with the HCPL-0872.
ACPL-7970
3-WIRE
SERIAL
INTERFACE
INPUT
CURRENT
RSHUNT
VIN+
VIN–
VDD1
GND1
ISOLATED
5 V
0.1 MF
MCLK
MDAT
VDD2
GND2
NON-
ISOLATED
5 V
1 MF
HCPL-0872
MCLK1
MDAT1
GND
VDD
SCLK
SDAT
CS
ISOLATION
BARRIER
GND1 GND2
1 MF
0.1
MF
Digital Interface IC
The HCPL-0872 Digital Interface IC (SO-16 package) is a
digital  lter that converts the single-bit data stream from
the modulator into 15-bit output words and provides a
serial output interface that is compatible with SPI, QSPI,
and Microwire protocols, allowing direct connection to a
microcontroller. Instead of a digital  lter implemented in
software, the HCPL-0872 can be used together with the
ACPL-7970 to form an isolated programmable two-chip
A/D converter.
Available in an SO-16 surface-mount package, the Digital
Interface IC has features include  ve di erent conversion
modes (combinations of speed and resolution), three
di erent pre-trigger modes (allows conversion time < 1 s),
o set calibration, fast over-range (over-current, or short
circuits) detection, and adjustable threshold detection.
Figure 19. Typical application circuit for motor phase current sensing.
Programmable features are con gured via the Serial Con-
guration port. A second multiplexed input is available to
allow measurements with a second isolated modulator
without additional hardware. Refer to the HCPL-0872 data
sheet for details.
Notes:
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
Application Information
Digital Current Sensing Circuit
Figure 19 shows a typical application circuit for motor
control phase current sensing. By choosing the appro-
priate shunt resistance, a wide range of current can be
monitored, from less than 1 A to more than 100 A.
FLOATING
POSITIVE SUPPLY
RSENSE
VIN+
VIN–
VDD1
GND1
MCLK
MDAT
VDD2
GND2
NON-
ISOLATED
5 V/3.3 V
C3a
0.1 μF
ISOLATION
BARRIER
GATE
DRIVE
CIRCUIT
HV+
HV–
D1
5.1 V
C2
10 nF
MOTOR
R2a 22 Ω
+–
ACPL-7970GND1GND2
C1b 0.1 μF
R1
C1a 1 μF
C3b
1 μF
R2b 22 Ω
15
Power Supplies and Bypassing
As shown in Figure 19, a  oating power supply (which in
many applications could be the same supply that is used
to drive the high-side power transistor) is regulated to
5 V using a simple zener diode (D1); the value of resistor
R1 should be chosen to ensure su cient current can be
supplied from the existing  oating supply. The voltage
from the current sensing resistor or shunt (RSENSE) is
applied to the input of the ACPL-7970 through an RC anti-
aliasing  lter (R2 and C2). And  nally, a clock is connected
to the ACPL-7970 and data are connected to the digital
lter. Although the application circuit is relatively simple,
a few recommendations should be followed to ensure
optimal performance.
The power supply for the isolated modulator is most often
obtained from the same supply used to power the power
transistor gate drive circuit. If a dedicated supply is required,
in many cases it is possible to add an additional winding
on an existing transformer. Otherwise, some sort of simple
isolated supply can be used, such as a line powered trans-
former or a high-frequency DC-DC converter.
An inexpensive 78L05 three terminal regulator can also be
used to reduce the  oating supply voltage to 5 V. To help
attenuate high-frequency power supply noise or ripple, a
resistor or inductor can be used in series with the input of
the regulator to form a low-pass  lter with the regulator’s
input bypass capacitor.
As shown in Figure 19, bypass capacitors (C1a, C1b, C3a
and C3b) should be located as close as possible to the
input and output power-supply pins of the isolated
modulator. The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
isolated modulator. A bypass capacitor (C2) is also recom-
mended at the input due to the switched-capacitor nature
of the input circuit. The input bypass capacitor also forms
part of the anti-aliasing  lter, which is recommended to
prevent high frequency noise from aliasing down to lower
frequencies and interfering with the input signal.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away from
input signals, the use of ground and power planes, etc. In
addition, the layout of the PCB can also a ect the isolation
transient immunity (CMR) of the isolated modulator, due
primarily to stray capacitive coupling between the input
and the output circuits. To obtain optimal CMR perfor-
mance, the layout of the PC board should minimize any
stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the isolated modulator.
Shunt Resistors
The current-sensing shunt resistor should have low re-
sistance (to minimize power dissipation), low inductance
(to minimize di/dt induced voltage spikes which could
adversely a ect operation), and reasonable tolerance (to
maintain overall circuit accuracy). Choosing a particu-
lar value for the shunt is usually a compromise between
minimizing power dissipation and maximizing accuracy.
Smaller shunt resistances decrease power dissipation,
while larger shunt resistances can improve circuit accuracy
by utilizing the full input range of the isolated modulator.
The  rst step in selecting a shunt is determining how
much current the shunt will be sensing. The graph in
Figure 20 shows the RMS current in each phase of a three-
phase induction motor as a function of average motor
output power (in horsepower, hp) and motor drive supply
voltage. The maximum value of the shunt is determined
by the current being measured and the maximum recom-
mended input voltage of the isolated modulator. The
maximum shunt resistance can be calculated by taking
the maximum recommended input voltage and dividing
by the peak current that the shunt should see during
normal operation. For example, if a motor will have a
maximum RMS current of 10 A and can experience up to
50% overloads during normal operation, then the peak
current is 21.1 A (= 10 x 1.414 x 1.5). Assuming a maximum
input voltage of 200 mV, the maximum value of shunt
resistance in this case would be about 10 m.
The maximum average power dissipation in the shunt
can also be easily calculated by multiplying the shunt re-
sistance times the square of the maximum RMS current,
which is about 1 W in the previous example.
Figure 20. Motor Output Horsepower vs. Motor Phase Current and Supply.
MOTOR PHASE CURRENT - A (rms)
15
40
0
35
25
10
30
20
5
53530020251510
MOTOR OUTPUT POWER - HORSEPOWER
440 V
380 V
220 V
120 V
16
If the power dissipation in the shunt is too high, the resis-
tance of the shunt can be decreased below the maximum
value to decrease power dissipation. The minimum value
of the shunt is limited by precision and accuracy require-
ments of the design. As the shunt value is reduced, the
output voltage across the shunt is also reduced, which
means that the o set and noise, which are  xed, become
a larger percentage of the signal amplitude. The selected
value of the shunt will fall somewhere between the
minimum and maximum values, depending on the par-
ticular requirements of a speci c design.
When sensing currents large enough to cause signi -
cant heating of the shunt, the temperature coe cient
(tempco) of the shunt can introduce nonlinearity due to
the signal dependent temperature rise of the shunt. The
e ect increases as the shunt-to-ambient thermal resis-
tance increases. This e ect can be minimized either by
reducing the thermal resistance of the shunt or by using
a shunt with a lower tempco. Lowering the thermal resis-
tance can be accomplished by repositioning the shunt
on the PC board, by using larger PC board traces to carry
away more heat, or by using a heat sink.
For a two-terminal shunt, as the value of shunt resistance
decreases, the resistance of the leads becomes a signi -
cant percentage of the total shunt resistance. This has two
primary e ects on shunt accuracy. First, the e ective resis-
tance of the shunt can become dependent on factors such
as how long the leads are, how they are bent, how far they
are inserted into the board, and how far solder wicks up
the lead during assembly (these issues will be discussed
in more detail shortly). Second, the leads are typically
made from a material such as copper, which has a much
higher tempco than the material from which the resistive
element itself is made, resulting in a higher tempco for the
shunt overall. Both of these e ects are eliminated when a
four-terminal shunt is used. A four-terminal shunt has two
additional terminals that are Kelvin-connected directly
across the resistive element itself; these two terminals are
used to monitor the voltage across the resistive element
while the other two terminals are used to carry the load
current. Because of the Kelvin connection, any voltage
drops across the leads carrying the load current should
have no impact on the measured voltage.
Several four-terminal shunts from Isotek (Isabellenhütte)
suitable for sensing currents in motor drives up to 71 Arms
(71 hp or 53 kW) are shown in Table 11; the maximum
current and motor power range for each of the PBV series
shunts are indicated. For shunt resistances from 50 m
down to 10 m, the maximum current is limited by the
input voltage range of the isolated modulator. For the 5
mand 2 mshunts, a heat sink may be required due to
the increased power dissipation at higher currents.
When laying out a PC board for the shunts, a couple of
points should be kept in mind. The Kelvin connections to
the shunt should be brought together under the body
of the shunt and then run very close to each other to the
input of the isolated modulator; this minimizes the loop
area of the connection and reduces the possibility of stray
magnetic  elds from interfering with the measured signal.
If the shunt is not located on the same PC board as the
isolated modulator circuit, a tightly twisted pair of wires
can accomplish the same thing.
Also, multiple layers of the PC board can be used to increase
current carrying capacity. Numerous plated-through vias
should surround each non-Kelvin terminal of the shunt to
help distribute the current between the layers of the PC
board. The PC board should use 2 or 4 oz. copper for the
layers, resulting in a current carrying capacity in excess of
20 A. Making the current carrying traces on the PC board
fairly large can also improve the shunt’s power dissipa-
tion capability by acting as a heat sink. Liberal use of vias
where the load current enters and exits the PC board is
also recommended.
Table 11. Isotek (Isabellenhütte) four-terminal shunt summary.
Shunt Resistor
Part Number
Shunt
Resistance Tol.
Maximum
RMS Current
Motor Power Range
120 Vac – 440 Vac
m% A hp kW
PBV-R050-0.5 50 0.5 3 0.8-3 0.6-2
PBV-R020-0.5 20 0.5 7 2-7 1.4-5
PBV-R010-0.5 10 0.5 14 4-14 3-10
PBV-R005-0.5 5 0.5 25 (28) 7-25 (8-28) 5-19 (6-21)
PBV-R002-0.5 2 0.5 39 (71) 11-39 (19-71) 8-29 (14-53)
Note: Values in brackets are a heatsink for the shunt.
17
Shunt Connections
The recommended method for connecting the isolated
modulator to the shunt resistor is shown in Figure 19. VIN+
of the ACPL-7970 is connected to the positive terminal of
the shunt resistor, while VIN– is shorted to GND1, with the
power-supply return path functioning as the sense line to
the negative terminal of the current shunt. This allows a
single pair of wires or PC board traces to connect the isolated
modulator circuit to the shunt resistor. By referencing the
input circuit to the negative side of the sense resistor, any
load current induced noise transients on the shunt are
seen as a common-mode signal and will not interfere with
the current-sense signal. This is important because the
large load currents  owing through the motor drive, along
with the parasitic inductances inherent in the wiring of the
circuit, can generate both noise spikes and o sets that are
relatively large compared to the small voltages that are
being measured across the current shunt.
If the same power supply is used both for the gate drive
circuit and for the current sensing circuit, it is very important
that the connection from GND1 of the isolated modulator
to the sense resistor be the only return path for supply
current to the gate drive power supply in order to eliminate
potential ground loop problems. The only direct connec-
tion between the isolated modulator circuit and the gate
drive circuit should be the positive power supply line.
In some applications, however, supply currents  owing
through the power-supply return path may cause o set
or noise problems. In this case, better performance may
be obtained by connecting VIN+ and VIN– directly across
the shunt resistor with two conductors, and connecting
GND1 to the shunt resistor with a third conductor for the
power-supply return path, as shown in Figure 21. When
connected this way, both input pins should be bypassed.
To minimize electromagnetic interference of the sense
signal, all of the conductors (whether two or three are
used) connecting the isolated modulator to the sense
resistor should be either twisted pair wire or closely
spaced traces on a PC board.
The resistor R2 in series with the input lead forms a low
pass anti-aliasing  lter with the input bypass capacitor
C2. The resistor performs another important function
as well; it dampens any ringing which might be present
in the circuit formed by the shunt, the input bypass
capacitor, and the inductance of wires or traces connect-
ing the two. Undamped ringing of the input circuit near
the input sampling frequency can alias into the baseband
producing what might appear to be noise at the output
of the device.
FLOATING
POSITIVE SUPPLY
GATE
DRIVE
CIRCUIT
D1
5.1 V
C1b 0.1 μF
R1
C1a 1 μF
VIN+
VIN–
VDD1
GND1
MCLK
MDAT
VDD2
GND2
NON-
ISOLATED
5 V/3.3 V
C3a
0.1 μF
ISOLATION
BARRIER
ACPL-7970GND1GND2
C3b
1 μF
C2a
10nF
R2a 22 Ω
R2b 22 Ω
RSENSE
HV+
HV–
MOTOR
+– C2b
10nF
Figure 21. Schematic for three conductor shunt connection.
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Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-2856EN - July 18, 2012
Voltage Sensing
The ACPL-7970 can also be used to isolate signals with
amplitudes larger than its recommended input range
with the use of a resistive voltage divider at its input. The
only restrictions are that the impedance of the divider be
relatively small (less than 1 k) so that the input resistance
(24 k) and input bias current (0.3 A) do not a ect the
accuracy of the measurement. An input bypass capacitor
is still required, although the damping resistor is not
(the resistance of the voltage divider provides the same
function). The low-pass  lter formed by the divider resis-
tance and the input bypass capacitor may limit the achiev-
able bandwidth. To obtain higher bandwidth, the input
bypass capacitor (C2) can be reduced, but it should not be
reduced much below 1000 pF to maintain adequate input
bypassing of the isolated modulator.