LM10520
LM10520 Single-Phase Buck Controller for AVS Systems
Literature Number: SNVS638
LM10520
November 2, 2010
Single-Phase Buck Controller for AVS Systems
General Description
The LM10520 is a single-phase Energy Management Unit
(EMU) that actively reduces system-level power consumption
by utilizing a continuous, real-time, closed-loop Adaptive Volt-
age Scaling (AVS) scheme. The AVS technology enables
optimum energy management delivery to the load in order to
maximize system-level energy savings.
The LM10520 operates cooperatively with PowerWise®
AVS-compatible ASICs, SoCs, and processors to optimize
supply voltages adaptively over process and temperature
variations. The device is controlled via the high-speed serial
PWI 2.0 open-standard interface. It also supports Dynamic
Voltage Scaling (DVS) using frequency-voltage pairs from
pre-characterized lookup tables.
The LM10520 features a fixed-frequency voltage-mode PWM
control architecture which is adjustable from 50 kHz to 1MHz
with one external resistor. In addition, the LM10520 allows the
switching frequency to be synchronized to an external clock
signal over the range of 250 kHz to 1MHz. This wide range of
switching frequency gives the power supply designer the flex-
ibility to make better tradeoffs between component size, cost
and efficiency.
Features include the ability to startup with a pre-biased load
on the output, soft-start, input under-voltage lockout (UVLO)
and Power good (based on both under-voltage and over-volt-
age detection). In addition, the soft-start pin can be used for
implementing precise tracking, for the purpose of sequencing
with respect to an external rail.
Key Specifications
Features
■Typical power savings with AVS: 20 to 50%
■PWI 2.0 interface
■7-bit AVS control for one output (typical range of 0.6V to
1.2V)
■Precision enable
■Integrated, non-overlapping NFET drivers
■Switching frequency over 50 kHz to 1MHz
■Switching frequency synchronize range from 250 kHz to
1MHz
■Startup into pre-biased output
■Power Stage input from 1V to 14V
■Control stage input from 3V to 6V
■Power Good flag and shutdown
■Output over-voltage and under-voltage detection
■Low-side adjustable current sensing
■Adjustable soft start
■Tracking and sequencing with shutdown and soft-start
pins
■eTSSOP-28 package
Applications
■AVS-Enabled FPGAs
■AVS-Enabled ASICs
© 2010 National Semiconductor Corporation 301106 www.national.com
LM10520 Single-Phase Buck Controller for AVS Systems
Typical Application Circuit
30110601
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LM10520
Connection Diagram
30110602
28-Lead Plastic TSSOP
NS Package Number MTC28
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LM10520
Pin Descriptions
Number Pad Name Type Pad Description
DAP GND Connect Die Attach Pad to ground
1 BOOT Analog Boot cap voltage. Connect boot capacitor to this pin.
2 LG Output Low Side MOSFET gate drive.
3 PGND GND Power ground.
4 VCC Power 5V bias input
5 PWGD GND Power good signal
6 ISEN Analog Current limit sense
7 VIN Power High voltage bias input
8 NC No Connect
9 VCC5 Power 5V bias output
10 FLT_N I/O External fault input, active low. Causes output to be disabled and
resets R0 (output voltage register)
11 VDD Power Digital circuitry bias
12 ADDR Analog Connect a resistor from this to ground to set the PWI address
13 ENBIAS Input Enable for digital circuitry
14 CONTROL Input Enable for output voltage
15 IOUT1 Analog Connect this pin the FB pin
16 RESET_N Input Digital circuitry reset, active low
17 CNTL_EN Output Digital circuitry output which control Vout enable/disable
18 VPWI Power PWI I/O bias input
19 SPWI I/O PWI signal
20 SCLK Output PWI clock
21 ON/OFF Input Enable for internal 5V LDO
22 EAO Analog Error amp output
23 SS/TRACK Analog Connecting a capacitor to ground will set the softstart time.
Optionally, if this pin is driven externally the output will track the
voltage at this pin
24 FB Feedback connection
25 FREQ/SYNC Analog Connecting a resistor from this pin to ground will set the switching
frequency. Alternatively, a clock source can drive this pin, and the
LM10520 will synchronize to the clock frequency.
26 SD Input Shutdown for the analog circuitry
27 PGND GND Power ground
28 HG Analog High side MOSFET drive
Order Information
Order Number Package Marking Supplied As
LM10520MH NOPB LM10520 48 Units on Rail
LM10520MHE NOPB LM10520 250 Units on Tape and Real
LM10520MHX NOPB LM10520 2500 Units on Tape and Real
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LM10520
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ON/OFF, VIN -0.3V to 16V
VCC -0.3V to 6V
LG, PGND, SGND, PWGD, HG,
SD, FB, SS/TRACK, EAO, FREQ/
SYNC -0.3V to VCC + 0.3V
BOOT -0.3V to 18V
ISEN -0.3V to 14V
VPWI -0.2V to VDD
SPWI, SCLK -0.2 to VPWI
All other pins -0.2V to 6V
Junction Temperature 150°C
Storage Temperature -45°C to 150°C
ESD Tolerance (Note 2)
Human Body Model 1.5 kV
Soldering Information
See product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Operating Ratings
VIN 3.5V to 16V
VCC, VDD 3V to 5.5V
VPWI 1.6V to 3.6V
BOOT Voltage 1V to 17V
Junction Temperature -40°C to 125°C
Note: VPWI cannot be higher than
VDD
Thermal Properties
Junction-to-Ambient Thermal
Resistance 26°C/W
Electrical Characteristics
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design,
test, or statistical analysis.
Symbol Parameter Conditions Min Typ Max Units
VFB FB Pin Voltage VCC = 3V to 6V 0.591 0.6 0.609 V
VON UVLO Thresholds VCC Rising
VCC Falling
2.79
2.42
V
IQ
Operating VCC/VDD Current
VCC = 3.3V, VSD = 3.3V
fSW = 600 kHz, VCC connected to
VDD
2.15 2.71
mA
VCC = VDD = 5V, VSD = 5V
fSW = 600 kHz 2.315 3.01
Shutdown VCC/VDD Current VCC = VDD = 3.3V,
VSD = EN_BIAS= 0V
2.5 13 µA
Shutdown VIN Current ON/OFF = 0V 0.05 2
tPWGD1 PWGD Pin Response Time VFB Rising 10 µs
tPWGD2 PWGD Pin Response Time VFB Falling 10 µs
ISS-ON SS Pin Source Current VSS = 0V 710 14 µA
ISS-OC SS Pin Sink Current During Over
Current
VSS = 2.0V 90 µA
ISEN-TH ISEN Pin Source Current Trip Point 25 40 55 µA
IFB FB Pin Current Sourcing 20 nA
IADDR Address pin source current 7.8 µA
IAVS
LSB DAC Step size IDAC-MAX / 2n (1 ≤ n ≤ 7) 470 nA
Resolution 7 Bits
FS Full Scale 56.69 µA
INL Integral Non-Linearity −2 2 LSB
DNL Differential Non-Linearity −0.5 0.5
ZE Zero Code Error/Offset Error 57 nA
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LM10520
Symbol Parameter Conditions Min Typ Max Units
ERROR AMPLIFIER
GBW Error Amplifier Unity Gain Bandwidth 9 MHz
G Error Amplifier DC Gain 118 dB
SR Error Amplifier Slew Rate 2 V/µs
IEAO EAO Pin Current Sourcing and
Sinking Capability
14
16
mA
VEAO Error Amplifier Output Voltage Minimum 1 V
Maximum 2.2 V
GATE DRIVE
IQ-BOOT BOOT Pin Quiescent Current VBOOT = 12V, VSD = 0 18 90 µA
RHG_UP High-Side MOSFET Driver Pull-Up
ON resistance VBOOT = 5V @ 350 mA Sourcing 2.7 Ω
RHG_DN High-Side MOSFET Driver Pull-
Down ON resistance 350 mA Sinking 0.8 Ω
RLG_UP Low-Side MOSFET Driver Pull-Up
ON resistance VBOOT = 5V @ 350 mA Sourcing 2.7 Ω
RLG_DN Low-Side MOSFET Driver Pull-
Down ON resistance 350 mA Sinking 0.8 Ω
OSCILLATOR
fSW
PWM Frequency
RFADJ = 750 kΩ 50 kHz
RFADJ = 100 kΩ 300
RFADJ = 42.2 kΩ475 600 725
RFADJ = 18.7 kΩ 1000
LM10520 External Synchronizing
Signal Frequency Voltage Swing = 0V to VCC 250 1000
SYNCL
LM10520 Synchronization Signal
Low Threshold fSW = 250 kHz to 1 MHz 1V
SYNCH
LM10520 Synchronization Signal
High Threshold fSW = 250 kHz to 1 MHz 2 V
DMAX Max High-Side Duty Cycle fSW = 300 kHz
fSW = 600 kHz
fSW = 1 MHz
86
78
67
%
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LM10520
Symbol Parameter Conditions Min Typ Max Units
LOGIC AND CONTROL INPUTS
EN_BIASTH Precision enable threshold Rising 1.32 1.4 V
Falling 1.09 1.19
IIL Input Current Low FLT_N, RESET_N −10 µA
ENBIAS, CONTROL −1
SPWI, SCLK −1
IIH Input Current High FLT_N, RESET_N 1µA
ENBIAS, CONTROL 10
SPWI, SCLK 5
VIL Input Low Voltage CONTROL, FLT_N, RESET_N 0.5 V
VIH Input High Voltage CONTROL, FLT_N, RESET_N 1.1
VIL PWI Input Low Voltage, PWI SPWI, SCLK, 1.5 < VPWI < 3.3 30 % of
VPWI
VIH PWI Input High Voltage, PWI SPWI, SCLK, 1.5 < VPWI < 3.3 70
fSCLK PWI2 SCLK **DC useful for testing/debug 0 15M Hz
VSTBY-IH Standby High Trip Point VFB = 0.575V, VBOOT = 3.3V
VSD Rising
1.1 V
VSTBY-IL Standby Low Trip Point VFB = 0.575V, VBOOT = 3.3V
VSD Falling
0.232 V
VSD-IH SD Pin Logic High Trip Point VSD Rising 1.3 V
VSD-IL SD Pin Logic Low Trip Point VSD Falling 0.8 V
LOGIC AND CONTROL OUTPUTS
VOL Output Low Level CNTL_EN, ISINK ≤ 1mA 0.4 V
VOH Output High Level CNTL_EN, ISINK ≤ 1mA VDD - 0.4
VOH PWI Output High Level, PWI SPWI, ISOURCE ≤ 1mA VPWI -
0.4
VPWGD-TH-LO PWGD Pin Trip Points VFB Falling 0.408 0.434 0.457 V
VPWGD-TH-HI PWGD Pin Trip Points VFB Rising 0.677 0.710 0.742 V
VPWGD-HYS PWGD Hysteresis VFB Falling
VFB Rising
60
90
mV
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device
operates correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: ESD using the human body model which is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
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LM10520
Typical Performance Characteristics
Internal Reference Voltage vs Temperature
30110658
Frequency vs Temperature
30110660
Output Voltage vs Output Current
30110656
Switch Waveforms
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 3A, CSS = 12 nF, fSW = 1MHz
30110646
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LM10520
Start-Up (Full-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 3A, CSS = 12 nF, fSW = 1MHz
30110648
Start-Up (No-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
CSS = 12 nF, fSW = 1MHz
30110649
Shutdown (Full-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 3A, CSS = 12 nF, fSW = 1MHz
30110650
Load Transient Response
PVIN = 12V, AVIN = 4.5V,
VOUT = 1.2V, FSW = 300 kHz
30110653
Line Transient Response (VIN = 3V to 9V)
VCC = 3.3V, VOUT = 1.2V
IOUT = 2A, fSW = 1 MHz
30110654
Frequency vs. Frequency Adjust Resistor
30110655
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LM10520
Maximum Duty Cycle vs Frequency
VCC = 3.3V
30110692
Maximum Duty Cycle vs VCC
fSW = 600 kHz
30110693
Maximum Duty Cycle vs VCC
fSW = 1 MHz
30110694
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LM10520
Block Diagram
30110603
LM10520 PWI Register Map
The PWI 2.0 standard defines 32 8-bit base registers, and up to 256 8-bit extended registers, on each PWI slave. The table below
summarizes these registers and shows default register bit values after reset, as programmed by the factory. The following sub-
sections provide additional details on the use of each individual register.
SUMMARY
Base Registers
Register
Address
Register
Name
Register Usage Type Reset Default Value
7 6 5 4 3 2 1 0
0x00 R0 IAVS R/W 0* Configured by R9
0x03 R3 R/O 0 0 0 0 1 1 1 FLT_N
0x04 R4 Device Capability R/O 0 0 0 0 0 0 1 0
0x09 R9 IAVS Default R/W I AVS Default Code
0x0A R10 Ramp Control R/W 1 0 0 1 1 1 0 0
0x0F R15 Revision ID N/A 0 0 0 0 0 0 0 0
0x1F R31 Reserved
Do not write to
R/W - - - - - - - -
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LM10520
Note: A bit with an asterisk (*) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. A bit with a hyphen (-)
denotes a bit in an unimplemented register location. A write into unimplemented register(s) will be ignored. A read of an unimplemented register(s)
will produce a “No response frame”. Please refer to PWI specification version 2.0 for further information.
R0 - IAVS
AVS Feedback Current Injection
Address 0x00
Type R/W
Reset Default 8h'7F
Bit Field Name Description or Comment
7 Sign This bit is fixed to '0'. Reading this bit will result in a '0'. Any data written into this bit
position using the Register Write command is ignored.
6:0 IAVS Sourcing Current Programmed voltage value. Default value is in bold.
Current Data Code [6:0] Current (µA)
7h'00 60
7h'xx Linear Scaling
7h'7F 0 (default)
R3 - Status
LM10520 Status
Address 0x03
Type R/O
Reset Default –
Bit Field Name Description or Comment
7:4 Not Used Always read back 0
3:1 Not Used Always read back 1
0 FLT_N 1: FLT_N is high (no fault)
0: FLT_N is low (fault)
R4 - Device Capability Register
Address 0x04
Type R/O
Reset Default 8h'02
Bit Field Name Description or Comment
7:3 Always read back 0
2:0 Always read back 010, specifying PWI 2.0
R9 - IAVS Default Register
Address 0x09
Type R/W
Reset Default 8h'7F
Bit Field Name Description or Comment
7 Sign Always read back 0.
6:0 IAVS Default Current Data Code [6:0] Current (µA)
7h'00 60
7h'xx Linear Scaling
7h'7F 0 (default)
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LM10520
R10 - Ramp Control
Address 0x0A
Type R/W
Reset Default 8h'9C
Bit Field Name Description or Comment
7 Ramp Control Enable 1: Enabled
0: Disabled
6 Not Used Always read 0
5:3 Ramp Time Step Control Ramp Time Step Control Ramp Time Step (µs)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
6
8
12
16
2:0 Ramp Code Step Control Ramp Code Step Rising Step
(LSB)
Falling Step
(LSB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
6
8
12
16
1
1
2
3
4
5
6
8
R15 - Revision ID Register
Address 0x7F
Type R/O
Reset Default 8h'00
Bit Field Name Description or Comment
7:0 Always read back 0
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LM10520
Application Information
The device is a PowerWise Interface (PWI) compliant energy
management unit (EMU). It operates cooperatively with pro-
cessors using National Semiconductor’s Advanced Power
Controller (APC) to provide Adaptive or Dynamic Voltage
Scaling (AVS, DVS) which drastically improves processor ef-
ficiencies compared to conventional power delivery methods.
The device consists of PWI registers, logic, and a switching
DC/DC buck controller to supply the AVS or DVS voltage do-
main.
VOLTAGE SCALING
The device is designed to be used in a voltage scaling system
to lower the power dissipation of SoC or ASICs. By scaling
the supply voltage with the clock frequency and process vari-
ations, dramatic power savings can be achieved. Two types
of voltage scaling are supported, dynamic voltage scaling
(DVS) and adaptive voltage scaling (AVS). DVS systems
switch between pre-characterized voltages which are paired
to clock frequencies used for frequency scaling in the ASIC.
AVS systems track the ASIC’s performance and optimizes the
supply voltage to the required performance. AVS is a closed
loop system that provides process and temperature compen-
sation such that for any given process, temperature, or clock
frequency, the minimum supply voltage is delivered.
DIGITALLY ASSISTED VOLTAGE SCALING
The device delivers fast, controlled voltage scaling transients
with the help of a digital state machine. The state machine
automatically optimizes the slew rate of the output to provide
large signal transients with minimal over- and undershoot.
This is an important characteristic for voltage scaling systems
that rely on minimal over- and undershoot to set voltages as
low as possible and save energy.
POWERWISE INTERFACE
The device is programmable via the low-power, 2-wire Pow-
erWise Interface (PWI). This serial interface controls the var-
ious voltages and states of the regulator in the device. The
output voltage is programmable with 7-bit resolution and an
adjustable range, set by the feedback resistors, from 0.6V –
Vin*Dmax (see electrical characteristics for Dmax). This high
resolution voltage control affords accurate temperature and
process compensation in AVS. The device supports the full
command set as described in PWI 1.0/2.0 specification:
•Core Voltage Adjust
•Reset
•Sleep
•Shutdown
•Wakeup
•Register Read
•Register Write
•Authenticate
•Synchronize
The output voltage of the switching regulator is programmed
via the Core Voltage Adjust command.
PWI ADDRESS
A resistor from the ADDR pin to ground sets the device's PWI
address. The device senses the resistance as it is initializing
from the shutdown state. The device will not update the ad-
dress until it cycles through shutdown again. Use the table
below to choose the appropriate resistor to place form ADDR
pin to ground.
PWI Address Resistance (± 1% tolerance)
0≤ 40.2 kΩ
160.4 kΩ
280.6 kΩ
3100 kΩ
4120 kΩ
5140 kΩ
6160 kΩ
7180 kΩ
INPUTS: ON/OFF, ENBIAS, CONTROL, FLT_N, RESET_N,
SCLK, SPWI
•ON/OFF:
The ON/OFF logic input enables the internal LDO (VCC5
output pin).
•ENBIAS:
The ENBIAS logic input enables the internal logic of the
LM10520. The LM10520 goes through an initialization
procedure upon the rising edge of ENBIAS. Initialization is
complete within 100 µsec, after which the device is ready
to be used. If at any point ENBIAS goes low, the device
enters a low Iq shutdown state.
The ENBIAS input is buffered internally by a Schmitt
trigger with precision thresholds to allow accurate output
voltage sequencing off of the input rail.
•CONTROL:
The CONTROL logic input allows control of the CNTL_EN
output without incurring delays associated with
initialization. This signal is effectively ANDed with the
internal ‘ready’ signal, which is high once initialization is
complete.
The CONTROL pin level toggles the device between
Active and Sleep states, and will reset the R0 register.
•FLT_N:
The FLT_N logic input resets and holds the R0 register
when its input signal is low. It has no effect on CNTL_EN.
This provides a convenient way to support automatic fault
recovery modes in the slave power regulator. When
connected to a standard PWGD pin of a DC/DC regulator,
FLT_N will reset and hold R0 as long as PWGD is low,
allowing the slave regulator to recover from the fault by
returning to the default voltage. Once FLT_N returns high,
R0 can be written to.
•RESET_N:
The RESET_N provides a separate, level controlled logic
reset.
•SCLK and SPWI:
SCLK and SPWI provide serial PWI communication.
•CNTL_EN:
The CNTL_EN output connects to the SD# pin. CNTL_EN
allows power state control via the PWI interface or
ENBIAS/CONTROL logic inputs. LM10520 will drive
CNTL_EN to the VDD voltage to enable the buck controller
circuitry, and to 0 V to disable the circuitry.
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LM10520
IAVS OUTPUT CURRENT: CONTROLLING THE OUTPUT
VOLTAGE
The LM10520 uses a 7-bit current DAC to control the output
voltage. Since it is a current output, IAVS can be connected
directly to the feedback node. IAVS has a range of 0 – 60 µA
with 7 bits of resolution, or a 0.469 µA LSB.
IAVS should be connected to the feedback node of LM10520
as shown in Figure 1. The output voltage VOUT is expressed
as:
Where VFB = the regulated feedback voltage of the slave
regulator. This equation is valid for VOUT > VFB.
30110611
FIGURE 1. Connecting IAVS to the Feedback Node
Using Register R9 to Change the Default Output Voltage
The LM10520 default IAVS current is set by R9. R9 is trimmed
to 0x7F, so that IAVS = 0µA when power is applied to
LM10520. Between power cycling, R9 can be changed so that
IAVS defaults to values between 0 - 60 μA. This can be useful
for software trim of the default output voltage of the LM10520
controlled regulator. In order to do this, the system must take
care to write to R9 before enabling the output. (The output can
be enabled/disabled while keeping the LM10520 logic on via
the CONTROL input.) Therefore, R9 must be written to by
some system controller that is on a different power domain
than that provided by LM10520. In addition, the
“INITIAL_VDD” register in the Advanced Power Controller
(APC) must have the same value as R9 so that the APC and
LM10520 default to the same voltage code.
Digital Slew Rate Control
The IAVS and IAVS Mirror outputs have an adjustable, digital
slew rate control. The slew rate control is programmed in reg-
ister R10.
30110615
FIGURE 2. Digital Slew Rate Control
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LM10520
LM10520 effectively overrides the internal reference of the
slave regulator to allow it to operate in an AVS system. The
amount of current drawn from the AVS enabled power supply
when scaling voltage depends on several factors determined
by the well known equation for current in a capacitor:IC = Cdv/
dt
Where C is the total output capacitance seen by the power
supply: dv is the voltage step, dt is the step time.
The digital slew rate control of LM10520 allows independent
manipulation of the dv and dt terms to accommodate a wide
range of output capacitances.
STATES
Startup
During the startupt state, the LM10520 initializes all its regis-
ters and enables its bandgap. This process typically takes
1.116 msec. CNTL_EN is low during startup.
Active
During the active state, CNTL_EN is is high, the IAVS DACs
are enabled, and PWI registers can be accessed.
Sleep
During the sleep state, CNTL_EN is low, the IAVS DACs are
disabled, and PWI registers can be accessed.
Fault
During the fault state, the IAVS current register (R0) is reset,
after which the LM10520 automatically returns to its previous
state.
Shutdown
During the shutdown state, CNTL_EN is low, the IAVS DACs
are disabled, and most internal circuitry is disabled. Only the
PWI state machine is biased to allow register access.
30110618
FIGURE 3. LM10520 State Diagram
VOLTAGE MODE CONTROLLER
The LM10520 incorporates control circuitry and drivers for
synchronous buck PWM regulation. It uses voltage mode
control to achieve the low duty cycles necessary for the low
conversion ratios in an AVS system. It has flexible input en-
able controls to allow logic level control of output voltage
enable, bias enable, and internal LDO enable. In addition, an
active low fault input can be used for system fault response
sequencing. These inputs allow simple, system level control
of the device state. The LM10520 also includes input under-
voltage lock-out (UVLO) and a power good (PWGD) flag
(based on over-voltage and under-voltage detection). The
over-voltage and under-voltage signals are OR-gated to drive
the power good signal and provide a logic signal to the system
if the output voltage goes out of regulation. Current limit is
achieved by sensing the voltage VDS across the low side
MOSFET. The LM10520 is also able to stat-up with the output
pre-biased with a load. The LM10520 also allows the switch-
ing frequency to be a synchronized with an external clock
source.
START UP/SOFT-START
When VCC exceeds 2.79V and the shutdown pin (SD) sees a
logic high, the soft-start period begins. Then an internal, fixed
10 µA source begins charging the soft-start capacitor. During
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LM10520
soft-start the voltage on the soft-start capacitor CSS is con-
nected internally to the non-inverting input of the error ampli-
fier. The soft-start period lasts until the voltage on the soft-
start capacitor exceeds the LM10520 reference voltage of
0.6V. At this point the reference voltage takes over at the non-
inverting error amplifier input. The capacitance of CSS deter-
mines the length of the soft-start period, and can be
approximated by:
Where CSS is in µF and tSS is in ms.
During soft start the Power Good flag is forced low and it is
released when the FB pin voltage reaches 70% of 0.6V. At
this point the chip enters normal operation mode, and the
output overvoltage and undervoltage monitoring starts.
SETTING THE DEFAULT AND PROGRAMMABILITY
RANGE OF THE OUTPUT VOLTAGE
The LM10520 has a flexible output voltage range control.
When the system is starting up, the output voltage exits soft-
start and AVS has not been enabled by the load (the load is
the AVS enabled processor, and is booting up). This is the
default voltage of the LM10520, and is set by the feedback
resistor divider ratio. Once the automatic AVS authentication
process has successfully completed, the AVS loop is en-
gaged and the LM10520 automatically reduces the voltage.
A 7-bit current source is injected into the feedback resistor
node to achieve voltage scaling. Therefore, the range and
resolution of the device is adjustable via the top feedback re-
sistor.
SETTING THE SWITCHING FREQUENCY
During fixed-frequency mode of operation the PWM frequen-
cy is adjustable between 50 kHz and 1 MHz and is set by an
external resistor, RFADJ, between the FREQ/SYNC pin and
ground. The resistance needed for a desired frequency is ap-
proximated by the curve FREQUENCY vs. FREQUENCY
ADJUST RESISTOR in the Typical Performance Character-
istics section.
When it is desired to synchronize the switching frequency with
an external clock source, the LM10520 has the unique ability
to synchronize from this external source within the range of
250 kHz to 1MHz. The external clock signal should be AC
coupled to the FREQ/SYNC pin as shown below in Figure 4,
where the RFADJ is chosen so that the fixed frequency is ap-
proximately within ±30% of the external synchronizing clock
frequency. An internal protection diode clamps the low level
of the synchronizing signal to approximately -0.5V. The inter-
nal clock sychronizes to the rising edge of the external clock.
30110689
FIGURE 4. AC Coupled Clock
It is recommended to choose an AC coupling capacitance in
the range of 50 pF to 100 pF. Exceeding the recommended
capacitance may inject excessive energy through the internal
clamping diode structure present on the FREQ/SYNC pin.
The typical trip level of the synchronization pin is 1.5V. To
ensure proper synchronization and to avoid damaging the IC,
the peak-to-peak value (amplitude) should be between 2.5V
and VCC. The minimum width of this pulse must be greater
than 100 ns, and it's maximum width must be 100 ns less than
the period of the switching cycle.
The external clock synchronization process begins once the
LM10520 is enabled and an external clock signal is detected.
During the external clock synchronization process the internal
clock initially switches at approximately 1.5 MHz and de-
creases until it has matched the external clock’s frequency.
The lock-in period is approximately 30 µs if the external clock
is switching at 1MHz, and about 100 µs if the external clock
is at 200 kHz. When there is no clock signal present, the
LM10520 enters into fixed-frequency mode and begins
switching at the frequency set by the RFADJ resistor. If the ex-
ternal clock signal is removed after frequency synchroniza-
tion, the LM10520 will enter fixed-frequency mode within two
clock cycles. If the external clock is removed within the 30 µs
lock-in period, the LM10520 will re-enter fixed-frequency
mode within two internal clock cycles after the lock-in period.
OUTPUT PRE-BIAS STARTUP
If there is a pre-biased load on the output of the LM10520
during startup, the IC will disable switching of the low-side
MOSFET and monitor the SW node voltage during the off-
time of the high-side MOSFET. There is no load current
sensing while in pre-bias mode because the low-side MOS-
FET never turns on. The IC will remain in this pre-bias mode
until it sees the SW node stays below 0V during the entire
high-side MOSFET's off-time. Once it is determined that the
SW node remained below 0V during the high-side off-time,
the low-side MOSFET begins switching during the next
switching cycle. Figure 5 shows the SW node, HG, and LG
signals during pre-bias startup. The pre-biased output voltage
should not exceed VCC + VGS of the external High-Side MOS-
FET to ensure that the High-Side MOSFET will be able to
switch during startup.
30110691
FIGURE 5. Output Pre-Bias Mode Waveforms
TRACKING A VOLTAGE LEVEL
The LM10520 can track the output of a master power supply
during soft-start by connecting a resistor divider to the SS/
TRACK pin. In this way, the output voltage slew rate of the
LM10520 will be controlled by the master supply for loads that
require precise sequencing. When the tracking function is
17 www.national.com
LM10520
used no soft-start capacitor should be connected to the SS/
TRACK pin. However in all other cases, a CSS value of at least
1nF between the soft-start pin and ground should be used.
30110607
FIGURE 6. Tracking Circuit
One way to use the tracking feature is to design the tracking
resistor divider so that the master supply’s output voltage
(VOUT1) and the LM10520’s output voltage (represented sym-
bolically in Figure 6 as VOUT2, i.e. without explicitly showing
the power components) both rise together and reach their
target values at the same time. For this case, the equation
governing the values of the tracking divider resistors RT1 and
RT2 is:
The current through RT1 should be about 4mA for precise
tracking. The final voltage of the SS/TRACK pin should be set
higher than the feedback voltage of 0.6V (say about 0.65V as
in the above equation). If the master supply voltage was 5V
and the LM10520 output voltage was 1.8V, for example, then
the value of RT1 needed to give the two supplies identical soft-
start times would be 150Ω. A timing diagram for the equal soft-
start time case is shown in Figure 7.
30110608
FIGURE 7. Tracking with Equal Soft-Start Time
TRACKING A VOLTAGE SLEW RATE
The tracking feature can alternatively be used not to make
both rails reach regulation at the same time but rather to have
similar rise rates (in terms of output dV/dt). This method en-
sures that the output voltage of the LM10520 always reaches
regulation before the output voltage of the master supply. In
this case, the tracking resistors can be determined based on
the following equation:
For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with
RT1 set to 150Ω as before, RT2 is calculated from the above
equation to be 265Ω. A timing diagram for the case of equal
slew rates is shown in Figure 8.
30110610
FIGURE 8. Tracking with Equal Slew Rates
MOSFET GATE DRIVERS
The LM10520 has two gate drivers designed for driving N-
channel MOSFETs in a synchronous mode. Note that unlike
most other synchronous controllers, the bootstrap capacitor
of the LM10520 provides power not only to the driver of the
upper MOSFET, but the lower MOSFET driver too (both
drivers are ground referenced, i.e. no floating driver).
Two things must be kept in mind here. First, the BOOT pin
has an absolute maximum rating of 18V. This must never be
exceeded, even momentarily. Since the bootstrap capacitor
is connected to the SW node, the peak voltage impressed on
the BOOT pin is the sum of the input voltage (VIN) plus the
voltage across the bootstrap capacitor (ignoring any forward
drop across the bootstrap diode). The bootstrap capacitor is
charged up by a given rail (called VBOOT_DC here) whenever
the upper MOSFET turns off. This rail can be the same as
VCC or it can be any external ground-referenced DC rail. But
care has to be exercised when choosing this bootstrap DC
rail that the BOOT pin is not damaged. For example, if the
desired maximum VIN is 14V, and VBOOT_DC is chosen to be
the same as VCC, then clearly if the VCC rail is 6V, the peak
voltage on the BOOT pin is 14V + 6V = 20V. This is unac-
ceptable, as it is in excess of the rating of the BOOT pin. A
VCC of 3V would be acceptable in this case. Or the VIN range
must be reduced accordingly. There is also the option of de-
riving the bootstrap DC rail from another 3V external rail,
independent of VCC.
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LM10520
The second thing to be kept in mind here is that the output of
the low-side driver swings between the bootstrap DC rail level
of VBOOT_DC and Ground, whereas the output of the high-side
driver swings between VIN+ VBOOT_DC and Ground. To keep
the high-side MOSFET fully on when desired, the Gate pin
voltage of the MOSFET must be higher than its instantaneous
Source pin voltage by an amount equal to the 'Miller plateau'.
It can be shown that this plateau is equal to the threshold
voltage of the chosen MOSFET plus a small amount equal to
Io/g. Here Io is the maximum load current of the application,
and g is the transconductance of this MOSFET (typically
about 100 for logic-level devices). That means we must
choose VBOOT_DC to at least exceed the Miller plateau level.
This may therefore affect the choice of the threshold voltage
of the external MOSFETs, and that in turn may depend on the
chosen VBOOT_DC rail.
So far, in the discussion above, the forward drop across the
bootstrap diode has been ignored. But since that does affect
the output of the driver somewhat, it is a good idea to include
this drop in the following examples. Looking at the Typical
Application schematic, this means that the difference voltage
VCC - VD1, which is the voltage the bootstrap capacitor
charges up to, must always be greater than the maximum tol-
erance limit of the threshold voltage of the upper MOSFET.
Here VD1 is the forward voltage drop across the bootstrap
diode D1. This may place restrictions on the minimum input
voltage and/or type of MOSFET used.
A basic bootstrap circuit can be built using one Schottky diode
and a small capacitor, as shown in Figure 9. The capacitor
CBOOT serves to maintain enough voltage between the top
MOSFET gate and source to control the device even when
the top MOSFET is on and its source has risen up to the input
voltage level. The charge pump circuitry is fed from VCC,
which can operate over a range from 3.0V to 6.0V. Using this
basic method the voltage applied to the gates of both high-
side and low-side MOSFETs is VCC - VD. This method works
well when VCC is 5V±10%, because the gate drives will get at
least 4.0V of drive voltage during the worst case of VCC-MIN =
4.5V and VD-MAX = 0.5V. Logic level MOSFETs generally
specify their on-resistance at VGS = 4.5V. When VCC = 3.3V
±10%, the gate drive at worst case could go as low as 2.5V.
Logic level MOSFETs are not guaranteed to turn on, or may
have much higher on-resistance at 2.5V. Sub-logic level
MOSFETs, usually specified at VGS = 2.5V, will work, but are
more expensive, and tend to have higher on-resistance. The
circuit in Figure 9 works well for input voltages ranging from
1V up to 14V and VCC = 5V±10%, because the drive voltage
depends only on VCC.
30110612
FIGURE 9. Basic Charge Pump (Bootstrap)
Note that the LM10520 can be paired with a low cost linear
regulator like the LM78L05 to run from a single input rail be-
tween 6.0 and 14V. The 5V output of the linear regulator
powers both the VCC and the bootstrap circuit, providing effi-
cient drive for logic level MOSFETs. An example of this circuit
is shown in Figure 10.
30110613
FIGURE 10. LM78L05 Feeding Basic Charge Pump
19 www.national.com
LM10520
Figure 11 shows a second possibility for bootstrapping the
MOSFET drives using a doubler. This circuit provides an
equal voltage drive of VCC - 3VD + VIN to both the high-side
and low-side MOSFET drives. This method should only be
used in circuits that use 3.3V for both VCC and VIN. Even with
VIN = VCC = 3.0V (10% lower tolerance on 3.3V) and VD = 0.5V
both high-side and low-side gates will have at least 4.5V of
drive. The power dissipation of the gate drive circuitry is di-
rectly proportional to gate drive voltage, hence the thermal
limits of the LM10520 IC will quickly be reached if this circuit
is used with VCC or VIN voltages over 5V.
30110619
FIGURE 11. Charge Pump with Added Gate Drive
All the gate drive circuits shown in the above figures typically
use 100 nF ceramic capacitors in the bootstrap locations.
POWER GOOD SIGNAL
The open drain output on the Power Good pin needs a pull-
up resistor to a low voltage source. The pull-up resistor should
be chosen so that the current going into the Power Good pin
is less than 1mA. A 100 kΩ resistor is recommended for most
applications.
The Power Good signal is an OR-gated flag which takes into
account both output over-voltage and under-voltage condi-
tions. If the feedback pin (FB) voltage is 18% above its nom-
inal value (118% x VFB = 0.708V) or falls 28% below that value
(72% x VFB = 0.42V) the Power Good flag goes low. The
Power Good flag can be used to signal other circuits that the
output voltage has fallen out of regulation, however the
switching of the LM10520 continues regardless of the state of
the Power Good signal. The Power Good flag will return to
logic high whenever the feedback pin voltage is between 72%
and 118% of 0.6V.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low-
side MOSFET while it is on. The RDSON of the MOSFET is a
known value; hence the current through the MOSFET can be
determined as:
VDS = IOUT x RDSON
The current through the low-side MOSFET while it is on is also
the falling portion of the inductor current. The current limit
threshold is determined by an external resistor, RCS, connect-
ed between the switching node and the ISEN pin. A constant
current (ISEN-TH) of 40 µA typical is forced through RCS, caus-
ing a fixed voltage drop. This fixed voltage is compared
against VDS and if the latter is higher, the current limit of the
chip has been reached. To obtain a more accurate value for
RCS you must consider the operating values of RDSON and
ISEN-TH at their operating temperatures in your application and
the effect of slight parameter differences from part to part.
RCS can be found by using the following equation using the
RDSON value of the low side MOSFET at it's expected hot
temperature and the absolute minimum value expected over
the full temperature range for the for the ISEN-TH which is 25
µA:
RCS = RDSON-HOT x ILIM / ISEN-TH
For example, a conservative 15A current limit in a 10A design
with a RDSON-HOT of 10 mΩ would require a 6kΩ resistor. The
minimum value for RCS in any application is 1kΩ. Because
current sensing is done across the low-side MOSFET, no
minimum high-side on-time is necessary. The LM10520 en-
ters current limit mode if the inductor current exceeds the
current limit threshold at the point where the high-side MOS-
FET turns off and the low-side MOSFET turns on. (The point
of peak inductor current, see Figure 12). Note that in normal
operation mode the high-side MOSFET always turns on at the
beginning of a clock cycle. In current limit mode, by contrast,
the high-side MOSFET on-pulse is skipped. This causes in-
ductor current to fall. Unlike a normal operation switching
cycle, however, in a current limit mode switching cycle the
high-side MOSFET will turn on as soon as inductor current
has fallen to the current limit threshold. The LM10520 will
continue to skip high-side MOSFET pulses until the inductor
current peak is below the current limit threshold, at which point
the system resumes normal operation.
30110688
FIGURE 12. Current Limit Threshold
Unlike a high-side MOSFET current sensing scheme, which
limits the peaks of inductor current, low-side current sensing
is only allowed to limit the current during the converter off-
time, when inductor current is falling. Therefore in a typical
current limit plot the valleys are normally well defined, but the
peaks are variable, according to the duty cycle. The PWM
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LM10520
error amplifier and comparator control the off-pulse of the
high-side MOSFET, even during current limit mode, meaning
that peak inductor current can exceed the current limit thresh-
old. Assuming that the output inductor does not saturate, the
maximum peak inductor current during current limit mode can
be calculated with the following equation:
Where TSW is the inverse of switching frequency fSW. The 200
ns term represents the minimum off-time of the duty cycle,
which ensures enough time for correct operation of the cur-
rent sensing circuitry.
In order to minimize the time period in which peak inductor
current exceeds the current limit threshold, the IC also dis-
charges the soft-start capacitor through a fixed 90 µA sink.
The output of the LM10520 internal error amplifier is limited
by the voltage on the soft-start capacitor. Hence, discharging
the soft-start capacitor reduces the maximum duty cycle D of
the controller. During severe current limit this reduction in duty
cycle will reduce the output voltage if the current limit condi-
tions last for an extended time. Output inductor current will be
reduced in turn to a flat level equal to the current limit thresh-
old. The third benefit of the soft-start capacitor discharge is a
smooth, controlled ramp of output voltage when the current
limit condition is cleared.
DESIGN CONSIDERATIONS
The following is a design procedure for all the components
needed to create the Typical Application Circuit shown on the
front page. This design converts 3.3V (VIN) to 1.2V (VOUT) at
a maximum load of 4A with an efficiency of 89% and a switch-
ing frequency of 300 kHz. The same procedures can be
followed to create many other designs with varying input volt-
ages, output voltages, and load currents.
Input Capacitor
The input capacitors in a Buck converter are subjected to high
stress due to the input current trapezoidal waveform. Input
capacitors are selected for their ripple current capability and
their ability to withstand the heat generated since that ripple
current passes through their ESR. Input rms ripple current is
approximately:
Where duty cycle D = VOUT/VIN.
The power dissipated by each input capacitor is:
where n is the number of paralleled capacitors, and ESR is
the equivalent series resistance of each capacitor. The equa-
tion above indicates that power loss in each capacitor de-
creases rapidly as the number of input capacitors increases.
The worst-case ripple for a Buck converter occurs during full
load and when the duty cycle (D) is 0.5. For this 3.3V to 1.2V
design the duty cycle is 0.364. For a 4A maximum load the
ripple current is 1.92A.
Output Inductor
The output inductor forms the first half of the power stage in
a Buck converter. It is responsible for smoothing the square
wave created by the switching action and for controlling the
output current ripple (ΔIOUT). The inductance is chosen by
selecting between tradeoffs in efficiency and response time.
The smaller the output inductor, the more quickly the con-
verter can respond to transients in the load current. However,
as shown in the efficiency calculations, a smaller inductor re-
quires a higher switching frequency to maintain the same
level of output current ripple. An increase in frequency can
mean increasing loss in the MOSFETs due to the charging
and discharging of the gates. Generally the switching fre-
quency is chosen so that conduction loss outweighs switching
loss. The equation for output inductor selection is:
L = 1.6 µH
Here we have plugged in the values for output current ripple,
input voltage, output voltage, switching frequency, and as-
sumed a 40% peak-to-peak output current ripple. This yields
an inductance of 1.6 µH. The output inductor must be rated
to handle the peak current (also equal to the peak switch cur-
rent), which is (IOUT + (0.5 x ΔIOUT)) = 4.8A, for a 4A design.
The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak,
and has a direct current resistance (DCR) of 12 mΩ. After
selecting the Coilcraft DO3316P-222P for the output inductor,
actual inductor current ripple should be re-calculated with the
selected inductance value, as this information is needed to
select the output capacitor. Re-arranging the equation used
to select inductance yields the following:
VIN(MAX) is assumed to be 10% above the steady state input
voltage, or 3.6V at VIN = 3.3V. The re-calculated current ripple
will then be 1.2A. This gives a peak inductor/switch current
will be 4.6A.
Output Capacitor
The output capacitor forms the second half of the power stage
of a Buck switching converter. It is used to control the output
voltage ripple (ΔVOUT) and to supply load current during fast
load transients.
In this example the output current is 4A and the expected type
of capacitor is an aluminum electrolytic, as with the input ca-
pacitors. Other possibilities include ceramic, tantalum, and
solid electrolyte capacitors, however the ceramic type often
do not have the large capacitance needed to supply current
for load transients, and tantalums tend to be more expensive
than aluminum electrolytic. Aluminum capacitors tend to have
very high capacitance and fairly low ESR, meaning that the
ESR zero, which affects system stability, will be much lower
than the switching frequency. The large capacitance means
that at the switching frequency, the ESR is dominant, hence
the type and number of output capacitors is selected on the
21 www.national.com
LM10520
basis of ESR. One simple formula to find the maximum ESR
based on the desired output voltage ripple, ΔVOUT and the
designed output current ripple, ΔIOUT, is:
In this example, in order to maintain a 2% peak-to-peak output
voltage ripple and a 40% peak-to-peak inductor current ripple,
the required maximum ESR is 20 mΩ. The Sanyo 4SP560M
electrolytic capacitor will give an equivalent ESR of 14 mΩ.
The capacitance of 560 µF is enough to supply energy even
to meet severe load transient demands.
MOSFETs
Selection of the power MOSFETs is governed by a trade-off
between cost, size, and efficiency. One method is to deter-
mine the maximum cost that can be endured, and then select
the most efficient device that fits that price. Breaking down the
losses in the high-side and low-side MOSFETs and then cre-
ating spreadsheets is one way to determine relative efficien-
cies between different MOSFETs. Good correlation between
the prediction and the bench result is not guaranteed, how-
ever. Single-channel buck regulators that use a controller IC
and discrete MOSFETs tend to be most efficient for output
currents of 2 to 10A.
Losses in the high-side MOSFET can be broken down into
conduction loss, gate charging loss, and switching loss. Con-
duction, or I2R loss, is approximately:
PC = D (IO2 x RDSON-HI x 1.3)
(High-Side MOSFET)
PC = (1 - D) x (IO2 x RDSON-LO x 1.3)
(Low-Side MOSFET)
In the above equations the factor 1.3 accounts for the in-
crease in MOSFET RDSON due to heating. Alternatively, the
1.3 can be ignored and the RDSON of the MOSFET estimated
using the RDSON Vs. Temperature curves in the MOSFET
datasheets.
Gate charging loss results from the current driving the gate
capacitance of the power MOSFETs, and is approximated as:
PGC = n x (VDD) x QG x fSW
where ‘n’ is the number of MOSFETs (if multiple devices have
been placed in parallel), VDD is the driving voltage (see MOS-
FET Gate Drivers section) and QGS is the gate charge of the
MOSFET. If different types of MOSFETs are used, the ‘n’ term
can be ignored and their gate charges simply summed to form
a cumulative QG. Gate charge loss differs from conduction
and switching losses in that the actual dissipation occurs in
the LM10520, and not in the MOSFET itself.
Switching loss occurs during the brief transition period as the
high-side MOSFET turns on and off, during which both current
and voltage are present in the channel of the MOSFET. It can
be approximated as:
PSW = 0.5 x VIN x IO x (tr + tf) x fSW
where tr and tf are the rise and fall times of the MOSFET.
Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage ap-
plied to either MOSFET is 3.6V. The maximum drive voltage
at the gate of the high-side MOSFET is 3.1V, and the maxi-
mum drive voltage for the low-side MOSFET is 3.3V. Due to
the low drive voltages in this example, a MOSFET that turns
on fully with 3.1V of gate drive is needed. For designs of 5A
and under, dual MOSFETs in SO-8 provide a good trade-off
between size, cost, and efficiency.
Support Components
CIN2 - A small (0.1 to 1 µF) ceramic capacitor should be placed
as close as possible to the drain of the high-side MOSFET
and source of the low-side MOSFET (dual MOSFETs make
this easy). This capacitor should be X5R type dielectric or
better.
RCC, CCC- These are standard filter components designed to
ensure smooth DC voltage for the chip supply. RCC should be
1 to 10Ω. CCC should 1µF, X5R type or better.
CBOOT- Bootstrap capacitor, typically 100 nF.
RPULL-UP – This is a standard pull-up resistor for the open-
drain power good signal (PWGD). The recommended value
is 100 kΩ connected to VCC. If this feature is not necessary,
the resistor can be omitted.
D1 - A small Schottky diode should be used for the bootstrap.
It allows for a minimum drop for both high and low-side
drivers. The MBR0520 or BAT54 work well in most designs.
RCS - Resistor used to set the current limit. Since the design
calls for a peak current magnitude (IOUT + (0.5 x ΔIOUT)) of
4.8A, a safe setting would be 6A. (This is below the saturation
current of the output inductor, which is 7A.) Following the
equation from the Current Limit section, a 1.3 kΩ resistor
should be used.
RFADJ - This resistor is used to set the switching frequency of
the chip. The resistor value is approximated from the Fre-
quency vs Frequency Adjust Resistor curve in the Typical
Performance Characteristics section. For 300 kHz operation,
a 100 kΩ resistor should be used.
CSS - The soft-start capacitor depends on the user require-
ments and is calculated based on the equation given in the
section titled START UP/SOFT-START. Therefore, for a 7 ms
delay, a 12 nF capacitor is suitable.
Control Loop Compensation
The LM10520 uses voltage-mode (‘VM’) PWM control to cor-
rect changes in output voltage due to line and load transients.
VM requires careful small signal compensation of the control
loop for achieving high bandwidth and good phase margin.
The control loop is comprised of two parts. The first is the
power stage, which consists of the duty cycle modulator, out-
put inductor, output capacitor, and load. The second part is
the error amplifier, which for the LM10520 is a 9MHz op-amp
used in the classic inverting configuration. Figure 13 shows
the regulator and control loop components.
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LM10520
30110664
FIGURE 13. Power Stage and Error Amp
One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to see.
Software tools such as Excel, MathCAD, and Matlab are use-
ful for showing how changes in compensation or the power
stage affect system gain and phase.
The power stage modulator provides a DC gain ADC that is
equal to the input voltage divided by the peak-to-peak value
of the PWM ramp. This ramp is 1.0Vpk-pk for the LM10520.
The inductor and output capacitor create a double pole at fre-
quency fDP, and the capacitor ESR and capacitance create a
single zero at frequency fESR. For this example, with VIN =
3.3V, these quantities are:
In the equation for fDP, the variable RL is the power stage re-
sistance, and represents the inductor DCR plus the on resis-
tance of the top power MOSFET. RO is the output voltage
divided by output current. The power stage transfer function
GPS is given by the following equation, and Figure 14 shows
Bode plots of the phase and gain in this example.
a = LCO(RO + RC)
b = L + CO(RORL + RORC + RCRL)
c = RO + RL
30110669
30110670
FIGURE 14. Power Stage Gain and Phase
The double pole at 4.5 kHz causes the phase to drop to ap-
proximately -130° at around 10 kHz. The ESR zero, at 20.3
kHz, provides a +90° boost that prevents the phase from
dropping to -180°. If this loop were left uncompensated, the
bandwidth would be approximately 10 kHz and the phase
margin 53°. In theory, the loop would be stable, but would
suffer from poor DC regulation (due to the low DC gain) and
would be slow to respond to load transients (due to the low
bandwidth.) In practice, the loop could easily become unsta-
ble due to tolerances in the output inductor, capacitor, or
changes in output current, or input voltage. Therefore, the
loop is compensated using the error amplifier and a few pas-
sive components.
For this example, a Type III, or three-pole-two-zero approach
gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including
Type III, a single pole is placed at the origin to boost DC gain
as high as possible. Two zeroes fZ1 and fZ2 are placed at the
double pole frequency to cancel the double pole phase lag.
Then, a pole, fP1 is placed at the frequency of the ESR zero.
A final pole fP2 is placed at one-half of the switching frequency.
The gain of the error amplifier transfer function is selected to
give the best bandwidth possible without violating the Nyquist
stability criteria. In practice, a good crossover point is one-fifth
23 www.national.com
LM10520
of the switching frequency, or 60 kHz for this example. The
generic equation for the error amplifier transfer function is:
In this equation the variable AEA is a ratio of the values of the
capacitance and resistance of the compensation compo-
nents, arranged as shown in Figure 13. AEA is selected to
provide the desired bandwidth. A starting value of 80,000 for
AEA should give a conservative bandwidth. Increasing the
value will increase the bandwidth, but will also decrease
phase margin. Designs with 45-60° are usually best because
they represent a good trade-off between bandwidth and
phase margin. In general, phase margin is lowest and gain
highest (worst-case) for maximum input voltage and minimum
output current. One method to select AEA is to use an iterative
process beginning with these worst-case conditions.
1. Increase AEA
2. Check overall bandwidth and phase margin
3. Change VIN to minimum and recheck overall bandwidth
and phase margin
4. Change IO to maximum and recheck overall bandwidth
and phase margin
The process ends when the both bandwidth and the phase
margin are sufficiently high. For this example input voltage
can vary from 3.0 to 3.6V and output current can vary from 0
to 4A, and after a few iterations a moderate gain factor of 101
dB is used.
The error amplifier of the LM10520 has a unity-gain band-
width of 9 MHz. In order to model the effect of this limitation,
the open-loop gain can be calculated as:
The new error amplifier transfer function that takes into ac-
count unity-gain bandwidth is:
The gain and phase of the error amplifier are shown in Figure
15.
30110674
30110675
FIGURE 15. Error Amp. Gain and Phase
In VM regulators, the top feedback resistor RFB2 forms a part
of the compensation. Setting RFB2 to 10 kΩ±1%, usually gives
values for the other compensation resistors and capacitors
that fall within a reasonable range. (Capacitances > 1pF, re-
sistances < 1MΩ) CC1, CC2, CC3, RC1, and RC2 are selected
to provide the poles and zeroes at the desired frequencies,
using the following equations:
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LM10520
In practice, a good tradeoff between phase margin and band-
width can be obtained by selecting the closest ±10% capac-
itor values above what are suggested for CC1 and CC2, the
closest ±10% capacitor value below the suggestion for CC3,
and the closest ±1% resistor values below the suggestions
for RC1, RC2. Note that if the suggested value for RC2 is less
than 100Ω, it should be replaced by a short circuit. Following
this guideline, the compensation components will be:
CC1 = 27 pF±10%, CC2 = 820 pF±10%
CC3 = 2.7 nF±10%, RC1 = 39.2 kΩ±1%
RC2 = 2.55 kΩ±1%
The transfer function of the compensation block can be de-
rived by considering the compensation components as
impedance blocks ZF and ZI around an inverting op-amp:
As with the generic equation, GEA-ACTUAL must be modified to
take into account the limited bandwidth of the error amplifier.
The result is:
The total control loop transfer function H is equal to the power
stage transfer function multiplied by the error amplifier trans-
fer function.
H = GPS x HEA
The bandwidth and phase margin can be read graphically
from Bode plots of HEA as shown in Figure 16.
30110685
30110686
FIGURE 16. Overall Loop Gain and Phase
The bandwidth of this example circuit is 59 kHz, with a phase
margin of 60°.
25 www.national.com
LM10520
EFFICIENCY CALCULATIONS
The following is a sample calculation.
A reasonable estimation of the efficiency of a switching buck
controller can be obtained by adding together the Output
Power (POUT) loss and the Total Power (PTOTAL) loss:
The Output Power (POUT) for the Typical Application Circuit
design is (1.2V x 4A) = 4.8W. The Total Power (PTOTAL), with
an efficiency calculation to complement the design, is shown
below.
The majority of the power losses are due to the low side and
high side MOSFET’s losses. The losses in any MOSFET are
group of switching (PSW) and conduction losses (PCND).
PFET = PSW + PCND = 61.38 mW + 270.42 mW
PFET = 331.8 mW
FET Switching Loss (PSW)
PSW = PSW(ON) + PSW(OFF)
PSW = 0.5 x VIN x IOUT x (tr + tf) x fSW
PSW = 0.5 x 3.3V x 4A x 300 kHz x 31 ns
PSW = 61.38 mW
The FDS6898A has a typical turn-on rise time tr and turn-off
fall time tf of 15 ns and 16 ns, respectively. The switching
losses for this type of dual N-Channel MOSFETs are 0.061W.
FET Conduction Loss (PCND)
PCND = PCND1 + PCND2
PCND1 = I2OUT x RDS(ON) x k x D
PCND2 = I2OUT x RDS(ON) x k x (1-D)
RDS(ON) = 13 mΩ and the factor is a constant value (k = 1.3)
to account for the increasing RDS(ON) of a FET due to heating.
PCND1 = (4A)2 x 13 mΩ x 1.3 x 0.364
PCND2 = (4A)2 x 13 mΩ x 1.3 x (1 - 0.364)
PCND = 98.42 mW + 172 mW = 270.42 mW
There are few additional losses that are taken into account:
IC Operating Loss (PIC)
PIC = IQ_VCC x VCC,
where IQ-VCC is the typical operating VCC current
PIC= 1.7 mA x 3.3V = 5.61 mW
FET Gate Charging Loss (PGATE)
PGATE = n x VCC x QGS x fSW
PGATE = 2 x 3.3V x 3 nC x 300 kHz
PGATE = 5.94 mW
The value n is the total number of FETs used and QGS is the
typical gate-source charge value, which is 3 nC. For the FD-
S6898A the gate charging loss is 5.94 mW.
Input Capacitor Loss (PCAP)
where,
Here n is the number of paralleled capacitors, ESR is the
equivalent series resistance of each, and PCAP is the dissipa-
tion in each. So for example if we use only one input capacitor
of 24 mΩ.
PCAP = 88.8 mW
Output Inductor Loss (PIND)
PIND = I2OUT x DCR
where DCR is the DC resistance. Therefore, for example
PIND = (4A)2 x 11 mΩ
PIND = 176 mW
Total System Efficiency
PTOTAL = PFET + PIC + PGATE + PCAP + PIND
www.national.com 26
LM10520
Physical Dimensions inches (millimeters) unless otherwise noted
eTSSOP-28-Pin Package
NS Package Number MXA28B
27 www.national.com
LM10520
Notes
LM10520 Single-Phase Buck Controller for AVS Systems
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