Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 (R) The fido1100(R) Instruction Set Reference Guide for the 32-Bit Real-Time Communications Controller (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Copyright 2008 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107 fido(R), fido1100(R), and SPIDER are trademarks of Innovasic Semiconductor, Inc. I2CTM Bus is a trademark of Philips Electronics N.V. Motorola(R) is a registered trademark of Motorola, Inc. (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 2 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 TABLE OF CONTENTS List of Figures ..................................................................................................................................3 List of Tables ...................................................................................................................................3 List of Instructions ...........................................................................................................................4 Conventions .....................................................................................................................................7 1. Overview .................................................................................................................................8 1.1 Data-Movement Instructions .........................................................................................8 1.2 Integer Arithmetic Operations .......................................................................................8 1.3 Logic Instructions ..........................................................................................................9 1.4 Shift and Rotate Instructions .........................................................................................9 1.5 Bit Manipulation Instructions........................................................................................9 1.6 Binary-Coded Decimal Instructions ............................................................................10 1.7 Program Control Instructions ......................................................................................10 1.8 System Control Instructions ........................................................................................10 1.9 Instruction Attributes...................................................................................................10 1.10 Instruction Format .......................................................................................................10 1.11 Core Addressing Modes Summary .............................................................................11 1.12 Instruction Format for Single Effective Address Instruction Word ............................13 1.13 Format for the Brief Extension Word..........................................................................13 1.14 Format for the Full Extension Word ...........................................................................14 2. Instruction Descriptions ........................................................................................................17 3. For Additional Information .................................................................................................190 Index ............................................................................................................................................191 LIST OF FIGURES Figure 1. Shift and Rotate Instructions Diagram ..........................................................................39 LIST OF TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Instruction Word General Format ...................................................................................11 Core Addressing Modes Summary .................................................................................11 Instruction Format for Single Effective Address Instruction Word ................................13 Instruction Format for Brief Instruction Word ................................................................14 Format for the Full Extension Word ...............................................................................15 (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 3 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 LIST OF INSTRUCTIONS ABCD--Add Decimal with Extend ADD--Add ADDA--Add Address ADDI--Add Immediate ADDQ--Add Quick ADDX--Add Extended AND--And ANDI--And Immediate ANDI to CCR--And Immediate to Condition Code Register ANDI to SR--And Immediate to Status Register ASL/ASR--Arithmetic Shift BCC--Branch Conditionally BCHG--Test a Bit and Change BCLR--Test a Bit and Clear BGND--Enter Background Mode BKPT--Software Breakpoint BRA--Branch Always BSET--Test a Bit and Set BSR--Branch to Subroutine BTST--Test a Bit CHK--Check Register Against Bounds CHK2--Check Register Against Bounds CLR--Clear an Operand CMP--Compare CMP2--Compare Register Against Bounds CMPA--Compare Address CMPI--Compare Immediate CMPM--Compare Memory DBCC--Test Condition, Decrement and Branch DIVS/DIVSL--Signed Divide DIVU/DIVUL--Unsigned Divide EOR--Exclusive OR EORI--Exclusive OR Immediate EORI to CCR--Exclusive OR Immediate to Condition Code Register EORI to SR--Exclusive OR Immediate to Status Register EXG--Exchange Registers EXT/EXTB--Sign Extend ILLEGAL--Take Illegal Instruction Trap JMP--Jump JSR--Jump to Subroutine (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 4 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 LEA--Load Effective Address LINK--Link and Allocate LPSTOP--Low Power Stop LSL/LSR--Logical Shift MOVE--Move Data from Source to Destination MOVEA--Move Data from Source to Destination Address Register MOVEC--Move Control Register MOVEM--Move Multiple Registers MOVEP--Move Peripheral Data MOVEQ--Move Quick MOVES--Move Address Space MOVE from CCR --Move Data from the Condition Code Register MOVE to CCR --Move Data to the Condition Code Register MOVE from SR --Move Data from the Status Register MOVE USP--Move User Stack Pointer MULS--Signed Multiply MULU--Unsigned Multiply NBCD--Negate Decimal with Extend NEG--Negate NEGX--Negate with Extend NOP--No Operation NOT--Logical Complement OR--Inclusive Logical OR ORI--Inclusive OR Immediate ORI to CCR--Inclusive OR Immediate to Condition Code Register ORI to SR--Inclusive OR Immediate to Status Register PEA--Push Effective Address RESET--Reset External Devices ROL/ROR--Rotate Without Extend ROXL/ROXR--Rotate With Extend RTD--Return and Deallocate RTE--Return from Exception RTR--Return and Restore Condition Codes RTS--Return from Subroutine SBCD--Subtract Decimal with Extend SCC--Set According to Condition Code SLEEP--Sleep Current Context STOP--Load Status Register and Stop SUB--Subtract SUBA--Subtract Address SUBI--Subtract Immediate SUBQ--Subtract Quick (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 5 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 SUBX--Subtract Extended SWAP--Swap Register Halves TAS--Test and Set an Operand TRAP--Trap TRAPCC--Trap on Condition TRAPV--If V then Trap TRAPX--Trap to Master Context_0 TST--Test an Operand UNLK--Unlink (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 6 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 CONVENTIONS Arial Bold Designates headings, figure captions, and table captions. Blue Designates hyperlinks. Courier Designates code text. Italics Designates emphasis or caution related to nearby information. (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 7 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 1. Instruction Set Reference Guide September 4, 2008 Overview This document describes the fido1100 instruction set for the fido1100 communications controller and includes machine functions for the following operations: Data movement Arithmetic operations Logical operations Shifts and rotates Bit manipulation Binary-Coded Decimal (BCD) arithmetic Program control System control The following subsections summarize the fido1100 instructions available for these operations. 1.1 Data-Movement Instructions The MOVE instruction is the basic means of transferring and storing address and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE Or MOVEA) transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general MOVE instructions, there are several specific data-movement instructions--move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). 1.2 Integer Arithmetic Operations The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MULS--Signed Multiply, MULU--Unsigned Multiply), and divide (DIVS/DIVSL-- Signed Divide, DIVU/DIVUL--Unsigned Divide), as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear and negate instructions apply to all sizes of data operands. Signed and unsigned multiply and divide instructions include: (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 8 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Word multiply to produce a long-word product Long-word multiply to produce a long-word or quad-word product Division of a long-word dividend by a word divisor (word quotient and word remainder) Division of a long-word or quad-word dividend by a long-word divisor (long-word quotient and long-word remainder) A set of extended instructions provides multi-precision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT/EXTB), and negate binary with extend (NEGX). 1.3 Logic Instructions The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The TST instruction arithmetically compares the operand with zero, placing the result in the condition code register. 1.4 Shift and Rotate Instructions The arithmetic shift instructions, ASL/ASR, and logical shift instructions, LSL/LSR, provide shift operations in both directions. The ROL/ROR and ROXL/ROXR instructions perform rotate (circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory. Register shift and rotate operations shift all operand sizes. The shift count may be specified in the instruction operation word (to shift from one to eight places) or in a register (modulo 64-shift count). Memory shift and rotate operations shift word-length operands one bit-position only. The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROL/ROR instructions with a shift count of eight allows fast byte swapping. 1.5 Bit Manipulation Instructions Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed either on registers or on memory. The bit number is specified as immediate data or in a data register. Register operands are 32 bits long, and memory operands are 8 bits long. (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 9 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 1.6 Instruction Set Reference Guide September 4, 2008 Binary-Coded Decimal Instructions Five instructions support operations on Binary-Coded Decimal (BCD) numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). 1.7 Program Control Instructions A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. 1.8 System Control Instructions Privileged instructions, trapping instructions, and instructions that use or modify the condition code register provide system control operations. All of these instructions cause the processor to flush the instruction pipeline. 1.9 Instruction Attributes The attributes line specifies the size of the operands of an instruction. When an instruction can use operands of more than one size, a suffix is used with the mnemonic of the instruction: .B Byte .W Word .L Long word In instruction descriptions, the Condition Codes are defined as follows: X--extend bit N--negative bit Z--zero bit V--overflow bit C--Carry Bit 1.10 Instruction Format All instructions consist of at least one word. Some instructions can have as many as seven words, as shown in Table 1. The first word of the instruction, called the operation word, specifies instruction length and the operation to be performed. The remaining words, called extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argument counts. (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 10 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Table 1. Instruction Word General Format 5 0 Operation Word (one word, specifies operation and modes) Special Operand Specifiers (if any, one or two words) Immediate Operand or Source Address Extension (if any, one to three words) Destination Effective Address Extension (if any, one to three words) Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: Register Specification--A register field of the instruction contains the number of the register. Effective Address--An Effective-Address field of the instruction contains address mode information. Implicit Reference--The definition of an instruction implies the use of specific registers. The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register is an address or data register and how it is used. 1.11 Core Addressing Modes Summary Table 2 summarizes the various addressing modes of the fido1100 architecture: Table 2. Core Addressing Modes Summary Description Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement (R) Operation EA=Dn EA=An Syntax Dn An mode 000 001 reg n n No. of Ext Words 0 0 EA=(An) (An) 010 n 0 - EA=(An), An=An+Size (An)+ 011 n 0 4 An=An-Size, EA=(An) -(An) 100 n 0 4 IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 11 of 193 Notes - - http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Table 2. Core Addressing Modes Summary (Continued) Description Address Register Indirect with Displacement Address Register Indirect with Index (8-bit displacement) Address Register Indirect with Index (base displacement) Program Counter Indirect with Displacement Program Counter Indirect with Index (8-bit displacement) Program Counter Indirect with Index (base displacement) Absolute Short Address Absolute Long Address Immediate Operation EA=(An)+d16 Syntax (d16,An) mode 101 reg n No. of Ext Words 1 EA=(An)+(Xn*Scale) +d8 (d8,An,Xn.Size *Scale) 110 n 1 1,4,5 EA=(An)+(Xn*Scale) +bd (bd,An,Xn.Size *Scale) 110 n 1, 2 or 3 2,4,5 EA=(PC)+d16 (d16,PC) 111 010 1 3 EA=(PC)+(Xn*Scale) +d8 (d8,PC,Xn.Size *Scale) 111 011 1 1,4,5 EA=(PC)+(Xn*Scale) +bd (bd,PC,Xn.Size *Scale) 111 011 1, 2 or 3 2,4,5 EA given (xxx).W 111 000 1 7 EA given (xxx).L 111 001 2 7 no EA required #xxx 111 100 1 or 2 6 Notes 3 Notes: 1. Brief Format Extension Word contains index register indicator, scale, and 8-bit displacement. 2. Full Format Extension Word contains index register indicator, scale, and 8-bit displacement fixed at zero. Second and third extension words are optional and contain 16-bit or 32-bit base displacement. 3. Extension word is simply the 16-bit displacement and will be sign-extended to 32 bits before being used. 4. Size = 1, 2, or 4. 5. Scale = 1, 2, 4, or 8. 6. Immediate data provided as one or two extension words. Contains 8-, 16-, or 32-bit data. 7. Extension word(s) will simply contain the operand's effective address. One extension word (16 bits) will be sign-extended to 32-bit address, and two extension words will directly specify the address. (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 12 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Additional Details: Full Format Extension Word contains the following bits (among others): - BS Bit--Allows the base register (used above as An, Dn, or PC) to be suppressed. This part of the EA calculation will have an effective value of zero. - IS Bit--Allows the index register to be suppressed. This part of the EA calculation will have an effective value of zero. - BD Size Bits--Setting these to 00 allows the base displacement to be suppressed. This part of the EA calculation will have an effective value of zero. - I/IS Bits--Used by memory indirect addressing modes. For CPU32 should always be 000. If when IS Bit is set to a 1, setting this field to a non-zero value will cause an illegal instruction exception. - Of the various items that can be suppressed, at least one field must be active and not suppressed. 1.12 Instruction Format for Single Effective Address Instruction Word This instruction format is used when the instruction only specifies a single effective address and requires zero extension words. One example is the LEA instruction. The effective address field of the instruction op-code is sufficient to specify fully the source of the effective address. The general format is provided in Table 3. Table 3. Instruction Format for Single Effective Address Instruction Word 15 14 13 X X X 12 11 10 Op-Code X X X 9 8 7 6 X X X X 5 4 3 2 1 0 Effective Address Mode Register The instruction op-code specifies whether the selected register is an address register or a data register and how the register is to be used. 1.13 Format for the Brief Extension Word This is used by instructions that cannot use the single effective address instruction word format but only require a single extension word to specify fully the source of the effective address. One type of addressing mode would be instructions that are using an indexed addressing mode with an 8-bit displacement. For example: add.l 0x11(a1,a2.w*4),d1 or add.l (0x11,a1,a2.w*4),d1 (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 13 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 This uses address register indirect with index (8-bit displacement) and generates the following op-code followed by the brief extension word (both in hex): D2B1 A411 The general format is provided in Table 4. Table 4. Instruction Format for Brief Instruction Word 15 D/A 14 13 12 Register 11 W/L 10 9 Scale 8 0 7 6 5 4 3 2 1 Displacement 0 Where: D/A--Index register type - 0--Dn - 1--An Register--Index register number W/L--Word/Long Word Size - 0--16-bit word sign-extended to 32 bits - 1--32-bit long word used as is Scale--Scale factor - 00--0 - 01--1 - 10--2 - 11--4 Displacement--8-bit displacement value, can be zero 1.14 Format for the Full Extension Word This is used by instructions that cannot use either the single effective address-instruction word format or the brief extension word format. This is because it requires multiple extension words to specify fully the source of the effective address. One type of addressing mode would be instructions that are using an indexed addressing mode with a 16-bit or 32-bit displacement. For example: add.l 0x1111(a1,a2.w*4),d1 add.l (0x1111,a1,a2.w*4),d1 or (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 14 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 This uses address register indirect with index (16-bit base displacement) and generates the following op-code followed by the full extension word and finally the 16-bit displacement value (all in hex): D2B1 A520 1111 Another example is: add.l 0x22221111(a1,a2.w*4),d1 add.l (0x22221111,a1,a2.w*4),d1 or This uses address register indirect with index (32-bit base displacement) and generates the following op-code followed by the full extension word and finally the 32-bit displacement value (all in hex): D2B1 A530 2222 1111 The general format is provided in Table 5. Table 5. Format for the Full Extension Word 15 D/A 14 13 12 Register 11 10 9 8 7 6 5 4 W/L Scale 1 BS IS BD Size Base displacement (0, 1, or 2 words) 3 0 2 1 0 I/IS Where: D/A--Index register type - 0--Dn - 1--An Register--Index register number W/L--Word/Long Word Size - 0--16-bit word sign-extended to 32 bits - 1--32-bit long word used as is Scale--Scale factor - 00--0 - 01--1 - 10--2 - 11--4 (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 15 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 BS--Base Register Suppress - 0--Base register added - 1--Base register suppressed IS--Index Suppress - 0--Evaluate and add index operand - 1--Suppress index operand BD Size--Base Displacement Size - 00--Reserved (will cause an illegal instruction exception) - 01--Null displacement - 10--Word Displacement - 11--Long-Word Displacement I/IS--Index/Indirect Selection - Not used by fido1100, should always be 000, if IS = 1 and this not 000, will cause an illegal instruction exception Base displacement--16-bit or 32-bit displacement value (optional) (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 16 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 2. Instruction Set Reference Guide September 4, 2008 Instruction Descriptions Descriptions of the fido1100 instructions, presented alphabetically, are given on the following pages. Except where indicated, the following notation is used: Data Destination Source Vector An Ax, Ay Dn Rc Rn Dh, Dl Dr, Dq Dx, Dy Dym, Dyn Xn [An] cc d# # label list [...] (...) PC SP SR SSP USP FC DFC SFC + - / * = > Immediate data from an instruction Destination contents Source contents Location of exception vector Any address register (A7 to A0) Address registers used in computation Any data register (D7 to D0) Control register (VBR, SFC, DFC) Any address or data register Data registers, high- and low-order 32 bits of product Data registers, division remainder, division quotient Data registers, used in computation Data registers, table interpolation values Index register Address extension Condition code Displacement (e.g., d16 is a 16-bit displacement) Effective address Immediate data; a literal integer Assembly program label List of registers (e.g., D3-D0) Bits of an operand (e.g., [7] is Bit 7, [31-24] are Bits 31 to 24) Contents of a referenced location (e.g., (Rn) refers to the contents of Rn) Program counter Active stack pointer Status register Supervisor stack pointer User stack pointer Function code Destination function code register Source function code register Addition or post increment Subtraction or predecrement Division or conjunction Multiplication Equal to Not equal to Greater than (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 17 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller < & | ^ BCD LSW MSW {R/W} Instruction Set Reference Guide September 4, 2008 Greater than or equal to Less than Less than or equal to Boolean AND Boolean OR Boolean XOR (exclusive OR) Binary coded decimal, indicated by subscript (e.g., Source10 is a BCD source operand) Least significant word Most significant word Read/write indicator (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 18 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ABCD--Add Decimal with Extend Assembler Syntax: ABCD Dy, Dx ABCD - (Ay), - (Ax) Operation: Source10 + Destination10 + X bit Destination Attributes: Size = byte Privileged: No Condition Codes: X--Set the same as Carry Bit N--Undefined Z--Cleared if result is non-zero; unchanged otherwise V--Undefined C--Set if decimal carry was generated; cleared otherwise Note: Normal programming use of this instruction is to set the Z Bit prior to performing this operation. This allows the Z Bit to be tested during multiprecision operations. Instruction Format: 15 14 13 12 1 1 0 0 11 10 9 Op-Code Destination Register 8 7 6 5 1 0 0 0 4 3 2 1 0 Effective Address 0 R/M Source Register Where: Destination Register--Specifies either a data or an address register as the location of the destination operand. Register/Memory (R/M): - 0--Operands are addresses as Dn,Dn - 1--Operands are addresses as -(An),-(An) Source Register--Specifies either a data or an address register as the location of the source operand. Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 1, Core Addressing Modes Summary). ABCD--Add Decimal with Extend (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 19 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 This instruction only uses two addressing modes (determined by the R/M Bit): Data Register Direct--Dn,Dn (both source and destination are data registers). Address Register Indirect with Predecrement---(An),-(An) (both source and destination are pointed to by address registers). ABCD--Add Decimal with Extend (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 20 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ADD--Add Assembler Syntax: ADD , Dn ADD Dn, Operation: Source + Destination Destination Attributes: Size = byte, word or long Privileged: No Condition Codes: X--Set the same as Carry Bit N--Set if result is negative; cleared otherwise Z--Set if result is zero; cleared otherwise V--Set if overflow is generated; cleared otherwise C--Set if carry was generated; cleared otherwise Instruction Format: 15 14 13 12 11 10 9 Op-Code 1 1 0 1 Register 8 7 6 Opmode 5 4 3 2 1 0 Effective Address Mode Register Where: Register Field--Specifies any one of the eight data registers. Opmode Field--Specifies whether the effective address is the source or the destination as follows: Operation (EA) + (Dn) (Dn) (Dn) + (EA) (EA) Byte 000 100 Word 001 101 Long 010 110 Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 2, Core Addressing Modes Summary). ADD--Add (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 21 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Addressing modes for source operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Applies? Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Addressing modes for destination operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) (An)+ -(An) (d16,An) (d8,An,Xn.Size*Scale) (bd,An,Xn.Size*Scale) (d16,PC) (d8,PC,Xn.Size*Scale) (bd,PC,Xn.Size*Scale) (xxx).W (xxx).L #xxx 010 011 100 101 110 110 111 111 111 111 111 111 Notes - Word and long word only - - - - - - - - - - - ADDI and ADDQ are used if the source is immediate data Applies? - - N N N N N N 010 011 011 000 001 100 Yes Yes Yes Yes Yes Yes - - - Yes Yes - Notes - ADDA is used when the destination is an address register. - - - - - - - - - - - - ADD--Add (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 22 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ADDA--Add Address Assembler Syntax: ADDA An Operation: Source + Destination Destination Attributes: Size = word or long Privileged: No Condition Codes: X--Not affected N--Not affected Z--Not affected V--Not affected C--Not affected Instruction Format: 15 14 13 12 11 10 9 Op-Code 1 1 0 1 Register 8 7 6 Opmode 5 4 3 2 1 0 Effective Address Mode Register Where: Register Field--Specifies any one of the eight address registers as the destination. Opmode Field--Specifies the size of the operand: - 011--Word operation. The source operand is sign-extended to a long and the operation performed on the address register uses all 32 bits. - 111--Long operation. Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 3, Core Addressing Modes Summary) and always indicate a source operand. ADDA--Add Address (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 23 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Addressing modes for source operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Applies? Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Notes - - - - - - - - - - - - - - ADDA--Add Address (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 24 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ADDI--Add Immediate Assembler Syntax: ADDI #, Operation: Immediate Data + Destination Destination Attributes: Size = byte, word or long Privileged: No Condition Codes: X--Set same as Carry Bit N--Set if result is negative; cleared otherwise Z--Set if result is zero; cleared otherwise V--Set if overflow is generated; cleared otherwise C--Set if carry was generated; cleared otherwise Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Op-Code Effective Address 0 0 0 0 0 1 1 0 Size Mode Register Word Data (16 Bits) Byte Data (8 Bits) Long Data (32 Bits) Where: Size Field (size of immediate data must match operand size): - 00--Byte operation data is low-order byte of immediate word. - 01--Word operation data is the entire immediate word. - 10--Long operation data is in the next two immediate words. Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 4, Core Addressing Modes Summary) and always indicate a destination operand. ADDI--Add Immediate (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 25 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Addressing modes for destination operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Applies? Yes - Yes Yes Yes Yes Yes Yes - - - Yes Yes - Notes - - - - - - - - - - - - - - ADDI--Add Immediate (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 26 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ADDQ--Add Quick Assembler Syntax: ADDQ #, Operation: Immediate Data + Destination Destination - Immediate data is stored as a part of the instruction word (three bits) and can range from 1 to 8. Attributes: Size = byte, word or long - When the destination operand is a data register or is in memory the size can be byte, word, or long word. - When the destination operand is an address register size is word or long word only. - When adding to address registers the Condition Codes are not altered and entire register is used regardless of operand size. Privileged: No Condition Codes: X--Set same as Carry Bit N--Set if result is negative; cleared otherwise Z--Set if result is zero; cleared otherwise V--Set if overflow is generated; cleared otherwise C--Set if carry is generated; cleared otherwise Note: When adding to address registers the condition codes are not altered. Instruction Format: 15 14 13 12 11 10 9 Op-Code 0 1 0 1 Data 8 7 6 0 Size 5 4 3 2 1 0 Effective Address Mode Register Where: Data Field--Specifies three bits of immediate data with a value ranging from 1 to 8 (000 represents 8). ADDQ--Add Quick (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 27 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Size Field: - 00--Byte operation - 01--Word operation - 10--Long-Word operation Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 2, Core Addressing Modes Summary) and always indicate a destination operand. Addressing modes for destination operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Applies? Yes Yes Yes Yes Yes Yes Yes Yes - - - Yes Yes - Notes - Word and long word only - - - - - - - - - - - - ADDQ--Add Quick (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 28 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ADDX--Add Extended Assembler Syntax: ADDX Dy, Dx ADDX - (Ay), - (Ax) Operation: Source + Destination + X Bit Destination Attributes: Size = byte, word or long Privileged: No Condition Codes: X--Set same as Carry Bit N--Set if result is negative; cleared otherwise Z--Cleared if result is non-zero; unchanged otherwise V--Set if overflow occurs; cleared otherwise C--Set if carry was generated; cleared otherwise Note: Normal programming use of this instruction is to set the Z Bit prior to performing this operation. This allows this bit to be tested during multiprecision operations. Instruction Format: 15 14 13 12 1 1 0 1 11 10 9 Op-Code Destination Register 8 7 6 5 1 Size 0 4 3 2 1 0 Effective Address 0 R/M Source Register Where: Destination Register--Specifies either a data or an address register as the location of the destination operand. Size: - 00--Byte operation - 01--Word operation - 10--Long-Word operation - 11--Reserved Register/Memory (R/M): - 0--Operands are addresses as Dn,Dn - 1--Operands are addresses as -(An),-(An) Source Register--Specifies either a data or an address register as the location of the source operand. ADDX--Add Extended (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 29 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 This instruction only uses two addressing Modes (determined by the R/M Bit): Data Register Direct--Dn,Dn (both source and destination are data registers). Address Register Indirect with Predecrement---(An),-(An) (both source and destination are pointed to by address registers). ADDX--Add Extended (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 30 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 AND--And Assembler Syntax: AND ,Dn AND Dn, Operation: Source & Destination Destination Attributes: Size = byte, word or long Privileged: No Condition Codes: X--Not affected N--Set if most significant bit of result is set; cleared otherwise Z--Set if result is zero; cleared otherwise V--Always cleared C--Always cleared Instruction Format: 15 14 13 12 11 10 9 Op-Code 1 1 0 0 Register 8 7 6 Opmode 5 4 3 2 1 0 Effective Address Mode Register Where: Register Field--Specifies any one of the eight data registers. Opmode Field--Specifies whether the effective address is the source or the destination as follows: Operation (EA) & (Dn) (Dn) (Dn) & (EA) (EA) Byte 000 100 Word 001 101 Long 010 110 Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 5, Core Addressing Modes Summary). AND--And (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 31 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Addressing modes for source operand: Mode Register Addressing Mode Field Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Instruction Set Reference Guide September 4, 2008 Applies? Yes - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Addressing modes for destination operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Notes - - - - - - - - - - - - - Most assemblers use the ANDI instruction when the source is immediate data. Applies? - - Yes Yes Yes Yes Yes Yes - - - Yes Yes - Notes - - - - - - - - - - - - - - AND--And (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 32 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ANDI--And Immediate Assembler Syntax: ANDI #, Operation: Immediate Data & Destination Destination Attributes: Size = byte, word or long Privileged: No Condition Codes: X--Not affected N--Set if most significant bit of result is set; cleared otherwise Z--Set if result is zero; cleared otherwise V--Always cleared C--Always cleared Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Op-Code Effective Address 0 0 0 0 0 0 1 0 Size Mode Register Word Data (16 Bits) Byte Data (8 Bits) Long Data (32 Bits) Where: Size Field (size of immediate data must match operand size): - 00--Byte operation data is low-order byte of immediate word. - 01--Word operation data is the entire immediate word. - 10--Long operation data is in the next two immediate words. - 11--Reserved Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 2, Core Addressing Modes Summary) and always indicate a destination operand. ANDI--And Immediate (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 33 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Addressing modes for destination operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Applies? Yes - Yes Yes Yes Yes Yes Yes - - - Yes Yes - Notes - - - - - - - - - - - - - - ANDI--And Immediate (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 34 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ANDI to CCR--And Immediate to Condition Code Register Assembler Syntax: ANDI #, CCR Operation: Immediate Data Byte & CCR CCR Attributes: Size = byte Privileged: No Condition Codes: X--Cleared if [4] of immediate operand is zero; unchanged otherwise N--Cleared if [3] of immediate operand is zero; unchanged otherwise Z--Cleared if [2] of immediate operand is zero; unchanged otherwise V--Cleared if [1] of immediate operand is zero; unchanged otherwise C--Cleared if [0] of immediate operand is zero; unchanged otherwise Instruction Format: 15 14 13 12 0 0 0 0 0 0 0 0 11 0 0 10 0 0 9 1 0 8 0 0 7 0 6 5 4 3 2 1 0 1 1 1 0 0 Immediate Data Byte 0 0 Where: Immediate Data Byte--Immediate byte value to be ANDed with Condition Code Register. ANDI to CCR--And Immediate to Condition Code Register (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 35 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ANDI to SR--And Immediate to Status Register Assembler Syntax: ANDI #, SR Operation: Immediate Data Word & SR SR Attributes: Size = word Privileged: Yes Condition Codes: X--Cleared if [4] of immediate operand is zero; unchanged otherwise N--Cleared if [3] of immediate operand is zero; unchanged otherwise Z--Cleared if [2] of immediate operand is zero; unchanged otherwise V--Cleared if [1] of immediate operand is zero; unchanged otherwise C--Cleared if [0] of immediate operand is zero; unchanged otherwise Instruction Format: 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 0 0 1 0 0 1 1 Immediate Data Word 4 1 3 1 2 1 1 0 0 0 Where: Immediate Data Word--Immediate word value to be ANDed with Status Register Note: All implemented bits of the SR are affected. ANDI to SR--And Immediate to Status Register (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 36 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 ASL/ASR--Arithmetic Shift Assembler Syntax: ASd Dx,Dy ASd #, Dy ASd where d is direction, L or R Operation: Destination shifted by count Destination Attributes: Size = byte, word or long Privileged: No Notes: Arithmetically shift operand left or right. Shift either the contents of a data register or the contents of a memory location. Carry and Extend Bit of CCR receives last bit shifted out of operand. When shifting the contents of a data register, the shift count can be specified in two ways: - Immediate--Shift count contained in instruction op-code. - Register--Shift count is the value of a specified data register, modulo 64. Contents of address registers cannot be shifted. An operand in memory can be shifted by one bit only and operand size is restricted to a word. For Arithmetic Shift Left (ASL): - Operand is shifted left by the number of positions specified by the shift count. - The high-order bit is shifted into both the X and Carry Bits. - A zero is shifted into the low-order bit. - The overflow bit indicates if any sign changes occur during the shift. For Arithmetic Shift Right (ASR): - Operand is shifted right by the number of positions specified by the shift count. - The low-order bit is shifted into both the X and Carry Bits. - The sign bit (MSB) is shifted into the high-order bit. Condition Codes: X--Set according to the last bit shifted out of the operand. Unaffected for a shift count of zero. N--Set if most significant bit of result is set; cleared otherwise. Z--Set if result is zero; cleared otherwise. V--Set if the most significant bit is changed during the shift operation; cleared otherwise. ASL/ASR--Arithmetic Shift (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 37 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 C--Set according to the last bit shifted out of the operand. Cleared for a shift count of zero. See Figure 1 for a comparison of syntax, operand size, and operation of ASL/ASR, LSL/LSR, ROL/ROR, ROXL/ROXR, and SWAP instructions. ASL/ASR--Arithmetic Shift (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 38 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Instruction Syntax ASL Dn, Dn #(data), Dn (ea) Operand Size 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn, Dn #(data), Dn (ea) 8, 16, 32 8, 16, 32 16 Dn 16 ASR LSL LSR ROL ROR ROXL ROXR SWAP Operation 0 X/C X/C X/C 0 0 X/C C C C X X C MS LSW W Figure 1. Shift and Rotate Instructions Diagram Instruction Format (register shifts): 15 14 13 12 11 10 9 1 1 0 1 Count/Register 8 Dir 7 6 Size 5 I/R 4 0 3 0 2 1 0 Register Where: Count/Register Field: - I/R = 0--This field specifies the shift count; 1 through 7 indicate shift one to seven times and 0 indicates shift eight times. - I/R = 1--This field specifies the data register containing the shift count, modulo 64. ASL/ASR--Arithmetic Shift (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 39 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 Direction Field (Dir): - 0--Shift Right - 1--Shift Left Size Field: - 00--Byte operation - 01--Word operation - 10--Long operation - 11--Reserved I/R Field: - 0--Shift count is defined by the instruction word. - 1--Shift count is defined by the specified data register, modulo 64. Register Field--Specifies the data register to shift. Instruction Format (memory shifts): 15 14 13 12 11 10 9 8 Op-Code 1 1 1 0 0 0 0 Dir 7 6 1 1 5 4 3 2 1 0 Effective Address Mode Register Where: Direction Field (Dir): - 0--Shift Right - 1--Shift Left Effective-Address fields are as per Instruction Single Word Format and address mode tables (see Table 2, Core Addressing Modes Summary) and always indicate the operand to shift. Addressing modes for destination operand: Addressing Mode Mode Field Register Field Dn 000 N An 001 N (An) 010 N (An)+ 011 N -(An) 100 N (d16,An) 101 N (d8,An,Xn.Size*Scale) 110 N (bd,An,Xn.Size*Scale) 110 N (d16,PC) 111 010 (d8,PC,Xn.Size*Scale) 111 011 (bd,PC,Xn.Size*Scale) 111 011 (xxx).W 111 000 (xxx).L 111 001 #xxx 111 100 Applies? - - Yes Yes Yes Yes Yes Yes - - - Yes Yes - Notes - - - - - - - - - - - - - - ASL/ASR--Arithmetic Shift (R) IA222080723-01 UNCONTROLLED WHEN PRINTED OR COPIED Page 40 of 193 http://www.Innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Instruction Set Reference Guide September 4, 2008 BCC--Branch Conditionally Assembler Syntax: BCC