Product Specification
PE42451
Page 3 of 11
Document No. DOC-22914-2 │www.psemi.com ©2009-2014 Peregrine Semiconductor Corp. All rights reserved.
Table 3. Pin Descriptions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® de vice, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be take n to avoid exceeding the
specified rating.
Latch-Up Avoidance
Unlike conventional CMO S devices, UltraCMOS®
devices are immune to latch-up.
Table 4. Absolute Maximum Ratings
Exceeding ab solute maximum rati ngs may cau se
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table.
Symbol Parameter/Conditions Min Max Units
TST Storage temperature range -60 +150 °C
PMAX
Maximum Operating Power
(RFX-RFC, All Bands (50Ω),
100% duty cycle) 33 dBm
PMAX
Maximum power into
termination (RFX, All Bands
(50Ω),100% duty cycle) 24 dBm
VESD ESD Voltage HBM6, All Pins 3500 V
VESD ESD Voltage MM7, All Pins 150 V
Notes: 6. Human Body Model ESD Voltage (HBM, MIL_STD 883
Method 3015.7)
7. Machine Model ESD Voltage (JESD22-A115-A)
Mode V3 V2 V1
All off 0 0 0
RF1 on 0 0 1
RF2 on 0 1 0
RF3 on 0 1 1
RF4 on 1 0 0
RF5 on 1 0 1
All off 1 1 0
Unsupported 1 1 1
Table 5. Truth Table
Exposed
Ground
Paddle
GND
RF5
GND
GND GND
Vdd
V1
V2
GND
RFC
GND
GND
Vss
EXT
/
GND
RF4
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
1
V3
RF1
GND GND
GND
RF3
GND
GND
RF2
GND
7
8
9
10
11
12
Figure 3. Pin Configuration (Top View)
Moisture Sensitivity Level
The Moisture Sensitivity Le vel rating for the PE42451 in
the 24-lead 4x4 QFN package is MSL 1.
Note: 4. Blocking capacitors needed only when non-zero DC
voltage present.
5. Pin 20 must be grounded when using internal Vss supply
Switching Frequency
The PE42451 has a maxim um 25 kHz switching rate
when the internal negative voltage generator is used
(pin 20=GND). The rate at which the PE4245 1 can be
switched is only limited to the switching time if an
external -3 V supply is provided (pin 20 =VssEXT ).
Pin # Name Description
1, 3, 4, 6, 7, 9, 10,
12, 13, 15, 21, 23, 24 GND Ground
2 RF54 RF I/O
5 RF44 RF I/O
8 RF34 RF I/O
11 RF24 RF I/O
14 RF14 RF I/O
16 VDD Supply
17 V1 Switch control input, CMOS logic level
18 V2 Switch control input, CMOS logic level
19 V3 Switch control input, CMOS logic level
20 VssEXT /
GND5 External Vss Control / Ground
22 RFC4 RF Common
Paddle GND Ground for proper device operation
Optional External Vss Control (VssEXT)
For proper operation, the V ssEXT control must be
grounded or at the Vss vol t age specified in the
Operating Ranges table (Table 2). When the Vss EXT
control pin on the package is grounded the switch
FET’s are biased with an internal low sp ur negative
voltage generator. For appl ications that require the
lowest possib le spur performance, VssEXT can be
applied to bypass the internal negative voltage
generator to eliminate the spurs.