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General Description
The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±7.5ns skew between any parallel
data input and the reference clock. An external
155MHz reference clock is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clock for tim-
ing the outgoing data streams.
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clock from an external
clock/data recovery device (MAX3876), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clock output, and the MAX3832 pro-
vides a 155MHz LVDS clock output. An internal frame
detector looks for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopback modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) packages and are specified over the
upper commercial (0°C to +85°C) temperature range.
Features
♦+3.3V Single Supply
♦1.45W Power Dissipation (MAX3831)
♦4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock Generator
♦Frame Detection Maintains Channel Assignment
♦±7.5ns Elastic Store Range
♦2.5ps RMS Serial-Data Output Random Jitter
♦8ps Serial-Data Output Deterministic Jitter
♦622Mbps LVDS Parallel Input/Output
♦2.488Gbps Serial CML Input/Output
♦On-Chip Pattern Generator Provides
High-Speed BIST
♦System Test Flexibility: System Loopback,
Line Loopback
♦Loss-of-Frame Indicator
Applications
SDH/SONET Backplanes ATM Switching Networks
High-Speed Parallel Links Line Extenders
Intrarack/Subrack Dense Digital Cross-
Interconnects Connects
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
________________________________________________________________ Maxim Integrated Products 1
19-1534; Rev 1; 10/99
TTL
LVDS
LVDS
LVDS
4
4
4
4
TTL TTL TTL
TTL
2.5Gbps
CDR
CMOS
OVERHEAD
2.5Gbps
OPTICAL
TRANSCEIVER
TTL
CML
CML
GND
TRIEN
+3.3V
0.33µF
0.1µF
VCC
FIL+ FIL-
PDI1+ TO PDI4+
PDI1- TO PDI4-
PDO1+ TO PDO4+
PDO1- TO PDO4-
PCLKO+
PCLKO-
SCLKI-
SCLKI+
SDI-
SDI+
SDO+
SDO-
MAX3831
MAX3832
MAX3876
LVDS RCLKI+
RCLKI-
RSETES
LBEN
RSETFR
TEST LOF PLBEN
155MHz REF
CLOCK INPUT
TTL
Typical Application Circuit
Ordering Information
PART
MAX3831UCB
MAX3832UCB 0°C to +85°C
0°C to +85°C
TEMP. RANGE PIN-PACKAGE
64 TQFP-EP
64 TQFP-EP
Pin Configuration appears at end of data sheet.
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, LVDS differential load = 100Ω±1%, CML load = 50Ω±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C and VCC = +3.3V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (VCC)...............................-0.5V to +5.0V
Input Voltage (LVDS, TTL)..........................-0.5V to (VCC + 0.5V)
CML Input Voltage ..........................(VCC - 0.8V) to (VCC + 0.5V)
FIL+, FIL- Voltage.......................................-0.5V to (VCC + 0.5V)
TTL Output Voltage ....................................-0.5V to (VCC + 0.5V)
LVDS Output Voltage ..................................-0.5V to (VCC +0.5V)
CML Output Currents..........................................................22mA
Continuous Power Dissipation (TA= +85°C) (Note 1)
64-Pin TQFP-EP (derate 40.0mW/°C above +85°C) .........2.6W
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Short outputs together (Note 3)
TRIEN = VCC
TRIEN = GND
Figure 1
LVDS input, VOS = 1.2V
CONDITIONS
V
VCC - VCC +
0.6 0.4
VIS
Single-Ended Input Voltage Range
VVCC - 0.2Output Common-Mode Voltage
Ω85 100 115Differential Output Impedance
mVp-p640 800 1000VODp-p
Differential Output Voltage
mA12Output Current
Ω80 120
Differential Output Impedance MΩ>1
mV±25
∆VOS
Change in Magnitude of Output
Offset Voltage for Complementary
States
V1.125 1.275VOS
Output Offset Voltage
mV±25
∆VOD
Change in Magnitude of
Differential Output Voltage for
Complementary States
mA
440 580
ICC
Supply Current
mV250 400
VOD
Differential Output Voltage
V0.925VOL
Output Voltage Low
V1.475VOH
Output Voltage High
µA270IOS
Input Common-Mode Current
mV0 2400VIN
Input Voltage Range
mV-100 +100VIDTH
Differential Input Threshold
mV90VHYST
Threshold Hysteresis
Ω85 100 115RIN
Input Impedance
UNITSMIN TYP MAXSYMBOLPARAMETER
Figure 2
Ω85 100 115Differential Input Impedance
mVp-p400 1200Differential Input Voltage Swing
LVDS INPUTS AND OUTPUTS
CML INPUTS AND OUTPUTS
Note 1: Based on empirical data from the MAX3831/MAX3832 evaluation kit.
CML inputs and outputs open,
LVDS input VOS = 1.2V (Note 2)
MAX3831
MAX3832 480 614
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, LVDS differential load = 100Ω±1%, CML load = 50Ω±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C and VCC = +3.3V.)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, LVDS differential load = 100Ω±1%, CML load = 50Ω±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C and VCC = +3.3V.) (Note 4)
TRIEN = GND
IOL = 2mA
IOH = 20µA
VIH = 2.0V
VIL = 0
CONDITIONS
kΩ6Output Impedance
V0.4VOL
Output Voltage Low
V2.4VOH
Output Voltage High
V2.0VIH
Input Voltage High
V0.8VIL
Input Voltage Low
µA-250 -50IIH
Input Current High
µA-550 -100IIL
Input Current Low
UNITSMIN TYP MAXSYMBOLPARAMETER
Note 2: When TEST = GND, the pattern generator will consume an additional 30mA.
Note 3: Guaranteed by design and characterization.
(Note 7)
(Note 5)
20% to 80%
CONDITIONS
psp-p
818SDJ
Serial-Data Output Deterministic
Jitter
psRMS
3.5
Mbps622.08Parallel Input Data Rate
ns±7.5tes
Maximum Parallel Input Skew
Gbps2.48832Serial-Data Output Rate
ps120tr, tf
Serial-Data Output Rise/Fall Time
UNITSMIN TYP MAXSYMBOLPARAMETER
Figure 3
Figure 3
Mbps622.08PDO±Parallel-Data Output Rate
Gbps2.48832Serial-Data Input Rate
ps100tSU
Serial-Data Setup Time
ps100tH
Serial-Data Hold Time
(Note 6) psp-p
40
SRJSerial-Data Output Random Jitter
TTL INPUTS AND OUTPUTS
MAX3831
PCLKO±Parallel-Clock Output Frequency MHz
622.08
MAX3831, Figure 3tCLK-Q
PCLKO to PDO_ Delay ps-100 90 300
Any differential pairtSKEW1
LVDS Differential Skew ps65
PDO1± to PDO4±tSKEW2
LVDS Channel-to-Channel Skew ps<100
LVDS Three-State Enable Time ns30
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset.
Note 6: Measured with a reference clock jitter of <1psRMS.
Note 7: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.
MAX3832 155.52
20% to 80%LVDS Output Rise/Fall Time ps350
4:1 MULTIPLEXER WITH CLOCK GENERATOR
1:4 DEMULTIPLEXER
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
4 _______________________________________________________________________________________
SINGLE-ENDED OUTPUT |VOD|
VOD
VPDO- VOH
VOS
VODp-p = VPDO+ - VPDO-
-VOD
+VOD
0V
0V (DIFF)
VOL
VPDO+
DIFFERENTIAL OUTPUT
D
PDO+
RL = 100Ω
PDO-
V
Figure 1. Definition of the LVDS Output
SDI+
SDI-
VID
(SDI+) - (SDI-) 400mVp-p MIN
1200mVp-p MAX
200mV MIN
600mV MAX
Figure 2. Definition of the CML Input
SCLKI
SDI
PCLKO
PDO1–PDO4
NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).
tSCLK = 1 / fSCLK
tSU
tCLK-Q
tH
Figure 3. Timing Parameters
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
_______________________________________________________________________________________ 5
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3831/2 toc01
50ps/div
223-1 PRBS PATTERN
SERIAL-DATA OUTPUT JITTER
MAX3831/2 toc02
5ps/div
WIDEBAND RMS
JITTER = 2.48ps
0
200
100
400
300
500
600
-50 0 25-25 50 75 100
SUPPLY CURRENT vs. TEMPERATURE
MAX3831/2 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX3832
MAX3831
-10
-6
-8
-2
-4
2
0
4
8
6
10
0 0.4 0.60.2 0.8 1.0 1.2 1.4 1.6
ELASTIC STORE RANGE
MAX3831/2 toc04
DATA TO RCLKI DELAY AT RESET (ns)
VARIATION OF DATA DELAY AFTER RESET (ns)
CHANNEL ALIGNED TO RCLKI
ERROR-FREE OPERATION
-20
20
0
60
40
80
100
-50 0 25-25 50 75 100
SERIAL-DATA HOLD TIME
MAX3831/2 toc05
TEMPERATURE (°C)
HOLD TIME (ps)
20
0
60
40
80
100
-50 0 25-25 50 75 100
SERIAL-DATA SETUP TIME
MAX3831/2 toc06
TEMPERATURE (°C)
SETUP TIME (ps)
0
100
50
200
150
250
300
-50 0 25-25 50 75 100
MAX3831
PARALLEL CLOCK-TO-DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3831/2 toc07
TEMPERATURE (°C)
PCLKO TO PDO_ PROPAGATION DELAY (ps)
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
6 _______________________________________________________________________________________
7
Self-Test Enable. When this TTL input is forced low, the built-in pattern generator generates
a standard OC-12 SONET-like frame of 12 A1s, 12 A2s, and 9696 bytes of 27- 1 pseudo-
random bits. This also enables an internal serial-system-loopback path. The CML inputs
(SDI± and the SCLK±) and the LVDS inputs are ignored in this mode. An internal 15kΩpull-
up resistor pulls TEST high for normal operation.
TEST
9
8Positive CML Serial-Data Input, 2.488GbpsSDI+
Negative CML Serial-Data Input, 2.488GbpsSDI-
12
11 Positive CML Serial-Clock Input, 2.488GHzSCLKI+
Negative CML Serial-Clock Input, 2.488GHzSCLKI-
15
14 Negative LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832)PCLKO-
Positive LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832)PCLKO+
30
18–23, 26, 27 No ConnectionN.C.
Frame Reset. When this TTL input is forced low, the frame detector and pattern generator
are reset. The LOF output is also asserted low. An internal 15kΩpull-up resistor pulls
RSETFR high for normal operation.
RSETFR
33
31 TTL Loss-of-Frame Output. Asserts low in a loss-of-frame condition.
LOF
3-State Enable. When this TTL input is forced low, all TTL and LVDS outputs go into a high-
impedance state. An internal 15kΩpull-up resistor pulls TRIEN high for normal operation.
TRIEN
35, 37, 40, 42
34, 36, 39, 41 Negative LVDS Parallel-Data Output, 622MbpsPDO4- to PDO1-
Positive LVDS Parallel-Data Output, 622MbpsPDO4+ to PDO1+
45, 47, 51, 53
44, 46, 50, 52 Negative LVDS Parallel-Data Input, 622MbpsPDI4- to PDI1-
Positive LVDS Parallel-Data Input, 622MbpsPDI4+ to PDI1+
54
Parallel System Loopback Enable. When this TTL input is forced low, the LVDS parallel
inputs route through the elastic store to the LVDS parallel outputs. This bypasses the high-
speed mux and demux. An internal 15kΩpull-up resistor pulls PLBEN high for normal oper-
ation.
PLBEN
PIN FUNCTIONNAME
6
Line Loopback Enable. When this TTL input is forced low, the CML serial-data inputs (SDI±)
route directly to the CML serial-data outputs (SDO±). No other inputs or outputs are affected.
An internal 15kΩpull-up resistor pulls LBEN high for normal operation. See Test Loopbacks.
LBEN
4Positive CML Serial-Data Output, 2.488GbpsSDO+
3Negative CML Serial-Data Output, 2.488GbpsSDO-
2, 5, 10, 13,
17, 24, 38, 55,
59, 64
+3.3V Supply VoltageVCC
1, 16, 25, 28,
29, 32, 43, 48,
49, 60, 63
Supply GroundGND
Pin Description
56 Negative LVDS Reference Clock Input, 155.52MHz RCLKI-
57 Positive LVDS Reference Clock Input, 155.52MHzRCLKI+
_______________Detailed Description
The MAX3831/MAX3832 use a 4:1 mux and 1:4 demux
with an elastic store buffer to simplify SDH/SONET
interconnect I/O routing. The 622Mbps low-voltage dif-
ferential signal (LVDS) parallel inputs pass through the
10-bit elastic store buffer, which accommodates ±7.5ns
skew on any single input relative to the 155MHz refer-
ence clock input RCLKI. This reference clock is
required to synthesize the internal 2.488GHz clock
used to drive the elastic store and 4:1 multiplexer. All
TTL and LVDS outputs can be placed in a high-imped-
ance state. See Figure 4 for a functional diagram.
The 4:1 mux bit-interleaves the parallel data, providing
a 2.488Gbps CML serial output to the optical or electri-
cal driver. The CML serial input receives the
2.488Gbps data, the demux deinterleaves it to
622Mbps and sends the data to the frame detector.
The frame detector monitors one 622Mbps channel and
rolls the demux into the proper channel assignment.
The MAX3831/MAX3832 include high-speed, built-in
self-test (BIST), which also allows testing of the
622Mbps parallel-system loopback and the 2.488Gbps
line loopback.
Elastic Store Buffer
Each parallel-data input, PDI1 to PDI4, passes through
its respective 10-bit elastic store buffer. Following an
elastic store reset, this buffer accommodates ±7.5ns of
skew on any input relative to the 155MHz reference
clock. Figure 5 illustrates the elastic store buffer rela-
tionship with RCLKI. The Elastic Store Range graph in
the Typical Operating Characteristics shows the
amount of data skew tolerated.
Following a 10µs power-up period, the locations of the
individual data-channel bit transitions are acquired,
guaranteeing data preservation. The output of this
block passes directly into the 4:1 mux. After power-up,
the elastic store buffer must be reset by applying a low
pulse on RSETES for at least 10ns.
Due to the inherent uncertainty of the data transitions
between the parallel-data inputs there is no bit or frame
alignment between these inputs. However, the demux
ensures proper channel assignment is maintained.
Bit-Interleaved Multiplexer/
Demultiplexer
The MAX3831/MAX3832 use a bit interleave/deinterleave
mux/demux. To guarantee channel assignment, one of
the four channels is inverted before multiplexing to pro-
vide a reference for the frame detector during demulti-
plexing. After demultiplexing, the same channel is
inverted back to the original data format.
Frame Detector
After a 2.5Gbps serial data is bit deinterleaved into four
622Mbps channels, an SDH/SONET frame detector
monitors the fourth channel, looking for the 32-bit pat-
tern (A1A1A2A2) in the OC-12 header. To maintain cor-
rect channel assignment, the demux outputs rotate until
this 32-bit overhead pattern is reliably detected. A loss-
of-frame output, LOF, indicates when the received data
is in or out of frame. When LOF goes high, the frame
pattern is detected and the demux outputs are correct-
ly assigned. When LOF is low, the frame detection cir-
cuitry is searching for the correct frame. A RSETFR
(TTL, active low) is included to reset the frame detector
when necessary.
The frame detector uses an algorithm to detect an in-
frame condition and a loss-of-frame condition; this algo-
rithm is implemented to meet the SONET in-frame and
false-frame specs. The frame_search state will occur
upon start-up or reset. In this state, the frame detector
scans through the incoming serial data searching for the
framing pattern in the channel 4 output of the demux.
While in this state, if the framing pattern is not found
within 250µs, the demux channels are shifted (rolled)
and the frame search continues (Figure 6).
In-frame will be declared if two consecutive framing
patterns are found at the correct byte locations within
the SONET frame (9720 bytes). If this pattern is not pre-
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
_______________________________________________________________________________________________________ 7
Pin Description (continued)
PIN FUNCTIONNAME
58
Elastic Store Reset. The elastic buffer is centered on a rising edge of RSETES, maximizing
the elastic store range. Data must be present for 10µs before applying a pulse of at least
10ns. An internal 15kΩpull-up resistor pulls RSETES high for normal operation.
RSETES
62
61 Negative PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-.FIL-
Positive PLL Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-.FIL+
EP Ground. This must be soldered to a circuit board for proper thermal performance (see
Package Information).
Exposed Paddle
MAX3831/MAX3832
sent at the correct location (false frame), the state
machine will return to the frame_search state described
above. While in the in_frame state, each frame will be
checked for a framing pattern at the correct location.
Four consecutive false frames will cause the state
machine to return to the frame_search state described
above. The false-frame counter is reset with three or
fewer consecutive false frames.
Built-In Self-Test
with On-Chip Serial Loopback
An on-chip pattern generator can be enabled to pro-
duce a 622Mbps SDH/SONET-like transport overhead
followed by a pseudorandom bit sequence. This consists
of 12 A1s, 12 A2s, and a pseudorandom bit stream
(PRBS = 27- 1). When TEST is low, this pattern is distrib-
uted to all parallel inputs, bypassing the LVDS input
buffers. Note, this pattern is skewed by one 622MHz
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
DATA INPUT
A0A0PDI1
PDI2
PDI3
PDI4
≥10ns
-tes
+tes
RCLKI
PDI1
PDI2
PDI3
PDI4
B1B1
C0C0
D1D1
A0
B1
C0
D1
A1
A0 A1
B2B0
B1 B2
C0 C1
D0 D1
C1
D0
DATA OUTPUT OF ELASTIC STORE
AT t = to
DATA OUTPUT OF ELASTIC STORE
AT t > to
RSETES
Figure 5. Example of Elastic Store Function
8 _______________________________________________________________________________________
(155MHz)
RCLKI+
RCLKI-
PDI1+
PDI1-
PDI2+
PDI2-
PDI3+
PDI3-
PDI4+
PDI4-
PDO1+
PDO1-
PDO2+
PDO2-
PDO3+
PDO3-
PDO4+
PDO4-
PCLKO+
PCLKO-
RSETFR
FRAME
DETECTOR
CLOCK
GENERATOR
LOF
622MHz
2.488GHz
2.488Gbps
SDO+
SDO-
SDI+
SDI-
SCLKI+
SCLKI-
LINE LOOPBACK
2.488Gbps
SYSTEM LOOPBACK
ROTATE
CK
ES
ES
ES
ES
FIL-FIL+
2.488GHz
155MHz
622MHz
D
CK
4:1
MUX
FREQUENCY
GENERATOR
*MAX3831: fPCLKO = 622MHz, MAX3832: fPCLKO = 155MHz
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
TRIEN
LBEN
TEST
622Mbps PARALLEL LOOPBACK
1:4
DEMUX
TEST RSETES
PATTERN
GENERATOR
PLBEN
*
MAX3831
MAX3832
Figure 4. Functional Diagram
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
_______________________________________________________________________________________ 9
FRAME DETECT
START-UP OR RESET
START 250µs TIMER
FRAME_SEARCH
LOF = 0
FRAME
PATTERN
DETECTED?
1 FRAME DETECTED
RESET BYTE
AND FRAME
FRAME
PATTERN
DETECTED?
IN_FRAME
FRAME
PATTERN
DETECTED?
FRAME
PATTERN
DETECTED?
FRAME
PATTERN
DETECTED?
FRAME
PATTERN
DETECTED?
TIMER
TIMED OUT? ROLL DATA
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
LOF = 1
Figure 6. Frame Detection Flow Diagram
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
10 ______________________________________________________________________________________
clock cycle between each channel. In this test mode, ser-
ial data is internally looped back to the demux. All frame
detect logic is exercised using this mode. The CML
inputs (SDI± and SCLKI±) and LVDS inputs (PDI_±) are
ignored in this mode. After the BIST mode is enabled, the
loss-of-frame flag LOF goes high, indicating that the self-
test has passed. In normal operation, TEST is left open
(internally pulled high), disabling the pattern generator
and accepting data from the parallel input channels.
Test Loopbacks
Two additional test loopbacks are provided: parallel
system loopback and serial line loopback.
Parallel System Loopback
In parallel system loopback, four 622Mbps parallel
input channels are phase aligned by an associated 10-
bit elastic store and routed to the output LVDS buffers.
This loopback is controlled by setting PLBEN low.
Normal data transmission is resumed when PLBEN
goes high (internally pulled high).
Serial Line Loopback
Serial line loopback is used for testing the performance
of the optical transceiver and the transmission link. The
received 2.488Gbps data stream is routed to the trans-
mit CML output buffer. Line loopback is enabled when
LBEN is asserted low. When LBEN is left open (internally
pulled high), normal serial-data transmission resumes.
LVDS Parallel Interface
The MAX3831 parallel interface includes four OC-12
data inputs, a 155MHz reference clock input, four
622Mbps parallel-data outputs, and a 622MHz parallel-
clock output (MAX3832, fPCLKO = 155MHz). All parallel
inputs and outputs are LVDS compatible to minimize
power dissipation, speed transition time, and improve
noise immunity. The 155MHz input signal at RCLKI
requires a duty cycle between 40% and 60%.
The LVDS outputs go into a high-impedance state when
TRIEN is forced low. This simplifies system checks by
allowing vectors to be forced on the LVDS outputs.
CML Serial Interface
The MAX3831/MAX3832 provide a 2.488Gbps serial-
data stream to a driver and accept 2.488Gbps serial
data and a 2.488GHz clock signal from an external
clock and data recovery device (MAX3876). The high-
speed interface is CML compatible, resulting in lower
system power dissipation and excellent performance
(Figure 7).
__________Applications Information
Low-Voltage Differential
Signal Inputs/Outputs
The MAX3831/MAX3832 have LVDS inputs and outputs
for interfacing with high-speed digital circuitry. All LVDS
inputs and outputs are compatible with the IEEE-1596.3
LVDS specification. This technology uses 250mV to
400mV differential low-voltage amplitudes to achieve
fast transition times, minimize power dissipation, and
improve noise immunity.
For proper operation, the parallel clock and data LVDS
outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require
100Ωdifferential DC termination between the inverting
and noninverting outputs. Do not terminate these out-
puts to ground. The parallel-data LVDS inputs (PDI_+,
PDI_-) are internally terminated with 100Ωdifferential
input resistance and therefore do not require external
termination.
Interfacing with PECL/ECL
Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
50Ωtermination (Figures 8 and 9). Observe the com-
mon-mode input voltage specifications. AC-coupling is
required if a VCC other than 3.3V is used to maintain the
input common-mode level (Figure 8).
MAX3831
MAX3832
MAX3876
50Ω
50Ω
50Ω
50Ω
VCC
VCC
SDI+
SDI-
SDO+
SDO-
Figure 7. CML-to-CML Interface
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
______________________________________________________________________________________ 11
MAX3831
MAX3832
50Ω
50Ω
VCC
100Ω
PECL
LEVELS
SDI+
25Ω
25Ω
*SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL
IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
RT*
0.1µF
0.1µF
SDI-
RT*
MAX3831
MAX3832
50Ω
50Ω
82Ω
82Ω
82Ω
82Ω
VCC = 3.3V
VCC = 3.3V
PECL
OUTPUT
SDI+
SDI-
Figure 8. PECL-to-CML Interface Figure 9. Direct Coupling of a PECL Output into the MAX3831/
MAX3832
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3831/MAX3832 high-speed inputs
and outputs.
Place power-supply decoupling as close to VCC as
possible. To reduce feedthrough, take care to isolate
the input signals from the output signals.
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
12 ______________________________________________________________________________________
Pin Configuration
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
SCLKI+
N.C.
GND
TQFP-EP
TOP VIEW
FIL+
FIL-
GND
VCC
RCLKI+
RCLKI-
VCC
5253 49
5051
PDI1+
PDI1-
PDI2+
PDI2-
GND
N.C.
N.C.
N.C.
N.C.
N.C.
GND
VCC
N.C.
N.C.
GND
GND
GND
PDI3+
PDI3-
PDI4+
PDI4-
GND
PDO1+
PDO1-
PDO2+
PDO2-
VCC
33
34
35
36
37 PDO3+
PDO3-
PDO4+
PDO4-
VCC
SDI-
SDI+
GND
PCLKO+
PCLKO-
VCC
SCLKI-
VCC
SDO+
SDO-
VCC
48 GNDGND
64
VCC
VCC
2322212019 2726252418 2928 32313017
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
MAX3831
MAX3832
TRIEN
RSETFR
RSETES
LOF
TEST
LBEN
PLBEN
___________________Chip Information
TRANSISTOR COUNT: 14,134
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
______________________________________________________________________________________ 13
Package Information
64L, TQFP.EPS
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
14 ______________________________________________________________________________________
Package Information (continued)
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
______________________________________________________________________________________ 15
NOTES
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
NOTES
