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April 1st, 2010
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REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 1 of 40
M51995AP/AFP
Switching Regulator Control REJ03D0835-0300
Rev.3.00
Jun 06, 2008
Description
M51995A is the primary switching regulator controller which is especially designed to get the regulated DC voltage
from AC power supply.
This IC can directly drive the MOS-FET with fast rise and fast fall output pulse.
Type M51995A has the functions of not only high frequency OSC and fast output drive but also current limit with fast
response and high sensibility so the true “fast switching regulator” can be realized.
It has another big feature of current protection to short and over current, owing to the integrated timer-type protection
circuit, if few parts are added to the primary side.
The M51995A is equivalent to the M51977 with externally re-settable OVP (over voltage protection) circuit.
Features
• 500 kHz operation to MOS FET
Output current : ±2 A
Output rise time 60 ns, fall time 40 ns
Modified totempole output method with small through current
• Compact and light-weight power supply
Small start-up current : 90 µA typ.
Big difference between “start-up voltage” and “stop voltage” makes the smoothing capacitor of the power input
section small.
Start-up threshold 16 V, stop voltage 10 V
Packages with high power dissipati on are used t o wi t h-st a nd t he heat generated by the gat e-drive current of MOS
FET.
16-pin DIP, 20-pin SOP 1.5 W (at 25°C)
• Simplified peripheral circuit with pr otection circuit and built-in large-capacity totempole output
High-speed current limiting circuit using pulse-by-pulse method (Two system of CLM+pin, CLM−pin)
Protection by intermittent operation of outp ut over current : Timer protection circuit
Over-voltage protection circuit with an externally re-settable latch (OVP)
Protection circuit for output miss action at low supply voltage (UVLO)
• High-performance and highly functional power supply
Triangular wave oscillator for easy dead time setting
Application
Feed forward regulator, fly-back regulator
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 2 of 40
Recommended Operating Conditions
• Supply voltage range: 12 to 36 V
• Operating frequency: less than 500 kHz
• Oscillator frequency setting resistance
T-ON pin resistance RON: 10 k to 75 kΩ
T-OFF pin resistance ROFF: 2 k to 30 kΩ
Block Diagram
Under
voltage
lockout
Voltage
regulator
7.1 V
5.8 V
15.2 k 3 k 500
F/B DET GND
V
CC
Latch
ON/OFF
OVP (shut down)
Oscillator capacitance
CF
Oscillator resistance
T-ON (ON duty)
Oscillator resistance
T-OFF (OFF duty)
VF
CLM+
+Current limit
CLM−
−Current limit
CT
Intermittent operation
determine capacitance
Collecto
r
V
OUT
Emitter
6 S1 S
1 S1 S
PWM
Comparator
PWM
latch
+
−
OP AMP
2.5 V
Intermittent
action
Intermittent
action and
OSC control
−Current
limit latch
+Current
limit latch
Oscillator
(triangle)
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 3 of 40
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
9
10
12
11
Collector
M51995AP
(Top view)
Outline: PRDP0016AA-A (16P4)
M51995AFP
(Top view)
Outline: PRSP0020DA-A (20P2N-A)
VOUT
Emitter
VF
ON/OFF
OVP
DET
F/B
Collector
VOUT
Emitter
VF
ON/OFF
Heat sink pin
OVP
DET
F/B
VCC
CLM+
CLM−
GND
CT
T-OFF
CF
T-ON
VCC
CLM+
CLM−
GND
CT
T-OFF
CF
T-ON
Heat sink pin
Note: Connect the heat sink pin to GND.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 4 of 40
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage VCC 36 V
Collector voltage VC 36 V
±2 Peak Output current IO
±0.15 A Continuous
VF terminal voltage VVF V
CC V
ON/OFF terminal voltage VON/OFF V
CC V
CLM−terminal voltage VCLM− −4.0 to +4.0 V
CLM+terminal voltage VCLM+ −0.3 to +4.0 V
OVP terminal current IOVP 8 mA
DET terminal voltage VDET 6 V
DET terminal input current IDET 5 mA
F/B terminal voltage VFB 0 to 10 V
T-ON terminal input current ITON −1 mA
T-OFF terminal input current ITOFF −2 mA
Power dissipation Pd 1.5 W Ta = 25°C
Thermal derating factor Kθ 12 mW/°C Ta > 25°C
Operating temperature Topr −30 to +85 °C
Storage temperature Tstg −40 to +125 °C
Junction temperature Tj 150 °C
Notes: 1. “+” sign shows the direction of current flow into the IC and “−” sign shows the current flow from the IC.
2. This terminal has the constant voltage characteristic of 6 to 8 V, when current is supplied from outside. The
maximum allowable voltage is 6 V when the constant voltage is applied to this terminal. And maximum
allowable current into this terminal is 5 mA.
3. The low impedance voltage supply should not be applied to the OVP terminal.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 5 of 40
Electrical Characteristics
(VCC = 18 V, Ta = 25°C, unless otherwise noted)
Limits
Block Item Symbol
Min. Typ. Max.
Unit Test Conditions
Operating supply voltage
range VCC V
CC(STOP) — 35 V
Operation start-up voltage VCC(START) 15.2 16.2 17.2 V
Operation stop voltage VCC(STOP) 9.0 9.9 10.9 V
Difference voltage between
operation start and stop ∆VCC 5.0 6.3 7.6 V
∆VCC = VCC(START) −
VCC(STOP)
50 90 140 µA VCC = 14.5V,
Ta = 25°C
Stand-by current ICCL
40 90 190 µA VCC = 14.5V,
−30 ≤ Ta ≤ 85°C
Operating circuit current ICCO 10 15 21 mA VCC = 30V
0.95 1.31 5.0 mA VCC = 25V Circuit current in OFF state ICC OFF 50 90 140 µA VCC = 14V
0.95 1.35 2.0 mA VCC = 25V
Circuit current in timer OFF
state ICC CT — 160 240 µA VCC = 14V
1.3 2.0 3.0 mA VCC = 25V
Supply
voltage
circuit
current
Circuit current in OVP state ICC OVP 125 200 310 µA VCC = 9.5V
ON/OFF terminal high
threshold voltage VTHH ON/OFF 2.1 2.6 3.1 V
ON/OFF terminal low
threshold voltage VTHL ON/OFF 1.9 2.4 2.9 V
ON/OFF
ON/OFF terminal
hysteresis voltage ∆VTHON/OFF 0.1 0.2 3.0 V
Current at 0% duty IFBMIND −2.1 −1.54 −1.0 mA
F/B terminal input
current
Current at maximum duty IFBMAXD −0.90 −0.55 −0.40 mA F/B terminal input
current
Current difference between
max and 0% duty ∆IFB −1.35 −0.99 −0.70 mA ∆IFB =
IFBMIND − IFBMAXD
Terminal voltage VFB 4.9 5.9 7.1 V
F/B terminal input
current = 0.95mA
F/B
Terminal resistance RFB 420 600 780 Ω
Detection voltage VDET 2.4 2.5 2.6 V
Input current of detection
amp IINDET — 1.0 3.0 µA VDET = 2.5V
Detection
Voltage gain of detection
amp GAVDET 30 40 — dB
OVP terminal H threshold
voltage VTHOVPH 540 750 960 mV
OVP terminal hysteresis
voltage ∆VTHOVP — 30 — mV
∆VTHOVP =
VTHOVPH − VTHOVPL
OVP terminal threshold
current ITHOVP 80 150 250 µA
OVP terminal input current IINOVP 80 150 250 µA VOVP = 400mV
OVP reset supply voltage VCCOVPC 7.5 9.0 10.0 V
Difference supply voltage
between operation stop
and OVP reset
VCC(STOP) –
VCCOVPC 0.55 1.20 — V
OVP terminal is
open.
(high impedance)
−480 –320 –213 VCC = 30V
OVP
Current from OVP terminal
for OVP reset ITHOVPC
−210 −140 −93
µA VCC = 18V
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 6 of 40
(VCC = 18 V, Ta = 25°C, unless otherwise noted)
Limits
Block Item Symbol
Min. Typ. Max.
Unit Test Conditions
Timer frequency fTIMER 0.27 0.40 0.60 Hz CT = 4.7µF
−193 −138 −102 VCT = 3.3V,
Ta = −5°C
−178 −127 −94 Ta = 25°C
Timer charge current ITIMECH
−147 −105 −78
µA
Ta = 85°C
Timer
OFF time/ON time ratio TIMEOFF/ON 7.0 8.7 11.0 —
CLM−terminal threshold
voltage VTHCLM− −220 −200 −180 mV −5 ≤ Ta ≤ 85°C
CLM−terminal current IINCLM− −170 −125 −90 µA VCLM– = −0.1V
CLM−
Delay time from CLM− to
VOUT TPDCLM− — 120 — ns
CLM+ terminal threshold
voltage VTHCLM+ 180 200 220 mV −5 ≤ Ta ≤ 85°C
CLM+ terminal current IINCLM+ −270 −205 −140 µA VCLM+ = 0V
CLM+
Delay time from CLM+ to
VOUT TPDCLM+ — 90 — ns
Oscillating frequency fosc 170 188 207 kHz
Maximum ON duty TDUTY 47.0 50.0 53.0 %
RON = 20kΩ,
ROFF = 17kΩ
CF = 220pF,
−5 ≤ Ta ≤ 85°C
Upper limit voltage of
oscillation waveform VOSCH 3.97 4.37 4.77 V fOSC = 188kHz
Lower limit voltage of
oscillation waveform VOSCL 1.76 1.96 2.16 V fOSC = 188kHz
Oscillator
Voltage difference between
upper limit and lower limit
of OSC waveform
∆VOSC 2.11 2.41 2.71 V fOSC = 188kHz
VF =
5V 170 188 207
OSC frequency in
CLM operating
state VF =
2V
fOSCVF
108 124 143
kHz RON = 20kΩ,
ROFF = 17kΩ
CF = 220pF
Duty in CLM
operating state VF =
0.2V TVFDUTY 11.0 13.7 22.0 —
Min off duty/Max on
duty
VF voltage at timer
operating start VTHTIME 2.7 3.0 3.3 V
VF
VF terminal input current IVF — 2 6 µA Source current
VOL1 — 0.05 0.4 V VCC = 18V, IO = 10mA
VOL2 — 0.7 1.4 V
VCC = 18V,
IO = 100mA
VOL3 — 0.69 1.0 V VCC = 5V, IO = 1mA
Output low voltage
VOL4 — 1.3 2.0 V VCC = 5V, IO = 100mA
VOH1 16.0 16.5 — V
VCC = 18V,
IO = −10mA
Output high voltage
VOH2 15.5 16.0 — V
VCC = 18V,
IO = −100mA
Output voltage rise time TRISE — 50 — ns No load
Output
Output voltage fall time TFALL — 35 — ns No load
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 7 of 40
Main Characteristics
Power Dissipation Pd (mW)Circuit Current ICC (mA)Circuit Current ICC (mA)
Thermal Derating
(Maximum Rating)
Ambient Temperature Ta (°C)
Circuit Current vs. Supply Voltage
(Normal Operation)
Supply Voltage VCC (V)
Supply Voltage VCC (V) Supply Voltage VCC (V)
Supply Voltage VCC (V)
Circuit Current vs. Supply Voltage
(OFF State)
Circuit Current vs. Supply Voltage
(OVP Operation)
Circuit Current vs. Supply Voltage
(Timer OFF State)
OVP Terminal Threshold Voltage vs.
Ambient Temperature
Ambient Temperature Ta (°C)
Circuit Current ICC (mA)Circuit Current ICC (mA)
OVP Terminal Threshold Voltage
VTHOVP (V)
1800
1500
1200
900
600
300
0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
3.2
2.4
1.2
2.8
2.0
1.6
0.4
0.8
0
22 m
18 m
16 m
14 m
12 m
10 m
100 µ
50 µ
0
3.2
2.4
0.8
2.8
1.6
2.0
1.2
0.4
0
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
0
25 50 75 100 125 150
85 010203040
01020304010 20 30 40
010203040 −40 −20 0 20 40 60 80 100
OVP reset point
8.87 V (−30 °C)
8.94 V (25 °C)
9.23 V (85 °C)
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
RON = 18 kΩ
ROFF = 20 kΩfOSC = 500 kHz
fOSC = 100 kHz
H threshold voltage
(VTHOVPH)
L threshold voltage
(VTHOVPL)
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 8 of 40
Threshold Voltage of ON/OFF Terminal vs.
Ambient Temperature
Threshold Current of ON/OFF Terminal vs.
Ambient Temperature
Threshold Voltage of ON/OFF Terminal
V
THON/OFF
(V)
Threshold Current of ON/OFF Terminal
I
THON/OFF
(µA)
Input Current of VF Terminal vs.
Input Voltage
Discharge Current of Timer vs.
Ambient Temperature
Input Current of VF Terminal I
VF
(µA)
Discharge Current of Timer I
TIMEOFF
(µA)
VF Terminal Voltage V
VF
(V)
Charge Current of Timer vs.
Ambient Temperature
ON and OFF Duration of Timer vs.
Ambient Temperature
(Intermittent Operation)
Charge Current of Timer I
TIMEON
(µA)
ON Duration of Timer T
ON
(ms)
Ambient Temperature Ta (°C) Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)Ambient Temperature Ta (°C)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
25.0
20.0
15.0
5.0
0
0
175
150
125
100
75
18
17
16
15
14
13
12
11
10
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
−200
−180
−160
−140
−120
−100
−80
−60
−40
−60 −40 −200 20406080100 −60 −40 −20 0 20 40 60 80 100
−60 −40 −200 20406080100
−60 −40 −20 0 20 40 60 80 100−60 −40 −200 20406080100
1.4
1.3
1.2
1.1
1.0
012345678910
OFF Duration of Timer T
OFF
(s)
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
ON→OFF
OFF→ON
ON→OFF
OFF→ON
Timer ON…Circuit operation ON
Timer OFF…Circuit operation OFF
Timer ON
Timer OFF
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 9 of 40
VF Threshold Voltage for Timer vs.
Ambient Temperature
VF Threshold Voltage for Timer (V)
Threshold Voltage of CLM+ Terminal vs.
Ambient Temperature
Threshold Voltage of CLM+ Terminal
V
THCLM+
(mV)
CLM+ Terminal Current vs.
CLM+ Terminal Voltage
CLM+ Terminal Current I
INCLM+
(µA)
CLM+ Terminal Voltage V
CLM+
(V)
Threshold Voltage of CLM− Terminal vs.
Ambient Temperature
CLM− Terminal Current vs.
CLM− Terminal Voltage
Threshold Voltage of CLM− Terminal
V
THCLM−
(mV)CLM− Terminal Current I
INCLM−
(µA)
CLM− Terminal Voltage V
CLM−
(V)
Output High Voltage vs.
Output Source Current
Output High Voltage V
CC
-V
OH
(V)
Output Source Current I
OH
(A)
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)
4.0
3.0
3.5
2.5
2.0
−60 −40 0−20 20 40 60 80 100
−60 −40 0−20 20 40 60 80 100
−60 −40 0−20 20 40 60 80 100
210
200
205
195
190
−210
−205
−200
−195
−190
400
300
200
100
0
0 0.1 0.3 0.5 0.70.2 0.4 0.6 0.8 0.9 1.0
−500
−400
−300
−200
−100
0
0−0.2 −0.4 −0.6 −0.8 −1.0
2.6
2.4
2.2
2.0
1.8
1.6
1.2
1.4
1.0
0.8
0.6
1 m 10 m 100 m 1 10
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
V
CC
= 18 V
Ta = 25°C
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 10 of 40
Output Low Voltage vs.
Output Sink Current
Detection Voltage vs.
Ambient Temperature
Output Sink Current IOL (A)
Input Current of Detection AMP vs.
Ambient Temperature
Detection AMP Voltage Gain vs.
Frequency
Detection Voltage VDET (V)
Output Low Voltage VOL (V)
Frequency f (Hz)
ON Duty vs.
F/B Terminal Input Current
ON Duty vs.
F/B Terminal Input Current
ON Duty (%)
ON Duty (%)
F/B Terminal Input Current IF/B (mA) F/B Terminal Input Current IF/B (mA)
Input Current of Detection AMP IINDET (µA)
Detection AMP Voltage Gain GDET (dB)
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C)
5.0
4.0
3.0
2.0
0
1.0
1 m 10 m 100 m 1 10
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
−60 −40 −20 0 20 40 60 80 100
2.56
2.52
2.46
2.50
2.44
2.42
2.54
2.48
2.40
−60 −40 −20 0 20 40 60 80 100
50.0
40.0
30.0
20.0
10.0
0
100 1 k 10 k 100 k 1 M 10 M
50
40
30
20
0
10
0 0.5 1.0 1.5 2.0 2.5
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Ta = 25°C
V
CC
= 18 V
V
CC
= 5 V
(f
OSC
= 100 kHz)
R
ON
= 18 kΩ
R
OFF
= 20 kΩ
(f
OSC
= 200 kHz)
R
ON
= 18 kΩ
R
OFF
= 20 kΩ
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 11 of 40
ON Duty vs.
F/B Terminal Input Current
Upper & Lower Limit Voltage of OSC vs.
Ambient Temperature
ON Duty vs. R
OFF
F/B Terminal Input Current I
F/B
(mA)
Oscillating Frequency vs.
CF Terminal Capacity
CF Terminal Capacity (pF)
Oscillating Frequency vs.
Ambient Temperature
ON Duty (%)
ON Duty (%)
Oscillating Frequency f
OSC
(kHz)Oscillating Frequency f
OSC
(kHz)
Oscillating Frequency f
OSC
(kHz)
Upper & Lower Limit Voltage of OSC
V
OSCH
, V
OSCL
(V)
R
OFF
(kΩ)
Oscillating Frequency vs.
Ambient Temperature
Ambient Temperature Ta (°C)
Ambient Temperature Ta (°C) Ambient Temperature Ta (°C)
120
110
100
90
80
−60 −40 −20 0 20 40 60 80 100
700
600
500
400
300
200
−60 −40 −20 0 20 40 60 80 100
5.4
5.2
4.8
4.4
4.0
2.2
2.0
1.8
1.6
−60 −40 −20 0 20 40 60 80 100
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5
10000
1000
100
10
1
1310 3100 31000 310000
100
90
80
70
60
50
40
20
30
0
10
1357
10 357
100
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
(f
OSC
= 500 kHz)
R
ON
= 18 kΩ
R
OFF
= 20 kΩ
f
OSC
= 500 kHz
f
OSC
= 200 kHz
f
OSC
= 100 kHz
R
ON
= 18 kΩ
R
OFF
= 20 kΩ
f
OSC
= 100 kHz
f
OSC
= 200 kHz
f
OSC
= 500 kHz
R
ON
= 22 kΩ
R
OFF
= 12 kΩ
R
ON
= 36 kΩ
R
OFF
= 6.2 kΩ
R
ON
= 24 kΩ
R
OFF
= 20 kΩ
51 kΩ
36 kΩ
24 kΩ
22 kΩ
18 kΩ
15 kΩ
10 kΩ
RON = 75 kΩ
R
ON
= 24 kΩ
R
OFF
= 20 kΩ
C
F
= 47 pF
R
ON
= 24 kΩ
R
OFF
= 20 kΩ
C
F
= 330 pF
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 12 of 40
ON Duty vs.
Ambient Temperature
ON Duty vs.
Ambient Temperature
Input Voltage of Terminal vs.
Expansion Rate of Period
Ambient Temperature Ta (°C)
ON Duty vs.
Ambient Temperature
Ambient Temperature Ta (°C)
Input Voltage of Terminal vs.
Expansion Rate of Period
Input Voltage of Terminal V
VF
(V)
ON Duty (%)
ON Duty (%)Input Voltage of Terminal V
VF
(V)
OVP Terminal Input Current I
OVP
(A) ON Duty (%)
Expansion Rate of Period (Times)
OVP Terminal Input Current vs.
Input Voltage
Ambient Temperature Ta (°C)
Expansion Rate of Period (Times) OVP Terminal Input Voltage V
OVP
(V)
5.0
4.0
3.0
2.0
0
1.0
0 2 4 6 8 101214161820
0 2 4 6 8 101214161820−60 −40 −20 0 20 40 60 80 100
−60 −40 −20 0 20 40 60 80 100
1 m
100 µ
10 µ
1 µ
0.2 0.4 0.6 0.8 1.0
100
90
80
70
60
50
30
10
40
20
0
100
90
80
70
60
50
30
10
40
20
0
−60 −40 −20 0 20 40 60 80 100
5.0
4.0
3.0
2.0
1.0
0
100
90
80
70
60
50
40
20
30
0
10
R
ON
= 36 kΩ, R
OFF
= 6.2 kΩ
R
ON
= 22 kΩ, R
OFF
= 12 kΩ
R
ON
= 24 kΩ, R
OFF
= 20 kΩ
R
ON
= 22 kΩ, R
OFF
= 22 kΩ
R
ON
= 18 kΩ, R
OFF
= 24 kΩ
R
ON
= 15 kΩ, R
OFF
= 27 kΩ
R
ON
= 36 kΩ, R
OFF
= 6.2 kΩ
R
ON
= 22 kΩ, R
OFF
= 12 kΩ
R
ON
= 24 kΩ, R
OFF
= 20 kΩ
R
ON
= 22 kΩ, R
OFF
= 22 kΩ
R
ON
= 18 kΩ, R
OFF
= 24 kΩ
R
ON
= 15 kΩ, R
OFF
= 27 kΩ
R
ON
= 36 kΩ, R
OFF
= 6.2 kΩ
R
ON
= 22 kΩ, R
OFF
= 12 kΩ
R
ON
= 24 kΩ, R
OFF
= 20 kΩ
R
ON
= 22 kΩ, R
OFF
= 22 kΩ
R
ON
= 18 kΩ, R
OFF
= 24 kΩ
R
ON
= 15 kΩ, R
OFF
= 27 kΩ
(f
OSC
= 100 kHz)
(f
OSC
= 500 kHz) (f
OSC
= 100 kHz)
(1)
(2) (4)
(5) (6)
(3)
(1)
(2) (4)
(5) (6)
(3)
(f
OSC
= 200 kHz)
(1) R
ON
= 15 kΩ, R
OFF
= 27 kΩ
(2) R
ON
= 18 kΩ, R
OFF
= 24 kΩ
(3) R
ON
= 22 kΩ, R
OFF
= 22 kΩ
(4) R
ON
= 24 kΩ, R
OFF
= 20 kΩ
(5) R
ON
= 22 kΩ, R
OFF
= 12 kΩ
(6) R
ON
= 36 kΩ, R
OFF
= 6.2 kΩ
(f
OSC
= 500 kHz)
(1) R
ON
= 15 kΩ, R
OFF
= 27 kΩ
(2) R
ON
= 18 kΩ, R
OFF
= 24 kΩ
(3) R
ON
= 22 kΩ, R
OFF
= 22 kΩ
(4) R
ON
= 24 kΩ, R
OFF
= 20 kΩ
(5) R
ON
= 22 kΩ, R
OFF
= 12 kΩ
(6) R
ON
= 36 kΩ, R
OFF
= 6.2 kΩ
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 13 of 40
Current from OVP Terminal for OVP Reset
ITHOVPC (µA)
Supply Voltage VCC (V)
Current from OVP Terminal for OVP
Reset vs. Supply Voltage
800
0
400
600
700
200
100
300
500
0101525 4035520
30
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Horizontal-axis: 20 ns/div
Vertical-axis: 50 mA/div
Horizontal-axis: 20 ns/div
Vertical-axis: 10 mA/div
Output Through Current Waveform
at Rising Edge of Output Pulse
Output Through Current Waveform
at Falling Edge of Output Pulse
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 14 of 40
Application Example
(1) Example application circuit diagram of feed forward regulator
M51995AP
1
2
4
3 14 13 15 9 10 11 12 8 6 7
5
16
++
+
+
+
+
+
A
C
CFIN
A
CFCT
RON ROFF
CVCC
R2
R1
A
OVP
F/B
ON/OFF
VOUT1
VOUT2
Note: Pin No. is related with M51995AP
(2) Example application circuit diagram of fly-back regulator
R
ON
M51995AP
1
2
4
3 14 13 15 9 10 11 12 8 6 7
5
16
+
+
+
Note: Pin No. is related with M51995AP
R1
OVP F/B
R21
R22
C
VCC
R
OFF
C
F
A
C
C
FIN
V
OUT
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 15 of 40
(3) Feed forward types SMPS with multi-output
A
C
CFIN
VOUT
Collector VCC
ON/OFF
VF
Emitter
CLM−
GND
CLM+
T-OFF
CF
T-ON
CT
F/B
OVP
DET
M51995AP
CFCT
+
+
RON ROFF
+
+
CVCC
R2
R1
A
A
+ +
VOUT2
VOUT1
+
OVP
F/B
ON/OFF
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 16 of 40
Function Description
Type M51995AP and M51995AFP are especially designed for off-line primary PWM control IC of switching mode
power supply (SMPS) to get DC voltage from AC power supply.
Using this IC, smart SMPS can be realized with reasonable cost and compact size as the number of external electric
parts can be reduced and also parts can be replaced by reasonable one.
In the following circuit diagram, MOS FET is used for output transistor, however bipolar transistor can be used with no
problem.
Start-up Circuit Section
The start-up current is such low current level as typical 90 µA, as shown in figure 1, when the VCC voltage is increased
from low level to start-up voltage VCC(START).
In this voltage range, only a few parts in this IC, which has the function to make the output voltage low level, is alive
and ICC current is used to keep output low level. The large voltage difference between VCC(START) and VCC(STOP) makes
start-up easy, because it takes rather long duration from VCC(START) to VCC(STOP).
Circuit Current I
CC
(mA)
Supply Voltage V
CC
(V)
ICCO
≈ 14 mA
ICCL
≈ 90 µA
VCC
(STOP)
≈ 9.9 V
VCC
(START)
≈ 16.2 V
Figure 1 Circuit Current vs. Supply Voltage
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 17 of 40
Oscillator Section
The oscillation waveform is the triangle one. The ON-d uration of output pu lse depends on the rising dur ation of the
triangle waveform and dead-time is decided by the falling duration.
The rising duration is determined by the product of external resistor RON and capacitor CF and the falling duration is
mainly determined by the product of resistor ROFF and capacitor CF.
Waveform of
CF terminal
Waveform of V
OUT
terminal in Max
ON dutycondition
V
OSCH
≈ 4.4 V
V
OSCL
≈ 2.0 V
V
OH
V
OL
Figure 2 OSC Waveform at Normal Condition
(no-operation of intermittent action and OSC control circuit)
1. Oscillator operation when intermittent action and OSC co ntrol circuit does not operate
Figure 3 show s the equivalent charging and discharging circuit d iag ram of os cillator when the current limiting
circuit does not operate. It means that intermittent action and OSC con trol circuit does not operate.
The current flows through RON from the constant voltage source of 5.8 V. CF is charged up by the same amplitude
as RON current, when internal switch SW1 is switched to “charging side”. The rise rate of CF terminal is given as
VT-ON
RON × CF
≈ (V/s) ………………………………………… (1)
where VT-ON ≈ 4.5 V
The maximum on duration is approximately given as
≈ (s) ………………… (2)
(V
OSCH
− V
OSCL
) × R
ON
× C
F
V
T-ON
where VOSCH ≈ 4.4 V
VOSCL ≈ 2.0 V
CF is discharged by the summed-up of ROFF current and one sixteenth (1/16) of RON current by the function of Q2,
Q3 and Q4 when SW1, SW2 are switched to “discharge side”.
So fall rate of CF terminal is given as
≈ + (V/s) ………………… (3)
V
T-OFF
R
OFF
× C
F
V
T-ON
16 × R
ON
× C
F
The minimum off duration approximately is given as
≈ (s) …………………… (4)
(V
OSCH
− V
OSCL
) × C
F
V
T-OFF
R
OFF
+
V
T-ON
16 × R
ON
where VT−OFF ≈ 3.5 V
The cycle time of oscillation is given by the summation of equations 2 and 4.
The frequency including the dead-time is not influenced by the temperature because of the built-in temperature
compensating circuit.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 18 of 40
T-ON
From VF
signal
Vz = 4.2 V
T-OFF
CF
R
ON
R
OFF
C
F
M51995A
Q3
Q4
1/16
Q2
SW2
SW1
Charging
Discharging
5.8 V
Switched by
charging and
discharging signal
Q1
Figure 3 Schematic Diagram of Charging and Discharging Control Circuit for OSC Capacitor CF
2. Oscillator operation when intermittent action and OSC control circuit op erates.
When over current signal is applied to CLM+ or CLM− terminal, and the current limiting circuit, intermittent action
and OSC control circuit starts to op erate. In this case T-OFF terminal voltage depends on VF terminal voltage, so
the oscillation frequ ency decreases and dead-time spreads.
The rise rate of oscillation waveform is given as
VT-ON
RON × CF
≈ (V/s) ………………………………………… (5)
The fall rate of oscillation waveform is given as
≈ + (V/s) ………………… (6)
V
VF
− V
VFO
R
OFF
× C
F
V
T-ON
16 × R
ON
× C
F
where VT-ON ≈ 4.5 V
VVF ; VF terminal voltage
VVFO ≈ 0.4 V
VVF − VFO = 0 if VVF − VVFO < 0
VVF − VVFO = VT-OFF if VVF – VVFO > VT−OFF ≈ 3.5 V
So when VVF > 3.5 V, the operation is just same as that in the no current limiting operation state.
The maximum on-duration is just same as that in the no-operation state of intermittent and o s cillation control circuit
and is given as follows;
≈ (s) ………………… (7)
(V
OSCH
− V
OSCL
) × R
OFF
× C
F
V
T-ON
The minimum off-duration is approximately given as;
+
≈ (s) ………………… (8)
(V
OSCH
− V
OSCL
) × C
F
V
VF
− V
VFO
R
OFF
× C
F
V
T-ON
16 × R
ON
× C
F
The oscillation period is giv en by the summation of equation (7) and (8).
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 19 of 40
As shown in figure 5 , the internal circuit kills the first output pulse in the output waveform. The output waveform
will appear from the second pulse cycle because the duration of first cycle takes CF charging time longer comparing
with that at the stable operating state.
Usually the applied voltage to VF terminal must be proportional the output voltage of the regulator.
So when the over current occurs and the output voltage of the regulator becomes low, the off-duration becomes wide.
There are two methods to get the control voltage, which depends on the output voltage, on primary side. For the fly
back type regulator application, the induced voltage on the third or bias winding is dependent on output voltage. On
the other hand, for the feed forward type regulator application, it can be used that the output voltage depends on the
product of induced voltage and “on-duty”, as the current of choke coil will continue at over load condition, it means
the “continuous current” condition.
Figure 6 shows one of the examples for VF terminal application for the feed forward type regulator.
Voltage waveform of
CF terminal
Voltage waveform of
output terminal at
Max ON duty
V
OSCH
≈ 4.4 V
V
OSCL
≈ 2.0 V
V
OH
V
OL
Figure 4 OSC Waveform with Operation of Intermittent and OSC Control Circuit Operation
Start from 0 V
First
pulse
Operation start
0
0
V
OSCH
V
OSCL
V
OH
V
OL
Voltage waveform of
CF terminal
Voltage waveform of
output terminal at
Max ON duty
No generate
pulse
Figure 5 Relation between OSC and Output Waveform Circuit Operation at Start-up
M51995A
V
OUT
VF
R
VFFB
C
VFFB
Figure 6 Feedback Loop with Low Pass Filter from Output to VF Terminal
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 20 of 40
PWM Comparator and PWM Latch Section
Figure 7 shows the PWM comparator and latch section. The on-duration of output waveform coincides with the rising
duration of CF terminal waveform, when the infinitive resistor is connected between F/B terminal and GND.
When the F/B terminal has finite impedance and current flows out from F/B terminal, “A” point potential shown in
figure 7 depends on this current. So the “A” point potential is close to GND level when the flow-out current becomes
large.
“A” point potential is compared with the CF terminal oscillator waveform and PWM comparator, and the latch circuit is
set when the potential of o scillator waveform is higher than “A” point potential.
On the other hand , this latch circuit is reset by high level signal during the dead-time of oscillation (falling duration of
oscillation waveform). So the “B” point potential o r output waveform of latch circuit is the one sho wn in figure 8.
The final output waveform or “C” point potential is got by combining the “B” point signal and dead-time signal
logically. (please refer to figure 8)
+
−
≈ 7.1 V
5.8 V
Point A
PWM
COMP.
CF
M51995A
F/B
6 S 1 S
Latch Point B To
output
Point C
From
OSC
500 Ω
200 µA
3 k
15.2 k
Figure 7 PWM Comparator and Latch Circuit
Waveform of
OSC & point A
Point B
Point C
OSC waveform
Point A
Figure 8 Waveforms of PWM Comparator Input point A, Latch Circuit Points B and C
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 21 of 40
Current Limiting Section
When the current-limit signal is applied before the crossing instant of “A” pint potential and CF terminal voltage shown
in figure 7, th is signal makes the output “off” and th e off state will continue until next cycle. Figure 9 shows the timing
relation among them.
The current limiting circuit has two input terminals, one has the detector-sensitivity of +200 mV to the GND terminal
and the other has −200 mV. The circuit will be latched if the input signal is over the limit of either terminal.
If the current limiting circuit is set, no waveform is generated at outpu t terminal howev er this state is reset during the
succeeding dead-time.
So this current limiting circuit is able to have the function in every cycle, and is named “pulse-by-pulse curren t limit”.
It is rather recommended to use not "CLM+" but "CLM−" terminal, as the influence from the gate drive current of MOS
FET can be eliminated and wide voltage rating of +4 V to −4 V is guaranteed for absolute maximum rating.
There happen some noise voltage on RCLM during the switching of power transistor due to the snubber circuit and stray
capacitor of the transformer windings.
To eliminate the abnormal operation by the noise voltage, the low pass filter, which consists of RNF and CNF is used as
shown in figure 10.
It is recommended to use 10 to 100 Ω for RNF because such range of RNF is not influenced by the flow-out current of
some 200 µA from CLM terminal and CNF is designed to have the enough value to absorb the noise voltage.
V
THCLM
≈ 200 mV
V
THCLM
≈ −200 mV
(a) +current limit
(b) −current limit
OSC waveform of
CF terminal
Waveform of
CLM+ terminal
Current limit signal
to set latch
Waveform of
V
OUT
terminal
OSC waveform of
CF terminal
Waveform of
CLM− terminal
Current limit signal
to set latch
Waveform of
V
OUT
terminal
Figure 9 Operating Waveforms of Current Limiting Circuit
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 22 of 40
+
M51995A
VOUT
CLM+
GND
CNF
RNF
RCLM
+
M51995A
VOUT
CLM−
GND
CNF
RNF
RCLM
(a) In case of CLM+ (b) In case of CLM−
Figure 10 How to Connect Current Limit Circuit
Intermittent Action and Oscillation Control Section
When the internal current limiting circuit states to operate and also the VF level decreases to lower than the certain level
of some 3 V, the dead-time spreads and intermittent action and OSC control circu it (which is one of the timer-type-
protection circuit) starts to operate.
The intermittent action and OSC contro l circuit is the one to generate the control signal for oscillator and intermittent
action circuit.
Figure 11 shows the timing-chart of this circuit. When the outpu t o f intermittent action and oscillation control is at
“high” level, the waveform of oscillator depends on the VF terminal voltage and the intermittent action circuit begins to
operate.
OSC waveform
of CF terminal
Current limit
signal
Output of current
limit latch
Output of
intermittent action and
OSC control circuit
(a) With current limit signal
(b) Without current limit signal
OSC waveform
of CF terminal
Current limit
signal
Output of current
limit latch
Output of
intermittent action and
OSC control circuit
GND
GND
GND
Figure 11 Timing Chart of Intermittent and OSC Control Circuit
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 23 of 40
Intermittent Action Circuit Section
Intermittent action circuit will start to operate when the output signal from the intermittent action and oscillation control
circuit are “high” and also VF terminal voltage is lo wer than VTHTIME of about 3 V.
Figure 12 shows the block diagram of intermittent action circuit. Transistor Q is on state when VF terminal voltag e is
higher than VTHTIME of about 3 V, so the CT terminal voltage is near to GND potential.
When VF terminal voltage is lower than VTHTIME, Q becomes “off” and the CT has the possibility to be charged u p.
Under this condition, if the intermittent action and oscillation control signal beco me “high” the switch SWA will close
only in this “high” durati on and CT is charged up by the current of 120 µA through SWA (SWB is open) and CT terminal
potential will rise. The output pulse can be generated only this duration. When the CT terminal voltage reaches to 8 V,
the control logic circuit makes the SWA “off” and SWB “on”, in order to flow in the ITIMEOFF of 15 µA to CT terminal.
The IC operation will be ceased in the falling duration.
On the other hand, when CT terminal voltage decreases to lower than 2 V, the IC operation will be reset to original state,
as the control logic circuit makes the SWA “on” and SWB “off”.
Therefore the parts in power circuit including secondary rectifier diodes are protected from the overheat by the over
current.
I
TIMEOFF
(≈ 15 µA)
I
TIMEON
(≈ 120 µA)
Control
logic
A
B
SW
A
SW
B
C
T
CT
Q
VF
V
THTIME
(≈ 3 V)
+
+
−
Figure 12 Block Diagram of Intermittent Action Circuit
No operating
duration
8 V
2 V
Figure 13 Waveform of CT Terminal
Figure 14 shows the ICC versus VCC in this timer-off duration.
In this duration the power is not supplied to IC from the third winding of transformer but through from the resistor R1
connected to VCC line.
If the R1 shown in Application Example is selected adequate value, VCC terminal voltage will be kept at not so high or
low but adequate value, as the ICC versus VCC characteristics has such the one shown in figure 14.
To ground the CT terminal is recommended, when the intermittent mode is not used.
In this case the oscillated freq uency will become low but the IC will neither stop the oscillation nor change to the
intermittent action mode, when the current limit function becomes to operate and the VF terminal voltage beco mes low.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 24 of 40
Circuit Current ICC (mA)
Supply Voltage VCC (V)
2.0
1.5
1.0
0.5
0
0 5 10 15 20 25 30
Figure 14 ICC vs. VCC in Timer-off Duration of Intermittent Action Circuit
Voltage Detector Circuit (DET) Section
The DET terminal can be used to control the output voltage which is determined by the winding ratio of fly back
transformer in fly-back system or in case of common ground circuit of primary and secondary in feed forward system.
The circuit diagram is quite similar to that of shunt regulator type 431 as shown in figure 15. As well known from
figure 15 and figu re 16, the output of OP AMP has the current-sink ability, when the DET terminal voltage is higher
than 2.5 V but it becomes high impedance state when lower than 2.5 V DET terminal and F/B terminal have inverting
phase characteristics each other, so it is recommended to connect the resistor and capacitor in series between them for
phase compensation. It is very important, one can not connect by resistor directly as there is the voltage difference
between them and the capacitor has the DC stopper function.
≈ 7.1 V
DET
5.4 k
10.8 k10.8 k
1.2 k
F/B
6 S
3 k 500 Ω
1 S
10 S
Figure 15 Equivalent Circuit Diagram of Voltage Detector
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 25 of 40
≈ 7.1 V
F/B
DET
2.5 V
500 Ω
6 S
3 k
1 S
+
−
OP
AMP
Figure 16 Equivalent Circuit Diagram of Voltage Detector
ON-OFF Circuit Section
Figure 17 shows the circuit diagram of ON-OFF circuit. The current flown into the ON-OFF terminal makes the Q4
“on” and the switching o peration stop. On the other han d, the switching operation will recov er as no current flown into
ON/OFF terminal makes Q4 “off”. As the constant current source connected to Q4 base terminal has such the
hysteresis characteristics of 20 µA at operation and 3 µA at stopping. So the unstable operation is not appeared even if
the ON/OFF terminal voltage signal varies slowly.
Q4
Q3
Q2
Q1
2 k
I
ON/OFF
Operate stop at Q4 ON
I: 3 µA at stopping
I: 20 µA at operating
Figure 17 ON/OFF Circuit
Figure 18 shows how to connect the ON/OFF terminal. The switching operation will stop by switch-off and op erate by
switch-on.
Transistor or photo transistor can be replaced by this switch, of course. No resistor of 30 to 100 kΩ is connected and
ON/OFF terminal is directly connected to GND, when it is not necessary to use the ON/OFF operation.
Figure 19 shows the ICC versus VCC characteristics in OFF state and VCC will be kept at not so high or low but at the
adequate voltage, when R1 shown in Application Example is selected properly.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 26 of 40
V
CC
ON/OFF
30 k to 100 kΩ
M51995A
Figure 18 Connecting of ON/OFF Terminal
Circuit Current ICC (mA)
Supply Voltage VCC (V)
1.6
1.2
0.8
0.4
0
0 5 10 15 20 25 30
Figure 19 ICC vs. VCC in OFF State
OVP Circuit (Over Voltage Protection Circuit) Section
OVP circuit is basically positive feedback circuit constructed by Q2, Q3 as shown in figure 20.
Q2, Q3 turn on and the circuit operation of IC stops, when the input signal is applied to OVP terminal. (threshold
voltage ≈ 750 mV)
The current value of I2 is about 150 µA when the OVP does not operates but it decreases to about 2 µA when OVP
operates.
It is necessary to input the sufficient larger current (800 µA to 8 mA) than I2 for triggering the OVP operation.
The reason to decrease I2 is that it is necessary that ICC at the OVP rest supply voltage is small.
It is necessary that OVP state holds by circuit current from R1 in the application example, so this IC has the
characteristic of small ICC at the OVP reset supply voltage (≈stand-by current +20 µA)
On the other hand, the circuit current is large in the higher supply voltage, so the supply voltage of this IC doesn’t
become so high by the voltage drop across R1.
This characteristic is shown in figure 21.
The OVP terminal i nput current i n t he vol t age l ower t han the OVP threshold volta ge is based on I2 and t he input current
in the voltage hig her than the OVP threshold voltage is the sum of the current flowing to the base of Q3 and the current
flowing from the collector of Q2 to the base.
For holding in the latch state, it is necessary that the OVP terminal voltage is kep t in the voltage higher than VBE of Q3.
So if the capacitor is connected between the OVP terminal and GND, even though Q2 turns on in a moment by the
surge voltage, etc. this latch action does not hold if the OVP terminal voltage does not become higher than VBE of Q3
by charging this capacitor.
For resetting OVP state, it is necessary to make the OVP terminal voltage lower than the OVP L th reshold voltage or
mak e VCC lower than the OVP reset supply voltage.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 27 of 40
As the OVP reset voltage is settled on the rather high voltage of 9.0 V, SMPS can be reset in rather short time from the
switch-off of the AC power source if the smoothing capacitor is not so large value.
V
CC
OVP
GND
8 k
12 k Q1
Q2
2.5 k
400
I
2
7.8 V
100 µA
I
1
Q3
Note: I
1
= 0 when OVP operates
Figure 20 Detail Diagram of OVP Circuit
Circuit Current ICC (mA)
Supply Voltage VCC (V)
8
7
6
5
4
2
0
3
1
0 5 10 15 25 3520 30 40
OVP reset point
8.82 V (−30 °C)
8.97 V (25 °C)
9.07 V (85 °C)
Ta = 25 °C
Ta = 85 °C
Ta = −30 °C
Figure 21 Circuit Current vs. Supply Voltage (OVP Operation)
Output Section
It is required that the output circuit has the high sink and source abilities for MOS FET drive. It is well known that the
totempole circuit has high sink and source ability. However, it has the demerit of high through current.
For example, the through current may reach such the high current level of 1 A, if type M51995A has the “conventional”
totempole circuit. For the high frequency application such as higher than 100 kHz, this through current is very
important factor and will cause n ot only the large ICC current and the inevitable heat-up of IC but also the noise voltage.
This IC uses the improved totempole circuit, so without deteriorating the characteristic of operating speed, its through
current is approximately 100 mA.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 28 of 40
Application Note of Type M51995AP/AFP
Design of Start-up Circuit and the Power Supply of IC
1. The start-up circuit when it is not necessary to set the start and stop input voltage
+
M51995A
V
CC
GND
C
VCC
R1 V
F
Main transformer
Third winding o
r
bias winding
Rectified DC
voltage from
smoothing capacitor
Figure 22 Start-up Circuit Diagram (when it is not necessary to set the start and stop input v oltage)
Figure 22 shows one of the example circuit diagram of the start–up circuit which is used when it is not necessary to
set the start and stop voltage.
It is recommended that the current more than 300 µA flows through R1 in order to overcome the operation start-up
current ICC(START) and CVCC is in the range of 10 to 47 µF. The product of R1 by CVCC causes the time delay of
operation, so the response time will be long if the product is too much large.
Just after the start-up, the ICC current is supplied from CVCC, however, under the steady state condition, IC will be
supplied from the third winding or bias winding of transformer, the winding ratio of the third winding must be
designed so that the induced voltage may be higher than the operation-stop voltage VCC(STOP).
The VCC voltage is recommended to be 12 V to 17 V as the normal and optimum gate voltage is 10 to 15 V and the
output voltage (VOH) of type M51995AP/AFP is about (VCC − 2 V).
It is not necessary that the ind uced voltage is settled higher than the operation start-up voltage VCC(START), and the
high gate drive voltage causes high gate dissipation, on the other hand, too low gate drive voltage does not make the
MOS FET fully on-state or the saturation state.
2. The start-up circuit when it is not necessary to set the start and stop input voltage
It is recommend to use the third winding of “forward winding” or “positive polarity” as shown in figure 23, when
the DC source voltages at both the IC operation start and stop must be settled at the specified v alues.
The input voltage (VIN(START)), at which the IC operation starts, is decided by R1 and R2 utilizing the low start-up
current characteristics of type M51995AP/AFP.
The input voltage (VIN(STOP)), at whi c h the IC operat i on st ops, i s deci ded by t he rat i o of thi rd wi ndi ng of t ransformer.
The VIN(START) and VIN(STOP) are given by following equations.
VIN (START) ≈ R1 × ICCL + ( + 1) × VCC (START) ……… (9)
R1
R2
V
IN (STOP)
≈ (V
CC (STOP)
− V
F
) × + V'
IN RIP (P-P)
…… (10)
N
P
N
B
2
1
Where
ICCL is the operation start-up current of IC
VCC(START) is the operation start-up voltage of IC
VCC(STOP) is the operation stop voltage of IC
VF is the forward voltage of rectifier diode
V’IN(P-P) is the peak to peak ripple voltage of
VCC terminal ≈ V'IN RIP (P-P)
NB
NP
It is required that the VIN(START) must be higher than VIN(STOP).
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 29 of 40
When the th ird winding is the “fly back winding” or “reverse polarity”, the VIN(START) can be fixed, however,
VIN(STOP) can not be settled by this system, so the au xiliary circuit is required.
+
M51995A
Primary winding
of transformer
Third winding of
transformer
Rectified DC
voltage from
smoothing capacitor V
IN
R1
R2 C
VCC
GND
V
CC
V
F
N
P
N
B
Figure 23 Start-up Circuit Diagram (when it is not necessary to set the start and stop input v oltage)
3. Notice to the VCC, VCC line and GND line
+
M51995A
Collector
Output
Emitter GND
CVCC
VCC
Main
transformer
third winding
RCLM
Figure 24 How to Design the Conductor-pattern of Type M51995A on PC Board (schematic example)
To avoid the abnormal IC operation, it is recommended to design the VCC is not vary abruptly and has few spike
voltage, which is induced from the stray capacity between the winding of main transformer.
To reduce the spike voltage, the CVCC, which is connected between VCC and ground, must have the good high
frequency characteristics.
To design the conductor-pattern on PC board, following cautions must be considered as shown in figure 24.
(1) To separate the emitter line of type M51995A from the GND line of the IC
(2) The locate the CVCC as near as possible to type M51995A and connect directly
(3) To separate the collector line of type M51995A from the VCC line of the IC
(4) To connect the ground terminals of peripheral parts of ICS to GND of type M51995A as short as possible
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 30 of 40
4. Power supply circuit for easy start-up
When IC starts to operate, the voltage of the CVCC begins to d ecrease till the CVCC becomes to be charged from the
third winding of main-transformer as the ICC of the IC increases abruptly. In case shown in figure 22 and 23, some
“unstable start-up” or “fall to start-up” may happen, as the charging interval of CVCC is very short duration; that is
the charging does occur only the duration while the induced winding voltage is higher than the CVCC voltage, if the
induced winding voltage is nearly equal to the “operation-stop voltage” of type M51995.
It is recommended to use the 10 to 47 µF for CVCC1, and about 5 times capacity bigger than CVCC1 for CVCC2 in figure
25.
++
V
CC
GND
C
VCC1
C
VCC2
R1
Main
transformer
third winding
M51995A
Figure 25 DC Source Circuit for Stable Start-up
OVP Circuit
(1) To avoid the miss operation of OVP
It is recommended to connect the capacitor between OVP terminal and GND for avoiding the miss operation by the
spike noise.
The OVP terminal is connected with the sink current source (≈150 µA) in IC when OVP does not operate, for
absorbing the leak current of the photo coupler in the application.
So the resistance between the OVP terminal and GND for leak-cut is not necessary.
If the resistance is connected, the supply current at the OVP reset supply voltage becomes large.
As the result, the OVP reset supply voltage may become higher than the operation stop voltage.
In that case, the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation
stop voltage.
So it should be avoided absolutely to connect the resistance between the OVP terminal and GND.
+
V
CC
OVP
GND
Photo couple
r
10 k
M51995A
Figure 26 Peripheral Circuit of OVP Terminal
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 31 of 40
2. Application circuit to make the OVP-reset time fast
The reset time may becomes problem when the discharge time constant of CFIN • (R1 + R2) is long. Under such the
circuit condition, it is recommended to discharge the CVCC forcedly and to make the VCC low value. This makes the
OVP-reset time fast.
+ +
To main
transformer
R1
VCC
GND
CVCC
R2
CFIN
The time constant of
this part should be short
M51995A
Figure 27 Example Circuit Diagram to Make the OVP-Reset-Time Fast
3. OVP setting method using the induced third winding voltage on fly back system
For the over voltage protection (OVP), the induced fly back type third winding voltage can b e utilized, as the
induced third winding voltage depends on the output voltage. Figure 28 shows one of the example circuit diagram.
+
Main
transformer
third winding
V
CC
OVP
GND
C
VCC
470 Ω
M51995A
Figure 28 OVP Setting Method Using the Induced Third Winding Voltage on Fly Back System
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 32 of 40
Current Limiting Circuit
1. Peripheral circuit of CLM+, CLM− terminal
+
+
R1
V
CC
Collector C
VCC
V
OUT
CLM+
EmitterGND
M51995A
R
NF1
R
NF2
C
NF
R
CLM
C
FIN
Input
smoothing
capacitor
Figure 29 Peripheral Circuit Diagram of CLM+ Terminal
+
+
R1
V
CC
Collector C
VCC
V
OUT
CLM−
Emitter
GND
M51995A
R
NF1
R
NF2
C
NF
R
CLM
C
FIN
Input
smoothing
capacitor
Figure 30 Peripheral Circuit Diagram of CLM− Terminal
Figure 29 and 30 show the example circuit diagrams around the CLM+ and CLM− terminal. It is required to
connect the low pass filter, as the main current or d rain current contains the spike curren t esp ecially during the turn-
on duration of MOS FET.
1,000 pF to 22,000 pF is recommended for CNF and the RNF1 and RNF2 have the functions both to adjust the “current-
detecting-sensitivity” and to consist the low p ass filter.
To design the RNF1 and RNF2, it is required to consider the influence of CLM terminal source current (IINCLM+ or
INFCLM−), which value is in the range of 90 to 270 µA.
In order to be not influenced from these resistor paralleled value of RNF1 and RNF2, (RNF1/RNF2) is recommended to
be less than 100 Ω.
The RCLM should be the non-inductive resistor.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 33 of 40
2. Over current limiting curve
(1) In case of feed forward system
(a) Feed forward system (b) Primary and secondary current
I1
I2
IP1
IP2
I1
CLM
RCLM
I2
Figure 31 Primary and Secondary Current Waveforms Under the Current Limiting Operation
Condition on Feed Forward System
Figure 31 shows the primary and secondary current wave-forms under the current limiting operation.
At the typical application of pulse-by-pulse primary current detecting circuit, the secondary current depends on
the primary current. As the peak value of secondary current is limited to specified value, the characteristics
curve of output voltage versus output current become to the one as shown in figure 32.
The demerit of the pulse by pulse current limiting system is that the output pulse width can not reduce to less
than some value because of the delay time of low pass filter connected to the CLM terminal and propagation
delay time TPDCLM from CLM terminal to output terminal of type M51995A. The typical TPDCLM is 100 ns.
As the frequency becomes higher, the delay time must be shorter. And as the secondary output voltage becomes
higher, the dynamic range of on-duty must be wider; it means that it is required to make the on-duration much
more narrower.
So this system has the demerit at the higher oscillating frequency and higher o utput voltage applicatio ns.
Output Current
Output Voltage
Figure 32 Over Current Limiting Curve on Feed Forward System
To improve these points, the oscillating frequency is set low u s ing the characteristics of VF terminal.
When the current limiting circuit operates under the over current condition, the oscillating frequency decreases
in accordance with the decrease of VF terminal voltage, if the VF is lower than 3.5V.And also the dead time
becomes longer.
Under the condition of current limiting operation, the output current I2 continues as shown in figure 31. So the
output voltage depends on the product of the input primary voltage VIN and the on-duty.
If the third winding polarity is positive, the VCC depends on VIN, so it is concluded that the smoothed voltage of
VOUT terminal depends on the output DC voltage of the SMPS.
So the sharp current limiting characteristics will be got, if the VOUT voltage if feed back to VF terminal through
low pass filter as shown in figu re 33.
It is recommended to use 15 kΩ for RVFFB, and 10,000 pF for CVFFB in figure 33.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 34 of 40
M51995A
VOUT
VF
RVFFB
CVFFB
Figure 33 Feed Back Loop through Low Pass Filter from VOUT to VF Terminal
Figure 34 shows how to control the knee point where the frequency becomes decrease,
From
V
OUT
To VF From
V
OUT
To VF From
V
OUT
To VF
To make the knee
point high
To make the knee
point low
Figure 34 How to Control the Knee Point
(2) In case of fly back system
The DC output voltage of SMPS depends on the VCC Voltage of type M51995A when the polarity of the third
winding is negative and the system is fly back. So the operation of type M51995A will stop when the VCC
becomes lower than “Operation-stop voltage” of M51995A when the DC output voltage of SMPS decreases
under specified value at over load condition.
DC Output Voltage
DC Output Current
Point that V
CC
voltage
or third winding
voltage decreases
under "Operation-Stop Voltage"
Figure 35 Over Current Limiting Curve on Fly Back System
M51995A
V
CC
Collector
VF
R1
R2
C
VCC
+
Figure 36 Circuit Diagram to make Knee Point Low on Fly Back System
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 35 of 40
However, the M51995A will non-operate and operate intermittently, as the VCC voltage rises in accordance with
the decrease of ICC current.
The fly back system has the constant output power characteristics as shown in figure 35 when the peak primary
current and the operating frequency are constant.
To control the increase of DC output current, the operating frequency is decreased using the characteristics of
VF terminal when the over current limiting function begins to operate.
The voltage which mode by dividing the VCC is applied to VF terminal as shown in figure 36, as the induced
third winding voltage depends on the DC output voltage of SMPS.
15 kΩ or less is recommended for R2 in figure 36, it is noticed that the current flows through R1 and R2 will
superpose on the ICC(START) current.
If the R1 is connected to CVCC2 in figure 25, the current flows through R1 and R2 is independent of the ICC(START).
(3) Application circuit to keep the non-operating condition when over load current condition will continue for
specified duration
The CT terminal voltage will begin to rise and the capacitor connected to CT terminal will be charged-up, if the
current limiting function starts, and VF terminal voltage decreases below VTHTIME (∼ 3 V).
If the charged-up CT terminal voltage is applied to OVP terminal through the level-shifter consisted of buffer
transistor and resistor, it makes type M51995A keep non-operating condition.
V
CC
C
T
CT
OVP
M51995A
+
Figure 37 Application Circuit Diagram to Keep the Non-Operating Condition when Over Load Current
Condition will Continue for Specified Duration
Output Circuit
1. The output terminal characteristics at the VCC voltage lower than the “Operation-stop” voltage
The output terminal has the current sink ability even though the VCC voltage lower than the “Operation-stop”
voltage or VCC(STOP) (It means that the terminal is “Output low state” and please refer characteristics of output low
voltage versus sink current.)
This characteristics has the merit not to damage the MOS FET at the stop of operation when the VCC voltage
decreases lower than the voltage of VCC (STOP), as the gate charge of MOS FET, which shows the capacitive load
characteristics to the output terminal, is drawn out rapidly.
The output terminal has the draw-out ability above the VCC voltage of 2 V, however, lower than the 2 V, it loses the
ability and the outp ut terminal potential may rise due to the leakage current.
In this case, it is recommended to connect the resistor of 100 kΩ between gate and source of MOS FET as shown in
figure 38.
M51995A
V
OUT
To main
transformer
R
CLM
100 kΩ
Figure 38 Circuit Diagram to Prevent the MOS FET Gate Potential Rising
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 36 of 40
2. MOS FET gate drive power dissipation
Figure 39 shows the relation between the applied gate voltage and the stored gate charge.
In the region 1, the charge is mainly stored at CGS as the depletion is spread and CGD is small owing to the off-state
of MOS FET and the high drain voltage.
In the region 2, the CGD is multiplied by the “mirror effect” as the characteristics of MOS FET transfers from off-
state to on-state.
In the region 3, both the CGD and CGS affect to the characteristics as the MOS FET is on-state and the drain voltage
is low.
Gate-source Voltage V
GS
(V)
Total Stored Gate Charge (nC)
20
15
10
5
0
0481216
20
Drain
I
D
V
D
C
DS
CGS
Source
V
GS
Gate
C
GD
V
DS
= 80 V
200 V
320 V
I
D
= 4 A
(1)
(2)
(3)
Figure 39 The Relation between Applied Gate-Source Voltage and Stored Gate Charge
The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation
between gate drive current ID and total gate charge QGSH is shown by following equation;
ID = QGSH • fOSC ……………………………………………… (11)
Where
fosc is switching frequency
As the gate drive current may reach up to several tenths milliamperes at 500 kHz operation, depending on the size of
MOS FET, the power dissipation caused by the gate current can not be neglected.
In this case, following action will be considered to avoid heat up of type M51995A.
(1) To attach the heat sink to type M51995A
(2) To use the printed circuit board with the good thermal conductivity
(3) To use the buffer circuit shown next section
3. Output buffer circuit
It is recommended to use the output buffer circuit as shown in figure 40, when type M51995A drives the large
capacitive load or bipolar transistor.
V
OUT
M51995A
Figure 40 Output Buffer Circuit Diagram
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 37 of 40
DET Circuit
Figure 41 shows how to use the DET circuit for the voltage detector and error amplifier.
C4
C2 R3
C1
C
F/B
DET
R1
Detecting
voltage
B
A
R2
M51995A
Figure 41 How to use the DET Circuit for the Voltage Detector
For the phase shift compensatio n, it is recommended to connected the CR network between DET terminal and F/B
terminal.
Figure 42 shows the gain-frequency characteristics between point B and point C shown in figure 41.
Log G (dB)
Log ωω
1
ω
2
G1
GAVDET
(DC Voltage gain)
Figure 42 Gain-Frequency Characteristics between Point B and C shown in Figure 41
The G1, ω1 and ω2 are given by following equations;
G1 = ……………………… (12)
R3
R1 / R2
1
C2 • R3
ω
1
= ………………………… (13)
C1 + C2
C1 • C2 • R3
ω
2
= ………………… (14)
At the start of the operation, there happen to be no output pulse due to F/B terminal current through C1 and C2, as the
potential of F/B terminal rises sharply just after the start of the operation.
Not to lack the output pulse, is recommended to connect the capacitor C4 as shown by broken line.
Please take notice that the current flows through the R1 and R2 are superposed to ICC(START). Not to superpose, R1 is
connected to CVCC2 as shown in figure 25.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 38 of 40
How to Get the Narrow Pulse Width During the Start of Operation
Figure 43 shows how to get the narrow pulse width during the start of the operation. If the pulse train of forcedly
narrowed pulse-width continues too long, the misstart of operation may happen, so it is recommended to make the
output pulse width narrow only for a few pulse at the start of operation. 0.1µF is recommended for the C.
M51995A
F/B
To photo
coupler
100 Ω
C
Figure 43 How to Get the Narrow Pulse Width During the Start of Operation
How to Synchronize with External Circuit
Type M51995A has no function to synchronize with external circuit, however, there is some application circuit for
synchronization as shown in figure 44. If this circuit is used, the synchronization may be out of order at the overload
condition when the current limiting function starts to operate and VF terminal voltage beco mes lower than 3 V.
M51995A
T-ON CF T-OFF CT
CT
ROFF
CF
RON
Q1
Q2
+
120 µA
Synchronous
pulse
0 V
0 V
Maximum pulse width of
synchronous pulse
Minimum pulse width of
synchronous pulse
Synchronize
waveform
Oscillating
waveform
Figure 44 How to Synchronize with External Circuit
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 39 of 40
Driver Circuit for Bipolar Transistor
When the bipolar transistor is used instead of MOS FET, the base current of bipolar transistor must be sinked by the
negative base voltage source for the switching-off duration, in order to make the switching speed of bipolar transistor
fast one.
In this case, over current can not be detected by detecting resistor in series to bipolar transistor, so it is recommended to
use the CT (current transformer).
V
CC
−V
SS
(−2 V to −5 V)
V
OUT
M51995A
EmitterGND
V
CC
Collector
Figure 45 Driver Circuit Diagram (1) for Bipolar Transistor
For the low current rating transistor, type M51995A can drive it directly as shown in figure 46.
V
OUT
GND
V
CC
M51995A
Emitter
Collector
Bipolar
transisto
Figure 46 Driver Circuit Diagram (2) for Bipolar Transistor
Attention for Heat Generation
The maximum ambient temperature of type M51995A is +85°C, however, the ambient temperature in vicinity of the IC
is not uniform and varies place by place, as the amount of power dissipation is fearfully large and the power dissipation
is generated locally in the switching regulator.
So it is one of the good idea to check the IC package temperature.
The temperature difference between IC junction and the surface of IC package is 15°C or less, when the IC junction
temperature is measured by temperature dependency of forward voltage of pin junction, and IC package temperature is
measured by “thermo-viewer”, and also the IC is mounted on the “phenol-base” PC board in normal atmosphere.
So it is concluded that the maximum case temperature (surface temperature of IC) rating is 120°C with adequate mar gin .
As type M51995 has the modified totempole driver circuit, the transient through current is very small and the total
power dissipation is decreased to the reasonable power level.
M51995AP/AFP
REJ03D0835-0300 Rev.3.00 Jun 06, 2008
Page 40 of 40
Package Dimensions
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1.421.12
bp
A1
HE
y0.1
e1.27
c
0° 8°
L0.4 0.6 0.8
00.1 0.2
A2.1
7.5 7.8 8.1
A21.8
E5.2 5.3 5.4
D12.5 12.6 12.7
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.35 0.4 0.5
0.18 0.2 0.25
P-SOP20-5.3x12.6-1.27 0.3g
MASS[Typ.]
20P2N-APRSP0020DA-A
RENESAS CodeJEITA Package Code Previous Code
Detail F
L
A
2
A
1
y
Index mark
*1
*2
*3
110
11
20
F
H
E
E
eb
p
A
c
D
INCLUDE TRIM OFFSET.
DIMENSION "*3" DOES NOT
NOTE)
DO NOT INCLUDE MOLD FLASH.
DIMENSIONS "*1" AND "*2"1.
2.
*3
*3
*2
*1
16 9
81
SEATING PLANE
e
1
c
E
A
1
A
2
L A
D
eb
2
b
p
b
3
2.792.29
4.5
A
1
b
3
15°
e2.54
c
L3.0
0.51
1.4 1.5 1.8
A
E6.156.36.45
D 18.8 19.0 19.2
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.22 0.27 0.34
P-DIP16-6.3x19-2.54 1.0g
MASS[Typ.]
16P4PRDP0016AA-A
RENESAS CodeJEITA Package Code Previous Code
b
p
0.4 0.5 0.6
e
1
7.627.32 7.92
b
2
0.9 1.0 1.3
A
2
3.3
0°
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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Renesas Technology Taiwan Co., Ltd.
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Renesas Technology Singapore Pte. Ltd.
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Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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