LTC3315A Dual 5V, 2A Synchronous Step-Down DC/DCs in 2mm x 2mm LQFN FEATURES DESCRIPTION Dual Outputs Each with 2A Output Current nn High Efficiency: 19m NMOS and 75m PMOS nn Wide Bandwidth, Fast Transient Response nn Switching Frequency Synchronizable Up to 3MHz nn V Range: 2.25V to 5.5V IN nn V OUT Range: 0.5V to VIN nn V OUT Accuracy: 1% nn Low Ripple Burst Mode(R) Operation nn Peak Current Mode Control nn Minimum On-Time: 25ns nn Safely Tolerates Inductor Saturation in Overload nn Shutdown Current: 1.2A nn Precision 400mV Enable Thresholds nn Internal Soft-Start and Compensation nn Power Good Output nn Low Profile, Thermally Enhanced 12-Lead 2mm x 2mm x 0.74mm LQFN Package nn AEC-Q100 Qualified for Automotive Applications The LTC(R)3315A features dual 2A monolithic synchronous step-down converters operating from a 2.25V to 5.5V input supply in one package for space-constrained applications with demanding performance requirements. Using constant frequency, peak current mode control at switching frequencies up to 3MHz with a minimum ontime as low as 25ns, both bucks achieve high efficiency and fast transient response in a very small application footprint. nn The LTC3315A operates in forced continuous or pulse skip mode for low noise or in Burst Mode(R) operation for high efficiency at light loads. The common buck switching frequency is 2MHz and can be synchronized to an external oscillator via the MODE/SYNC pin. The LTC3315A can regulate outputs as low as 500mV. Other features include precision enable thresholds, a PGOOD signal, output overvoltage protection, thermal shutdown, output short-circuit protection, and up to 100% duty cycle operation for low dropout. The LTC3315A is available in a compact 2mm x 2mm LQFN package. APPLICATIONS Servers, Telecom Supplies, Optical Networking Distributed DC Power Systems (POL) nn FPGA, ASIC, P Core Supplies nn Industrial/Automotive/Communications nn All registered trademarks and trademarks are the property of their respective owners. nn TYPICAL APPLICATION Efficiency vs Load Current Dual 2MHz 2A Buck Regulators VIN SW1 10F 140k 6.8pF VOUT1 1.2V, 2A FB1 EN1 VIN 100k LTC3315A 1H SW2 10F 261k EN2 22F MODE/SYNC GND fSW = 2MHz 4.7pF VOUT2 1.8V, 2A FB2 PGOOD 100k 3315A TA01a 1.0 90 0.9 80 0.8 70 0.7 60 0.6 50 40 30 20 0.5 Burst Mode OPERATION VIN = 3.3V, VOUT = 1.2V L = 880nH, L DCR = 19m fSW = 2MHz 10 0 1m 0.4 0.3 0.2 EFFICIENCY POWER LOSS 10m 100m LOAD CURRENT (A) POWER LOSS (W) 33F EFFICIENCY (%) VIN 2.25V TO 5.5V 880nH 100 0.1 1 2 0 3315A TA01b Rev. A Document Feedback For more information www.analog.com 1 LTC3315A ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) 2 FB2 3 EN2 4 SW1 FB1 12 11 13 GND 5 6 SW2 1 PGOOD EN1 MODE/SYNC TOP VIEW VIN................................................................ -0.3V to 6V EN1, EN2............... -0.3V to Lesser of (VIN + 0.3V) or 6V FB1, FB2................ -0.3V to Lesser of (VIN + 0.3V) or 6V MODE/SYNC......... -0.3V to Lesser of (VIN + 0.3V) or 6V PGOOD.......................................................... -0.3V to 6V IPGOOD.......................................................................5mA Operating Junction Temperature (Notes 2, 3): LTC3315AE......................................... -40C to 125C LTC3315AI.......................................... -40C to 125C LTC3315AJ......................................... -40C to 150C LTC3315AH......................................... -40C to 150C LTC3315AMP...................................... -55C to 150C Storage Temperature Range................... -65C to 150C Maximum Reflow (Package Body) Temperature.... 260C 10 VIN 9 GND 8 GND 7 VIN LQFN PACKAGE 12-LEAD (2mm x 2mm x 0.74mm) TJMAX = 150C, JA = 51C/W, JCBOTTOM = 8.6C/W, JCTOP = 80C/W, JB = 12C/W, JT = 0.8C/W, AND VALUES DETERMINED PER JESD51-7 ON A JEDEC 2S2P PC EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION PART MARKING* TAPE AND REEL (MINI) LTC3315AEV#TRMPBF TAPE AND REEL LTC3315AEV#TRPBF LTC3315AIV#TRMPBF LTC3315AIV#TRPBF LTC3315AJV#TRMPBF LTC3315AJV#TRPBF LTC3315AHV#TRMPBF LTC3315AHV#TRPBF LTC3315AMPV#TRMPBF LTC3315AMPV#TRPBF DEVICE FINISH CODE LHFY e4 PACKAGE TYPE MSL RATING LQFN (Laminate Package with QFN Footprint) TEMPERATURE RANGE (SEE NOTE 2) -40C to 125C -40C to 125C -40C to 150C MSL 3 -40C to 150C -55C to 150C AUTOMOTIVE PRODUCTS** LTC3315AEV#WTRMPBF LTC3315AIV#WTRMPBF LTC3315AEV#WTRPBF LTC3315AIV#WTRPBF LTC3315AJV#WTRMPBF LTC3315AJV#WTRPBF LTC3315AHV#WTRMPBF LTC3315AHV#WTRPBF LHFY e4 LQFN (Laminate Package with QFN Footprint) -40C to 125C -40C to 125C MSL 3 -40C to 150C -40C to 150C * Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. * Recommended LGA and BGA PCB Assembly and Manufacturing Procedures * Device temperature grade is indicated by a label on the shipping container. * LGA and BGA Package and Tray Drawings *TRM = 500 pieces. * Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for thesemodels. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Notes 2, 3). VIN = 3.3V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply Operating Supply Voltage (VIN) l 2.25 5.5 V Rev. A 2 For more information www.analog.com LTC3315A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C (Notes 2, 3). VIN = 3.3V unless otherwise specified. PARAMETER CONDITIONS VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis VIN Rising l MIN TYP MAX UNITS 2.05 2.15 150 2.25 V mV VIN Quiescent Current in Shutdown 1.2 2 A VIN Quiescent Current with One Buck Enabled Burst Mode, Buck in Regulation, Sleeping All Modes, Not Sleeping (Note 4) 45 1.5 70 2.3 A mA VIN Quiescent Current with Both Bucks Enabled Burst Mode, Bucks in Regulation, Sleeping All Modes, Not Sleeping (Note 4) 70 2.8 110 4.2 A mA Enable Threshold Enable Threshold Hysteresis VEN Rising 400 50 425 mV mV EN Pin Leakage VEN = 5.5V 20 nA 500 505 mV 0.015 0.05 %/V 20 nA l 375 Voltage Regulation, Buck 1 and Buck 2 Regulated Feedback Voltage (VFB) l Feedback Voltage Line Regulation 2.25V VIN 5.5V Feedback Pin Input Current VFB = 500mV 495 PMOS Current Limit (ILIM) Current out of SW, VOUT/VIN 0.2 2.9 3.2 3.5 A NMOS Current Limit (IVALLEY) Current out of SW 2.4 2.7 3.0 A NMOS Reverse Current Limit Current into SW, Forced Continuous 0.5 1 1.5 A PMOS ON-Resistance 75 m NMOS ON-Resistance 19 m SW Leakage Current Shutdown, VIN = 5.5V Minimum On Time VIN = 5.5V Maximum Duty Cycle Overtemperature Shutdown (OT) Overtemperature Shutdown Hysteresis 25 l l 200 nA 45 ns 100 Temperature Rising (Note 5) % 165 5 C C Power Good/Soft-Start PGOOD Rising Threshold PGOOD Hysteresis As a Percentage of the Regulated VOUT l l 97 0.6 98 1.1 99 1.6 % % Overvoltage Rising Threshold Overvoltage Hysteresis As a Percentage of the Regulated VOUT l l 107 1 110 2.2 114 3.5 % % 20 nA PGOOD Delay 120 PGOOD Leakage Current VPGOOD = 5.5V PGOOD Pull-Down Resistance VPGOOD = 0.1V Soft-Start Time (Note 6) s 10 20 l 0.25 1 3 ms Internal Oscillator Frequency (fSW) l 1.85 2 2.15 MHz Synchronization Frequency Range l 1 3 MHz Minimum SYNC High or Low Pulse Width l 40 SYNC Level High on MODE/SYNC SYNC Level Low on MODE/SYNC l l 1.2 Oscillator and MODE/SYNC MODE/SYNC No Clock Detect Time MODE/SYNC Pin Threshold ns V V 0.4 10 For Programming Pulse Skipping Mode For Programming Burst Mode Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. l l VIN - 0.1 s 0.1 V V Note 2: The LTC3315A is tested under pulsed load conditions such that TJ TA. The LTC3315AE is guaranteed to meet specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, Rev. A For more information www.analog.com 3 LTC3315A ELECTRICAL CHARACTERISTICS characterization, and correlation with statistical process controls. The LTC3315AI is guaranteed over the -40C to 125C operating junction temperature range, the LTC3315AJ and the LTC3315AH are guaranteed over the -40C to 150C operating junction temperature range, and the LTC3315AMP is guaranteed over the -55C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ in C) is calculated from ambient temperature (TA in C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD * JA) where JA (in C/W) is the package thermal impedance. See High Temperature Considerations section for more details. Note 3: The LTC3315A includes overtemperature protection which protects the device during momentary overload conditions. Junction temperatures will exceed 150C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Static current, switches not switching. Actual current will be higher due to gate charge losses at the switching frequency. Note 5: Overtemperature shutdown is not tested in production. Note 6: The soft-start time is the time from the start of switching until the FB pin reaches 475mV. TYPICAL PERFORMANCE CHARACTERISTICS 510 VFB vs Temperature 150 PMOS RDS(ON) vs Temperature 125 502 500 498 496 494 VIN = 2.25V VIN = 3.3V VIN = 5.5V 40 35 100 75 50 30 25 20 15 10 25 492 5 490 -50 -25 0 0 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 0 2.20 NMOS, VIN = 5.5V, SW = 5.5V NMOS, VIN = 3.3V, SW = 3.3V PMOS, VIN = 5.5V, SW = 0V PMOS, VIN = 3.3V, SW = 0V 2.16 2.12 2.0 1.6 1.2 0.8 0.4 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3315ab G04 2.20 VIN = 5.5V VIN = 3.3V VIN = 2.25V 2.12 2.08 2.04 2.00 1.96 1.92 2.08 2.04 2.00 1.96 1.92 1.88 1.88 1.84 1.84 1.80 -50 -25 0 Oscillator Frequency vs VIN 2.16 FREQUENCY (MHz) 2.4 25 50 75 100 125 150 TEMPERATURE (C) 3315ab G03 Oscillator Frequency vs Temperature FREQUENCY (MHz) 2.8 0 3315ab G02 NMOS, PMOS Leakage vs Temperature 3.2 0 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 3315 G01 LEAKAGE (A) NMOS RDS(ON) vs Temperature 45 RDS(ON) (m) RDS(ON) (m) VFB (mV) 504 50 VIN = 2.25V VIN = 3.3V VIN = 5.5V 508 506 TA = 25C, VIN = 3.3V, unless otherwise noted. 25 50 75 100 125 150 TEMPERATURE (C) 3315aba G05 1.80 2 2.5 3 3.5 4 VIN (V) 4.5 5 5.5 3315ab G06 Rev. A 4 For more information www.analog.com LTC3315A TYPICAL PERFORMANCE CHARACTERISTICS VIN Quiescent Current vs Temperature, All Modes, Not Sleeping VIN Shutdown Quiescent Current vs Temperature 10.0 BOTH BUCKS ENABLED 2.4 4.0 2.0 1.8 ONE BUCK ENABLED 1.6 3.0 1.2 1.0 1.0 0 0.8 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) VIN = 5.5V VIN = 3.3V VIN = 2.25V 0 70 150C 25C -50C 20 10 50 2.2 40 30 3 3.5 4 VIN (V) 4.5 5 1.9 0 -50 -25 5.5 410 3.3 CURRENT OUT OF SW PIN (A) 380 370 360 350 340 330 0 25 50 75 100 125 150 TEMPERATURE (C) 3315ab G13 0 25 50 75 100 125 150 TEMPERATURE (C) 3315 G12 Efficiency vs ILOAD Syncing, Forced Continuous Current Limit vs Temperature 3.4 390 1.8 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 3315ab G11 EN RISING EN FALLING 400 320 -50 -25 0 3315ab G10 EN Threshold vs Temperature 420 2.1 2.0 20 100 PMOS NMOS 90 3.1 3.0 2.9 2.8 70 60 50 40 30 2.7 20 2.6 10 2.5 -50 -25 VIN = 3.3V VOUT = 1.2V 80 3.2 EFFICIENCY (%) 2.5 UVLO RISING UVLO FALLING 2.3 10 2 25 50 75 100 125 150 TEMPERATURE (C) UVLO Threshold vs Temperature 2.4 VIN (V) 30 0 3315ab G09 VIN = 2.25V VIN = 3.3V VIN = 5.5V 60 MINIMUM ON TIME (ns) MINIMUM ON TIME (ns) 30.0 -50 -25 Minimum On Time vs Temperature 40 ONE BUCK ENABLED 3315ab G08 Minimum On Time vs VIN 50 BOTH BUCKS ENABLED 60.0 40.0 25 50 75 100 125 150 TEMPERATURE (C) 3315ab G7 60 70.0 50.0 1.4 2.0 0 -50 -25 VEN (mV) IVIN (A) IVIN (mA) 5.0 0 80.0 2.2 6.0 VIN = 5.5V VIN = 3.3V VIN = 2.25V 90.0 2.6 7.0 IVIN (A) 100.0 2.8 8.0 70 VIN Quiescent Current vs Temperature, Burst Mode, Sleeping 3.0 VIN = 5.5V VIN = 3.3V 9.0 TA = 25C, VIN = 3.3V, unless otherwise noted. 0 25 50 75 100 125 150 TEMPERATURE (C) 3315ab G14 0 1m 10m 100m LOAD CURRENT (A) 1MHz, L = 1.5H, DCR = 33m 2MHz, L = 880nH, DCR = 19m 3MHz, L = 560nH, DCR = 16m 1 2 3315ab G15 Rev. A For more information www.analog.com 5 LTC3315A TYPICAL PERFORMANCE CHARACTERISTICS VOUT Load Regulation 1.212 VOUT Line Regulation 1.208 1.206 106 OV RISING OV FALLING PGOOD RISING PGOOD FALLING 102 100 98 96 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 1.204 1.202 1.200 1.198 1.198 1.196 1.194 1.194 1.192 1.192 1.190 1.190 10m 100m LOAD CURRENT (A) 1 2 1.188 100 Efficiency vs ILOAD, VOUT = 0.8V, VIN = 3.3V 100 90 90 80 80 80 70 70 70 fSW = 2MHz L = 680nH L DCR = 17m 40 30 20 10 0 1m 10m 100m LOAD CURRENT (A) 1 60 50 fSW = 2MHz L = 680nH L DCR = 17m 40 30 20 BURST MODE PULSE SKIP FORCED CONTINUOUS 10 0 1m 2 10m 100m LOAD CURRENT (A) 1 50 30 0 1m 100 Efficiency vs ILOAD, VOUT = 1.2V, VIN = 3.3V 100 80 70 70 70 30 20 10 0 1m fSW = 2MHz L = 880nH L DCR = 19m 10m 100m LOAD CURRENT (A) 1 50 40 30 20 BURST MODE PULSE SKIP FORCED CONTINUOUS 10 2 3315ab G22 EFFICIENCY (%) 90 80 EFFICIENCY (%) 90 60 0 1m fSW = 2MHz L = 880nH L DCR = 19m 10m 100m LOAD CURRENT (A) 1 3315ab G18 BURST MODE PULSE SKIP FORCED CONTINUOUS 10m 100m LOAD CURRENT (A) 3315ab G23 1 2 60 50 40 30 10 2 5.5 Efficiency vs ILOAD, VOUT = 1.2V, VIN = 5.5V 20 BURST MODE PULSE SKIP FORCED CONTINUOUS 5 3315ab G21 80 40 4.5 fSW = 2MHz L = 680nH L DCR = 17m 40 90 50 3.5 4 VIN (V) 3315ab G20 Efficiency vs ILOAD, VOUT = 1.2V, VIN = 2.25V 60 3 60 10 2 2.5 Efficiency vs ILOAD, VOUT = 0.8V, VIN = 5.5V 20 BURST MODE PULSE SKIP FORCED CONTINUOUS 3315ab G19 100 EFFICIENCY (%) 90 50 2 3315ab G17 EFFICIENCY (%) EFFICIENCY (%) 1.200 1.196 Efficiency vs ILOAD, VOUT = 0.8V, VIN = 2.25V 60 EFFICIENCY (%) 1.206 1.202 3315ab G16 100 1.208 1.204 1.188 1m ILOAD = 0A ILOAD = 2A VOUT = 1.2V 1.210 VOUT (V) 108 1.212 VIN = 5.5V VIN = 5.0V VIN = 3.3V VIN = 2.25V VOUT = 1.2V 1.210 110 VOUT (V) PERCENTAGE OF THE REGULATED VOUT (%) PGOOD, OV vs Temperature 112 104 TA = 25C, VIN = 3.3V, unless otherwise noted. 0 1m fSW = 2MHz L = 880nH L DCR = 19m BURST MODE PULSE SKIP FORCED CONTINUOUS 10m 100m LOAD CURRENT (A) 1 2 3315ab G24 Rev. A 6 For more information www.analog.com LTC3315A TYPICAL PERFORMANCE CHARACTERISTICS 100 Efficiency vs ILOAD, VOUT = 1.8V, VIN = 3.3V 100 90 80 80 80 70 70 70 60 50 fSW = 2MHz L = 1H L DCR = 20m 40 30 20 10 10m 100m LOAD CURRENT (A) 1 50 fSW = 2MHz L = 1H L DCR = 20m 40 30 10 0 1m 2 10m 100m LOAD CURRENT (A) 1 100 100 90 80 80 70 70 EFFICIENCY (%) 90 60 fSW = 2MHz L = 1.2H L DCR = 23m 40 30 20 10 0 1m 60 50 fSW = 2MHz L = 1H L DCR = 20m 40 30 BURST MODE PULSE SKIP FORCED CONTINUOUS 10 2 0 1m 10m 100m LOAD CURRENT (A) 3315ab G26 Efficiency vs ILOAD, VOUT = 2.5V, VIN = 3.3V 50 Efficiency vs ILOAD, VOUT = 1.8V, VIN = 5.5V 20 BURST MODE PULSE SKIP FORCED CONTINUOUS 3315ab G25 EFFICIENCY (%) 10m 100m LOAD CURRENT (A) 1 3315ab G27 50 fSW = 2MHz L = 1.2H L DCR = 23m 40 30 0 1m BURST MODE PULSE SKIP FORCED CONTINUOUS 10m 100m LOAD CURRENT (A) 3315ab G28 100 100 90 90 80 80 70 70 50 40 30 20 10 0 1m fSW = 2MHz L = 1.2H L DCR = 23m 10m 100m LOAD CURRENT (A) 1 60 50 40 30 10 2 2 Efficiency vs ILOAD, VOUT = 3.3V, VIN = 5.5V 20 BURST MODE PULSE SKIP FORCED CONTINUOUS 1 3315ab G29 Efficiency vs ILOAD, VOUT = 3.3V, VIN = 4.2V 60 2 60 10 2 1 Efficiency vs ILOAD, VOUT = 2.5V, VIN = 5.5V 20 BURST MODE PULSE SKIP FORCED CONTINUOUS EFFICIENCY (%) 0 1m 60 20 BURST MODE PULSE SKIP FORCED CONTINUOUS EFFICIENCY (%) 90 EFFICIENCY (%) 90 EFFICIENCY (%) EFFICIENCY (%) 100 Efficiency vs ILOAD, VOUT = 1.8V, VIN = 2.25V TA = 25C, VIN = 3.3V, unless otherwise noted. 0 1m 3315ab G30 fSW = 2MHz L = 1.2H L DCR = 23m BURST MODE PULSE SKIP FORCED CONTINUOUS 10m 100m LOAD CURRENT (A) 1 2 3315ab G31 Rev. A For more information www.analog.com 7 LTC3315A TYPICAL PERFORMANCE CHARACTERISTICS Transient Response, Pulse Skip Mode TA = 25C, VIN = 3.3V, unless otherwise noted. Transient Response, Burst Mode Operation Transient Response, FC Mode ILOAD 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV IL 1A/DIV IL 1A/DIV IL 1A/DIV VOUT 50mV/DIV LOAD STEP: 0.1A TO 1.5A, 5A/s 10s/DIV VOUT 50mV/DIV LOAD STEP: 0.1A TO 1.5A, 5A/s 3315ab G32 10s/DIV VOUT 50mV/DIV 10s/DIV 3315ab G34 REFER TO BUCK 1 IN TYPICAL APPLICATION: DUAL 1.2V AND 0.8V 2MHz, 2A BUCK REGULATORS, VIN = 3.3V REFER TO BUCK 1 IN TYPICAL APPLICATION: DUAL 1.2V AND 0.8V 2MHz, 2A BUCK REGULATORS, VIN = 3.3V REFER TO BUCK 1 IN TYPICAL APPLICATION: DUAL 1.2V AND 0.8V 2MHz, 2A BUCK REGULATORS, VIN = 3.3V Startup Transient, Pulse Skip Mode Startup Transient, FC Mode Startup Transient, Burst Mode EN 2V/DIV EN 2V/DIV EN 2V/DIV VOUT 500mV/DIV VOUT 500mV/DIV VOUT 500mV/DIV IL 500mA/DIV PGOOD 5V/DIV LOAD STEP: 0.1A TO 1.5A, 5A/s 3315ab G33 IL 500mA/DIV IL 500mA/DIV RLOAD = 120 200s/DIV 3315ab G35 REFER TO BUCK 1 IN TYPICAL APPLICATION: DUAL 1.2V AND 0.8V 2MHz, 2A BUCK REGULATORS, VIN = 3.3V PGOOD 5V/DIV RLOAD = 120 200s/DIV 3315ab G36 REFER TO BUCK 1 IN TYPICAL APPLICATION: DUAL 1.2V AND 0.8V 2MHz, 2A BUCK REGULATORS, VIN = 3.3V PGOOD 5V/DIV RLOAD = 120 200s/DIV 3315ab G37 REFER TO BUCK 1 IN TYPICAL APPLICATION: DUAL 1.2V AND 0.8V 2MHz, 2A BUCK REGULATORS, VIN = 3.3V Rev. A 8 For more information www.analog.com LTC3315A PIN FUNCTIONS EN1 (Pin 1): Enable Input for Buck Regulator 1. Active high. The EN1 pin has a precision threshold and an optional external resistor divider from VIN or another supply programs when Buck Regulator 1 is enabled. If the precision threshold is not required, drive EN1 to VIN to enable. Do not float. FB1 (Pin 2): Feedback Input for Buck Regulator 1. Program the output voltage and close the control loop by connecting this pin to the middle node of a resistor divider between the output and ground. The LTC3315A regulates FB1 to 500mV (typical). A phase lead capacitor connected between VOUT1 and FB1 may be used to optimize transient response. FB2 (Pin 3): Feedback Input for Buck Regulator 2. Program the output voltage and close the control loop by connecting this pin to the middle node of a resistor divider between the output and ground. The LTC3315A regulates FB2 to 500mV (typical). A phase lead capacitor connected between VOUT2 and FB2 may be used to optimize transient response. EN2 (Pin 4): Enable Input for Buck Regulator 2. Active high. The EN2 pin has a precision threshold and an optional external resistor divider from VIN or another supply programs when Buck Regulator 2 is enabled. If the precision threshold is not required, drive EN2 to VIN to enable. Do not float. PGOOD (Pin 5): Power Good Output. Open drain output. When the regulated output voltage of either enabled switching regulator falls below its PGOOD threshold or rises above its overvoltage threshold, this pin is driven low. When both buck regulators are disabled PGOOD is driven low. SW2 (Pin 6): Switch Node for Buck Regulator 2. Connect an inductor to this pin with a short, wide trace. VIN (Pin 7, Pin 10): Input Supply Pins. The VIN pins supply current to internal circuitry and to each buck's PMOS power switch. Connect both VIN pins together with a short, wide trace and bypass to GND with low ESR capacitors located as close as possible to the pins. GND (Pin 8, Pin 9, Exposed Pad Pin 13): Ground. Connect the exposed pad to a continuous ground plane on the printed circuit board directly under the LTC3315A for electrical contact and rated thermal performance. Additionally, Pin 8 and Pin 9 should be shorted to the exposed pad with a wide trace. SW1 (Pin 11): Switch Node for Buck Regulator 1. Connect an inductor to this pin with a short, wide trace. MODE/SYNC (Pin 12): Mode Selection and External Clock Synchronization Input. Ground this pin to enable pulseskipping mode. For higher efficiency at light loads, tie this pin to VIN to enable Burst Mode. For fast transient response and constant frequency operation over a wide load range, float this pin to enable forced continuous mode. Drive MODE/SYNC with an external clock to synchronize both buck converters to the applied frequency. When syncing, the operating mode is forced continuous. The slope compensation is automatically adapted to the external clock frequency. In the absence of an external clock both buck converters will switch at the default switching frequency. Rev. A For more information www.analog.com 9 LTC3315A BLOCK DIAGRAM VIN BUCK1 1 EN1 0.4V 12 + - ENBUCK1 BUCK CONTROL OT MODE/SYNC 0 OSCILLATOR VC1 PULSE SKIP MODE DETECTION FC 0.55V 0.4V + - 0.55V 0.5V FB1 VIN BUCK2 0.5V 11 2 7 0.49V 180 0.4V 4 + - GM SW1 BURST INTERNAL REFERENCE EN2 SWITCH LOGIC AND ANTISHOOT THROUGH 10 OVER TEMPERATURE DETECT ENBUCK2 OT BUCK CONTROL VC2 + - SWITCH LOGIC AND ANTISHOOT THROUGH + - GM SW2 0.5V FB2 6 3 FB1 0.49V 0.55V + - + - PGOOD 5 ENBUCK1 ENBUCK2 FB2 0.49V + - GND: PINS 8, 9, 13 (EXPOSED PAD) 3315ab BD Rev. A 10 For more information www.analog.com LTC3315A OPERATION Buck Switching Regulators The LTC3315A is a 5V dual 2A monolithic, constant frequency, peak current mode step-down DC/DC converter. The synchronous buck switching regulators are internally compensated and require only external feedback resistors to set the output voltage. An internal oscillator, which can be externally synchronized, turns on the internal PMOS power switch at the beginning of each clock cycle. Current in the inductor ramps up until the PMOS current comparator trips and turns off the PMOS. The peak inductor current, IPEAK, at which the PMOS turns off is controlled by an internal VC voltage which the error amplifier regulates by comparing the voltage on the feedback (FB) pin with an internal 500mV reference. An increase in the load current causes a reduction in the feedback voltage relative to the reference, causing the error amplifier to raise the VC voltage (and IPEAK) until the average inductor current matches the new load current. When the PMOS turns off, the NMOS turns on and ramps down the inductor current for the remainder of the clock cycle or, if in pulse skipping mode or Burst Mode, until the inductor current falls to zero. If an overload condition results in excessive current flowing through the NMOS, the next clock cycle will be skipped until the current returns to a safe level. Each buck switching regulator has its own SW, FB, and EN pins. The buck input supplies are internally connected, but each VIN pin should have its own input bypass capacitor (see Applications Information). The enable pins have precision 400mV thresholds which may be used to provide event-based power-up sequencing by connecting the enable pin to the output of another buck through a resistor divider. If the EN pin of a buck is low, that buck is in shutdown and in a low quiescent current state. If both EN pins are low, both bucks are in shutdown, the SW pins are high impedance, and the quiescent current of the LTC3315A is 1A (typical). If either EN pin is above the enable threshold of 400mV its respective buck is enabled. Both buck regulators have forward and reverse inductor current limiting, soft-start to limit inrush current during start-up, and short-circuit protection. When both bucks are disabled and either buck is subsequently enabled, there is a 400s (typical) delay while internal circuitry powers up followed by a 100s (typical) no start time before switching commences and the soft-start ramp begins. If a second buck is then enabled, it will also have a 100s (typical) no start time. If the second buck is enabled within 400s of the first buck, it will wait until the expiry of the 400s to begin its no start time. The buck switching regulators are switched 180 out of phase with respect to each other. The phase determines the fixed edge of the switching sequence, which is when the PMOS turns on. The PMOS off (NMOS on) phase is subject to the regulated duty cycle of each buck. Mode Selection The buck switching regulators operate in three different modes set by the MODE/SYNC pin: pulse skipping mode (when the MODE/SYNC pin is set low), forced continuous PWM mode (when the MODE/SYNC pin is floating), and Burst Mode (when the MODE/SYNC pin is set high). The MODE/SYNC pin sets the operating mode for both buck switching regulators. In pulse skipping mode, the oscillator operates continuously and positive SW transitions are aligned to the clock. Negative inductor current is disallowed and during light loads switch pulses are skipped to regulate the output. In forced continuous mode, the oscillator runs continuously, no pulses are skipped, and switching occurs in every cycle. To maintain regulation, the inductor current is allowed to reverse under light load conditions. This mode allows the buck to run at a fixed frequency with minimal output ripple. In forced continuous mode if the inductor current reaches -1A (typical, 1A into the SW pin) the NMOS will turn off for the remainder of the cycle to limit the current. In Burst Mode operation, at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. The regulator then goes into a sleep state, during which time the output capacitor provides the load current. In sleep most of the regulator's circuitry is powered down, helping to conserve input power. When the output voltage drops below its programmed value, the circuitry is powered back on and another burst cycle begins. Rev. A For more information www.analog.com 11 LTC3315A OPERATION The sleep time decreases as load current increases. In Burst Mode operation, the regulator will burst at light loads whereas at higher loads it will operate in constant frequency PWM mode. Synchronizing the Oscillator to an External Clock Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values and improves transient response. Operation at lower frequencies improves efficiency by reducing switching losses but requires larger inductance and/or capacitance values to maintain low output voltage ripple. The LTC3315A operates at a default frequency of 2MHz. The LTC3315A's internal oscillator is synchronized through an internal PLL circuit to an external frequency by applying a square wave clock signal to the MODE/SYNC pin. During synchronization, the Buck 1 PMOS turn-on is locked to the rising edge of the external frequency source. Buck2 will be 180 out of phase with respect to Buck1. While syncing, the buck switching regulators operate in forced continuous mode. The synchronization frequency range is 1MHz to 3MHz. After detecting an external clock on the SYNC pin, the internal PLL starts up at the default frequency. The internal PLL then gradually adjusts its operating frequency to match the frequency and phase of the SYNC signal. When the external clock is removed the LTC3315A will detect the absence of the external clock within approximately 10s. During this time it will continue to provide clock cycles. Once the external clock removal has been detected, the oscillator will gradually adjust its operating frequency back to the default. Power Failure Reporting Via PGOOD Pin Power failure faults are reported via the PGOOD pin. Both buck switching regulators have an internal power good (PGOOD) signal and if a buck is enabled its internal PGOOD signal must be high for the PGOOD pin to be high. When the regulated output voltage of an enabled buck rises above 98% of its programmed value, the PGOOD signal transitions high. If the regulated output voltage subsequently falls below 97% of its programmed value, the PGOOD signal is pulled low. If either enabled buck's internal PGOOD signal stays low for greater than 120s, then the PGOOD pin is pulled low, indicating to a microprocessor that a power fault has occurred. The 120s filter time prevents the pin from being pulled low during a transient event. In addition, whenever PGOOD transitions high there will be a 120s assertion delay. The LTC3315A also reports overvoltage conditions at the PGOOD pin. If either enabled buck regulator's output voltage rises above 110% of its programmed value, the PGOOD pin is pulled low after 120s. Similarly, if all enabled outputs that are overvoltage subsequently fall below 107.8% of their programmed value, the PGOOD pin transitions high again after 120s. An error condition that pulls the PGOOD pin low is not latched. When the error condition goes away, the PGOOD pin is released and is pulled high if no other error condition exists. PGOOD is also pulled low in the following scenarios: if neither buck switching regulator is enabled, if VIN is below the UVLO threshold, or if the LTC3315A is over temperature (see below). Output Overvoltage Protection During an output overvoltage event, when the FB pin voltage is greater than 110% of its regulated value, the LTC3315A PMOS will be turned off immediately. An output overvoltage event should not happen under normal operating conditions. Overtemperature Protection To prevent thermal damage, the LTC3315A incorporates an overtemperature (OT) function. When the LTC3315A die temperature reaches 165C (typical, not tested) all enabled buck switching regulators are shut down and remain in shutdown until the die temperature falls to 160C (typical, not tested). Rev. A 12 For more information www.analog.com LTC3315A OPERATION Output Voltage Soft-Start Low Supply Operation Soft starting the output prevents current surge on the input supply and/or output voltage overshoot. During soft-start, the output voltage will proportionally track an internal voltage ramp. An active pull-down circuit discharges that internal voltage in the case of fault conditions. The ramp will restart when the fault is cleared. Fault conditions that initiate the soft-start ramp are the VIN voltage falling too low or thermal shutdown. The LTC3315A is designed to operate down to an input supply voltage of 2.25V. An important thermal design consideration is that the RDS(ON) of the power switches increases at low input. Consider the worst case LTC3315A power dissipation and die junction temperature at the lowest input voltage. Recovery from an output short-circuit (see below) may involve another soft-start cycle if the FB voltage falls more than 120mV (typical) below regulation. During such a recovery, the FB voltage will quickly charge up to 120mV (typical) and then follow the soft-start ramp until regulation is reached. The peak inductor current level at which the current comparator shuts off the PMOS is controlled by the error amplifier. When the output current increases, the error amplifier raises the internal VC voltage until the average inductor current matches the load current. The LTC3315A clamps the maximum internal VC voltage, thereby limiting the peak inductor current. Dropout Operation As the input supply voltage approaches the output voltage, the duty cycle increases toward 100%. Further reduction of the supply voltage forces the PMOS to remain on for more than one cycle, eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the DC voltage drop across the internal PMOS and the inductor. Output Short-Circuit Protection and Recovery When the output is shorted to ground, the inductor current decays very slowly during the downslope because the voltage across the inductor is low. To keep the inductor current in control a secondary limit is imposed on the valley of the inductor current. If the inductor current measured through the NMOS remains greater than IVALLEY at the end of the cycle, the PMOS will be held off. Subsequent switching cycles will be skipped until the inductor current falls below IVALLEY. APPLICATIONS INFORMATION Buck Switching Regulator Output Voltage and Feedback Network VOUT BUCK SWITCHING FB REGULATOR The output voltage of the buck switching regulators is programmed by a resistor divider connected from the switching regulator's output to ground and is given by: R2 VOUT = VFB 1+ R1 R2 R1 CFF + COUT (OPTIONAL) 3315ab F01 (1) as shown in Figure1 where VFB = 500mV. Typical values for R1 range from 40k to 1M. 1% resistors are recommended to maintain output voltage accuracy. The buck regulator transient response may improve with an optional phase lead capacitor CFF that helps cancel Figure1. Feedback Components the pole created by the feedback resistors and the input capacitance of the FB pin. Experimentation with capacitor values between 2pF and 22pF may improve transient response. The values used in the typical application circuits are a good starting point. Rev. A For more information www.analog.com 13 LTC3315A APPLICATIONS INFORMATION Operating Frequency Selection and Trade-Offs Selection of the operating frequency is a trade-off between efficiency, component size, transient response, and input voltage range. The LTC3315A can operate at frequencies between 1MHz and 3MHz. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. Higher switching frequencies allow for higher control loop bandwidth and, therefore, faster transient response. The disadvantages of higher switching frequencies are lower efficiency, because of increased switching losses, and a smaller input voltage range, because of minimum switch on-time limitations. The minimum on-time of the buck regulator imposes a minimum operating duty cycle. The highest switching frequency (fSW(MAX)) for a given application can be calculated as follows: fSW(MAX) = VOUT (2) t ON(MIN) * VIN(MAX) where VIN(MAX) is the maximum input voltage, VOUT is the output voltage and tON(MIN) is the minimum top switch on-time. This equation shows that a slower switching frequency might be necessary to accommodate a high VIN/VOUT ratio. The LTC3315A is capable of a maximum duty cycle of 100%, therefore, the VIN-to-VOUT dropout is limited by the RDS(ON) of the PMOS, the inductor DCR, and the load current. Inductor Selection and Maximum Output Current Considerations in choosing an inductor are inductance, RMS current rating, saturation current rating, DCR, and core loss. Select the inductor value based on the following equations: L L V VOUT * 1- OUT for 0.5 (3) 0.6A * fSW VIN(MAX) VIN(MAX) VOUT VIN(MAX) 2.4A * fSW for VOUT VIN(MAX) > 0.5 (4) where fSW is the switching frequency and VIN(MAX) is the maximum applied input voltage. To avoid overheating of the inductor, choose an inductor with an RMS current rating that is greater than the maximum expected output load of the application. Overload and short-circuit conditions need to be taken into consideration. In addition ensure that the saturation current rating (typically labeled ISAT) is either higher than 3.5A, the maximum current limit of the LTC3315A, or higher than the maximum expected load plus half the inductor ripple: 1 ISAT > ILOAD(MAX) + IL 2 (5) where ILOAD(MAX) is the maximum output load current for the application and IL is the inductor ripple current calculated as: IL = V * 1- OUT L * fSW VIN VOUT (6) To keep the efficiency high, choose an inductor with the lowest series resistance (DCR) and a core material intended for high frequency applications. Table1 shows recommended inductors from several manufacturers. Input Capacitors Bypass the input of the LTC3315A with at least two ceramic capacitors, one near each VIN pin for best performance. Connect the ground of each capacitor to a wide PCB trace on the top layer of the PCB that connects pins 8 and 9 with the exposed pad. These capacitors should be 0603 or 0805 in size. Smaller 0201 capacitors can also be placed as close as possible to the LTC3315A directly on the traces leading from VIN (Pin 7) and GND (Pin 8) and on the traces leading from VIN (Pin 10) and GND (Pin 9) to reduce input noise with minimal (if at all) increase in application footprint. See the layout section for more detail. X7R or X5R capacitors are recommended for best performance across temperature and input voltage variations (see Table2). Note that larger input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or if there Rev. A 14 For more information www.analog.com LTC3315A APPLICATIONS INFORMATION Table1. Recommended Inductors MANUFACTURER FAMILY L (nH) MAX IDC (A) MAX DCR (m) SIZE IN mm (L x W x H) Murata DFE18SAN_G0 240 - 470 3.6 - 4.9 30 - 54 1.6 x 0.8 x 1.0 Murata DFE252010F 330 - 680 3.5 - 4.8 21 - 37 2.5 x 2.0 x 1.0 Vishay IHLP-1212BZ-11 220 - 1500 4.0 - 7.5 11.4 - 32 3.0 x 3.0 x 2.0 Vishay IHHP-0806AB-01 220 - 470 3.6 - 5.0 16 - 35 2.0 x 1.6 x 1.2 Wurth Elektronik WE-MAPI 330 - 1500 3.7 - 5.5 17 - 39 3.0 x 3.0 x 2.0 Wurth Elektronik WE-PMCI 250 - 470 3.6 - 4 12.5 - 31 3.2 x 2.5 x 1.2 Coilcraft XEL3515 72 - 560 3.2 - 23.7 6.5 - 16 3.5 x 3.2 x 1.5 is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with an electrolytic capacitor. A ceramic input capacitor combined with trace or cable inductance forms a high quality (underdamped) tank circuit. If the LTC3315A circuit is plugged in to a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the voltage rating. This situation is easily avoided (see Linear Technology Application Note 88). Table2. Ceramic Capacitor Manufacturers MANUFACTURER URL AVX www.avxcorp.com Murata www.murata.com TDK www.tdk.com Taiyo Yuden www.t-yuden.com Samsung www.samsungsem.com Wurth Elektronik www.we-online.com Output Capacitor, Output Ripple, and Loop Response The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LTC3315A at the SW pin to produce the DC output. In this role it determines the output ripple; thus, low impedance at the switching frequency is important. The second function is to store energy in order to satisfy transient loads and to stabilize the LTC3315A's control loop. The LTC3315A is internally compensated and designed to operate at a high bandwidth for fast transient response capability. The selection of COUT affects the bandwidth of the system, but the transient response is also affected by VOUT, VIN, fSW and other factors. A good place to start is with an output capacitance value of approximately: C OUT = 80F * MHz 500mV fSW VOUT (7) where COUT is the recommended output capacitor value and fSW is the switching frequency. A lower value of output capacitor saves space and cost, but transient performance will suffer and loop stability must be verified. Ceramic capacitors have very low equivalent series resistance (ESR) and provide the best output ripple and transient performance. Use X5R or X7R ceramic capacitors. (see Table2). Even better output ripple and transient performance can be achieved by using low-ESL reverse geometry or three terminal ceramic capacitors. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop increases the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. Although affected by VOUT, VIN, fSW, tON(MIN), the equivalent series inductance (ESL) of the output capacitor, and other factors, the output droop, VDROOP, is usually about 3 times the linear drop of the first cycle: VDROOP = 3 * IOUT C OUT * fSW (8) where IOUT is the load step. Rev. A For more information www.analog.com 15 LTC3315A APPLICATIONS INFORMATION Transient performance and control loop stability can be improved with a higher COUT and/or the addition of a feedforward capacitor, CFF, placed between VOUT and FB. Capacitor CFF provides phase lead compensation by creating a high frequency zero which improves the phase margin and the high-frequency response. The values used in the typical application circuits are a good starting point. LTpowerCAD(R) is a useful tool to help optimize CFF and COUT for the desired transient performance. Applying a load transient and monitoring the response of the system or using a network analyzer to measure the actual loop response are two ways to experimentally verify transient performance and control loop stability, and to optimize CFF and COUT. When using the load transient response method to stabilize the control loop, apply an output current pulse going from 20% to 100% of full load current having a very fast rise time. This will produce a transient on the output voltage. Monitor VOUT for overshoot or ringing that might indicate a stability problem (see Application Note 149). Using the Precision Enable Threshold The LTC3315A has precision threshold enable pins for each buck regulator to enable or disable each buck. When both are forced low, the device enters into a low current shutdown mode. The rising threshold of both EN comparators is 400mV, with 50mV of hysteresis. The EN pins can be tied to VIN if the shutdown feature is not used. Adding a resistor divider from VIN to an EN pin to ground programs the LTC3315A to regulate that output only when VIN is above a desired voltage. Typically, this threshold, VIN(EN), is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws near constant power from its input source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. The VIN(EN) threshold prevents the regulator from operating at source voltages where problems may occur. Referring to Figure2, this threshold can VIN BUCK SWITCHING EN REGULATOR R4 R3 3315ab F02 Figure2. EN Divider be adjusted by setting the values of R3 and R4 such that they satisfy the following equation: R4 VIN(EN) = 400mV * 1+ R3 (9) The buck regulator will remain off until VIN is above VIN(EN). The buck regulator will remain enabled until VIN falls to 0.875 * VIN(EN) and EN is 350mV. Alternatively a resistor divider from the output of one buck to the EN pin of the second buck to ground provides event based power-up sequencing as the first buck reaching regulation enables the second buck. Replace VIN(EN) in Equation 9 with the desired output voltage of the first buck (e.g. 90% of the regulated value) at which the second buck is enabled. PCB Considerations The LTC3315A is a high performance IC designed for high efficiency and fast transient response. For optimal results carefully consider the layout of the PCB board and follow the below list to ensure proper operation. See Figure3 for a recommended PCB layout. 1.Connect the exposed pad of the package (Pin 13) directly to a large, unbroken ground plane under the application circuit on the layer closest to the surface layer to minimize thermal and electrical impedance. Additionally, short the exposed pad to ground pins 8 and 9 on the top layer. See the Analog Devices Application Note, Application Notes for Thermally Enhanced Leaded Plastic Packages for the proper size and layout of the thermal vias and solder stencils. 2.Both of the input supply pins should have local decoupling capacitors with their grounded pins connecting on the top layer to the ground plane around pin 8, Rev. A 16 For more information www.analog.com LTC3315A APPLICATIONS INFORMATION VOUT2 VIN COUT2 L2 CFF2 CIN2 R4 7 4 13 7 R1 1 10 R3 R2 R1, R3 KELVIN TO GND ON LAYER 4 TO VIAS ON EXPOSED PAD, PIN 13 CIN1 CFF1 L1 GND COUT1 VOUT1 GROUND PLANE ON LAYER 2 3315ab F03 Figure3. Recommended LTC3315A PCB Layout pin 9, and the exposed pad. These capacitors provide the AC current to the internal power MOSFETs and their drivers. Large, switched currents flow in these capacitors and it is important to minimize inductance from these capacitors by choosing a small case size such as 0603 and placing them close to the VIN pins of theLTC3315A. To further minimize inductance and input noise, smaller 0201 capacitors can be placed as close as possible to the LTC3315A directly on the traces leading from VIN (Pin7) and GND (Pin8) and on the traces leading from VIN (Pin 10) and GND (Pin9) minimal (if at all) increase in application footprint. 3.The switching power traces connecting SW1 and SW2 to their respective inductors should be minimized to reduce radiated EMI and parasitic coupling. Due to the large voltage swing on the switching nodes, high input impedance sensitive nodes, such as the feedback nodes, should be kept far away or shielded from the switching nodes or poor performance couldresult. 4.The GND side of the switching regulator output capacitors connects directly to the thermal ground plane of the IC. Minimize the trace length from the output capacitor to the inductor(s)/pin(s). High Temperature Considerations A thermal representation of the LTC3315A thermally enhanced LQFN package is shown in Figure4 with the silicon die and thermal metrics identified. The current source represents power loss PD on the die; node voltages represent temperatures; electrical impedances represent conductive thermal impedances JCBOTTOM, JCTOP, VIA, CB, and convective thermal impedances CA and BA. The junction temperature, TJ, is calculated from the ambient temperature, TA, as: TJ = TA + PD * JA(11) where, neglecting the JCTOP + CA path: JA JCB + CB + BA CB + BA ! + VIA (12) 2 2 where JCB = JCBOTTOM = 10C/W. The value of JA=51C/W reported in the Pin Configuration section corresponds to JEDEC standard 2S2P test PCB, which does not have good thermal vias, i.e., VIA is relatively high. Assuming, somewhat arbitrarily but not unreasonably, that VIA ~ (CB + BA)/2, and back calculating it is seen that (CB + BA)/2 = VIA 60C/W for such a board. Rev. A For more information www.analog.com 17 LTC3315A APPLICATIONS INFORMATION The importance of thermal vias becomes clear observing that if the test PCB had low-thermal-resistance vias, the JA would have been reduced by up to 10C/W, which is an improvement of up to 20%. Similarly, having more ground planes that are larger, uninterrupted and highercopper-weight improves CB + BA, which has a dominant effect on JA, given the low value of JCBOTTOM of the package. The maximum load current should be derated as the ambient temperature approaches the maximum junction rating. Power dissipation within the LTC3315A is estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss. TA DIE PD TA CA PACKAGE SUBSTRATE LQFN JCTOP TJ BA BA JCBOTTOM CB CB PCB TA VIA CB CB PCB 3315ab F04 BA TA BA TA Figure4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink Rev. A 18 For more information www.analog.com LTC3315A TYPICAL APPLICATIONS Dual 1.5V and 1.8V 2MHz, 2A Buck Regulators, VIN = 2.5V VIN 2.5V 470nH 10F 1F 0201 VIN 200k EN1 10F 1F 0201 SW1 LTC3315A 3.3pF 100k SW2 261k EN2 22F FB1 470nH VIN VOUT1 1.5V, 2A 3.3pF VOUT2 1.8V, 2A 22F FB2 100k MODE/SYNC GND fSW = 2MHz PGOOD 1M VOUT2 3315A TA02 Rev. A For more information www.analog.com 19 LTC3315A TYPICAL APPLICATIONS Dual 1.2V and 0.8V 2MHz, 2A Buck Regulators, VIN = 3.3V 680nH VIN 3.3V VIN SW1 140k 10F 6.8pF VOUT1 1.2V, 2A 33F FB1 EN1 VIN 100k LTC3315A 560nH SW2 10F 60.4k EN2 10pF VOUT2 0.8V, 2A 33F FB2 100k MODE/SYNC PGOOD 1M GND VOUT1 3315A TA03 fSW = 2MHz Dual 3.3V and 2.5V 2MHz, 2A Buck Regulators, VIN = 5V 1.2H VIN 5V VIN 10F SW1 1F 0201 562k 2.7pF VOUT1 3.3V, 2A 22F FB1 EN1 VIN 10F 100k LTC3315A SW2 1F 0201 1.2H 402k EN2 3.3pF VOUT2 2.5V, 2A 22F FB2 100k MODE/SYNC PGOOD 1M GND fSW = 2MHz VIN 3315A TA04 Rev. A 20 For more information www.analog.com LTC3315A TYPICAL APPLICATIONS Dual 1.2V and 0.8V 1MHz, 2A Buck Regulators, VIN = 3.3V 1.2H VIN 3.3V VIN SW1 140k 22F 6.8pF VOUT1 1.2V, 2A 47F FB1 EN1 VIN 100k LTC3315A 1.0H SW2 22F 60.4k EN2 20pF VOUT2 0.8V, 2A 68F FB2 100k 1MHz MODE/SYNC PGOOD 1M GND VIN 3315A TA05 fSW = 1MHz Dual 1.2V and 0.8V 3MHz, 2A Buck Regulators, VIN = 3.3V 470nH VIN 3.3V VIN SW1 140k 4.7F 4.7pF VOUT1 1.2V, 2A 22F FB1 EN1 VIN 100k LTC3315A 330nH SW2 4.7F 60.4k EN2 6.8pF VOUT2 0.8V, 2A 22F FB2 100k 3MHz MODE/SYNC PGOOD GND fSW = 3MHz 1M VIN 3315A TA06 Rev. A For more information www.analog.com 21 For more information www.analog.com 0.70 0.05 2.50 0.05 0.25 0.05 5 0.70 SUGGESTED PCB LAYOUT TOP VIEW 2.50 0.05 0.70 0.0000 aaa Z 2x D PACKAGE TOP VIEW 0.2500 PIN 1 CORNER 0.2500 X aaa Z // bbb Z 0.7500 0.2500 0.0000 0.2500 0.7500 PACKAGE OUTLINE Y E 2x Z H1 MIN 0.65 0.01 0.30 0.22 DETAIL C SUBSTRATE SYMBOL A A1 L b D E D1 E1 e H1 H2 aaa bbb ccc ddd eee fff DETAIL B H2 MOLD CAP NOM 0.74 0.02 0.40 0.25 2.00 2.00 0.70 0.70 0.50 0.24 REF 0.50 REF DIMENSIONS 12b eee M Z X Y fff M Z DETAIL C A1 12x 0.10 0.10 0.10 0.10 0.15 0.08 MAX 0.83 0.03 0.50 0.28 e/2 e L SUBSTRATE THK MOLD CAP HT NOTES DETAIL A DETAIL B A (Reference LTC DWG # 05-08-1530 Rev B) ddd Z Z 22 e 7 6 D1 e 0.250 5 DETAIL A PACKAGE BOTTOM VIEW 6 11 b 12 4 1 PIN 1 NOTCH 0.14 x 45 4 SEE NOTES DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII 5 6 LQFN 12 0618 REV B METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES 4 3. PRIMARY DATUM -Z- IS SEATING PLANE 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 E1 b 10 ccc M Z X Y ccc M Z X Y LQFN Package 12-Lead (2mm x 2mm x 0.74mm) LTC3315A PACKAGE DESCRIPTION Rev. A LTC3315A REVISION HISTORY REV DATE DESCRIPTION A 11/19 Added AEC-Q100 Qualified Added #W Flow Part Numbers PAGE NUMBER 1 2 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 23 LTC3315A TYPICAL APPLICATION Dual Buck Regulators with Supply Sequencing VIN 2.25V TO 5.5V 880nH 10F 1F 0201 VIN 140k EN1 10F 169k 1F 0201 SW1 LTC3315A VIN VOUT1 1.2V, 2A 33F FB1 100k 1.0H SW2 261k EN2 100k 6.8pF 4.7pF VOUT2 1.8V, 2A 22F FB2 0.1F 100k MODE/SYNC GND fSW = 2MHz PGOOD 1M VOUT1 3315A TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3309A 6A, Low Voltage, Synchronous Step-Down DC/DC in 2mm x 2mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 6A at Switching Frequencies Up to 3MHz. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RT Programming, SYNC Input. 2mm x 2mm LQFN LTC3310S 10A, Low Voltage, Synchronous Step-Down Silent Switcher(R) in 3mm x 3mm LQFN Monolithic Synchronous Step-Down DC/DC Capable of Supplying 10A at Switching Frequencies Up to 5MHz. Silent Switcher Architecture for Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to VIN Output Voltage Range with 1% Accuracy. PGOOD Indication, RT Programming, SYNC Input. Configurable for Paralleling Power Stages. 3mm x 3mm LQFN LTC3370/ LTC3371 4-Channel 8A Configurable 1A Buck DC/DCs Four Synchronous Buck Regulators with 8 x 1A Power Stages. Can Connect Up to Four Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 8 Output Configurations Possible. Precision PGOOD Indication. LTC3371 Has a Watchdog Timer. LTC3370: 32-Lead 5mm x 5mm QFN. LTC3371: 38-Lead 5mm x 7mm QFN and TSSOP LTC3374/ LTC3374A 8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 15 Output Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. 38-Lead 5mm x 7mm QFN and TSSOP LTC3375 8-Channel Parallelable 1A Buck DC/DCs Eight 1A Synchronous Buck Regulators. Can Connect Up to Four Power Stages in Parallel to Make a High Current Output (4A Maximum) with a Single Inductor. 15 Output Configurations Possible. Precision Enable Inputs and PGOOD_ALL Reporting. I2C Programming with a Watchdog Timer and Pushbutton. 48-Lead 7mm x 7mm QFN LT8614 42V, 4A Synchronous Step-Down Silent Switcher(R) with 2.5A Quiescent Current Synchronous Micropower Step-Down DC/DC Converter with Silent Switcher Architecture. Up to 96% Efficiency at 1MHz, 12VIN to 5VOUT. Up to 94% Efficiency at 2MHz, 12VIN to 5VOUT. VIN: 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5A, ISD <1A, 18-Lead 3mm x 4mm QFN Rev. A 24 11/19 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2019