1
FEATURES
DESCRIPTION
UC1707 , UC2707 , UC3707
www.ti.com
............................................................................................................................................. SLUS177B MARCH 1999 REVISED SEPTEMBER 2008
DUAL CHANNEL POWER DRIVER
Analog Shutdown With Optional LatchTwo Independent Drivers Low Quiescent Current1.5 A Totem Pole Outputs 5 V to 40 V OperationInverting and Non-Inverting Inputs Thermal Shutdown Protection40 ns Rise and Fall Into 1000 pF 16-Pin Dual-In-Line PackageHigh-Speed, Power MOSFET Compatible 20-Pin PLCC and CLCC PackageLow Cross-Conduction Current Spike
The UC1707 family of power drivers is made with a high-speed Schottky process to interface between low-levelcontrol functions and high-power switching devices particularly power MOSFETs. These devices contain twoindependent channels, each of which can be activated by either a high or low input logic level signal. Each outputcan source or sink up to 1.5 A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, it can be forced low in common throughthe action either of a digital high signal at the Shutdown terminal or a differential low-level analog signal. TheShutdown command from either source can either be latching or not, depending on the status of the LatchDisable pin.
Supply voltage for both V
IN
and V
C
can independently range from 5 V to 40 V.
These devices are available in two-watt plastic " bat-wing " DIP for operation over a 0 ° C to 70 ° C temperaturerange and, with reduced power, in a hermetically sealed cerdip for 55 ° C to +125 ° C operation. Also available insurface mount DW, Q, L packages.
TRUTH TABLE(Each Channel)
(1)
INV. N.I. OUT
H H LL H HH L LLLL
(1) OUT = INV and N.I.OUT = INV or N.I.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
BLOCK DIAGRAM
CONNECTION DIAGRAMS
UC1707 , UC2707 , UC3707
SLUS177B MARCH 1999 REVISED SEPTEMBER 2008 .............................................................................................................................................
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2Submit Documentation Feedback Copyright © 1999 2008, Texas Instruments Incorporated
Product Folder Link(s): UC1707 UC2707 UC3707
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
UC1707 , UC2707 , UC3707
www.ti.com
............................................................................................................................................. SLUS177B MARCH 1999 REVISED SEPTEMBER 2008
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
IN
Supply voltage N/J package 40 VV
C
Collector supply voltage N/J package 40 VOutput current (each output, source or sink) steady-state N/J package ± 500 mAN package ± 1.5Peak transient AJ package ± 1.0N package 20Capacitive discharge energy mJJ package 15Digital inputs
(1)
N/J-package 5.5 VAnalog stop inputs N/J package V
IN
N package 2Power dissipation at T
A
= 25 ° C WJ package 1N package 5Power dissipation at T (leads/case) = 25 ° C
(1)
WJ package 2Operating temperature range 55 +125 ° CStorage temperature range 65 +150 ° CLead temperature (soldering, 10 seconds) 300 ° C
(1) All voltages are with respect to the four ground pins which must be connected together. All currents are positive into, negative out of thespecified terminal. Digital drive can exceed 5.5 V if input current is limited to 10 mA. Consult packaging section of databook for thermallimitations and considerations of package.
Unless otherwise stated, these specifications apply for T
A
= 55 ° C to +125 ° C for the UC1707, 25 ° C to +85 ° C for theUC2707, and 0 ° C to +70 ° C for the UC3707; V
IN
= V
C
= 20 V. T
A
= T
J
.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Supply current V
IN
= 40 V 12 15 mAV
C
Supply current V
C
= 40 V, outputs low 5.2 7.5 mAV
C
Leakage current V
IN
= 0, V
C
- 30 V, no load 0.05 0.1 mADigital input low level 0.8 VDigital input high level 2.2 VInput current V
I
= 0 0.06 1.0 mAInput leakage V
I
= 5 V 0.05 0.1 mAI
O
= 50 mA 2.0V
C
V
O
Output high sat. VI
O
= 500 mA 2.5I
O
= 50 mA 0.4V
O
Output low sat. VI
O
= 500 mA 2.5Analog threshold V
CM
= 0 to 15 V 100 130 160 mVInput bias current V
CM
= 0 10 20 µAThermal shutdown 155 ° CShutdown threshold Pin 7 input 0.4 1.0 2.2 VLatch disable threshold Pin 3 input 0.8 1.2 2.2 V
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TYPICAL SWITCHING CHARACTERISTICS
UC1707 , UC2707 , UC3707
SLUS177B MARCH 1999 REVISED SEPTEMBER 2008 .............................................................................................................................................
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V
IN
= V
C
= 20 V, T
A
= 25 ° C. Delays measured to 10% output change.
PARAMETER TEST CONDITIONS OUTPUT CL = UNIT
From Inv. Input to Output open 1.0 2.2 nFRise time delay 40 50 60 ns10% to 90% rise 25 40 50 nsFall time delay 30 40 50 ns90% to 10% fall 25 40 50 ns
From N.I. Input to Output
Rise time delay 30 40 50 ns10% to 90% rise 25 40 50 nsFall time delay 45 55 65 ns90% to 10% fall 25 40 50 nsV
C
cross-conduction current spike duration Output rise 25 nsOutput fall 0 nsAnalog shutdown delay Stop non-Inv. = 0 V 180 nsStop Inv. = 0 to 0.5 V 180 nsDigital shutdown delay 2 V input on Pin 7 50 ns
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Product Folder Link(s): UC1707 UC2707 UC3707
SIMPLIFIED INTERNAL CIRCUITRY
UC1707 , UC2707 , UC3707
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............................................................................................................................................. SLUS177B MARCH 1999 REVISED SEPTEMBER 2008
Figure 1. Typical Digital Input Gate
Figure 2. Typical Digital Input Gate Figure 3. Latch Disable
Copyright © 1999 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
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SHUTDOWN CIRCUIT DESCRIPTION
UC1707 , UC2707 , UC3707
SLUS177B MARCH 1999 REVISED SEPTEMBER 2008 .............................................................................................................................................
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SIMPLIFIED INTERNAL CIRCUITRY (continued)
Figure 4. Use of the Shutdown Pin
The function of the circuitry is to be able to provide a shutdown of the device. This is defined as functionality thatwill drive both outputs to the low state. There are three different inputs that govern this shutdown capability.Analog Stop Pins The differential inputs to this comparator provide a way to execute a shutdown.Latch Disable Pin Assuming that the Shutdown pin is left open, a high on this pin disables the latchingfunctionality of the Analog Stop shutdown. A low on this pin enables the latching functionality of the AnalogStop shutdown. If a shutdown occurs through the Analog Stop circuit while Latch Disable is high, then theoutputs will go low, but will return to normal operation as soon as the Analog Stop circuit allows it. If ashutdown occurs through the Analog Stop circuit while Latch Disable is low, then the outputs will go low andremain low even if the Analog Stop circuit no longer drives the shutdown. The outputs will remain " latched "low (in shutdown) until the Latch Disable goes high and the Analog Stop circuit allows it to return fromshutdown or the VIN voltage is cycled to 0V and then returned above 5V.Shutdown Pin This pin serves two purposes.1. It can be used as an output of the Analog Stop circuit.2. It can be used as an input to force a shutdown or to force the device out of shutdown. This pin canoverride both the Analog Stop circuit as well as the Latch Disable Pin. When driving hard logic levels intothe Shutdown pin, the Latch Disable functionality will be overridden and the Latch Disable will not functionas it does when used in conjunction with the Analog Stop circuit. When the Shutdown pin is high, theoutputs will be in the low state (shutdown). When the Shutdown pin is low (hard logic low) the outputs willoperate normally, regardless of the state of the Latch Disable pin or the Analog Stop pins.
In order to use the Shutdown Pin with the Latch Disable functional it is necessary to use either a diode in serieswith the Shutdown signal or to use an open collector pull-up so that the Shutdown pin is not pulled low. Thisconfiguration will allow the Latch Disable function to work with the Shutdown pin.
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Product Folder Link(s): UC1707 UC2707 UC3707
UC1707 , UC2707 , UC3707
www.ti.com
............................................................................................................................................. SLUS177B MARCH 1999 REVISED SEPTEMBER 2008
SIMPLIFIED INTERNAL CIRCUITRY (continued)UG1707 SHUTDOWN TRUTH TABLE
ANALOG STOP PREVIOUS STATE OFSHUTDOWN LATCH DISABLE OUTPUTLOGIC OUTPUT
X 0 X X Follows Input LogicX 1 X X Low (Shutdown)1 Open X X Low (Shutdown)0 Open 0 Shutdown
(1)
Latched Shutdown0 Open 0 Normal Follows Input Logic0 Open 1 X Follows Input Logic
(1) If the output was previously in Shutdown and Latch Disable was low and stays low, then even if the Analog Stop Logic is changed or theShutdown pin is open, the outputs will remain in Shutdown.
Figure 5. Transformer Coupled Push-Pull MOSFET Drive Circuit
Figure 6. Current Limiting
Copyright © 1999 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707 , UC2707 , UC3707
SLUS177B MARCH 1999 REVISED SEPTEMBER 2008 .............................................................................................................................................
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Figure 7. Over-Voltage Protection Figure 8. Power MOSFET Drive Circuit
Figure 9. Charge Pump Circuits
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Product Folder Link(s): UC1707 UC2707 UC3707
UC1707 , UC2707 , UC3707
www.ti.com
............................................................................................................................................. SLUS177B MARCH 1999 REVISED SEPTEMBER 2008
Figure 10. Power Bipolar Drive Circuit
Figure 11. Transformer Coupled MOSFET Drive Circuit
Copyright © 1999 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): UC1707 UC2707 UC3707
UC1707 , UC2707 , UC3707
SLUS177B MARCH 1999 REVISED SEPTEMBER 2008 .............................................................................................................................................
www.ti.com
Figure 12. Power MOSFET Drive Circuit Using Negative Bias Voltageand Level Shifting to Ground Reference PWM
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-87619012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8761901EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
5962-8761901V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8761901VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
5962-8761903VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
5962-8761903VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
UC1707J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC1707J/80313 OBSOLETE CDIP J 16 TBD Call TI Call TI
UC1707J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC1707L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC1707L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC2707DW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2707DWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2707DWTR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2707DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC2707N ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC2707NG4 ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC2707Q ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
UC2707QG3 ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
UC3707DW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3707DWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UC3707DWTR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3707DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC3707J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC3707N ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
UC3707NG4 ACTIVE PDIP N 16 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1707, UC1707-SP, UC3707, UC3707M :
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 3
Catalog: UC3707, UC1707, UC3707M, UC3707
Military: UC1707
Space: UC1707-SP
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC2707DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3707DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2707DWTR SOIC DW 16 2000 367.0 367.0 38.0
UC3707DWTR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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