IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 1
DR030-0A 09/28/2001
Document Title
1M x 16 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 28,2001
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
2Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 1,024 cycles /16 ms
•Refresh Mode:
RAS-Only, CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% (IC41C16100A(S))
3.3V ± 10% (IC41LV16100A(S))
• Byte Write and Byte Read operation via two CAS
• Self Refresh 1024 cycles for S version
DESCRIPTION
The ICSI IC41C16100A(S) and IC41LV16100A(S) are 1,048,
576 x 16-bit high-performance CMOS Dynamic Random
Access Memories. These devices offer an accelerated cycle
access called EDO Page Mode. EDO Page Mode allows 1,024
random accesses within a single row with access cycle time as
short as 20 ns per 16-bit word. The Byte Write control, of upper
and lower byte, makes the 16100 series ideal for use in
16-, 32-bit wide data bus systems.
These features make the IC41C16100A(S) and IC41LV16100A
(S) ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IC41C16100A(S) and IC41LV16100A(S) are packaged in a
42-pin 400mil SOJ and 400mil 50- (44-) pin TSOP-2.
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
Max. RAS Access Time (tRAC)5060ns
Max. CAS Access Time (tCAC)1315ns
Max. Column Address Access Time (tAA)2530ns
Min. EDO Page Mode Cycle Time (tPC)2025ns
Min. Read/Write Cycle Time (tRC) 84 104 ns
42-Pin SOJ
PIN CONFIGURATIONS
50(44)-Pin TSOP-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-15 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
Vcc Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 3
DR030-0A 09/28/2001
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
4Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
TRUTH TABLE
Function RASRAS
RASRAS
RAS LCASLCAS
LCASLCAS
LCAS UCASUCAS
UCASUCAS
UCAS WEWE
WEWE
WE OEOE
OEOE
OE Address tR/tCI/O
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write
(1,2)
LLLH
→
LL
→
H ROW/COL DOUT, DIN
EDO Page-Mode Read
(2)
1st Cycle: L H
→
LH
→
L H L ROW/COL DOUT
2nd Cycle: L H
→
LH
→
L H L NA/COL DOUT
Any Cycle: L L
→
HL
→
H H L NA/NA DOUT
EDO Page-Mode Write
(1)
1st Cycle: L H
→
LH
→
L L X ROW/COL DIN
2nd Cycle: L H
→
LH
→
L L X NA/COL DIN
EDO Page-Mode
(1,2)
1st Cycle: L H
→
LH
→
LH
→
LL
→
H ROW/COL DOUT, DIN
Read-Write 2nd Cycle: L H
→
LH
→
LH
→
LL
→
H NA/COL DOUT, DIN
Hidden Refresh Read
(2)
L
→
H
→
L L L H L ROW/COL DOUT
Write
(1,3)
L
→
H
→
L L L L X ROW/COL DIN
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
(4)
H
→
L L L X X X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 5
DR030-0A 09/28/2001
Functional Description
The IC41C16100A(S) and IC41LV16100A(S) is a CMOS
DRAM optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 16 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first ten bits and CAS is used the
latter ten bits.
The IC41C16100A(S) and IC41LV16100A(S) has two CAS
controls, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IC41C16100A(S) and IC41LV16100A(S) CAS func-
tion is determined by the first CAS (LCAS or UCAS)
transitioning LOW and the last transitioning back HIGH.
The two CAS controls give the IC41C16100A(S) and
IS41LV16100A(S) both BYTE READ and BYTE WRITE
cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 128 ms.
i.e., 125 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRASS.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 1,024 rows must be refreshed
within the average internal refresh rate, prior to the re-
sumption of normal operation.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
6Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
VTVoltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
VCC Supply Voltage 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
IOUT Output Current 50 mA
PDPower Dissipation 1 W
TACommercial Operation Temperature 0 to +70 °C
TSTG Storage Temperature –55 to +125 ° C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TACommercial Ambient Temperature 0 — 70 ° C
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
CIN1Input Capacitance: A0-A9 5 pF
CIN2Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 7
DR030-0A 09/28/2001
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –5 5 µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) – 5 5 µA
0V ≤ VOUT ≤ Vcc
VOH Output High Voltage Level IOH = –5.0 mA (5V) 2. 4 — V
IOH = –2.0 mA (3.3V)
VOL Output Low Voltage Level IOL = 4.2 mA (5V) — 0 .4 V
IOL = 2.0 mA (3.3V)
ICC1Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commerical 5V — 2 mA
3.3V — 2
ICC2Standby Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V 5V — 1 mA
3.3V — 0.5
ICC3Operating Current: RAS, LCAS, UCAS, -50 — 160 mA
Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) - 60 — 14 5
Average Power Supply Current
ICC4Operating Current: RAS = VIL, LCAS, UCAS, -50 — 90 mA
EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -6 0 — 8 0
Average Power Supply Current
ICC5Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 — 160 mA
RAS-Only(2,3) tRC = tRC (min.) - 6 0 — 1 4 5
Average Power Supply Current
ICC6Refresh Current: RAS, LCAS, UCAS Cycling - 50 — 160 mA
CBR(2,3,5) tRC = tRC (min.) - 6 0 — 14 5
Average Power Supply Current
ICCS Self Refresh Current Self Refresh mode 5V — 5 00 µA
3.3V — 300 µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
8Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 8 4 — 1 0 4 — ns
tRAC Access Time from RAS(6, 7) —50—60 ns
tCAC Access Time from CAS(6, 8, 15) —13—15 ns
tAA Access Time from Column-Address(6) —25—30 ns
tRAS RAS Pulse Width 50 10 K 6 0 1 0 K ns
tRP RAS Precharge Time 3 0 — 4 0 — ns
tCAS CAS Pulse Width(26) 810K1010Kns
tCP CAS Precharge Time(9, 25) 10 — 10 — ns
tCSH CAS Hold Time (21) 38 — 40 — ns
tRCD RAS to CAS Delay Time(10, 20) 12 37 14 45 ns
tASR Row-Address Setup Time 0 — 0 — ns
tRAH Row-Address Hold Time 8 — 10 — ns
tASC Column-Address Setup Time(20) 0—0—ns
tCAH Column-Address Hold Time(20) 8—10—ns
tRAD RAS to Column-Address Delay Time(11) 10 25 12 30 ns
tRAL Column-Address to RAS Lead Time 2 5 — 3 0 — ns
tRSH RAS Hold Time(27) 8—10—ns
tRHCP RAS Hold Time from CAS Precharge 3 5 — 3 7 — ns
tCLZ CAS to Output in Low-Z(15, 29) 0—0—ns
tCRP CAS to RAS Precharge Time(21) 5—5—ns
tOD Output Disable Time(19, 28, 29) 012015ns
tOE Output Enable Time(15, 16) —12—15 ns
tOED Output Enable Data Delay (Write) 2 0 — 2 0 — ns
tOEHC OE HIGH Hold Time from CAS HIGH 5 — 5 — ns
tOEP OE HIGH Pulse Width 1 0 — 1 0 — ns
tRCS Read Command Setup Time(17, 20) 5—5—ns
tRRH Read Command Hold Time 10 — 10 — ns
(referenced to RAS)(12)
tRCH Read Command Hold Time 0 — 0 — ns
(referenced to CAS)(12, 17, 21)
tWCH Write Command Hold Time(17, 27) 8—10—ns
tWP Write Command Pulse Width(17) 8—10—ns
tWPZ WE Pulse Widths to Disable Outputs 10 — 1 0 — ns
tRWL Write Command to RAS Lead Time(17) 13 — 15 — ns
tCWL Write Command to CAS Lead Time(17, 21) 8—10—ns
tWCS Write Command Setup Time(14, 17, 20) 0—0—ns
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 9
DR030-0A 09/28/2001
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tOEH OE Hold Time from WE during 8 — 1 0 — ns
READ-MODIFY-WRITE cycle(18)
tDS Data-In Setup Time(15, 22) 0—0—ns
tDH Data-In Hold Time(15, 22) 8—10—ns
tRWC READ-MODIFY-WRITE Cycle Time 1 08 — 1 33 — ns
tRWD RAS to WE Delay Time during 6 4 — 7 7 — ns
READ-MODIFY-WRITE Cycle(14)
tCWD CAS to WE Delay Time(14, 20) 26 — 32 — ns
tAWD Column-Address to WE Delay Time(14) 39 — 47 — ns
tPC EDO Page Mode READ or WRITE 2 0 — 25 — ns
Cycle Time(24)
tRASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns
tCPA Access Time from CAS Precharge(15) —30—35ns
tPRWC EDO Page Mode READ-WRITE 5 6 — 68 — ns
Cycle Time(24)
tCOH Data Output Hold after CAS LOW 5 — 5 — ns
tOFF Output Buffer Turn-Off Delay from 0 1 2 0 1 5 ns
CAS or RAS(13,15,19, 29)
tWHZ Output Disable Delay from WE 310310ns
tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5—5—ns
tCHR CAS Hold Time (CBR REFRESH)(30, 21) 8—10—ns
tRPC RAS to CAS Precharge Time 5 — 5 — ns
tORD OE Setup Time prior to RAS during 0 — 0 — ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period (1,024 Cycles) — 1 6 — 1 6 ms
tTTransition Time (Rise or Fall)(2, 3) 150150ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
10 Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 11
DR030-0A 09/28/2001
READ CYCLE
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS tRC tRP
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF(1)
tRAC
tCLZ
tOES
tOE tOD
Undefined
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
12 Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
CAH
t
ASC
t
RAD
t
RAL
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
Valid Data
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 13
DR030-0A 09/28/2001
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
CAH
t
ASC
t
RAD
t
RAL
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid DOUT Valid DIN
Undefined
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
14 Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
EDO-PAGE-MODE READ CYCLE
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
tRASP tRP
ADDRESS
UCAS/LCAS
RAS
Row Row
tCAS
tCRP tRCD
tCSH tCP tCAS
tCAH
tCAS
tRAL
tRSH tCPtCP
tPC(1)
tASR
tRAH
tRAD
Column Column
tCAHtCAH
Column
tASCtASC
OE
I/O
WE
Open Open
Valid Data
tAA tAA
tCPA
tCAC tCAC
tRAC
tCOHtCLZ
tOEP
tOE tOD
tOEtOEHC
Valid Data
tRCH tRRH
tAA
tCPA
tCAC tOFFtCLZ
Valid Data
tOD
tASC
tRCS
Undefined
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 15
DR030-0A 09/28/2001
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP tRP
ADDRESS
UCAS/LCAS
RAS
Row Row
tCAS
tCRP tRCD
tCSH tCP tCAS
tCAH
tCAS
tRAL
tRSH tCPtCP
tPC
tASR
tRAH
tRAD
Column Column
tCAHtCAH
Column
tASCtASC
OE
I/O
WE
Valid Data
tASC
tWCS
tWCH
tCWL
tWP
tRHCP
tWCS
tWCH
tCWL
tWP
tDH
tDS
tWCS
tWCH
tCWL
tWP
Valid Data
tDS tDH
Valid Data
tDS
tRWL
tDH
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
16 Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
Note:
1. tPC is for LATE WRITE only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to
rising edge of CAS. Both measurements must meet the tPC specifications.
t
RASP
t
RP
ADDRESS
UCAS/LCAS
RAS
Row Row
t
CRP
t
RCD
t
CSH
t
CP
t
CAH
t
CAS
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
ASR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
t
CAS
t
CAS
OE
I/O
WE
t
ASC
t
RWD
t
RCS
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
t
CAC
t
CLZ
t
AWD
t
CWD
t
CWL
t
WP
t
AWD
t
CWD
t
CWL
t
RWL
t
WP
Open Open
D
IN
D
OUT
t
OE
t
OE
t
OE
t
OD
t
OEH
t
OD
t
OD
t
DH
t
DS
t
CPA
t
AA
t
CAC
t
CLZ
D
IN
D
OUT
t
DH
t
DS
t
CAC
t
CLZ
D
IN
D
OUT
t
CPA
t
AA
t
RAC
t
AA
t
PC
/ t
PRWC
(1)
Undefined
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 17
DR030-0A 09/28/2001
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
t
RASP
t
RP
ADDRESS
UCAS/LCAS
RAS
Row Row
t
CRP
t
RCD
t
PC
t
CSH
t
CP
t
CAH
t
CAS
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
ASR
Column (A) Column (N)
t
CAH
t
CAH
Column (B)
t
ASC
t
ASC
t
CAS
t
CAS
OE
I/O
WE
t
ASC
t
CAC
t
RCH
t
DH
Open Open
Valid Data (A)
t
OE
t
WCS
t
CAC
t
COH
D
IN
t
CPA
t
WCH
t
RAC
t
AA
t
PC
Valid Data (B)
t
WHZ
t
DS
t
RCS
t
AA
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
18 Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RASRAS
RASRAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
CAH
t
ASC
t
ASC
t
RAD
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column
Open Open
Valid Data
t
CSH
t
CAS
t
CRP
t
RCD
t
CP
t
RAH
t
ASR
t
RCH
t
RCS
t
RCS
t
AA
t
CAC
t
WHZ
t
RAC
t
CLZ
t
CLZ
t
OE
t
OD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
UCAS/LCAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Undefined
Don’t Care
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 19
DR030-0A 09/28/2001
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RAS
t
RP
t
RP
I/O
UCAS/LCAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
UCAS/LCAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Undefined
Don’t Care
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
20 Integrated Circuit Solution Inc.
DR030-0A 09/28/2001
SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)
t
RASS
t
RP
t
RPS
DQ
UCAS/LCAS
RAS
Open
t
CP
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
RPC
t
CSR
t
CHD
t
RPC
t
CP
Don’t Care
TIMING PARAMETERS
-50 -60
Symbol Min. Max. Min. Max. Units
tCHD 8— 10— ns
tCP 10 — 10 — ns
tCSR 5— 5— ns
tRASS 100 — 100 — µs
tRP 30 — 40 — ns
tRPS 84 — 104 — ns
tRPC 5— 5— ns
ORDERING INFORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
50 IC41C16100A-50K 400mil SOJ
IC41C16100A-50T 400mil TSOP-2
60 IC41C16100A-60K 400mil SOJ
IC41C16100A-60T 400mil TSOP-2
ORDERING INFORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
50 IC41C16100AS-50K 400mil SOJ
IC41C16100AS-50T 400mil TSOP-2
60 IC41C16100AS-60K 400mil SOJ
IC41C16100AS-60T 400mil TSOP-2
IC41C16100A/IC41C16100AS
IC41LV16100A/IC41LV16100AS
Integrated Circuit Solution Inc. 21
DR030-0A 09/28/2001
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION: 3.3V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
50 IC41LV16100A-50K 400mil SOJ
IC41LV16100A-50T 400mil TSOP-2
60 IC41LV16100A-60K 400mil SOJ
IC41LV16100A-60T 400mil TSOP-2
ORDERING INFORMATION: 3.3V
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
50 IC41LV16100AS-50K 400mil SOJ
IC41LV16100AS-50T 400mil TSOP-2
60 IC41LV16100AS-60K 400mil SOJ
IC41LV16100AS-60T 400mil TSOP-2
