Ver: 2.3
May 16, 2006 TEL: 886-3-5788833
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1
G2996
Global Mixed-mode Technology Inc.
DDR I/II Termination Regulator
Features
Operation Supply Voltage: 1.6V to 5.5V
Low Supply Current: 280µA @ 2.5V
Low Output Offset
Source and Sink Current
Low External Component Count
No Inductor Required
No external Resistors Required
Thermal Shutdown Protection
Suspend to RAM (STR) function
SOP-8 with Power-Pad package
Applications
DDR-SDRAM Termination Voltage
DDR-I / DDR-II Termination Voltage
SSTL-2
SSTL-3
General Description
The G2996 is a linear regulator designed to meet the
JEDEC SSTL-18 ,SSTL-2 and SSTL-3 (Series Stub
Termination Logic) specifications for termination of
DDR-SDRAM. It contains a high-speed operational
amplifier that provides excellent response to the load
transients. This device can deliver 1.5A/0.9A continu-
ous current and transient peaks up to 3A/1.8A in the
application as required for DDRI/II-SDRAM termination.
With an independent VSENSE pin, the G2996 can pro-
vide superior load regulation. The G2996 provides a
VREF output as the reference for the applications of the
chipset and DIMMs.
The G2996 can easily provide the accurate VTT and
VREF voltages without external resistors that PCB ar-
eas can be reduced. The quiescent current is as low
as 280µA @ 2.5V. So the power consumption can
meet the low power consumption applications.
The G2996 also has an active low shutdown (SD ) pin
that provides Suspend to RAM (STR) functionality.
When SD is pulled low, the VTT output will be tri-state
providing a high impendence, but VREF will remain ac-
tive. A power saving advantage can be obtained in this
mode through lowering the quiescent current to180µA
@ 2.5V.
Ordering Information
ORDER
NUMBER ORDER NUMBER
(Pb free) MARKING TEMP.
RANGE PACKAGE
G2996P1U G2996P1Uf G2996 -40°C to 85°C SOP-8
G2996F1U G2996F1Uf G2996 -40°C to 85°C SOP-8 (FD)
Note: P1:SOP-8 F1:SOP-8(FD)
U: Tape & Reel (FD): Thermal Pad
Pin Configuration Typical Application Circuit
VSENSE
8
6
5
1
2
3
4
SD
GND VTT
PVIN
AVIN
VDDQ
SOP-8
G2996
7
VREF
Thermal
Pad
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND VTT=1.25V
VREF=1.25V
VDDQ=2.5V
VDD=2.5V
SD
47µF220µF
0.01µF
VSENSE
8
6
5
1
2
3
4
SD
GND VTT
PVIN
AVIN
VDDQ
SOP-8
G2996
7
VREF
Thermal
Pad
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND VTT=1.25V
VREF=1.25V
VDDQ=2.5V
VDD=2.5V
SD
47µF220µF
0.01µF
Ver: 2.3
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G2996
Global Mixed-mode Technology Inc.
Absolute Maximum Ratings (1)
Supply Voltage
PVIN, AVIN, VDDQ to GND . . . . . . . . . . . -0.3V to +6V
Operating Ambient Temperature Range
TA . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Maximum Junction Temperature, TJ . . . . . . . . ..150°C
Storage Temperature Range, TSTG . . -65°C to+150°C
Reflow Temperature (soldering, 10 sec) . . . . . .260°C
Electrostatic Discharge, VESD
Human body mode . . . . . . . . . . . . . . . . . . . . .2000V(2)
Thermal Resistance Junction to Ambient, (θJA)
SOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130°C/W
SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W(3)
SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W(4)
SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . . 41°C/W(5)
Thermal Resistance Junction to Case, (θJC)
SOP-8 (FD) . . . . . . . . . . . . . . . . . . . . . . . . . ..12°C/W
Recommend Operation Range
Operating Ambient Temperature Range
TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
AVIN to GND . . . . . . . . . . . . . . . . . . . . . 1.6V to +5.5V
PVIN, SD, VDDQ to GND . . . . . . . . . . . . 1.6V to AVIN
Note:
(1) : Absolute maximum rating indicates limits beyond which damage to the device may occurs.
(2) : Human body model : C = 100pF, R = 1500Ω, 3 positive pulses plus 3 negative pulses
(3): The package is placed on a 2-layer PCB (1oz/1oz) with minimum footprint.
(4): The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. Please refer the evaluation board manual (EV2996-10) for pcb layout.
(5): The package is placed on a 2-layer PCB (2oz/2oz) with 6 vias. The airflow is used. Please refer the evaluation board manual
(EV2996-10) for pcb layout.
Electrical Characteristics
Specifications with standard typeface are for TA=25°C. unless otherwise specified, AVIN=PVIN=2.5V,
VDDQ=2.5V for DDR I, AVIN=PVIN=VDDQ=1.8V for DDRII.
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
VREF Voltage VREF VDDQ=1.7V
VDDQ=1.8V
VDDQ=1.9V
0.810
0.860
0.910
0.849
0.898
0.949
0.890
0.940
0.990
V
V
V
VREF Voltage VREF VDDQ=2.3V
VDDQ=2.5V
VDDQ=2.7V
1.11
1.21
1.31
1.145
1.245
1.345
1.19
1.29
1.39
V
V
V
VREF Output impendence ZREF I
REF =-30µA to + 30µA --- 1.15 --- kΩ
VTT Output voltage VTT
IOUT=0A
VDDQ=1.7V
VDDQ=1.8V
VDDQ=1.9V
IOUT=±0.9A
VDDQ=1.7V
VDDQ=1.8V
VDDQ=1.9V
0.810
0.860
0.910
0.810
0.860
0.910
0.847
0.896
0.947
0.847
0.896
0.947
0.890
0.940
0.990
0.890
0.940
0.990
V
V
V
V
V
V
VTT Output voltage VTT
IOUT=0A
VDDQ=2.3V
VDDQ=2.5V
VDDQ=2.7V
IOUT=±1.5A
VDDQ=2.3V
VDDQ=2.5V
VDDQ=2.7V
1.11
1.21
1.31
1.11
1.21
1.31
1.152
1.252
1.352
1.152
1.252
1.352
1.19
1.29
1.39
1.19
1.29
1.39
V
V
V
V
V
V
Ver: 2.3
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G2996
Global Mixed-mode Technology Inc.
Electrical Characteristics
Specifications with standard typeface are for TA=25°C. unless otherwise specified, AVIN=PVIN=2.5V,
VDDQ=2.5V for DDR I, AVIN=PVIN=VDDQ=1.8V for DDRII.
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
VTT Output Voltage Offset (VREF- VTT) VosVtt IOUT=0A
IOUT=-0.9A
IOUT=+0.9A
-40
-40
-40
0
0
0
40
40
40
mV
mV
mV
VTT Output Voltage Offset (VREF- VTT) VosVtt IOUT=0A
IOUT=-1.5A
IOUT=+1.5A
-40
-40
-40
0
0
0
40
40
40
mV
mV
mV
Quiescent Current IQ IOUT=0A --- 280 500 µA
VDDQ input Impedence ZVDDQ --- 100 --- kΩ
Quiescent Current in shutdown ISD SD =0 --- 180 300 µA
Shutdown leakage current IQ_SD --- 0.01 --- µA
VSENSE input current ISENSE --- 20 --- nA
VTT leakage current in shutdown IV SD =0, VTT =1.25V --- 0.01 --- µA
Minimum Shutdown High Level VIH 1.6 --- --- V
Maximum Shutdown Low Level VIL --- --- 0.8 V
Thermal Shutdown TSD --- 150 --- °C
Thermal Shutdown Hystersis THsy --- 25 --- °C
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G2996
Global Mixed-mode Technology Inc.
Typical Performance Characteristics
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF/Ceramic X7R/0603/6.3V/TDK, CPVIN=68µF/6.3V POSCAP Se-
ries/SANYO, CVTT=330µF*2/6.3V POSCAP Series/SANYO, TA=25°C, unless otherwise noted.
ILoad=0.5A Transient (Sinking) ILoad=0.5A Transient (Sourcing)
ILoad=1A Transient (Sinking) ILoad=1A Transient (Sourcing)
ILoad=1.5A Transient (Sinking) ILoad=1.5A Transient (Sourcing)
Ver: 2.3
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G2996
Global Mixed-mode Technology Inc.
Typical Performance Characteristics
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C,
unless otherwise noted.
IO=200m
IQ vs AVIN in SD
100
110
120
130
140
150
160
22.533.544.555.5
AVIN(V)
IQ(µA)
IQ vs AV IN
150
170
190
210
230
250
270
22.533.544.555.5
AVIN(V)
IQ(µA)
VIH and VIL
0.8
1
1.2
1.4
1.6
1.8
2
22.533.544.555.5
AVIN(V)
VSD(V)
VREF vs IREF
1.18
1.2
1.22
1.24
1.26
1.28
1.3
-30 -20 -10 0 10 20 30
IREF(µA)
VREF(V)
VREF vs VDDQ
0
0.5
1
1.5
2
2.5
3
22.533.544.555.5
VDDQ(V)
VREF(V)
VTT vs IOUT Temperature
1.232
1.236
1.24
1.244
1.248
1.252
-100 -75 -50 -25 0 25 50 75 100
IOUT(mA)
VTT(V)
25°C
85°C
0°C
VIH
VIL
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G2996
Global Mixed-mode Technology Inc.
Typical Performance Characteristics (continued)
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C,
unless otherwise noted.
IO=200m
VTT vs VDDQ
0
0.5
1
1.5
2
2.5
3
22.533.544.555.5
VDDQ(V)
VTT(V)
IQ vs AVIN in SD Temperature
100
110
120
130
140
150
160
22.533.544.555.5
AVIN(V)
IQ(µA)
25
°
85
°
0°C
IQ vs AVIN Temperature
150
170
190
210
230
250
270
22.533.544.555.5
AVIN(V)
IQ(µA)
0°C
85°C
25°C
Maximum Sourcing Current vs AVIN
(VDDQ=2.5V, PVIN=1.8V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
22.533.544.555.5
AVIN(V)
Output Current(A)
Maximum Sourcing Current vs AVIN
(VDDQ=2.5V, PVIN=3.3V)
2
2.2
2.4
2.6
2.8
3
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
Output Current(A)
Maximum Sourcing Current vs AVIN
(VDDQ=2.5V, PVIN=2.5V)
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
Output Current(A)
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G2996
Global Mixed-mode Technology Inc.
Typical Performance Characteristics (continued)
AVIN=2.5V, PVIN=2.5V, VDDQ=2.5V, CAVIN=0.1µF, CPVIN=47µF, CVREF=0.01µF, VSD=2.5V, CVTT=220µF, TA=25°C,
unless otherwise noted.
IO=200m
Maximum Sinking Current vs AVIN
(VDDQ=2.5V)
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
22.533.544.555.5
AVIN(V)
Output Current(A)
Maximum Sourcing Current vs AVIN
(VDDQ=1.8V, PVIN=1.8V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
Output Current(A)
Maximum Sinking Current vs AVIN
(VDDQ=1.8V)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
Output Current(A)
Maximum Sourcing Current vs AVIN
(VDDQ=1.8V, PVIN=3.3V)
2
2.2
2.4
2.6
2.8
3
2 2.5 3 3.5 4 4.5 5 5.5
AVIN(V)
Output Current(A)
VOSVTT vs Temperature(VDDQ=2.5V)
-30
-20
-10
0
10
20
30
0 25 50 75 100 125
Temperature(°C)
VOSVTT(mV)
Sourcing 1.5A
No Load
Sinking 1.5A
Recommended Minimum Footprint
SOP-8, SOP-8 (FD)
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G2996
Global Mixed-mode Technology Inc.
Pin Description
NUMBER NAME FUNCTION
1 GND Ground
2 SD Active low shutdown control pin
3 VSENSE Feedback pin for regulating VTT
4 VREF Buffered output that is a reference output of VDDQ/2
5 VDDQ Power Input for internal reference
6 AVIN Analog input pin
7 PVIN Power input pin
8 VTT Output voltage for connection to termination resistors, equal to VDDQ/2
Block Diagram
Description
The G2996 is a linear bus termination regulator de-
signed to meet the JEDEC SSTL-2 and SSTL-3 (Se-
ries Stub Termination Logic) specifications for termina-
tion of DDR-SDRAM. The output, VTT, is capable of
sinking and sourcing current while regulating the out-
put voltage equal to VDDQ/2. The G2996 is designed
to maintain the excellent load regulation and with fast
response time to minimum the transition preventing
shoot-through. The G2996 also incorporates two dis-
tinct power rails that separates the analog circuitry
(AVIN) from the power output stage (PVIN). This
power rails split can be utilized to reduce the internal
power dissipation. And this also permits G2996 to pro-
vide a termination solution for the next generation of
DDR-SDRAM (DDR II).
Series Stub Termination Logic (SSTL) was created to
improve signal integrity of the data transmission
across the memory bus. This termination scheme is
essential to prevent data error from signal reflections
while transmitting at high frequencies encountered
with DDR-SDRAM. The most common form of termi-
nation is Class II single parallel termination. This in-
volves one RS series resistor from the chipset to the
memory and one RT termination resistor, both 25Ω
typically. The resistors can be changed to scale the
current requirements from the G2996. This implemen-
tation can be seen below in Figure 1.
AVIN, PVIN
AVIN and PVIN are two independent input supply pins
for the G2996. AVIN is used to supply all the internal
analog circuits. PVIN is only used to supply the output
stage to create the regulated VTT. To keep the regula-
tion successfully, AVIN should be equal to or larger
than PVIN. Using a higher PVIN voltage will produce a
larger sourcing capability from VTT. But the internal
power loss will also increase and then the heat in-
creases. If the junction temperature exceeds the
thermal shutdown threshold than the G2996 will enter
the shutdown state that is the same as manual shut-
down, where VTT is tri-state and VREF remains active.
For SSTL-2 applications, the AVIN and PVIN can be
short together at 2.5V to minimize the PCB complexity
and to reduce the bypassing capacitors for the two
supply pins separately.
+
-+
-
PVIN
AVIN
VDDQ
SD
50k
50k
GND
VREF
VSENSE
VTT
+
-
+
-+
-
+
-
PVIN
AVIN
VDDQ
SD
50k
50k
GND
VREF
VSENSE
VTT
VDD
CHIPSET RS
VTT
RTMENORY
VREF
Figure 1. SSTL-Termination Scheme
VDD
CHIPSET RS
VTT
RTMENORY
VREF
Figure 1. SSTL-Termination Scheme
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G2996
Global Mixed-mode Technology Inc.
VDDQ
A voltage divider of two 50kΩ is connected between
VDDQ and ground, to create the internal reference
voltage (VDDQ/2). This guarantees that VTT will track
VDDQ/2 precisely. The optimal implementation of
VDDQ is as a remote sensing. This can be achieved
by connecting VDDQ directly to the 2.5V rail (SSTL-2
applications) at the DIMM instead of AVIN and PVIN.
This will ensure that the reference voltage tracks the
DDR memory rails precisely without a large voltage
drop from the power lines.
Vsense
The VSENSE pin is the feedback sensing pin of the op-
eration amplifier which regulates the VTT voltage. In
most motherboard applications, the termination resis-
tors will connect VTT in a long plane. If using the re-
mote sensing pin – VSENSE to the middle of the bus, the
significant long-trace IR drop resulting in a termination
voltage which is lower at one end than the other can
be avoided. This will provide a better distribution
across the entire termination bus. If the remote load
regulation is not used, the VSENSE pin must still be
connected to VTT for correct regulation. Care should be
taken when a long VSENSE trace is implemented in
close proximity to the memory. Noise pickup in the
VSENSE trace can cause problems with precise regula-
tion of VTT. A small 0.1µF ceramic capacitor placed
next to the VSENSE pin can help to filter any high fre-
quency signals and preventing errors.
VREF
VREF provides a buffered output of the internal refer-
ence voltage (VDDQ/2). It can support the reference
voltage of Northbridge chipset and memory. This out-
put remains active during the shutdown state and
thermal shutdown events to support the suspend to
RAM (STR) functionality. For better performance, us-
ing an output bypass capacitor close this pin is more
helpful for the noise. A ceramic capacitor in the range
of 0.1µF to 0.01µF is recommended.
VTT
VTT is the regulated output that is used to terminate the
bus resistors of DDR-SDRAM. It can precisely track
the VDDQ/2 voltage with the sinking and sourcing
current capability. The G2996 is designed to deliver
1.5A continuous current and peak current up to 3A
with a fast transient response @ 2.5V supply rail. The
maximum continuous current sourcing from VTT is a
function of PVIN. Using a higher PVIN will increase the
source current from VTT, but it also increase the inter-
nal power dissipation and reduce the efficiency. Al-
though the G2996 can deliver the larger current, care
should be taken for the thermal dissipation when lar-
ger current is required. The G2996 is packaged with
Power-Pad to increase the power dissipation capability.
When driving larger current, the larger heat-sink in the
PCB is strongly recommended to have a better ther-
mal performance. The RDS of MOS will increase when
the junction temperature increases. If the heat is not
dealt with well, the maximum output current will be
degraded. When the temperature exceeds the junction
temperature, the thermal shutdown protection is acti-
vated. That will drive the VTT output into tri-state until
the temperature returns below the hysteretic trigger
point.
Capacitors
The G2996 does not require the capacitors for input
stability, but it is recommended for improving the per-
formance during large load transition to prevent the
input power rail from dropping, especially for PVIN.
The input capacitor for PVIN should be as close as
possible. The typical recommended value is 50µF for
AL electrolytic capacitors, 10µF with X5R for the ce-
ramic capacitors. To prevent the excessive noise cou-
pling into this device, an additional 0.1µF ceramic ca-
pacitor can be placed on the AVIN power rail for the
better performance.
The output capacitor of the G2996 is suggested to use
the capacitors with low ESR. Using the capacitors with
low ESR (as ceramic, OS-CON, tantalum) will have
the better transition performance which is with smaller
voltage drop when the peak current occurring at the
transition. As a general recommendation the output
capacitor should be sized above 220µF with the low
ESR for SSTL applications with DDR-SDRAM.
Thermal Dissipation
When the current is sinking to or sourcing from VTT,
the G2996 will generate internal power dissipation
resulting in the heat. Care should be taken to prevent
the device from damages caused by the junction tem-
perature exceeding the maximum rating. The maxi-
mum allowable internal temperature rise (TRMAX) can
be calculated under the given maximum ambient
temperature (TAMAX) of the application and the maxi-
mum allowable junction temperature (TJMAX).
TRMAX= TJMAX - TAMAX
From this equation, the maximum power dissipation
(PDMAX) of the G2996 can be calculated:
PDMAX = TRMAX /θJA
θJA of the G2996 will be dependent on several vari-
ables: the packages used, the thickness and size of
the copper, the number of vias and the airflow. In the
package, the G2996 use the SOP-8 with Power-PAD
to improve the θJA . If the layout of the PCB can put a
larger size of copper to contact the Power-PAD of this
device, the θJA will be further improved. The better θJA
is not only protecting the device well, but also increas-
ing the maximum current capability at the same ambi-
ent temperature.
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G2996
Global Mixed-mode Technology Inc.
Typical Application Circuits
There are several application circuits shown in Figure
2 through 8 to illustrate some of the possible configu-
rations of the G2996. Figure 2~4 are the SSTL-2 ap-
plications. For the majority of applications that imple-
ment the SSTL-2 termination scheme, it is recom-
mended to connect all the input rails to 2.5V rail, as
seen in Figure 2. This provides an optimal trade-off
between power dissipation and component count.
In Figure 3, the power rails are split. The power rail of
the output stage (PVIN) can be as low as 1.8V, the
power rail of the analog circuit (AVIN) is operated
above 2V. The lower output stage power rail can lower
the internal power dissipation when sourcing from the
device and improve the efficiency, but the disadvan-
tage is the maximum continuous current sourcing from
VTT is reduced. This configuration is applied when the
power dissipation and efficiency are concerned.
In Figure 4, the power rail of the output stage (PVIN) is
connected to 3.3V to increase the maximum continu-
ous current sourcing from VTT. AVIN should be always
equal to or larger than PVIN. This configuration can
increase the source capability of this device, but the
power dissipation increases at the same time. It
should be more careful to prevent the junction tem-
perature from exceeding the maximum rating. Be-
cause of this risk, it is not recommended to supply the
output stage power rail (PVIN) with a voltage higher
than a nominal 3.3V rail.
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=1.25V
VREF=1.25V
VDDQ=2.5V
VDD=2.5V
SD
CIN
Figure 2. Recommended SSTL-2 Implementation
COUT
CREF
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=1.25V
VREF=1.25V
VDDQ=2.5V
VDD=2.5V
SD
CIN
Figure 2. Recommended SSTL-2 Implementation
COUT
CREF
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=1.25V
VREF=1.25V
VDDQ=2.5V
AVIN=3.3V or 5V
SD
CIN
Figure 4. SSTL-2 Implementation with higher voltage rails
COUT
CREF
PVIN=3.3V
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=1.25V
VREF=1.25V
VDDQ=2.5V
AVIN=3.3V or 5V
SD
CIN
Figure 4. SSTL-2 Implementation with higher voltage rails
COUT
CREF
PVIN=3.3V
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=1.25V
VREF=1.25V
VDDQ=2.5V
AVIN=1.8V or 5.5V
SD
CIN
Figure 3. Lower Power Dissipation SSTL-2 Implementation
COUT
CREF
PVIN=1.8V
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=1.25V
VREF=1.25V
VDDQ=2.5V
AVIN=1.8V or 5.5V
SD
CIN
Figure 3. Lower Power Dissipation SSTL-2 Implementation
COUT
CREF
PVIN=1.8V
Ver: 2.3
May 16, 2006 TEL: 886-3-5788833
http://www.gmt.com.tw
11
G2996
Global Mixed-mode Technology Inc.
In Figure 5 & 6, they are the application configurations
of DDR-II SDRAM bus terminations. Figure 5 is the
typical application scheme of DDR-II SDRAM. With the
separate VDDQ pin and an internal resistor divider, it
is possible to use the G2996 in applications utilizing
DDR-II memory. Figure 6 is used to increase the driv-
ing capability. The risk is the same as figure 4.
Figure 7 & 8 are used to scale the VTT to the wanted
value when the standard voltages of SSTL-2 do not
meet the requirements. Using R1 & R2, figure 7 can
shift VTT up to VDDQ/2 * (1+R1/R2) and figure 8 can
shift VTT down to VDDQ/2 * (1-R1/R2).
+
+
VDDQ
AVIN
VSENSE
PVIN
VTT
GND
VTT
VDD
CIN
Figure 7. Increasing VTT by Level Shifting
COUT
VDDQ
R1
R2
+
+
VDDQ
AVIN
VSENSE
PVIN VTT
GND
VTT
VDD
CIN
Figure 8. Decre a si ng VTT by Lev el Shifting
COUT
VDDQ
R1
R2
+
+
VDDQ
AVIN
VSENSE
PVIN
VTT
GND
VTT
VDD
CIN
Figure 7. Increasing VTT by Level Shifting
COUT
VDDQ
R1
R2
+
+
VDDQ
AVIN
VSENSE
PVIN
VTT
GND
VTT
VDD
CIN
Figure 7. Increasing VTT by Level Shifting
COUT
VDDQ
R1
R2
+
+
VDDQ
AVIN
VSENSE
PVIN VTT
GND
VTT
VDD
CIN
Figure 8. Decre a si ng VTT by Lev el Shifting
COUT
VDDQ
R1
R2
+
+
VDDQ
AVIN
VSENSE
PVIN VTT
GND
VTT
VDD
CIN
Figure 8. Decre a si ng VTT by Lev el Shifting
COUT
VDDQ
R1
R2
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=0.9V
VREF=0.9V
VDDQ=1.8V
AVIN=1.8V or 5.5V
SD
CIN
Figure 5. Recommended DDR-II Termination
COUT
CREF
PVIN=1.8V
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=0.9V
VREF=0.9V
VDDQ=1.8V
AVIN=3.3V or 5.5V
SD
CIN
Figure 6. DDR-II Termination with higher voltage rails
COUT
CREF
PVIN=3.3V
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=0.9V
VREF=0.9V
VDDQ=1.8V
AVIN=1.8V or 5.5V
SD
CIN
Figure 5. Recommended DDR-II Termination
COUT
CREF
PVIN=1.8V
+
+
+
SD VREF
VDDQ
AVIN VSENSE
PVIN VTT
GND
VTT=0.9V
VREF=0.9V
VDDQ=1.8V
AVIN=3.3V or 5.5V
SD
CIN
Figure 6. DDR-II Termination with higher voltage rails
COUT
CREF
PVIN=3.3V
Ver: 2.3
May 16, 2006 TEL: 886-3-5788833
http://www.gmt.com.tw
12
G2996
Global Mixed-mode Technology Inc.
Package Information
SOP-8 Package
Note:
1. Package body sizes exclude mold flash and gate burrs
2. Dimension L is measured in gage plane
3. Tolerance 0.10mm unless otherwise specified
4. Controlling dimension is millimeter conver t ed inch dim ensions ar e not necessarily exact .
5. Followed from JEDEC MS-012
DIMENSION IN MM DIMENSION IN INCH
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX.
A 1.35 1.60 1.75 0.053 0.063 0.069
A1 0.10 ----- 0.25 0.004 ----- 0.010
A2 ----- 1.45 ----- ----- 0.057 -----
B 0.33 ----- 0.51 0.013 ----- 0.020
C 0.19 ----- 0.25 0.007 ----- 0.010
D 4.80 ----- 5.00 0.189 ----- 0.197
E 3.80 ----- 4.00 0.150 ----- 0.157
e ----- 1.27 ----- ----- 0.050 -----
H 5.80 ----- 6.20 0.228 ----- 0.244
L 0.40 ----- 1.27 0.016 ----- 0.050
y ----- ----- 0.10 ----- ----- 0.004
θ 0° ----- 8° 0° ----- 8°
D
EH
7 °(4X)
A1
A2 A
e
B
y
C
L
θ
D
EH
7 °(4X)
A1
A2 A
e
B
y
C
L
θ
Ver: 2.3
May 16, 2006 TEL: 886-3-5788833
http://www.gmt.com.tw
13
G2996
Global Mixed-mode Technology Inc.
SOP- 8 (FD) Package
Note:
1. Package body sizes exclude mold flash and gate burrs
2. Dimension L is measured in gage plane
3. Tolerance 0.10mm unless otherwise specified
4. Controlling dimension is millimeter conver t ed inch dim ensions ar e not necessar ily exact.
5. Followed from JEDEC MS-012
DIMENSION IN MM DIMENSION IN INCH
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX.
A 1.45 1.50 1.55 0.057 0.059 0.061
A1 0.00 ----- 0.10 0.000 ----- 0.004
A2 ----- 1.45 ----- ----- 0.057 -----
B 0.33 ----- 0.51 0.013 ----- 0.020
C 0.19 ----- 0.25 0.007 ----- 0.010
D 4.80 ----- 5.00 0.189 ----- 0.197
E 3.80 ----- 4.00 0.150 ----- 0.157
e ----- 1.27 ----- ----- 0.050 -----
H 5.80 ----- 6.20 0.228 ----- 0.244
L 0.40 ----- 1.27 0.016 ----- 0.050
y ----- ----- 0.10 ----- ----- 0.004
θ 0° ----- 8° 0° ----- 8°
D1 2.22 ----- 2.60 0.087 ----- 0.102
E1 2.60 ----- 2.98 0.102 ----- 0.117
Taping Specification
PACKAGE Q’TY/REEL
SOP-8 2,500 ea
SOP-8 (FD) 2,500 ea
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
Feed Direction
Typical SO P Package O rientation
Feed Direction
Typical SO P Package O rientation
D
EH
7 °(4X)
A1
A2 A
e
B
y
C
L
θ
E1
D1
D
EH
7 °(4X)
A1
A2 A
e
B
y
C
L
θ
E1
D1
