TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 D High-Performance Fixed-Point Digital D D D D D Signal Processor (DSP) - TMS320C6203 - 4-, 3.33-ns Instruction Cycle Time - 250-, 300-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - 2 000, 2 400 MIPS C6203 and C6202/02B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package VelociTI Advanced Very-Long-InstructionWord (VLIW) TMS320C62x DSP Core - Eight Highly Independent Functional Units: - Six ALUs (32-/40-Bit) - Two 16-Bit Multipliers (32-Bit Result) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization 7M-Bit On-Chip SRAM - 3M-Bit Internal Program/Cache (96K 32-Bit Instructions) - 4M-Bit Dual-Access Internal Data (512K Bytes) - Organized as Two 256K-Byte Blocks for Improved Concurrency 32-Bit External Memory Interface (EMIF) - Glueless Interface to Synchronous Memories: SDRAM or SBSRAM - Glueless Interface to Asynchronous Memories: SRAM and EPROM - 52M-Byte Addressable External Memory Space D Four-Channel Bootloading D D D D D D D D D Direct-Memory-Access (DMA) Controller With an Auxiliary Channel Flexible Phase-Locked-Loop (PLL) Clock Generator 32-Bit Expansion Bus (XBus) - Glueless/Low-Glue Interface to Popular PCI Bridge Chips - Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses - Master/Slave Functionality - Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals Three Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial-Peripheral Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 352-Pin BGA Package (GJL) 384-Pin BGA Package (GLS) 0.15-m/5-Level Metal Process - CMOS Technology 3.3-V I/Os, 1.5-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI and TMS320C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. For more details, see the GLS BGA package bottom view. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Table of Contents GJL and GLS BGA packages (bottom view) . . . . . . . . . . . 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 C62x device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional and CPU (DSP core) block diagram . . . . . . . . . 7 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . 8 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 2 14 25 28 29 31 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 37 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 40 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 42 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 49 expansion bus synchronous FIFO timing . . . . . . . . . . . . 50 expansion bus asynchronous peripheral timing . . . . . . 52 expansion bus synchronous host-port timing . . . . . . . . 55 expansion bus asynchronous host-port timing . . . . . . . 61 XHOLD/XHOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 63 32 32 multichannel buffered serial port timing . . . . . . . . . . . . . 65 32 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 parameter measurement information . . . . . . . . . . . . . . . . 33 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 POST OFFICE BOX 1443 DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 77 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 GJL and GLS BGA packages (bottom view) GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 GLS 384-PIN BGA PACKAGE ( BOTTOM VIEW ) AB AA Y W V U T R P N M L K J H G F E D C B A 1 7 3 5 9 11 13 15 17 19 21 2 6 8 4 10 12 14 16 18 20 22 The C6203 and C6202/02B GLS BGA packages are pin-compatible with the C6204 GLW package except that the inner row of balls (which are additional power and ground pins) are removed for the C6204 GLW package. These balls are NOT applicable for the C6204 devices 340-pin GLW BGA package. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 description The TMS320C62x DSPs (including the TMS320C6203 device) compose the fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6203 (C6203) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C6203 offers cost-effective solutions to high-performance DSP-programming challenges. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 600 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The TMS320C62x DSPs include an on-chip memory, with the C6203 device offering the most memory at 7 Mbits. The C6203 device program memory consists of two blocks, with a 256K-byte block configured as memory-mapped program space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256K-byte blocks of RAM. The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XBus) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The C62x devices have a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the TMS320C6203, TMS320C6202/02B, and the TMS320C6204 pin-compatible C62x DSPs. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. This data sheet primarily focuses on the functionality of the TMS320C6203 device although it also identifies to the user the pin-compatibility of the C6203 and C6202/02B GLS, and the C6204 GLW BGA packages. For the functionality information on the TMS320C6202/02B devices, see the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors data sheet (literature number SPRS104). For the functionality information on the TMS320C6204 device, see the TMS320C6204 Fixed-Point Digital Signal Processor data sheet (literature number SPRS152). And for more details on the C6000 DSP part numbering, see Figure 4. TMS320C6000, C62x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. 4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 device characteristics (continued) Table 1. Characteristics of the Pin-Compatible TMS320C6203, TMS320C6202/02B, and TMS320C6204 DSPs HARDWARE FEATURES C6203 C6202 C6202B EMIF DMA 4-Channel With Throughput Enhancements 4-Channel 4-Channel With Throughput Enhancements 4-Channel With Throughput Enhancements Peripherals Expansion Bus McBSPs 3 3 3 2 32-Bit Timers 2 2 2 2 256K 256K 64K Block 0: 128K-Byte Mapped Program Block 1: 128K-Byte Cache/Mapped Program Block 0: 128K-Byte Mapped Program Block 1: 128K-Byte Cache/Mapped Program Size (Bytes) Internal Program Memory Organization Size (Bytes) Internal Data Memory Organization CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) Frequency MHz Cycle Time ns Core (V) Voltage PLL Options BGA Packages C6204 I/O (V) CLKIN frequency multiplier [Bypass (x1), x4, x6, x7, x8, x9, x10, and x11] 384K Block 0: 256K-Byte Mapped Program Block 1: 128K-Byte Cache/Mapped Program 512K 128K 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 0x0003 250, 300 3.33 ns (C6203-300) 4 ns (C6203-250) 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 128K 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 1 Block: 64K-Byte Cache/Mapped Program 64K 2 Blocks: Four 16-Bit Banks per Block 50/50 Split 0x0002 0x0003 0x0003 200, 250 250 200 4 ns (C6202-250) 5 ns (C6202-200) 1.5 1.8 3.3 3.3 x1, x4, x8, x10 (GJL Pkg) 4 ns (C6202B-250) 5 ns (C6204-200) 1.5 1.5 3.3 3.3 x1, x4, x8, x10 (GJL Pkg) x1, x4 (Both Pkgs) All PLL Options (GLS Pkg) x1, x4 (Both Pkgs) All PLL Options (GLS Pkg) 27 x 27 mm 352-pin GJL 352-pin GJL 352-pin GJL - 18 x 18 mm 384-pin GLS 384-pin GLS 384-pin GLS 340-pin GLW 16 x 16 mm - - - 288-pin GHK 0.15 m 0.18 m 0.15 m 0.15 m PD PD PP PP Process Technology m Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 C62x device compatibility The TMS320C6202, C6202B, C6203, and C6204 devices are pin-compatible; thus, making new system designs easier and providing faster time to market. The following list summarizes the C62x DSP device characteristic differences: D Core Supply Voltage (1.8 V versus 1.5 V) The C6202 device core supply voltage is 1.8 V while the C6202B, C6203, C6204 devices have core supply voltages of 1.5 V. D PLL Options Availability Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4, etc.] for each of the C62x DSP devices. For additional details on the PLL clock module and specific options for the C6203 device, see the Clock PLL section of this data sheet. For additional details on the PLL clock module and specific options for the C6202/02B devices, see the Clock PLL section of the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors data sheet (literature number SPRS104). And for additional details on the PLL clock module and specific options for the C6204 device, see the Clock PLL section of the TMS320C6204 Fixed-Point Digital Signal Processor data sheet (literature number SPRS152). D On-Chip Memory Size The C6202/02B, C6203, and C6204 devices have different on-chip program memory and data memory sizes (see Table 1). D McBSPs The C6202, C6202B, and C6203 devices have three McBSPs while the C6204 device has two McBSPs on-chip. For a more detailed discussion on migration concerns, and similarities/differences between the C6202, C6202B, C6203, and C6204 devices, see the How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603). 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 functional and CPU (DSP core) block diagram C6203 Digital Signal Processor SDRAM or SBSRAM Program Access/Cache Controller 32 SRAM External Memory Interface (EMIF) ROM/FLASH Internal Program Memory 2 Blocks Program/Cache (384K Bytes) I/O Devices C62x CPU (DSP Core) Timer 0 Instruction Fetch Timer 1 Data Path A I/O Devices HOST CONNECTION Master /Slave TI PCI2040 Power PC 683xx 960 Data Path B A Register File Multichannel Buffered Serial Port 1 .L1 .S1 .M1 .D1 Test B Register File .D2 .M2 .S2 In-Circuit Emulation .L2 Multichannel Buffered Serial Port 2 DMA Bus Interrupt Selector Synchronous FIFOs Control Logic Instruction Decode Multichannel Buffered Serial Port 0 Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Control Registers Instruction Dispatch Peripheral Control Bus Interrupt Control Internal Data Memory (512K Bytes) Data Access Controller 32 Expansion Bus (XBus) 32-Bit Direct Memory Access Controller (DMA) (See Table 1) PLL (x1, x4, x6, x7, x8, x9, x10, x11) POST OFFICE BOX 1443 PowerDown Logic Boot Configuration * HOUSTON, TEXAS 77251-1443 7 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 CPU (DSP core) description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the 256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 CPU (DSP core) description (continued) AAAAA AAAA AAAAA AAAA AAAAA A AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAA AAAAA A A AAAA AAAA AAAAA A A AAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAA AAAA A AAAAA AAAAA AAAA AAAAA AAAAA AAAAA A A src1 src2 .L1 dst long dst long src ST1 Data Path A long src long dst dst .S1 src1 32 8 dst src1 LD1 DA1 DA2 .D2 dst src1 src2 2X 1X src2 src1 dst A A A A LD2 src2 .M2 src1 dst src2 Data Path B src1 .S2 dst long dst long src ST2 long src long dst dst .L2 src2 src1 Register File A (A0-A15) A A A A src2 .D1 8 8 src2 .M1 AAAAAA AAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAAAA AAAAAA AAAAAA AAAAAAAA AAAAAA AAAAAA AAAAAAAA AAAAAAAA AAAAAA AAAAAA AAAAAA AA Register File B (B0-B15) 8 32 8 A A A A 8 Control Register File Figure 1. TMS320C62x CPU (DSP Core) Data Paths POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 memory map summary Table 2 shows the memory map address ranges of the C6203 device. The C6203 device has the capability of a MAP 0 or MAP 1 memory block configuration. These memory block configurations are set up at reset by the boot configuration pins (generically called BOOTMODE[4:0]). For the C6203 device, the BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically XD[4:0] pins). For more detailed information on the C6203 device settings, which include the device boot mode configuration at reset and other device-specific configurations, see the Boot Configuration section and the Boot Configuration Summary table of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 2. TMS320C6203 Memory Map Summary MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE MAP 1 External Memory Interface (EMIF) CE0 Internal Program RAM 384K 0000_0000 - 0005_FFFF EMIF CE0 Reserved 4M - 384K 0006_0000 - 003F_FFFF EMIF CE0 EMIF CE0 12M 0040_0000 - 00FF_FFFF EMIF CE1 EMIF CE0 4M 0100_0000 - 013F_FFFF Internal Program RAM EMIF CE1 384K 0140_0000 - 0145_FFFF EMIF CE1 Reserved 10 BLOCK SIZE (BYTES) MAP 0 4M - 384K 0146_0000 - 017F_FFFF EMIF Registers 256K 0180_0000 - 0183_FFFF DMA Controller Registers 256K 0184_0000 - 0187_FFFF Expansion Bus (XBus) Registers 256K 0188_0000 - 018B_FFFF McBSP 0 Registers 256K 018C_0000 - 018F_FFFF McBSP 1 Registers 256K 0190_0000 - 0193_FFFF Timer 0 Registers 256K 0194_0000 - 0197_FFFF Timer 1 Registers 256K 0198_0000 - 019B_FFFF Interrupt Selector Registers 512 019C_0000 - 019C_01FF Power-Down Registers 256K - 512 019C_0200 - 019F_FFFF Reserved 256K 01A0_0000 - 01A3_FFFF McBSP 2 Registers 256K 01A4_0000 - 01A7_FFFF Reserved 5.5M 01A8_0000 - 01FF_FFFF EMIF CE2 16M 0200_0000 - 02FF_FFFF EMIF CE3 16M 0300_0000 - 03FF_FFFF Reserved 1G - 64M 0400_0000 - 3FFF_FFFF XBus XCE0 256M 4000_0000 - 4FFF_FFFF XBus XCE1 256M 5000_0000 - 5FFF_FFFF XBus XCE2 256M 6000_0000 - 6FFF_FFFF XBus XCE3 256M 7000_0000 - 7FFF_FFFF Internal Data RAM 512K 8000_0000 - 8007_FFFF Reserved 2G - 512K 8008_0000 - FFFF_FFFF POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE0 CLKMODE1 CLKMODE2 PLLV PLLG PLLF Clock/PLL Reset and Interrupts TMS TDO TDI TCK TRST EMU1 EMU0 IEEE Standard 1149.1 (JTAG) Emulation RSV4 RSV3 RSV2 RSV1 RSV0 Reserved RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Control/Status CLKMODE2 is NOT available on the GJL package for the C6203 device. Figure 2. CPU (DSP Core) Signals POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 signal groups description (continued) Asynchronous Memory Control 32 ED[31:0] Data CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 TOUT1 TINP1 Memory Map Space Select 20 Synchronous Memory Control Word Address HOLD/ HOLDA Byte Enables ARE AOE AWE ARDY SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE HOLD HOLDA EMIF (External Memory Interface) Timer 1 Timer 0 TOUT0 TINP0 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Receive Receive CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSP2 Transmit CLKX2 FSX2 DX2 Receive CLKR2 FSR2 DR2 Clock CLKS2 McBSPs (Multichannel Buffered Serial Ports) Figure 3. Peripheral Signals 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 signal groups description (continued) 32 XD[31:0] XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 XRDY Data Clocks Byte-Enable Control/ Address Control I/O Port Control XHOLD XHOLDA XCLKIN XFCLK XOE XRE XWE/XWAIT XCE3 XCE2 XCE1 XCE0 Arbitration Expansion Bus Host Interface Control XCS XAS XCNTL XW/R XBLAST XBOFF Figure 3. Peripheral Signals (Continued) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION CLOCK/PLL CLKIN C12 B10 I Clock Input CLKOUT1 AD20 Y18 O Clock output at full device speed CLKOUT2 AC19 AB19 O Clock output at half of device speed * Used for synchronous memory interface CLKMODE0 B15 B12 I CLKMODE1 C11 A9 I CLKMODE2 - A14 I D13 C11 C12 A A PLL analog VCC connection for the low-pass filter D14 A11 A PLL low-pass filter connection to external components and a bypass capacitor PLLV PLLG PLLF C13 Clock mode selects * Selects what multiply factors of the input clock frequency the CPU frequency equals. For more details on the GJL and GLS CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL analog GND connection for the low-pass filter JTAG EMULATION TMS AD7 Y5 I TDO AE6 AA4 O/Z JTAG test-port mode select (features an internal pullup) TDI AF5 Y4 I JTAG test-port data in (features an internal pullup) TCK AE5 AB2 I JTAG test-port clock TRST AC7 AA3 I JTAG test-port reset (features an internal pulldown) EMU1 AF6 AA5 I/O/Z EMU0 AC8 AB4 I/O/Z JTAG test-port data out Emulation pin 1, pullup with a dedicated 20-k resistor Emulation pin 0, pullup with a dedicated 20-k resistor RESET AND INTERRUPTS RESET K2 J3 I Device reset NMI L2 K2 I Nonmaskable interrupt * Edge-driven (rising edge) EXT_INT7 V4 U2 EXT_INT6 Y2 U3 I External interrupts * Edge-driven * Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) O Interrupt acknowledge for all active interrupts serviced by the CPU O Active interrupt identification number * Valid during IACK for all active interrupts (not just external) * Encoding order follows the interrupt-service fetch-packet ordering EXT_INT5 AA1 W1 EXT_INT4 W4 V2 IACK Y1 V1 INUM3 V2 R3 INUM2 U4 T1 INUM1 V3 T2 INUM0 W2 T3 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. A = Analog Signal (PLL Filter) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-k resistor. 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION POWER-DOWN STATUS PD AB2 Y2 O Power-down modes 2 or 3 (active if high) A9 C8 I Expansion bus synchronous host interface clock input O Expansion bus FIFO interface clock output EXPANSION BUS XCLKIN XFCLK B9 A8 XD31 D15 C13 XD30 B16 A13 XD29 A17 C14 XD28 B17 B14 XD27 D16 B15 XD26 A18 C15 XD25 B18 A15 XD24 D17 B16 XD23 C18 C16 XD22 A20 A17 XD21 D18 B17 XD20 C19 C17 XD19 A21 B18 XD18 D19 A19 XD17 C20 C18 XD16 B21 B19 XD15 A22 C19 XD14 D20 B20 XD13 B22 A21 XD12 E25 C21 XD11 F24 D20 XD10 E26 B22 XD9 F25 D21 XD8 G24 E20 XD7 H23 E21 XD6 F26 D22 XD5 G25 F20 XD4 J23 F21 XD3 G26 E22 XD2 H25 G20 XD1 J24 G21 Expansion bus data * Used for transfer of data, address, and control * Also controls initialization of DSP modes and expansion bus at reset via pullup/ pulldown resistors (Note: Reserved boot configuration fields should be pulled down.) I/O/Z XD[30:16]- XD13 - XD12 - XD11 - XD10 - XD9 - XD8 - XD[4:0] - XCE[3:0] memory type XBLAST polarity XW/R polarity Asynchronous or synchronous host operation Arbitration mode (internal or external) FIFO mode Little endian/big endian Boot mode XD0 K23 G22 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL TYPE GLS DESCRIPTION EXPANSION BUS (CONTINUED) XCE3 F2 D2 XCE2 E1 B1 XCE1 F3 D3 XCE0 E2 C2 XBE3/XA5 C7 C5 XBE2/XA4 D8 A4 O/Z Expansion bus I/O port memory space enables * Enabled by bits 28, 29, and 30 of the word address * Only one asserted during any I/O port data access I/O/Z Expansion bus multiplexed byte-enable control/address signals * Act as byte-enable for host-port operation * Act as address for I/O port operation XBE1/XA3 A6 B5 XBE0/XA2 C8 C6 XOE A7 A6 O/Z Expansion bus I/O port output-enable XRE C9 C7 O/Z Expansion bus I/O port read-enable XWE/XWAIT D10 B7 O/Z Expansion bus I/O port write-enable and host-port wait signals XCS A10 C9 I XAS D9 B6 I/O/Z XCNTL B10 B9 I XW/R D11 B8 I/O/Z Expansion bus host-port write/read-enable. XW/R polarity is selected at reset. XRDY A5 C4 I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high) Expansion bus host-port burst last-polarity selected at reset Expansion bus host-port chip-select input Expansion bus host-port address strobe Expansion bus host control. XCNTL selects between expansion bus address or data register. XBLAST B6 B4 I/O/Z XBOFF B11 A10 I XHOLD B5 A2 I/O/Z Expansion bus hold request XHOLDA D7 B3 I/O/Z Expansion bus hold acknowledge Expansion bus back off EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AB25 Y21 CE2 AA24 W20 CE1 AB26 AA22 CE0 AA25 W21 BE3 Y24 V20 BE2 W23 V21 BE1 AA26 W22 O/Z Memory space enables * Enabled by bits 24 and 25 of the word address * Only one asserted during any external data access O/Z Byte-enable control * Decoded from the two lowest bits of the internal address * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) BE0 Y25 U20 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION EMIF - ADDRESS EA21 J25 H20 EA20 J26 H21 EA19 L23 H22 EA18 K25 J20 EA17 L24 J21 EA16 L25 K21 EA15 M23 K20 EA14 M24 K22 EA13 M25 L21 EA12 N23 L20 EA11 P24 L22 EA10 P23 M20 EA9 R25 M21 EA8 R24 N22 EA7 R23 N20 EA6 T25 N21 EA5 T24 P21 EA4 U25 P20 EA3 T23 R22 EA2 V26 R21 ED31 AD8 Y6 ED30 AC9 AA6 ED29 AF7 AB6 ED28 AD9 Y7 ED27 AC10 AA7 ED26 AE9 AB8 ED25 AF9 Y8 ED24 AC11 AA8 ED23 AE10 AA9 ED22 AD11 Y9 ED21 AE11 AB10 ED20 AC12 Y10 ED19 AD12 AA10 ED18 AE12 AA11 ED17 AC13 Y11 ED16 AD14 AB12 ED15 AC14 Y12 O/Z External address (word address) EMIF - DATA I/O/Z External data ED14 AE15 AA12 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION EMIF - DATA (CONTINUED) ED13 AD15 ED12 AC15 AA13 Y13 ED11 AE16 AB13 ED10 AD16 Y14 ED9 AE17 AA14 ED8 AC16 AA15 ED7 AF18 Y15 ED6 AE18 AB15 ED5 AC17 AA16 ED4 AD18 Y16 ED3 AF20 AB17 ED2 AC18 AA17 ED1 AD19 Y17 ED0 AF21 AA18 ARE V24 T21 O/Z Asynchronous memory read-enable AOE V25 R20 O/Z Asynchronous memory output-enable AWE U23 T22 O/Z Asynchronous memory write-enable ARDY W25 T20 I Asynchronous memory ready input I/O/Z External data EMIF - ASYNCHRONOUS MEMORY CONTROL EMIF - SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SDA10 AE21 AA19 O/Z SDRAM address 10 (separate for deactivate command) SDCAS/SSADS AE22 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe SDRAS/SSOE AF22 Y19 O/Z SDRAM row-address strobe/SBSRAM output-enable SDWE/SSWE AC20 AA20 O/Z SDRAM write-enable/SBSRAM write-enable EMIF - BUS ARBITRATION HOLD Y26 V22 I Hold request from the host HOLDA V23 U21 O Hold-request-acknowledge to the host TOUT0 F1 D1 O Timer 0 or general-purpose output TINP0 H4 E2 I Timer 0 or general-purpose input TOUT1 J4 F2 O Timer 1 or general-purpose output TINP1 G2 F3 I Timer 1 or general-purpose input DMAC3 Y3 V3 DMAC2 AA2 W2 DMAC1 AB1 AA1 TIMER 0 TIMER 1 DMA ACTION COMPLETE STATUS O DMA action complete DMAC0 AA3 W3 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 M4 K3 I CLKR0 M2 L2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX0 M3 K1 I/O/Z Transmit clock DR0 R2 M2 I Receive data DX0 P4 M3 O/Z Transmit data FSR0 N3 M1 I/O/Z Receive frame sync FSX0 N4 L3 I/O/Z Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 G1 E1 I CLKR1 J3 G2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX1 H2 G3 I/O/Z Transmit clock DR1 L4 H1 I Receive data DX1 J1 H2 O/Z Transmit data FSR1 J2 H3 I/O/Z Receive frame sync FSX1 K4 G1 I/O/Z Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) CLKS2 R3 N1 I CLKR2 T2 N2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX2 R4 N3 I/O/Z Transmit clock DR2 V1 R2 I Receive data DX2 T4 R1 O/Z Transmit data FSR2 U2 P3 I/O/Z Receive frame sync FSX2 T3 P2 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 L3 J2 I Reserved for testing, pullup with a dedicated 20-k resistor RSV1 G3 E3 I Reserved for testing, pullup with a dedicated 20-k resistor RSV2 A12 B11 I Reserved for testing, pullup with a dedicated 20-k resistor RSV3 C15 B13 O Reserved (leave unconnected, do not connect to power or ground) RSV4 D12 C10 O Reserved (leave unconnected, do not connect to power or ground) I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION SUPPLY VOLTAGE PINS A11 DVDD A3 A16 A7 B7 A16 B8 A20 B19 D4 B20 D6 C6 D7 C10 D9 C14 D10 C17 D13 C21 D14 G4 D16 G23 D17 H3 D19 H24 F1 K3 F4 K24 F19 L1 F22 L26 G4 N24 G19 P3 J4 T1 J19 T26 K4 U3 K19 U24 L1 W3 M22 W24 N4 Y4 N19 Y23 P4 AD6 P19 AD10 T4 AD13 T19 AD17 U1 AD21 U4 AE7 U19 AE8 U22 AE19 W4 AE20 W6 S 3.3-V supply voltage (I/O) AF11 W7 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) DVDD CVDD AF16 W9 - W10 - W13 - W14 - W16 - W17 - W19 - AB5 - AB9 - AB14 - AB18 A1 E7 A2 E8 A3 E10 A24 E11 A25 E12 A26 E13 B1 E15 B2 E16 B3 F7 B24 F8 B25 F9 B26 F11 C1 F12 C2 F14 C3 F15 C4 F16 C23 G5 C24 G6 C25 G17 C26 G18 D3 H5 D4 H6 D5 H17 D22 H18 D23 J6 D24 J17 E4 K5 E23 K18 S 3.3-V supply voltage (I/O) S 1.5-V supply voltage (core) AB4 L5 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) CVDD AB23 L6 AC3 L17 AC4 L18 AC5 M5 AC22 M6 AC23 M17 AC24 M18 AD1 N5 AD2 N18 AD3 P6 AD4 P17 AD23 R5 AD24 R6 AD25 R17 AD26 R18 AE1 T5 AE2 T6 AE3 T17 AE24 T18 AE25 U7 AE26 U8 AF1 U9 AF2 U11 AF3 U12 AF24 U14 AF25 U15 AF26 U16 - V7 - V8 - V10 - V11 - V12 - V13 - V15 - V16 S 1.5-V supply voltage (core) GROUND PINS A4 VSS A1 A8 A5 A13 A12 GND Ground pins A14 A18 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 22 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION GROUND PINS (CONTINUED) A15 VSS A22 A19 B2 A23 B21 B4 C1 B12 C3 B13 C20 B14 C22 B23 D5 C5 D8 C16 D11 C22 D12 D1 D15 D2 D18 D6 E4 D21 E5 D25 E6 D26 E9 E3 E14 E24 E17 F4 E18 F23 E19 H1 F5 H26 F6 K1 F10 K26 F13 M1 F17 M26 F18 N1 H4 N2 H19 N25 J1 N26 J5 P1 J18 P2 J22 P25 K6 P26 K17 GND Ground pins R1 L4 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 23 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION GROUND PINS (CONTINUED) R26 VSS L19 U1 M4 U26 M19 W1 N6 W26 N17 AA4 P1 AA23 P5 AB3 P18 AB24 P22 AC1 R4 AC2 R19 AC6 U5 AC21 U6 AC25 U10 AC26 U13 AD5 U17 AD22 U18 AE4 V4 AE13 V5 AE14 V6 AE23 V9 AF4 V14 AF8 V17 AF10 V18 AF12 V19 AF13 W5 AF14 W8 AF15 W11 AF17 W12 AF19 W15 AF23 W18 - Y1 - Y3 - Y20 - Y22 - AA2 GND Ground pins - AA21 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 24 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS TYPE DESCRIPTION GROUND PINS (CONTINUED) VSS - AB1 - AB3 - AB7 - AB11 - AB16 - AB20 GND Ground pins - AB22 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE) including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 DSP family member devices, including documentation. See this document for further information on TMS320 DSP documentation or any TMS320 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies in the industry. To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select "Find Development Tools". For device-specific tools, under "Semiconductor Products" select "Digital Signal Processors", choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 25 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GJL), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -300 is 300 MHz). Figure 4 provides a legend for reading the complete device name for any TMS320C6000 DSP family member. For the C6203 device orderable part numbers (P/Ns), see the Texas Instruments web site on the Worldwide web at http://www.ti.com URL, or contact the nearest TI field sales office, or authorized distributor. 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 device and development-support tool nomenclature (continued) TMS 320 C 6203 PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535) GLS ( ) 300 DEVICE SPEED RANGE 100 MHz 120 MHz 150 MHz 167 MHz DEVICE FAMILY 320 = TMS320t DSP family TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE GFN = 256-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt TECHNOLOGY C = CMOS DEVICE C6000 DSP: 6201 6202 6202B 6203 BGA = 200 MHz 233 MHz 250 MHz 300 MHz 6204 6205 6211 6211B 6414 6415 6416 6701 6711 6712 Ball Grid Array Figure 4. TMS320C6000 DSP Platform Device Nomenclature (Including TMS320C6203) MicroStar BGA is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 documentation support Extensive documentation supports all TMS320 DSP family devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XBus), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603) describes the migration concerns and identifies the similarities and differences between the C6202, C6202B, C6203, and C6204 C6000 DSP devices. The tools support documentation is electronically available within the Code Composer Studio IDE. For a complete listing of the latest C6000 DSP documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). C67x is a trademark of Texas Instruments. 28 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 clock PLL All of the internal C6203 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5, and Table 4 through Table 6 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the C6203 device and the external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Table 3 lists some examples of compatible CLKIN external clock sources: Table 3. Compatible CLKIN External Clock Sources COMPATIBLE PARTS FOR EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER MANUFACTURER JITO-2 Fox Electronix STA series, ST4100 series SaRonix Corporation SG-636 Epson America 342 Corning Frequency Control MK1711-S, ICS525-02 Integrated Circuit Systems Oscillators PLL 3.3V EMI Filter PLLV C3 10 mF C4 0.1 mF Internal to C6203 PLL CLKMODE0 CLKMODE1 CLKMODE2 PLLMULT PLLCLK CLKIN CLKIN 1 LOOP FILTER (For the PLL Options and CLKMODE pins setup, see Table 4 through Table 6) C2 C1 CPU CLOCK PLLG PLLF 0 R1 The CLKMODE2 pin is N/A on the C6203 GJL package. NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 clock PLL (continued) 3.3V PLLV CLKMODE0 CLKMODE1 CLKMODE2 PLL PLLMULT Internal to C6203 PLLCLK CLKIN CLKIN LOOP FILTER 1 CPU CLOCK PLLF PLLG 0 The CLKMODE2 pin is N/A on the C6203 GJL package. NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG. B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only Table 4. TMS320C6203 GLS Packages PLL Multiply and Bypass (x1) Options GLS PACKAGE - 18 x 18 mm BGA BIT (PIN NO.) CLKMODE2 (A14) CLKMODE1 (A9) CLKMODE0 (B12) DEVICES AND PLL CLOCK OPTIONS 0 0 0 Bypass (x1) 0 0 1 x4 0 1 0 x8 0 1 1 x10 1 0 0 x6 1 0 1 x9 1 1 0 x7 1 1 1 x11 Value f(CPU Clock) = f(CLKIN) x (PLL mode) Table 5. TMS320C6203 GJL Package PLL Multiply and Bypass (x1) Options GJL PACKAGE 27 x 27 mm BGA BIT (PIN NO.) Value CLKMODE2 (N/A) CLKMODE1 (C11) CLKMODE0 (B15) DEVICES AND PLL CLOCK OPTIONS 0 0 Bypass (x1) 0 1 x4 1 0 x8 1 x10 N/A 1 f(CPU Clock) = f(CLKIN) x (PLL mode) The CLKMODE2 pin is not available (N/A) on the C6203 GJL package. 30 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 clock PLL (continued) Table 6. TMS320C6203 PLL Component Selection Table CLKMODE CLKIN RANGE (MHz) x4 32.5-75 x6 21.7-50 x7 18.6-42.9 x8 16.3-37.5 x9 14.4-33.3 x10 13-30 x11 11.8-27.3 CPU CLOCK FREQUENCY RANGE (MHz) CLKOUT2 RANGE (MHz) R1 [1%] (Revision No.) C1 [10%] (Revision No.) C2 [10%] (Revision No.) TYPICAL LOCK TIME (s) 130-300 65-150 60.4 (1.x) 45.3 (2.x) 27 nF (1.x) 47 nF (2.x) 560 pF (1.x) 10 pF (2.x) 75 Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS device. The GJL device is restricted to x1, x4, x8, and x10 multiply factors. power-supply sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 absolute maximum ratings over operating case temperature ranges (unless otherwise noted) Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating case temperature ranges, TC:(default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40_C to105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C Temperature cycle range, (1000-cycle performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40_C to 125_C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT 1.43 1.5 1.57 V CVDD Supply voltage, Core Supply voltage, Core 1.65 1.7 1.75 V DVDD Supply voltage, I/O 3.14 3.3 3.46 V VSS VIH Supply ground 0 0 0 V High-level input voltage 2 VIL IOH Low-level input voltage 0.8 V High-level output current -8 mA IOL Low-level output current 8 mA 90 _C Default TC V 0 Operating case temperature A version -40 105 _C Supply voltage, Core for the C6203 1.7 V devices which are identified in the orderable part number with a "17" following the device number and the package type ids. electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER VOH VOL II IOZ IDD2V IDD2V IDD3V Ci TEST CONDITIONS High-level output voltage DVDD = MIN, Low-level output voltage Input current DVDD = MIN, IOH = MAX IOL = MAX MIN TYP MAX 2.4 UNIT V 0.6 V 10 uA 10 uA Off-state output current VI = VSS to DVDD VO = DVDD or 0 V Supply current, CPU + CPU memory access CVDD = NOM, CPU clock = 200 MHz 340 mA Supply current, peripherals Supply current, I/O pins CVDD = NOM, CPU clock = 200 MHz 235 mA DVDD = NOM, CPU clock = 200 MHz 45 Input capacitance mA 10 pF Co Output capacitance 10 pF TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Vcomm Output Under Test CT IOH Where: IOL IOH Vcomm CT = = = = 2 mA 2 mA 0.8 V 15-30-pF typical load-circuit capacitance Figure 7. Test Load Circuit for AC Timing Measurements signal transition levels All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels. Vref = 1.5 V Figure 8. Input and Output Voltage Reference Levels for ac Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 9. Rise and Fall Transition Time Voltage Reference Levels POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (PLL used) (see Figure 10) -250 NO. 1 2 3 4 MIN -300 MAX MIN MAX UNIT tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 4*M 3.33 * M ns Pulse duration, CLKIN high 0.4C 0.4C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C Transition time, CLKIN 5 ns 5 ns The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11) For more details, see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. timing requirements for CLKIN [PLL bypassed (x1)] (see Figure 10) -250 NO. 1 2 3 MIN -300 MAX MIN MAX UNIT tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 4 3.33 ns Pulse duration, CLKIN high 0.45C 0.45C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.45C 0.45C ns 4 Transition time, CLKIN 0.6 0.6 ns The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. The maximum CLKIN cycle time in PLL bypass mode (x1) is 200 MHz. 1 4 2 CLKIN 3 4 Figure 10. CLKIN Timings 34 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for XCLKIN (see Figure 11) -250 -300 NO. MIN 1 tc(XCLKIN) tw(XCLKINH) 2 Cycle time, XCLKIN Pulse duration, XCLKIN high 3 tw(XCLKINL) Pulse duration, XCLKIN low P = 1/CPU clock frequency in nanoseconds (ns). UNIT MAX 4P ns 1.8P ns 1.8P ns 1 2 XCLKIN 3 Figure 11. XCLKIN Timings switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 12) NO. 1 2 -250 -300 PARAMETER tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high 3 tw(CKO2L) Pulse duration, CLKOUT2 low P = 1/CPU clock frequency in ns. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. UNIT MIN MAX 2P - 0.7 2P + 0.7 ns P - 0.7 P + 0.7 ns P - 0.7 P + 0.7 ns 1 2 CLKOUT2 3 Figure 12. CLKOUT2 Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for XFCLK (see Figure 13) NO. -250 -300 PARAMETER MIN 1 2 tc(XFCK) tw(XFCKH) Cycle time, XFCLK Pulse duration, XFCLK high 3 tw(XFCKL) Pulse duration, XFCLK low P = 1/CPU clock frequency in ns. D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable 1 2 XFCLK 3 Figure 13. XFCLK Timings 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT MAX D * P - 0.7 D * P + 0.7 ns (D/2) * P - 0.7 (D/2) * P + 0.7 ns (D/2) * P - 0.7 (D/2) * P + 0.7 ns TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 14 - Figure 17) -250 -300 NO. UNIT MIN 3 tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high tsu(ARDYH-AREL) th(AREL-ARDYH) Setup time, ARDY high before ARE low tsu(ARDYL-AREL) th(AREL-ARDYL) Setup time, ARDY low before ARE low 10 11 tw(ARDYH) Pulse width, ARDY high 15 tsu(ARDYH-AWEL) th(AWEL-ARDYH) Setup time, ARDY high before AWE low tsu(ARDYL-AWEL) th(AWEL-ARDYL) Setup time, ARDY low before AWE low 4 6 7 9 16 18 1 ns 4.9 ns -[(RST - 3) * P - 6] ns (RST - 3) * P + 2 ns -[(RST - 3) * P - 6] ns (RST - 3) * P + 2 ns Hold time, EDx valid after ARE high Hold time, ARDY high after ARE low Hold time, ARDY low after ARE low Hold time, ARDY high after AWE low MAX 2P ns -[(WST - 3) * P - 6] ns (WST - 3) * P + 2 ns -[(WST - 3) * P - 6] ns 19 Hold time, ARDY low after AWE low (WST - 3) * P + 2 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous memory cycles# (see Figure 14 - Figure 17) NO. -250 -300 PARAMETER MIN 1 Output setup time, select signals valid to ARE low RS * P - 2 2 tosu(SELV-AREL) toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * P - 2 5 tw(AREL) Pulse width, ARE low 8 td(ARDYH-AREH) tosu(SELV-AWEL) Delay time, ARDY high to ARE high toh(AWEH-SELIV) tw(AWEL) Output hold time, AWE high to select signals invalid 12 13 14 UNIT TYP MAX ns ns RST * P 3P Output setup time, select signals valid to AWE low Pulse width, AWE low ns 4P + 5 WS * P - 3 ns ns WH * P - 2 ns WST * P ns 17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high 3P 4P + 5 ns RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width. # Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional 7P ns following the end of the cycle. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 1 2 1 2 1 2 CEx BE[3:0] EA[21:2] 3 4 ED[31:0] 1 2 AOE 6 7 ARE 5 AWE ARDY CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF's overhead. Figure 14. Asynchronous Memory Read Timing (ARDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 CEx 1 2 1 2 1 2 BE[3:0] EA[21:2] 3 4 ED[31:0] 1 2 AOE 8 10 9 ARE AWE 11 ARDY CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF's overhead. Figure 15. Asynchronous Memory Read Timing (ARDY Used) 38 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 CEx 12 13 12 13 12 13 12 13 BE[3:0] EA[21:2] ED[31:0] AOE 15 ARE 16 14 AWE ARDY If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely reflects the EMIF's overhead. Figure 16. Asynchronous Memory Write Timing (ARDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 12 13 12 13 12 13 12 13 CEx BE[3:0] EA[21:2] ED[31:0] AOE ARE 17 18 19 AWE 11 ARDY If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely reflects the EMIF's overhead. Figure 17. Asynchronous Memory Write Timing (ARDY Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 39 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 18) -250 NO. 7 8 MIN tsu(EDV-CKO2H) th(CKO2H-EDV) -300 MAX MIN MAX UNIT Setup time, read EDx valid before CLKOUT2 high 2.0 1.7 ns Hold time, read EDx valid after CLKOUT2 high 2.0 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles (see Figure 18 and Figure 19) -250 NO. 1 2 3 4 5 6 PARAMETER MIN tosu(CEV-CKO2H) toh(CKO2H-CEV) Output setup time, CEx valid before CLKOUT2 high tosu(BEV-CKO2H) toh(CKO2H-BEIV) Output setup time, BEx valid before CLKOUT2 high tosu(EAV-CKO2H) toh(CKO2H-EAIV) Output setup time, EAx valid before CLKOUT2 high Output hold time, CEx valid after CLKOUT2 high Output hold time, BEx invalid after CLKOUT2 high Output hold time, EAx invalid after CLKOUT2 high 9 Output setup time, SDCAS/SSADS valid before tosu(ADSV-CKO2H) CLKOUT2 high 10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high 11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high 12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high 13 14 tosu(EDV-CKO2H) toh(CKO2H-EDIV) 15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high 16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high Output setup time, EDx valid before CLKOUT2 high Output hold time, EDx invalid after CLKOUT2 high -300 MAX MIN MAX UNIT P - 0.8 P + 0.1 ns P-3 P - 2.3 ns P - 0.8 P + 0.1 ns P-3 P - 2.3 ns P - 0.8 P + 0.1 ns P-3 P - 2.3 ns P - 0.8 P + 0.1 ns P-3 P - 2.3 ns P - 0.8 P + 0.1 ns P-3 P - 2.3 ns P - 1.2 P + 0.1 ns P-3 P - 2.3 ns P - 0.8 P + 0.1 ns P-3 P - 2.3 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time. 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 Q3 9 Q4 10 SDCAS/SSADS 11 12 SDRAS/SSOE SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 18. SBSRAM Read Timing CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 Q1 Q2 Q3 Q4 6 13 14 ED[31:0] 9 10 15 16 SDCAS/SSADS SDRAS/SSOE SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 19. SBSRAM Write Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 20) -250 NO. 7 8 MIN tsu(EDV-CKO2H) th(CKO2H-EDV) MAX -300 MIN MAX UNIT Setup time, read EDx valid before CLKOUT2 high 1.2 0.5 ns Hold time, read EDx valid after CLKOUT2 high 2.7 2 ns switching characteristics over recommended operating conditions for synchronous DRAM cycles (see Figure 20-Figure 25) -250 NO. 1 2 3 4 5 6 PARAMETER MIN -300 MAX MIN MAX UNIT tosu(CEV-CKO2H) toh(CKO2H-CEV) Output setup time, CEx valid before CLKOUT2 high P - 0.9 P + 0.6 ns Output hold time, CEx valid after CLKOUT2 high P - 2.9 P - 1.8 ns tosu(BEV-CKO2H) toh(CKO2H-BEIV) Output setup time, BEx valid before CLKOUT2 high P - 0.9 P + 0.6 ns Output hold time, BEx invalid after CLKOUT2 high P - 2.9 P - 1.8 ns tosu(EAV-CKO2H) toh(CKO2H-EAIV) Output setup time, EAx valid before CLKOUT2 high P - 0.9 P + 0.6 ns Output hold time, EAx invalid after CLKOUT2 high P - 2.9 P - 1.8 ns P - 0.9 P + 0.6 ns 9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high 10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high P - 2.9 P - 1.8 ns 11 tosu(EDV-CKO2H) toh(CKO2H-EDIV) Output setup time, EDx valid before CLKOUT2 high P - 1.5 P + 0.6 ns 12 Output hold time, EDx invalid after CLKOUT2 high P - 2.8 P - 1.8 ns 13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high P - 0.9 P + 0.6 ns 14 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high P - 2.9 P - 1.8 ns 15 tosu(SDA10V-CKO2H) toh(CKO2H-SDA10IV) Output setup time, SDA10 valid before CLKOUT2 high P - 0.9 P + 0.6 ns 16 Output hold time, SDA10 invalid after CLKOUT2 high P - 2.9 P - 1.8 ns 17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high P - 0.9 P + 0.6 ns 18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high P - 2.9 P - 1.8 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time. 42 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ CLKOUT2 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 20. Three SDRAM READ Commands WRITE WRITE WRITE CLKOUT2 1 2 CEx 3 BE[3:0] 4 BE1 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 21. Three SDRAM WRT Commands POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV CLKOUT2 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 18 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 22. SDRAM ACTV Command DCAB CLKOUT2 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE SDCAS/SSADS 13 14 SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 23. SDRAM DCAB Command 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR CLKOUT2 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS/SSOE 9 10 SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 24. SDRAM REFR Command MRS CLKOUT2 1 2 5 6 CEx BE[3:0] EA[15:2] MRS Value ED[31:0] SDA10 17 18 9 10 13 14 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 25. SDRAM MRS Command POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 26) -250 -300 NO. MIN 3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. UNIT MAX P ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles (see Figure 26) NO. -250 -300 PARAMETER MIN 1 2 4 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) Delay time, HOLD low to EMIF Bus high impedance td(HOLDH-EMLZ) td(EMLZ-HOLDAH) Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus high impedance to HOLDA low UNIT 3P MAX ns 0 2P ns 3P 7P ns 5 Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus 1 4 C6203 C6203 EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. Figure 26. HOLD/HOLDA Timing 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 RESET TIMING timing requirements for reset (see Figure 27) -250 -300 NO. MIN UNIT MAX Width of the RESET pulse (PLL stable) 10P ns 1 tw(RST) Width of the RESET pulse (PLL needs to sync up) 250 s 10 tsu(XD) th(XD) Setup time, XD configuration bits valid before RESET high Hold time, XD configuration bits valid after RESET high 5P ns 11 5P ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL are stable. This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the Clock PLL section for PLL lock times. XD[31:0] are the boot configuration pins during device reset. switching characteristics over recommended operating conditions during reset# (see Figure 27) NO. PARAMETER -250 -300 MIN 2 3 4 5 6 7 8 9 td(RSTL-CKO2IV) td(RSTH-CKO2V) Delay time, RESET low to CLKOUT2 invalid td(RSTL-HIGHIV) td(RSTH-HIGHV) Delay time, RESET low to high group invalid td(RSTL-LOWIV) td(RSTH-LOWV) Delay time, RESET low to low group invalid td(RSTL-ZHZ) td(RSTH-ZV) Delay time, RESET low to Z group high impedance P Delay time, RESET high to CLKOUT2 valid ns 4P P Delay time, RESET high to high group valid ns ns 4P P Delay time, RESET high to low group valid Delay time, RESET high to Z group valid UNIT MAX ns ns 4P P ns ns 4P ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. # High group consists of: XFCLK, HOLDA Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 RESET TIMING (CONTINUED) CLKOUT1 1 10 11 RESET 2 3 4 5 6 7 8 9 CLKOUT2 HIGH GROUP LOW GROUP Z GROUP Boot Configuration XD[31:0] High group consists of: Low group consists of: Z group consists of: XFCLK, HOLDA IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA. XD[31:0] are the boot configuration pins during device reset. Figure 27. Reset Timing 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles (see Figure 28) -250 -300 NO. MIN 2 3 tw(ILOW) tw(IHIGH) UNIT MAX Width of the interrupt pulse low 2P ns Width of the interrupt pulse high 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. switching characteristics over recommended operating conditions during interrupt response cycles (see Figure 28) NO. -250 -300 PARAMETER MIN 1 4 5 6 UNIT MAX tR(EINTH - IACKH) td(CKO2L-IACKV) Response time, EXT_INTx high to IACK high Delay time, CLKOUT2 low to IACK valid -1.5 9P 10 ns ns td(CKO2L-INUMV) td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx valid -2.0 10 ns Delay time, CLKOUT2 low to INUMx invalid -2.0 10 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 Interrupt Number INUMx Figure 28. Interrupt Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 29, Figure 30, and Figure 31) -250 -300 NO. MIN 5 6 tsu(XDV-XFCKH) th(XFCKH-XDV) Setup time, read XDx valid before XFCLK high Hold time, read XDx valid after XFCLK high UNIT MAX 3 ns 2.5 ns switching characteristics over recommended operating conditions for synchronous FIFO interface (see Figure 29, Figure 30, and Figure 31) NO. -250 -300 PARAMETER MIN 1 2 3 4 7 8 td(XFCKH-XCEV) td(XFCKH-XAV) Delay time, XFCLK high to XCEx valid 1.5 4.5 ns Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid 1.5 4.5 ns td(XFCKH-XOEV) td(XFCKH-XREV) Delay time, XFCLK high to XOE valid 1.5 4.5 ns Delay time, XFCLK high to XRE valid 1.5 4.5 ns td(XFCKH-XWEV) td(XFCKH-XDV) Delay time, XFCLK high to XWE/XWAIT valid 1.5 4.5 ns 4.5 ns Delay time, XFCLK high to XDx valid 9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. 1.5 ns XFCLK 1 1 XCE3 2 XBE[3:0]/XA[5:2] 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT 6 5 XD[31:0] D1 D2 D3 FIFO read (glueless) mode only available in XCE3. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 29. FIFO Read Timing (Glueless Read Mode) 50 UNIT MAX POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 D4 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED) XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2] 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT 6 5 XD[31:0] D1 D2 D3 D4 XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 30. FIFO Read Timing XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2] 2 XA1 XA2 XA3 XA4 XOE XRE 7 7 XWE/XWAIT 9 8 XD[31:0] D1 D2 D3 D4 XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses. Figure 31. FIFO Write Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles (see Figure 32-Figure 35) -250 -300 NO. UNIT MIN 3 MAX tsu(XDV-XREH) th(XREH-XDV) Setup time, XDx valid before XRE high 4.5 ns Hold time, XDx valid after XRE high 2.5 ns tsu(XRDYH-XREL) th(XREL-XRDYH) Setup time, XRDY high before XRE low -[(RST - 3) * P - 6] ns (RST - 3) * P + 2 ns tsu(XRDYL-XREL) th(XREL-XRDYL) Setup time, XRDY low before XRE low -[(RST - 3) * P - 6] ns 10 (RST - 3) * P + 2 ns 11 tw(XRDYH) Pulse width, XRDY high 15 tsu(XRDYH-XWEL) th(XWEL-XRDYH) Setup time, XRDY high before XWE low tsu(XRDYL-XWEL) th(XWEL-XRDYL) Setup time, XRDY low before XWE low 4 6 7 9 16 18 Hold time, XRDY high after XRE low Hold time, XRDY low after XRE low Hold time, XRDY high after XWE low 2P ns -[(WST - 3) * P - 6] ns (WST - 3) * P + 2 ns -[(WST - 3) * P - 6] ns 19 Hold time, XRDY low after XWE low (WST - 3) * P + 2 ns To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input. RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous peripheral cycles# (see Figure 32-Figure 35) NO. -250 -300 PARAMETER MIN 1 Output setup time, select signals valid to XRE low RS * P - 2 2 tosu(SELV-XREL) toh(XREH-SELIV) Output hold time, XRE low to select signals invalid RH * P - 2 5 tw(XREL) Pulse width, XRE low 8 td(XRDYH-XREH) tosu(SELV-XWEL) Delay time, XRDY high to XRE high toh(XWEH-SELIV) tw(XWEL) Output hold time, XWE low to select signals invalid 12 13 14 UNIT TYP MAX ns ns RST * P Output setup time, select signals valid to XWE low Pulse width, XWE low 3P ns 4P + 5 WS * P - 3 ns ns WH * P - 2 ns WST * P ns 17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high 3P 4P + 5 ns RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width. # Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an additional 7P ns following the end of the cycle. 52 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 1 2 1 2 XCEx XBE[3:0]/ XA[5:2] 3 4 XD[31:0] 1 2 XOE 6 7 5 XRE XWE/XWAIT XRDY XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. Figure 32. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 1 2 1 2 XCEx XBE[3:0]/ XA[5:2] 3 4 XD[31:0] 1 2 XOE 8 10 9 XRE XWE/XWAIT 11 XRDY XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. Figure 33. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 CLKOUT1 12 13 12 13 12 13 XCEx XBE[3:0]/ XA[5:2] XD[31:0] XOE XRE 15 16 14 XWE/XWAIT XRDY XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. Figure 34. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used) Setup = 2 Strobe = 3 Not Ready Hold = 2 CLKOUT1 12 13 12 13 12 13 XCEx XBE[3:0]/ XA[5:2] XD[31:0] XOE XRE 17 18 19 XWE/XWAIT 11 XRDY XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses. XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses. XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses. Figure 35. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used) 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING timing requirements with external device as bus master (see Figure 36 and Figure 37) -250 -300 NO. MIN 1 2 3 4 5 6 7 8 9 10 16 17 18 UNIT MAX tsu(XCSV-XCKIH) th(XCKIH-XCS) Setup time, XCS valid before XCLKIN high 3.5 ns Hold time, XCS valid after XCLKIN high 2.8 ns tsu(XAS-XCKIH) th(XCKIH-XAS) Setup time, XAS valid before XCLKIN high 3.5 ns Hold time, XAS valid after XCLKIN high 2.8 ns tsu(XCTL-XCKIH) th(XCKIH-XCTL) Setup time, XCNTL valid before XCLKIN high 3.5 ns Hold time, XCNTL valid after XCLKIN high 2.8 ns tsu(XWR-XCKIH) th(XCKIH-XWR) Setup time, XW/R valid before XCLKIN high 3.5 ns Hold time, XW/R valid after XCLKIN high 2.8 ns tsu(XBLTV-XCKIH) th(XCKIH-XBLTV) Setup time, XBLAST valid before XCLKIN high Hold time, XBLAST valid after XCLKIN high 3.5 ns 2.8 ns tsu(XBEV-XCKIH) th(XCKIH-XBEV) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high 3.5 ns 2.8 ns tsu(XD-XCKIH) th(XCKIH-XD) Setup time, XDx valid before XCLKIN high 3.5 ns 2.8 ns 19 Hold time, XDx valid after XCLKIN high XW/R input/output polarity selected at boot. XBLAST input polarity selected at boot XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as bus master (see Figure 36 and Figure 37) NO. -250 -300 PARAMETER MIN 11 12 13 14 15 20 td(XCKIH-XDLZ) td(XCKIH-XDV) Delay time, XCLKIN high to XDx low impedance td(XCKIH-XDIV) td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx invalid 5 Delay time, XCLKIN high to XDx high impedance Delay time, XCLKIN high to XRDY invalid# 5 td(XCKIH-XRY) td(XCKIH-XRYLZ) 0 Delay time, XCLKIN high to XDx valid Delay time, XCLKIN high to XRDY low impedance td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance# P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. # XRDY operates as active-low ready input/output during host-port accesses. 21 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT MAX ns 16.5 ns ns 4P ns 16.5 ns 5 16.5 ns 2P + 5 3P + 16.5 ns 55 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R 8 7 XW/R XBE[3:0]/XA[5:2] 10 9 XBLAST 10 9 XBLAST 11 D1 XD[31:0] 20 13 14 12 D2 15 XRDY XW/R input/output polarity selected at boot XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XBLAST input polarity selected at boot XRDY operates as active-low ready input/output during host-port accesses. Figure 36. External Host as Bus Master--Read 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 D3 D4 15 21 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R 8 7 XW/R 17 16 XBE[3:0]/XA[5:2] XBE1 XBE2 XBE3 XBE4 10 9 XBLAST 10 9 XBLAST 19 18 D1 XD[31:0] 20 D2 D3 15 D4 15 21 XRDY XW/R input/output polarity selected at boot XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XBLAST input polarity selected at boot XRDY operates as active-low ready input/output during host-port accesses. Figure 37. External Host as Bus Master--Write POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 57 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) timing requirements with C62x as bus master (see Figure 38, Figure 39, and Figure 40) -250 -300 NO. MIN 9 10 11 12 14 15 UNIT MAX tsu(XDV-XCKIH) th(XCKIH-XDV) Setup time, XDx valid before XCLKIN high 3.5 ns Hold time, XDx valid after XCLKIN high 2.8 ns tsu(XRY-XCKIH) th(XCKIH-XRY) Setup time, XRDY valid before XCLKIN high 3.5 ns Hold time, XRDY valid after XCLKIN high 2.8 ns tsu(XBFF-XCKIH) th(XCKIH-XBFF) Setup time, XBOFF valid before XCLKIN high 3.5 ns Hold time, XBOFF valid after XCLKIN high 2.8 ns XRDY operates as active-low ready input/output during host-port accesses. switching characteristics over recommended operating conditions with C62x as bus master (see Figure 38, Figure 39, and Figure 40) NO. PARAMETER -250 -300 MIN 1 2 3 4 5 6 7 8 td(XCKIH-XASV) td(XCKIH-XWRV) Delay time, XCLKIN high to XAS valid 5 16.5 ns Delay time, XCLKIN high to XW/R valid 5 16.5 ns td(XCKIH-XBLTV) td(XCKIH-XBEV) Delay time, XCLKIN high to XBLAST valid 5 16.5 ns Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid 5 16.5 ns td(XCKIH-XDLZ) td(XCKIH-XDV) Delay time, XCLKIN high to XDx low impedance 0 td(XCKIH-XDIV) td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx invalid Delay time, XCLKIN high to XDx valid 13 td(XCKIH-XWTV) XW/R input/output polarity selected at boot. XBLAST output polarity is always active low. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. # XWE/XWAIT operates as XWAIT output signal during host-port accesses. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 ns 16.5 5 Delay time, XCLKIN high to XDx high impedance Delay time, XCLKIN high to XWE/XWAIT valid# 58 UNIT MAX 5 ns ns 4P ns 16.5 ns TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 1 1 XAS 2 2 XW/R XW/R 3 3 XBLAST 4 4 XBE[3:0]/XA[5:2] 5 7 6 AD XD[31:0] BE 9 8 D1 10 D2 D3 D4 11 12 XRDY 13 13 XWE/XWAIT XW/R input/output polarity selected at boot XBLAST output polarity is always active low. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XWE/XWAIT operates as XWAIT output signal during host-port accesses. Figure 38. C62x as Bus Master--Read XCLKIN 1 1 XAS XW/R 2 2 XW/R 3 3 XBLAST 4 4 6 7 XBE[3:0]/XA[5:2] 5 XD[31:0] Addr 8 D1 D2 D3 D4 11 XRDY 12 13 13 XWE/XWAIT XW/R input/output polarity selected at boot XBLAST output polarity is always active low. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XWE/XWAIT operates as XWAIT output signal during host-port accesses. Figure 39. C62x as Bus Master--Write POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 59 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) XCLKIN 1 1 XAS XW/R 2 2 4 4 XW/R XBLAST XBE[3:0]/XA[5:2] 6 7 5 XD[31:0] 8 Addr D1 11 D2 12 XRDY 15 14 XBOFF XHOLD XHOLDA XHOLD# XHOLDA# XW/R input/output polarity selected at boot XBLAST output polarity is always active low. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. Internal arbiter enabled # External arbiter enabled || This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 43 and Figure 44. Figure 40. C62x as Bus Master--BOFF Operation|| 60 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING timing requirements with external device as asynchronous bus master (see Figure 41 and Figure 42) -250 -300 NO. MIN UNIT MAX 1 tw(XCSL) Pulse duration, XCS low 4P ns 2 tw(XCSH) tsu(XSEL-XCSL) Pulse duration, XCS high 4P ns th(XCSL-XSEL) th(XRYL-XCSL) Hold time, expansion bus select signals valid after XCS low 3 4 10 11 12 13 14 Setup time, expansion bus select signals valid before XCS low 1 ns 3.4 ns P + 1.5 ns tsu(XBEV-XCSH) th(XCSH-XBEV) Setup time, XBE[3:0]/XA[5:2] valid before XCS high 1 ns Hold time, XBE[3:0]/XA[5:2] valid after XCS high 3 ns tsu(XDV-XCSH) th(XCSH-XDV) Setup time, XDx valid before XCS high 1 ns Hold time, XDx valid after XCS high 3 ns Hold time, XCS low after XRDY low P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. Expansion bus select signals include XCNTL and XR/W. XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. switching characteristics over recommended operating conditions with external device as asynchronous bus master (see Figure 41 and Figure 42) NO. PARAMETER -250 -300 MIN 5 6 7 8 td(XCSL-XDLZ) td(XCSH-XDIV) Delay time, XCS low to XDx low impedance 0 Delay time, XCS high to XDx invalid 0 td(XCSH-XDHZ) td(XRYL-XDV) Delay time, XCS high to XDx high impedance Delay time, XRDY low to XDx valid 9 td(XCSH-XRYH) Delay time, XCS high to XRDY high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT MAX ns 12 ns 4P ns -4 1 ns 0 12 ns 61 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED) 1 1 2 10 10 XCS 3 3 4 4 XCNTL XBE[3:0]/XA[5:2] 3 3 4 4 XR/W 3 3 4 4 XR/W 5 7 6 8 5 7 6 8 Word XD[31:0] 9 9 XRDY XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XW/R input/output polarity selected at boot Figure 41. External Device as Asynchronous Master--Read 1 10 2 10 1 XCS 3 3 4 4 XCNTL 11 11 12 12 XBE[3:0]/XA[5:2] 3 3 4 4 XR/W 3 3 4 4 XR/W 13 XD[31:0] 14 13 9 XRDY XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses. XW/R input/output polarity selected at boot Figure 42. External Device as Asynchronous Master--Write 62 14 word Word POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 XHOLD/XHOLDA TIMING timing requirements for expansion bus arbitration (internal arbiter enabled) (see Figure 43) -250 -300 NO. MIN 3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. UNIT MAX P ns switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter enabled) (see Figure 43) NO. -250 -300 PARAMETER MIN 1 2 4 5 td(XHDH-XBHZ) td(XBHZ-XHDAH) Delay time, XHOLD high to XBus high impedance td(XHDL-XHDAL) td(XHDAL-XBLZ) Delay time, XHOLD low to XHOLDA low UNIT 3P MAX ns 0 2P ns Delay time, XBus high impedance to XHOLDA high 3P Delay time, XHOLDA low to XBus low impedance 0 ns 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. All pending XBus transactions are allowed to complete before XHOLDA is asserted. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 XHOLD (input) 2 4 XHOLDA (output) 1 XBus 5 C6203 C6203 XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. Figure 43. Expansion Bus Arbitration--Internal Arbiter Enabled POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 63 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 XHOLD/XHOLDA TIMING (CONTINUED) switching characteristics over recommended operating conditions for expansion bus arbitration (internal arbiter disabled) (see Figure 44) NO. -250 -300 PARAMETER MIN 1 2 td(XHDAH-XBLZ) td(XBHZ-XHDL) Delay time, XHOLDA high to XBus low impedance Delay time, XBus high impedance to XHOLD low 2P 2P + 10 0 P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. 2 XHOLD (output) XHOLDA (input) 1 XBus C6203 XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. Figure 44. Expansion Bus Arbitration--Internal Arbiter Disabled 64 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT MAX 2P ns ns TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 45) -250 -300 NO. 2 3 tc(CKRX) tw(CKRX) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKR/X ext MIN 2P CLKR/X ext P - 1 CLKR int 9 CLKR ext 2 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0.5 CLKR int 3 CLKR ext 4.5 CLKX int 9 CLKX ext 2 CLKX int 6 CLKX ext 4 UNIT MAX ns ns ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz (P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. The minimum CLKR/X pulse duration is either (P - 1) or 4 ns, whichever is larger. For example, when running parts at 300 MHz (P = 3.3 ns), use 4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P - 1) = 9 ns as the minimum CLKR/X pulse duration. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 65 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 45) NO. -250 -300 PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 4 16 2P C - 1# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X CLKR/X int 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -2 3 CLKX int -2 3 CLKX ext 3 9 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 td(FXH-DXV) Delay time, FSX high to DX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode. ns ns CLKX int -1 5 CLKX ext 2 9 CLKX int -0.5 4 CLKX ext 2 11 FSX int -1 5 FSX ext 0 10 ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz (P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. 66 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 45. McBSP Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 67 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 46) -250 -300 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 46. FSR Timing When GSYNC = 1 68 UNIT MAX POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 47) -250 -300 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low SLAVE MAX MIN 12 5 Hold time, DR valid after CLKX low 4 P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT MAX 2 - 3P ns 5 + 6P ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 47) -250 -300 NO. PARAMETER MASTER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T-2 T+3 MIN ns L-2 L+3 ns -3 4 L-2 L+3 3P + 4 MAX 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 69 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 70 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 48) -250 -300 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high SLAVE MAX MIN 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT MAX 2 - 3P ns 5 + 6P ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 48) -250 -300 NO. PARAMETER MIN MAX L+3 ns T-2 T+3 ns Delay time, CLKX low to DX valid -2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from CLKX low -2 4 3P + 3 5P + 17 ns 2 Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) tdis(CKXL-DXHZ) 6 UNIT SLAVE L-2 th(CKXL-FXL) td(FXL-CKXH) 1 MASTER MIN MAX 7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+4 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 71 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 72 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 49) -250 -300 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high SLAVE MAX MIN 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT MAX 2 - 3P ns 5 + 6P ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 49) -250 -300 NO. PARAMETER MASTER 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T-2 T+3 MIN ns H-2 H+3 ns -3 4 H-2 H+3 3P + 4 MAX 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 73 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 74 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 50) -250 -300 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low SLAVE MAX MIN 12 5 Hold time, DR valid after CLKX low 4 P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT MAX 2 - 3P ns 5 + 6P ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 50) -250 -300 NO. PARAMETER MASTER MIN MAX H-2 H+3 ns T-2 T+2 ns Delay time, CLKX high to DX valid -3 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from CLKX high -2 4 3P + 3 5P + 17 ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) tdis(CKXH-DXHZ) 1 6 UNIT SLAVE MIN MAX 7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+5 2P + 2 4P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit. FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 75 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 76 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 DMAC, TIMER, POWER-DOWN TIMING switching characteristics over recommended operating conditions for DMAC outputs (see Figure 51) NO. -250 -300 PARAMETER MIN 1 tw(DMACH) Pulse duration, DMAC high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. UNIT MAX 2P - 3 ns 1 DMAC[3:0] Figure 51. DMAC Timing timing requirements for timer inputs (see Figure 52) -250 -300 NO. MIN 1 2 tw(TINPH) tw(TINPL) UNIT MAX Pulse duration, TINP high 2P ns Pulse duration, TINP low 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. switching characteristics over recommended operating conditions for timer outputs (see Figure 52) NO. -250 -300 PARAMETER MIN 3 4 tw(TOUTH) tw(TOUTL) UNIT MAX Pulse duration, TOUT high 2P - 3 ns Pulse duration, TOUT low 2P - 3 ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. 2 1 TINPx 4 3 TOUTx Figure 52. Timer Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 77 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics over recommended operating conditions for power-down outputs (see Figure 53) NO. -250 -300 PARAMETER MIN 1 tw(PDH) Pulse duration, PD high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. 1 PD Figure 53. Power-Down Timing 78 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 2P UNIT MAX ns TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 54) -250 -300 NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 11 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics over recommended operating conditions for JTAG test port (see Figure 54) NO. 2 -250 -300 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MIN MAX -4.5 13.5 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 54. JTAG Test-Port Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 79 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MECHANICAL DATA GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 25,20 SQ 24,80 25,00 TYP 1,00 16,30 NOM 0,50 AF AE AD AC AB AA Y 1,00 W V 16,30 NOM U T R P N M L 0,50 K J H G F E D C B A 1 3 2 Heat Slug 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 See Note E 3,50 MAX 1,00 NOM Seating Plane 0,70 0,50 NOTES: A. B. C. D. E. F. 0,10 M 0,60 0,40 0,15 4173516-2/D 01/00 All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL) Flip chip application only Possible protrusion in this area, but within 3,50 max package height specification Falls within JEDEC MO-151/AAL-1 thermal resistance characteristics (S-PBGA package) C/W NO 1 Air Flow m/s RJC RJA Junction-to-case 0.47 N/A Junction-to-free air 14.2 0.00 RJA RJA Junction-to-free air 12.3 0.50 Junction-to-free air 10.9 1.00 RJA Junction-to-free air m/s = meters per second 9.3 2.00 2 3 4 5 80 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C6203 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS086E - JANUARY 1999 - REVISED MAY 2001 MECHANICAL DATA GLS (S-PBGA-N384) PLASTIC BALL GRID ARRAY 18,10 SQ 17,90 16,80 TYP 0,80 0,40 AB AA Y W V 0,80 U T R P N M L K 0,40 J H G F E D C B A 1 3 2 5 4 7 6 9 8 11 13 15 17 19 21 10 12 14 16 18 20 22 Heat Slug 2,80 MAX 1,00 NOM Seating Plane 0,55 0,45 0,10 M 0,45 0,35 0,12 4188959/C 04/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL) Flip chip application only thermal resistance characteristics (S-PBGA package) NO 1 C/W Air Flow m/s RJC RJA Junction-to-case 0.85 N/A Junction-to-free air 21.6 0.0 RJA RJA Junction-to-free air 18.0 0.5 Junction-to-free air 15.5 1.0 5 RJA Junction-to-free air m/s = meters per second 12.8 2.0 2 3 4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 81 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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