TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DHigh-Performance Fixed-Point Digital
Signal Processor (DSP) – TMS320C6203
– 4-, 3.33-ns Instruction Cycle Time
– 250-, 300-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 2000, 2400 MIPS
DC6203 and C6202/02B GLS Ball Grid Array
(BGA) Packages are Pin-Compatible With
the C6204 GLW BGA Package†
DVelociTI Advanced Very-Long-Instruction-
Word (VLIW) TMS320C62x DSP Core
– Eight Highly Independent Functional
Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
DInstruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
D7M-Bit On-Chip SRAM
– 3M-Bit Internal Program/Cache
(96K 32-Bit Instructions)
– 4M-Bit Dual-Access Internal Data
(512K Bytes)
– Organized as Two 256K-Byte Blocks
for Improved Concurrency
D32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
– 52M-Byte Addressable External Memory
Space
DFour-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
DFlexible Phase-Locked-Loop (PLL) Clock
Generator
D32-Bit Expansion Bus (XBus)
– Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
DThree Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral Interface (SPI)
Compatible (Motorola)
DTwo 32-Bit General-Purpose Timers
DIEEE-1149.1 (JTAG‡)
Boundary-Scan-Compatible
D352-Pin BGA Package (GJL)
D384-Pin BGA Package (GLS)
D0.15-µm/5-Level Metal Process
– CMOS Technology
D3.3-V I/Os, 1.5-V Internal
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI and TMS320C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†For more details, see the GLS BGA package bottom view.
‡IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2001, Texas Instruments Incorporated
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table of Contents
input and output clocks 34. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 37. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 40. . . . . . . . . . . . . . . . .
synchronous DRAM timing 42. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 49. . . . . . . . . . . . . . . . . . . . . . . . . .
expansion bus synchronous FIFO timing 50. . . . . . . . . . . .
expansion bus asynchronous peripheral timing 52. . . . . .
expansion bus synchronous host-port timing 55. . . . . . . .
expansion bus asynchronous host-port timing 61. . . . . . .
XHOLD/XHOLDA timing 63. . . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buf fered serial port timing 65. . . . . . . . . . . . .
DMAC, timer , power-down timing 77. . . . . . . . . . . . . . . . . .
JTAG test-port timing 79. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GJL and GLS BGA packages (bottom view) 3. . . . . . . . . . .
description 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C62x device compatibility 6. . . . . . . . . . . . . . . . . . . . . . . . . . .
functional and CPU (DSP core) block diagram 7. . . . . . . . .
CPU (DSP core) description 8. . . . . . . . . . . . . . . . . . . . . . . .
memory map summary 10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal groups description 11. . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support 28. . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing 31. . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature ranges 32. . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 32. . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges
of supply voltage and operating case temperature 32
parameter measurement information 33. . . . . . . . . . . . . . . .
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
GJL and GLS BGA packages (bottom view)
GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
AF
AD
AB
AA
AC
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Y
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AB
GLS 384-PIN BGA PACKAGE (BOTTOM VIEW)
The C6203 and C6202/02B GLS BGA packages are pin-compatible with the C6204 GLW
package except that the inner row of balls (which are additional power and ground pins)
are removed for the C6204 GLW package.
These balls are NOT applicable for the C6204 devices 340-pin GLW BGA package.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description
The TMS320C62x DSPs (including the TMS320C6203 device) compose the fixed-point DSP generation in
the TMS320C6000 DSP platform. The TMS320C6203 (C6203) device is based on the high-performance,
advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI),
making these DSPs an excellent choice for multichannel and multifunction applications.
With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C6203
offers cost-effective solutions to high-performance DSP-programming challenges. The C6203 DSP possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. This
processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.
The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit
multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of
600 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip
memory, and additional on-chip peripherals.
The TMS320C62x DSPs include an on-chip memory, with the C6203 device offering the most memory at
7 Mbits. The C6203 device program memory consists of two blocks, with a 256K-byte block configured as
memory-mapped program space, and the other 128K-byte block user-configurable as cache or
memory-mapped program space. Data memory for the C6203 consists of two 256K-byte blocks of RAM.
The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three multichannel
buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XBus) that of fers ease of
interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external
memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The C62x devices have a complete set of development tools which includes: a new C compiler , an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
device characteristics
Table 1 provides an overview of the TMS320C6203, TMS320C6202/02B, and the TMS320C6204
pin-compatible C62x DSPs. The table shows significant features of each device, including the capacity of
on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. This data sheet
primarily focuses on the functionality of the TMS320C6203 device although it also identifies to the user the
pin-compatibility of the C6203 and C6202/02B GLS, and the C6204 GLW BGA packages. For the functionality
information on the TMS320C6202/02B devices, see the TMS320C6202, TMS320C6202B Fixed-Point Digital
Signal Processors data sheet (literature number SPRS104). For the functionality information on the
TMS320C6204 device, see the TMS320C6204 Fixed-Point Digital Signal Processor data sheet (literature
number SPRS152). And for more details on the C6000 DSP part numbering, see Figure 4.
TMS320C6000, C62x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device characteristics (continued)
Table 1. Characteristics of the Pin-Compatible TMS320C6203, TMS320C6202/02B, and TMS320C6204
DSPs
HARDWARE FEATURES C6203 C6202 C6202B C6204
EMIF √ √ √ √
DMA 4-Channel With
Throughput
Enhancements 4-Channel 4-Channel With
Throughput
Enhancements
4-Channel With
Throughput
Enhancements
Peripherals Expansion Bus √ √ √ √
McBSPs 3 3 3 2
32-Bit T imers 2 2 2 2
Size (Bytes) 384K 256K 256K 64K
Internal
Program
Memory Organization
Block 0:
256K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
Block 0:
128K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
Block 0:
128K-Byte Mapped
Program
Block 1:
128K-Byte
Cache/Mapped
Program
1 Block:
64K-Byte
Cache/Mapped
Program
Size (Bytes) 512K 128K 128K 64K
Internal Data
Memory Organization
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
2 Blocks:
Four 16-Bit Banks
per Block
50/50 Split
CPU ID +
CPU Rev ID Control Status Register
(CSR.[31:16]) 0x0003 0x0002 0x0003 0x0003
Frequency MHz 250, 300 200, 250 250 200
Cycle Time ns 3.33 ns (C6203-300)
4 ns (C6203-250) 4 ns (C6202-250)
5 ns (C6202-200) 4 ns (C6202B-250) 5 ns (C6204-200)
Core (V) 1.5 1.8 1.5 1.5
Voltage I/O (V) 3.3 3.3 3.3 3.3
PLL Options CLKIN frequency multiplier
[Bypass (x1), x4, x6, x7,
x8, x9, x10, and x11]
x1, x4, x8, x10
(GJL Pkg)
All PLL Options
(GLS Pkg)
x1, x4 (Both Pkgs)
x1, x4, x8, x10
(GJL Pkg)
All PLL Options
(GLS Pkg)
x1, x4 (Both Pkgs)
27 x 27 mm 352-pin GJL 352-pin GJL 352-pin GJL –
BGA 18 x 18 mm 384-pin GLS 384-pin GLS 384-pin GLS 340-pin GLW
Packages 16 x 16 mm – – – 288-pin GHK
Process
Technology µm 0.15 µm 0.18 µm 0.15 µm 0.15 µm
Product Status Product Preview (PP)
Advance Information (AI)
Production Data (PD) PD PD PP PP
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
C62x device compatibility
The TMS320C6202, C6202B, C6203, and C6204 devices are pin-compatible; thus, making new system
designs easier and providing faster time to market. The following list summarizes the C62x DSP device
characteristic differences:
DCore Supply Voltage (1.8 V versus 1.5 V)
The C6202 device core supply voltage is 1.8 V while the C6202B, C6203, C6204 devices have core supply
voltages of 1.5 V.
DPLL Options Availability
Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4, etc.] for each of the
C62x DSP devices. For additional details on the PLL clock module and specific options for the C6203
device, see the Clock PLL section of this data sheet.
For additional details on the PLL clock module and specific options for the C6202/02B devices, see the
Clock PLL section of the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors data sheet
(literature number SPRS104).
And for additional details on the PLL clock module and specific options for the C6204 device, see the Clock
PLL section of the TMS320C6204 Fixed-Point Digital Signal Processor data sheet (literature number
SPRS152).
DOn-Chip Memory Size
The C6202/02B, C6203, and C6204 devices have different on-chip program memory and data memory
sizes (see Table 1).
DMcBSPs
The C6202, C6202B, and C6203 devices have three McBSPs while the C6204 device has two McBSPs
on-chip.
For a more detailed discussion on migration concerns, and similarities/differences between the C6202,
C6202B, C6203, and C6204 devices, see the How to Begin Development and Migrate Across the
TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603).
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional and CPU (DSP core) block diagram
32
Multichannel
Buffered Serial
Port 1
32
Direct Memory
Access Controller
(DMA)
(See Table 1)
Test
C62x CPU (DSP Core)
Data Path B
B Register File
Program
Access/Cache
Controller
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
PLL
(x1, x4, x6, x7, x8,
x9, x10, x11)
Data
Access
Controller
Power-
Down
Logic
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
SDRAM or
SBSRAM
ROM/FLASH
SRAM
I/O Devices
Synchronous
FIFOs
I/O Devices
Timer 0
Timer 1
External Memory
Interface (EMIF)
Multichannel
Buffered Serial
Port 0
Multichannel
Buffered Serial
Port 2
Expansion
Bus (XBus)
32-Bit
Internal Program Memory
2 Blocks Program/Cache
(384K Bytes)
Control
Registers
Control
Logic
Internal Data
Memory
(512K Bytes)
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
C6203 Digital Signal Processor
Peripheral Control Bus
DMA
Bus
Boot Configuration
Interrupt
Selector
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (DSP core) description
The CPU fetches V elociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram
and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally, each side features a single data bus connected to all the registers on the other side, by
which the two sets of functional units can access data from the register files on the opposite side. While register
access by functional units on the same side of the CPU as the register file can service all the units in a single
clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
256-bit-wide fetch-packet boundary , the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU (DSP core) description (continued)
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long src
dst
src2
src1
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src1
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8
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8
8
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
ÁÁ
DA1
DA2
ST1
LD1
LD2
ST2
32
32
Register
File A
(A0–A15)
long src
long dst
long dst
long src
Data Path B
Data Path A
Register
File B
(B0–B15)
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map summary
Table 2 shows the memory map address ranges of the C6203 device. The C6203 device has the capability of
a MAP 0 or MAP 1 memory block configuration. These memory block configurations are set up at reset by the
boot configuration pins (generically called BOOTMODE[4:0]). For the C6203 device, the BOOTMODE
configuration is handled, at reset, by the expansion bus module (specifically XD[4:0] pins). For more detailed
information on the C6203 device settings, which include the device boot mode configuration at reset and other
device-specific configurations, see the Boot Configuration section and the Boot Configuration Summary table
of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
Table 2. TMS320C6203 Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE
MAP 0 MAP 1 BLOCK SIZE
(BYTES) HEX ADDRESS RANGE
External Memory Interface (EMIF) CE0 Internal Program RAM 384K 0000_0000 – 0005_FFFF
EMIF CE0 Reserved 4M – 384K 0006_0000 – 003F_FFFF
EMIF CE0 EMIF CE0 12M 0040_0000 – 00FF_FFFF
EMIF CE1 EMIF CE0 4M 0100_0000 – 013F_FFFF
Internal Program RAM EMIF CE1 384K 0140_0000 – 0145_FFFF
Reserved EMIF CE1 4M – 384K 0146_0000 – 017F_FFFF
EMIF Registers 256K 0180_0000 – 0183_FFFF
DMA Controller Registers 256K 0184_0000 – 0187_FFFF
Expansion Bus (XBus) Registers 256K 0188_0000 – 018B_FFFF
McBSP 0 Registers 256K 018C_0000 – 018F_FFFF
McBSP 1 Registers 256K 0190_0000 – 0193_FFFF
T imer 0 Registers 256K 0194_0000 – 0197_FFFF
T imer 1 Registers 256K 0198_0000 – 019B_FFFF
Interrupt Selector Registers 512 019C_0000 – 019C_01FF
Power-Down Registers 256K – 512 019C_0200 – 019F_FFFF
Reserved 256K 01A0_0000 – 01A3_FFFF
McBSP 2 Registers 256K 01A4_0000 – 01A7_FFFF
Reserved 5.5M 01A8_0000 – 01FF_FFFF
EMIF CE2 16M 0200_0000 – 02FF_FFFF
EMIF CE3 16M 0300_0000 – 03FF_FFFF
Reserved 1G – 64M 0400_0000 – 3FFF_FFFF
XBus XCE0 256M 4000_0000 – 4FFF_FFFF
XBus XCE1 256M 5000_0000 – 5FFF_FFFF
XBus XCE2 256M 6000_0000 – 6FFF_FFFF
XBus XCE3 256M 7000_0000 – 7FFF_FFFF
Internal Data RAM 512K 8000_0000 – 8007_FFFF
Reserved 2G – 512K 8008_0000 – FFFF_FFFF
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signal groups description
TRST
EXT_INT7
Clock/PLL
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and
Interrupts
DMA Status
Power-Down
Status
Control/Status
TDI
TDO
TMS
TCK
CLKIN
CLKOUT1
CLKMODE0
PLLV
PLLG
PLLF
EMU1
EMU0
RSV2
RSV1
RSV0
NMI
IACK
INUM3
INUM2
INUM1
INUM0
DMAC3
DMAC2
DMAC1
DMAC0
PD
RSV4
EXT_INT6
EXT_INT5
EXT_INT4
RESET
CLKOUT2
CLKMODE1
CLKMODE2†
†CLKMODE2 is NOT available on the GJL package for the C6203 device.
RSV3
Figure 2. CPU (DSP Core) Signals
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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signal groups description (continued)
CE3
ARE
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE
AWE
ARDY
SDA10
SDRAS/SSOE
SDCAS/SSADS
SDWE/SSWE
TOUT0
CLKX2
FSX2
DX2
CLKR2
FSR2
DR2
CLKS2
Data
Memory Map
Space Select
Word Address
Byte Enables
HOLD/
HOLDA
32
20
Asynchronous
Memory
Control
Synchronous
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Transmit
Transmit
Timer 0
Timers
McBSP1
McBSP2
Receive
Receive
Clock
Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Transmit
McBSP0
Receive
Clock
Figure 3. Peripheral Signals
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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signal groups description (continued)
XD[31:0]
XBE2/XA4
XBE1/XA3
XBE0/XA2
XRDY
XHOLD
XHOLDA
XFCLK
XCLKIN
XOE
XRE
Data
Byte-Enable
Control/
Address
Control
Arbitration
32 Clocks
I/O Port
Control
Expansion Bus
XWE/XWAIT
XCE3
XCE2
XCE1
XCE0
XCS
XAS
Host
Interface
Control
XCNTL
XW/R
XBLAST
XBOFF
XBE3/XA5
Figure 3. Peripheral Signals (Continued)
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
CLOCK/PLL
CLKIN C12 B10 I Clock Input
CLKOUT1 AD20 Y18 O Clock output at full device speed
CLKOUT2 AC19 AB19 O Clock output at half of device speed
•Used for synchronous memory interface
CLKMODE0 B15 B12 I Clock mode selects
•
CLKMODE1 C11 A9 I •Selects what multiply factors of the input clock frequency the CPU frequency
equals.
CLKMODE2 –A14 I For more details on the GJL and GLS CLKMODE pins and the PLL multiply
factors, see the Clock PLL section of this data sheet.
PLLV‡D13 C11 A§PLL analog VCC connection for the low-pass filter
PLLG‡D14 C12 A§PLL analog GND connection for the low-pass filter
PLLF‡C13 A11 A§PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS AD7 Y5 I JTAG test-port mode select (features an internal pullup)
TDO AE6 AA4 O/Z JTAG test-port data out
TDI AF5 Y4 I JTAG test-port data in (features an internal pullup)
TCK AE5 AB2 I JTAG test-port clock
TRST AC7 AA3 I JTAG test-port reset (features an internal pulldown)
EMU1 AF6 AA5 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶
EMU0 AC8 AB4 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶
RESET AND INTERRUPTS
RESET K2 J3 I Device reset
NMI L2 K2 I Nonmaskable interrupt
•Edge-driven (rising edge)
EXT_INT7 V4 U2
EXT_INT6 Y2 U3 External interrupts
•Edge-driven
EXT_INT5 AA1 W1 I
•
Edge-driven
•Polarity independently selected via the External Interrupt Polarity Register bits
EXT_INT4 W4 V2 (EXTPOL.[3:0])
IACK Y1 V1 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 V2 R3
INUM2 U4 T1 Active interrupt identification number
•
INUM1 V3 T2 O•Valid during IACK for all active interrupts (not just external)
•Encoding order follows the interrupt-service fetch-packet ordering
INUM0 W2 T3
•
Encoding order follows the interrupt-service fetch-packet ordering
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡PLL V , PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§A = Analog Signal (PLL Filter)
¶For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor . For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
POWER-DOWN STATUS
PD AB2 Y2 O Power-down modes 2 or 3 (active if high)
EXPANSION BUS
XCLKIN A9 C8 I Expansion bus synchronous host interface clock input
XFCLK B9 A8 O Expansion bus FIFO interface clock output
XD31 D15 C13
XD30 B16 A13
XD29 A17 C14
XD28 B17 B14
XD27 D16 B15
XD26 A18 C15
XD25 B18 A15
XD24 D17 B16
XD23 C18 C16
XD22 A20 A17
XD21 D18 B17
XD20 C19 C17 Expansion bus data
•Used for transfer of data, address, and control
XD19 A21 B18
•
Used for transfer of data, address, and control
•Also controls initialization of DSP modes and expansion bus at reset via pullup/
XD18 D19 A19 pulldown resistors
XD17 C20 C18 (Note: Reserved boot configuration fields should be pulled down.)
XD16 B21 B19 XD[30:16]–XCE[3:0] memory type
XD15 A22 C19 I/O/Z XD13 –XBLAST polarity
XD14 D20 B20 XD12 –XW/R polarity
XD11 –Asynchronous or synchronous host operation
XD13 B22 A21 XD11 –Asynchronous or synchronous host operation
XD10 –Arbitration mode (internal or external)
XD12 E25 C21 XD9 –FIFO mode
XD8 –Little endian/big endian
XD11 F24 D20 XD8 –Little endian/big endian
XD[4:0] –Boot mode
XD10 E26 B22
XD9 F25 D21
XD8 G24 E20
XD7 H23 E21
XD6 F26 D22
XD5 G25 F20
XD4 J23 F21
XD3 G26 E22
XD2 H25 G20
XD1 J24 G21
XD0 K23 G22
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
EXPANSION BUS (CONTINUED)
XCE3 F2 D2
XCE2 E1 B1 Expansion bus I/O port memory space enables
•
XCE1 F3 D3 O/Z •Enabled by bits 28, 29, and 30 of the word address
•Only one asserted during any I/O port data access
XCE0 E2 C2
•
Only one asserted during any I/O port data access
XBE3/XA5 C7 C5
XBE2/XA4 D8 A4 Expansion bus multiplexed byte-enable control/address signals
•
XBE1/XA3 A6 B5 I/O/Z •Act as byte-enable for host-port operation
•Act as address for I/O port operation
XBE0/XA2 C8 C6
•
Act as address for I/O port operation
XOE A7 A6 O/Z Expansion bus I/O port output-enable
XRE C9 C7 O/Z Expansion bus I/O port read-enable
XWE/XWAIT D10 B7 O/Z Expansion bus I/O port write-enable and host-port wait signals
XCS A10 C9 I Expansion bus host-port chip-select input
XAS D9 B6 I/O/Z Expansion bus host-port address strobe
XCNTL B10 B9 I Expansion bus host control. XCNTL selects between expansion bus address or data register.
XW/R D11 B8 I/O/Z Expansion bus host-port write/read-enable. XW/R polarity is selected at reset.
XRDY A5 C4 I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high)
XBLAST B6 B4 I/O/Z Expansion bus host-port burst last-polarity selected at reset
XBOFF B11 A10 I Expansion bus back off
XHOLD B5 A2 I/O/Z Expansion bus hold request
XHOLDA D7 B3 I/O/Z Expansion bus hold acknowledge
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 AB25 Y21
CE2 AA24 W20 Memory space enables
•
CE1 AB26 AA22 O/Z •Enabled by bits 24 and 25 of the word address
•Only one asserted during any external data access
CE0 AA25 W21
•
Only one asserted during any external data access
BE3 Y24 V20
BE2 W23 V21 Byte-enable control
•Decoded from the two lowest bits of the internal address
BE1 AA26 W22 O/Z
•
Decoded from the two lowest bits of the internal address
•Byte-write enables for most types of memory
BE0 Y25 U20 •Can be directly connected to SDRAM read and write mask signal (SDQM)
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
EMIF – ADDRESS
EA21 J25 H20
EA20 J26 H21
EA19 L23 H22
EA18 K25 J20
EA17 L24 J21
EA16 L25 K21
EA15 M23 K20
EA14 M24 K22
EA13 M25 L21
EA12 N23 L20
EA11 P24 L22 O/Z External address (word address)
EA10 P23 M20
EA9 R25 M21
EA8 R24 N22
EA7 R23 N20
EA6 T25 N21
EA5 T24 P21
EA4 U25 P20
EA3 T23 R22
EA2 V26 R21
EMIF – DATA
ED31 AD8 Y6
ED30 AC9 AA6
ED29 AF7 AB6
ED28 AD9 Y7
ED27 AC10 AA7
ED26 AE9 AB8
ED25 AF9 Y8
ED24 AC11 AA8
ED23 AE10 AA9
ED22 AD11 Y9 I/O/Z External data
ED21 AE11 AB10
ED20 AC12 Y10
ED19 AD12 AA10
ED18 AE12 AA11
ED17 AC13 Y11
ED16 AD14 AB12
ED15 AC14 Y12
ED14 AE15 AA12
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
EMIF – DATA (CONTINUED)
ED13 AD15 AA13
ED12 AC15 Y13
ED11 AE16 AB13
ED10 AD16 Y14
ED9 AE17 AA14
ED8 AC16 AA15
ED7 AF18 Y15
ED6 AE18 AB15 I/O/Z External data
ED5 AC17 AA16
ED4 AD18 Y16
ED3 AF20 AB17
ED2 AC18 AA17
ED1 AD19 Y17
ED0 AF21 AA18
EMIF – ASYNCHRONOUS MEMORY CONTROL
ARE V24 T21 O/Z Asynchronous memory read-enable
AOE V25 R20 O/Z Asynchronous memory output-enable
AWE U23 T22 O/Z Asynchronous memory write-enable
ARDY W25 T20 I Asynchronous memory ready input
EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10 AE21 AA19 O/Z SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS AE22 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE AF22 Y19 O/Z SDRAM row-address strobe/SBSRAM output-enable
SDWE/SSWE AC20 AA20 O/Z SDRAM write-enable/SBSRAM write-enable
EMIF – BUS ARBITRATION
HOLD Y26 V22 I Hold request from the host
HOLDA V23 U21 O Hold-request-acknowledge to the host
TIMER 0
TOUT0 F1 D1 O Timer 0 or general-purpose output
TINP0 H4 E2 I T imer 0 or general-purpose input
TIMER 1
TOUT1 J4 F2 O Timer 1 or general-purpose output
TINP1 G2 F3 I Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3 Y3 V3
DMAC2 AA2 W2
DMAC1 AB1 AA1 ODMA action complete
DMAC0 AA3 W3
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 M4 K3 I External clock source (as opposed to internal)
CLKR0 M2 L2 I/O/Z Receive clock
CLKX0 M3 K1 I/O/Z Transmit clock
DR0 R2 M2 I Receive data
DX0 P4 M3 O/Z Transmit data
FSR0 N3 M1 I/O/Z Receive frame sync
FSX0 N4 L3 I/O/Z Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 G1 E1 I External clock source (as opposed to internal)
CLKR1 J3 G2 I/O/Z Receive clock
CLKX1 H2 G3 I/O/Z T ransmit clock
DR1 L4 H1 I Receive data
DX1 J1 H2 O/Z Transmit data
FSR1 J2 H3 I/O/Z Receive frame sync
FSX1 K4 G1 I/O/Z Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
CLKS2 R3 N1 I External clock source (as opposed to internal)
CLKR2 T2 N2 I/O/Z Receive clock
CLKX2 R4 N3 I/O/Z Transmit clock
DR2 V1 R2 I Receive data
DX2 T4 R1 O/Z T ransmit data
FSR2 U2 P3 I/O/Z Receive frame sync
FSX2 T3 P2 I/O/Z T ransmit frame sync
RESERVED FOR TEST
RSV0 L3 J2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1 G3 E3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2 A12 B11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3 C15 B13 O Reserved (leave unconnected, do not connect to power or ground)
RSV4 D12 C10 O Reserved (leave unconnected, do not connect to power or ground)
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS
A11 A3
A16 A7
B7 A16
B8 A20
B19 D4
B20 D6
C6 D7
C10 D9
C14 D10
C17 D13
C21 D14
G4 D16
G23 D17
H3 D19
H24 F1
K3 F4
K24 F19
L1 F22
L26 G4
DVDD N24 G19 S3.3-V supply voltage (I/O)DVDD P3 J4 S3.3-V supply voltage (I/O)
T1 J19
T26 K4
U3 K19
U24 L1
W3 M22
W24 N4
Y4 N19
Y23 P4
AD6 P19
AD10 T4
AD13 T19
AD17 U1
AD21 U4
AE7 U19
AE8 U22
AE19 W4
AE20 W6
AF11 W7
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
AF16 W9
–W10
–W13
–W14
–W16
DVDD –W17 S3.3-V supply voltage (I/O)DVDD –W19 S3.3-V supply voltage (I/O)
–AB5
–AB9
–AB14
–AB18
A1 E7
A2 E8
A3 E10
A24 E11
A25 E12
A26 E13
B1 E15
B2 E16
B3 F7
B24 F8
B25 F9
B26 F11
C1 F12
C2 F14
CVDD C3 F15 S1.5-V supply voltage (core)CVDD C4 F16 S1.5-V supply voltage (core)
C23 G5
C24 G6
C25 G17
C26 G18
D3 H5
D4 H6
D5 H17
D22 H18
D23 J6
D24 J17
E4 K5
E23 K18
AB4 L5
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
AB23 L6
AC3 L17
AC4 L18
AC5 M5
AC22 M6
AC23 M17
AC24 M18
AD1 N5
AD2 N18
AD3 P6
AD4 P17
AD23 R5
AD24 R6
AD25 R17
AD26 R18
AE1 T5
AE2 T6
CVDD AE3 T17 S1.5-V supply voltage (core)
CVDD AE24 T18 S1.5-V supply voltage (core)
AE25 U7
AE26 U8
AF1 U9
AF2 U11
AF3 U12
AF24 U14
AF25 U15
AF26 U16
–V7
–V8
–V10
–V11
–V12
–V13
–V15
–V16
GROUND PINS
A4 A1
A8 A5
VSS A13 A12 GND Ground pins
A14 A18
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
A15 A22
A19 B2
A23 B21
B4 C1
B12 C3
B13 C20
B14 C22
B23 D5
C5 D8
C16 D11
C22 D12
D1 D15
D2 D18
D6 E4
D21 E5
D25 E6
D26 E9
E3 E14
VSS E24 E17 GND Ground pins
F4 E18
F23 E19
H1 F5
H26 F6
K1 F10
K26 F13
M1 F17
M26 F18
N1 H4
N2 H19
N25 J1
N26 J5
P1 J18
P2 J22
P25 K6
P26 K17
R1 L4
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
R26 L19
U1 M4
U26 M19
W1 N6
W26 N17
AA4 P1
AA23 P5
AB3 P18
AB24 P22
AC1 R4
AC2 R19
AC6 U5
AC21 U6
AC25 U10
AC26 U13
AD5 U17
AD22 U18
AE4 V4
VSS AE13 V5 GND Ground pinsVSS AE14 V6 GND Ground pins
AE23 V9
AF4 V14
AF8 V17
AF10 V18
AF12 V19
AF13 W5
AF14 W8
AF15 W11
AF17 W12
AF19 W15
AF23 W18
–Y1
–Y3
–Y20
–Y22
–AA2
–AA21
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL PIN NO.
SIGNAL
NAME GJL GLS TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
–AB1
–AB3
–AB7
VSS –AB11 GND Ground pinsVSS –AB16 GND Ground pins
–AB20
–AB22
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 DSP family member devices, including documentation. See
this document for further information on TMS320 DSP documentation or any TMS320 DSP support products
from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide
(SPRU052), contains information about TMS320 DSP-related products from other companies in the industry .
To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924.
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select
“Find Development Tools”. For device-specific tools, under “Semiconductor Products” select “Digital Signal
Processors”, choose a product family, and select the particular DSP device. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
TMS320C6203
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device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. T exas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GJL), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -300 is 300 MHz).
Figure 4 provides a legend for reading the complete device name for any TMS320C6000 DSP family member.
For the C6203 device orderable part numbers (P/Ns), see the Texas Instruments web site on the Worldwide
web at http://www.ti.com URL, or contact the nearest TI field sales office, or authorized distributor.
TMS320C6203
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device and development-support tool nomenclature (continued)
PREFIX DEVICE SPEED RANGE
TMS 320 C 6203 GLS 300
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
DEVICE FAMILY
320 = TMS320t DSP family
TECHNOLOGY
PACKAGE TYPE†
GFN = 256-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GHK = 288-pin plastic MicroStar BGAt
C = CMOS
DEVICE
C6000 DSP:
6201 6204 6414 6711
6202 6205 6415 6712
6202B 6211 6416
6203 6211B 6701
†BGA = Ball Grid Array
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
( )
Blank = 0°C to 90°C, commercial temperature
A=–40°C to 105°C, extended temperature
100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
Figure 4. TMS320C6000 DSP Platform Device Nomenclature (Including TMS320C6203)
MicroStar BGA is a trademark of Texas Instruments.
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documentation support
Extensive documentation supports all TMS320 DSP family devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices and tools; technical briefs;
development-support tools; on-line help; and hardware and software applications. The following is a brief,
descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory
interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct
memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XBus), peripheral
component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also
includes information on internal data and program memories.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x
devices, associated development tools, and third-party support.
The How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application
report (literature number SPRA603) describes the migration concerns and identifies the similarities and
differences between the C6202, C6202B, C6203, and C6204 C6000 DSP devices.
The tools support documentation is electronically available within the Code Composer Studio IDE. For a
complete listing of the latest C6000 DSP documentation, visit the Texas Instruments web site on the
Worldwide Web at http://www.ti.com uniform resource locator (URL).
C67x is a trademark of Texas Instruments.
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clock PLL
All of the internal C6203 clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
and T able 4 through T able 6 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter , a single clean power supply should power both the C6203 device and the external
clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter . The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Table 3 lists some examples of compatible CLKIN external clock sources:
Table 3. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN) PART NUMBER MANUFACTURER
JITO-2 Fox Electronix
STA series, ST4100 series SaRonix Corporation
Oscillators SG-636 Epson America
342 Corning Frequency Control
PLL MK1711-S, ICS525-02 Integrated Circuit Systems
CLKMODE0
CLKMODE1 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to
C6203
CPU
CLOCK
C1 R1
3.3V
10 mF0.1 mF
PLLF
EMI Filter
C3 C4
1
0
CLKMODE2†
(For the PLL Options
and CLKMODE pins setup,
see Table 4 through Table 6)
† The CLKMODE2 pin is N/A on the C6203 GJL package.
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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clock PLL (continued)
PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
Internal to C6203
CPU
CLOCK
PLLF
1
0
3.3V
CLKMODE0
CLKMODE1
CLKMODE2†
† The CLKMODE2 pin is N/A on the C6203 GJL package.
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
Table 4. TMS320C6203 GLS Packages PLL Multiply and Bypass (x1) Options†
GLS PACKAGE – 18 x 18 mm BGA
BIT (PIN NO.) CLKMODE2 (A14) CLKMODE1 (A9) CLKMODE0 (B12) DEVICES AND PLL
CLOCK OPTIONS
0 0 0 Bypass (x1)
0 0 1 x4
0 1 0 x8
0 1 1 x10
Value 1 0 0 x6
1 0 1 x9
1 1 0 x7
1 1 1 x11
†f(CPU Clock) = f(CLKIN) x (PLL mode)
Table 5. TMS320C6203 GJL Package PLL Multiply and Bypass (x1) Options†
GJL PACKAGE 27 x 27 mm BGA
BIT (PIN NO.) CLKMODE2 (N/A)‡CLKMODE1 (C11) CLKMODE0 (B15) DEVICES AND PLL
CLOCK OPTIONS
0 0 Bypass (x1)
0 1 x4
Value N/A 1 0 x8
1 1 x10
†f(CPU Clock) = f(CLKIN) x (PLL mode)
‡The CLKMODE2 pin is not available (N/A) on the C6203 GJL package.
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clock PLL (continued)
Table 6. TMS320C6203 PLL Component Selection Table†
CLKMODE‡CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1 [±1%]
(Revision No.) C1 [±10%]
(Revision No.) C2 [±10%]
(Revision No.)
TYPICAL
LOCK TIME
(µs)
x4 32.5–75
x6 21.7–50
x7 18.6–42.9
Ω
x8 16.3–37.5 130–300 65–150 60.4 Ω (1.x)
Ω
27 nF (1.x) 560 pF (1.x) 75
x9 14.4–33.3 130–300 65–150 45.3
Ω
(2.x)47 nF (2.x)10 pF (2.x) 75
x10 13–30
x11 11.8–27.3
†Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
‡CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS device. The GJL device is restricted to x1, x4, x8, and x10 multiply factors.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buf fers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A
normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing
the amount of time between the core supply power up and the I/O supply power up can minimize the effects
of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SL VA088)]. A Schottky diode can also be used
to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
TMS320C6203
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absolute maximum ratings over operating case temperature ranges (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) – 0.3 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, DVDD (see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature ranges, TC:(default) 0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(A version) –40_C to105_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature cycle range, (1000-cycle performance) –40_C to 125_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, Core 1.43 1.5 1.57 V
CVDD Supply voltage, Core‡1.65 1.7 1.75 V
DVDD Supply voltage, I/O 3.14 3.3 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –8 mA
IOL Low-level output current 8 mA
Default 0 90 _C
TCOperating case temperature A version –40 105 _C
‡Supply voltage, Core for the C6203 1.7 V devices which are identified in the orderable part number with a “17” following the device number and
the package type ids.
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.6 V
IIInput current§VI = VSS to DVDD ±10 uA
IOZ Off-state output current VO = DVDD or 0 V ±10 uA
IDD2V Supply current, CPU + CPU memory access¶CVDD = NOM, CPU clock = 200 MHz 340 mA
IDD2V Supply current, peripherals¶CVDD = NOM, CPU clock = 200 MHz 235 mA
IDD3V Supply current, I/O pins¶DVDD = NOM, CPU clock = 200 MHz 45 mA
CiInput capacitance 10 pF
CoOutput capacitance 10 pF
§TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
¶Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity , see the TMS320C6000 Power
Consumption Summary application report (literature number SPRA486).
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PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
Vcomm
IOL
CT
IOH
Output
Under
Test
50 Ω
Where: IOL =2 mA
IOH =2 mA
Vcomm = 0.8 V
CT=15–30-pF typical load-circuit capacitance
Figure 7. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 8. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and
VOL MAX and VOH MIN for output clocks.
Vref = VIL MAX (or VOL MAX)
Vref = VIH MIN (or VOH MIN)
Figure 9. Rise and Fall Transition Time Voltage Reference Levels
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INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN (PLL used)†‡§ (see Figure 10)
-250 -300
NO. MIN MAX MIN MAX UNIT
1 tc(CLKIN) Cycle time, CLKIN 4 * M 3.33 * M ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C ns
4 tt(CLKIN) T ransition time, CLKIN 5 5 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11) For more details, see the Clock PLL section of this data sheet.
§C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN [PLL bypassed (x1)]†¶ (see Figure 10)
-250 -300
NO. MIN MAX MIN MAX UNIT
1 tc(CLKIN) Cycle time, CLKIN 4 3.33 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C ns
4 tt(CLKIN) T ransition time, CLKIN 0.6 0.6 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
¶C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. The maximum CLKIN cycle time in PLL bypass mode
(x1) is 200 MHz.
CLKIN
1
2
3
4
4
Figure 10. CLKIN Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for XCLKIN† (see Figure 11)
NO. -250
-300 UNITNO. MIN MAX UNIT
1 tc(XCLKIN) Cycle time, XCLKIN 4P ns
2 tw(XCLKINH) Pulse duration, XCLKIN high 1.8P ns
3 tw(XCLKINL) Pulse duration, XCLKIN low 1.8P ns
†P = 1/CPU clock frequency in nanoseconds (ns).
XCLKIN
1
2
3
Figure 11. XCLKIN Timings
switching characteristics over recommended operating conditions for CLKOUT2†‡ (see Figure 12)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
1 tc(CKO2) Cycle time, CLKOUT2 2P – 0.7 2P + 0.7 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high P – 0.7 P + 0.7 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low P – 0.7 P + 0.7 ns
†P = 1/CPU clock frequency in ns.
‡The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
CLKOUT2
1
3
2
Figure 12. CLKOUT2 Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for XFCLK†‡ (see Figure 13)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
1 tc(XFCK) Cycle time, XFCLK D * P – 0.7 D * P + 0.7 ns
2 tw(XFCKH) Pulse duration, XFCLK high (D/2) * P – 0.7 (D/2) * P + 0.7 ns
3 tw(XFCKL) Pulse duration, XFCLK low (D/2) * P – 0.7 (D/2) * P + 0.7 ns
†P = 1/CPU clock frequency in ns.
‡D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable
XFCLK
1
2
3
Figure 13. XFCLK Timings
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ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§¶ (see Figure 14 – Figure 17)
NO. -250
-300 UNITNO. MIN MAX UNIT
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 1 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 4.9 ns
6 tsu(ARDYH-AREL) Setup time, ARDY high before ARE low –[(RST – 3) * P – 6] ns
7 th(AREL-ARDYH) Hold time, ARDY high after ARE low (RST – 3) * P + 2 ns
9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low –[(RST – 3) * P – 6] ns
10 th(AREL-ARDYL) Hold time, ARDY low after ARE low (RST – 3) * P + 2 ns
11 tw(ARDYH) Pulse width, ARDY high 2P ns
15 tsu(ARDYH-AWEL) Setup time, ARDY high before A WE low –[(WST – 3) * P – 6] ns
16 th(AWEL-ARDYH) Hold time, ARDY high after A WE low (WST – 3) * P + 2 ns
18 tsu(ARDYL-AWEL) Setup time, ARDY low before A WE low –[(WST – 3) * P – 6] ns
19 th(AWEL-ARDYL) Hold time, ARDY low after A WE low (WST – 3) * P + 2 ns
†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous memory
cyclesद# (see Figure 14 РFigure 17)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN TYP MAX UNIT
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * P – 2 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * P – 2 ns
5 tw(AREL) Pulse width, ARE low RST * P ns
8 td(ARDYH-AREH) Delay time, ARDY high to ARE high 3P 4P + 5 ns
12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS * P – 3 ns
13 toh(AWEH-SELIV) Output hold time, A WE high to select signals invalid WH * P – 2 ns
14 tw(AWEL) Pulse width, A WE low WST * P ns
17 td(ARDYH-AWEH) Delay time, ARDY high to A WE high 3P 4P + 5 ns
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
#Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
TMS320C6203
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
5
2
1
4
3
21
21
7
6
CLKOUT1
CEx†
BE[3:0]
ED[31:0]
AOE
ARE
AWE
ARDY
21
EA[21:2]
†CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read
HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.
Figure 14. Asynchronous Memory Read Timing (ARDY Not Used)
Setup = 2 Strobe = 3 Not Ready Hold = 2
8
21
4
3
21
21
21
11
10
9
CLKOUT1
CEx†
BE[3:0]
ED[31:0]
AOE
ARE
AWE
ARDY
EA[21:2]
†CEx stays active for seven minus the value of Read Hold cycles after the last access (DMA transfer or CPU access). For example, if read
HOLD = 1, then CEx stays active for six more cycles. This does not affect performance, it merely reflects the EMIF’s overhead.
Figure 15. Asynchronous Memory Read Timing (ARDY Used)
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
14
1312
1312
1312
1312
16
15
CEx†
BE[3:0]
ED[31:0]
AOE
ARE
AWE
ARDY
EA[21:2]
CLKOUT1
†If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value
of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely
reflects the EMIF’s overhead.
Figure 16. Asynchronous Memory Write Timing (ARDY Not Used)
Setup = 2 Strobe = 3 Not Ready Hold = 2
17
1312
1312
1312
1312
11
19
18
CEx†
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
CLKOUT1
†If no write accesses are scheduled for the next cycle and write hold is set to 1 or greater, then CEx stays active for three cycles after the value
of the programmed hold period. If write hold is set to 0, then CEx stays active for four more cycles. This does not affect performance, it merely
reflects the EMIF’s overhead.
Figure 17. Asynchronous Memory Write Timing (ARDY Used)
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 18)
-250 -300
NO. MIN MAX MIN MAX UNIT
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.0 1.7 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.0 1.5 ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 18 and Figure 19)
-250 -300
NO. PARAMETER MIN MAX MIN MAX UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P – 0.8 P + 0.1 ns
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high P – 3 P – 2.3 ns
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P – 0.8 P + 0.1 ns
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high P – 3 P – 2.3 ns
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P – 0.8 P + 0.1 ns
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high P – 3 P – 2.3 ns
9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before
CLKOUT2 high P – 0.8 P + 0.1 ns
10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2
high P – 3 P – 2.3 ns
11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2
high P – 0.8 P + 0.1 ns
12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2
high P – 3 P – 2.3 ns
13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§P – 1.2 P + 0.1 ns
14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high P – 3 P – 2.3 ns
15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2
high P – 0.8 P + 0.1 ns
16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2
high P – 3 P – 2.3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SDCAS/SSADS†
SDRAS/SSOE†
SDWE/SSWE†
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
65
43
21
8
7
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 18. SBSRAM Read Timing
CLKOUT2
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SDRAS/SSOE†
SDWE/SSWE†
SDCAS/SSADS†
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1615
109
1413
65
43
21
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 19. SBSRAM Write Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 20)
-250 -300
NO. MIN MAX MIN MAX UNIT
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 1.2 0.5 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 2.7 2 ns
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 20–Figure 25)
-250 -300
NO. PARAMETER MIN MAX MIN MAX UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high P – 0.9 P + 0.6 ns
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high P – 2.9 P – 1.8 ns
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high P – 0.9 P + 0.6 ns
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high P – 2.9 P – 1.8 ns
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high P – 0.9 P + 0.6 ns
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high P – 2.9 P – 1.8 ns
9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before
CLKOUT2 high P – 0.9 P + 0.6 ns
10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2
high P – 2.9 P – 1.8 ns
11 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§P – 1.5 P + 0.6 ns
12 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high P – 2.8 P – 1.8 ns
13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before
CLKOUT2 high P – 0.9 P + 0.6 ns
14 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2
high P – 2.9 P – 1.8 ns
15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high P – 0.9 P + 0.6 ns
16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high P – 2.9 P – 1.8 ns
17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before
CLKOUT2 high P – 0.9 P + 0.6 ns
18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2
high P – 2.9 P – 1.8 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
109
1615
6
5
4
3
21
8
7
READ
READ
READ
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 20. Three SDRAM READ Commands
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
1413
109
1615
12
11
6
5
4
3
2
1
WRITE
WRITE
WRITE
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 21. Three SDRAM WRT Commands
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
Bank Activate/Row Address
Row Address
18
17
15
5
2
1
ACTV
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 22. SDRAM ACTV Command
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†14
18
16
2
15
1
17
13
DCAB
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 23. SDRAM DCAB Command
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
10
9
18
17
2
1
REFR
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 24. SDRAM REFR Command
CLKOUT2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
MRS Value
14
10
18
6
2
1
5
17
9
13
MRS
†SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 25. SDRAM MRS Command
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 26)
NO. -250
-300 UNITNO. MIN MAX UNIT
3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 26)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 3P §ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2P ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 3P 7P ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, A WE , SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus External Requestor
Owns Bus DSP Owns Bus
C6203 C6203
1
3
25
4
†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, A WE , SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 26. HOLD/HOLDA Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RESET TIMING
timing requirements for reset† (see Figure 27)
NO. -250
-300 UNITNO. MIN MAX UNIT
Width of the RESET pulse (PLL stable)‡10P ns
1 tw(RST) Width of the RESET pulse (PLL needs to sync up)§250 µs
10 tsu(XD) Setup time, XD configuration bits valid before RESET high¶5P ns
11 th(XD) Hold time, XD configuration bits valid after RESET high¶5P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x1 1 when CLKIN and PLL
are stable.
§This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only (it does not apply to CLKMODE x1). The RESET signal is not connected
internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration
has been changed. During that time, RESET must be asserted to ensure proper device operation. See the Clock PLL section for PLL lock times.
¶XD[31:0] are the boot configuration pins during device reset.
switching characteristics over recommended operating conditions during reset†# (see Figure 27)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
2 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 invalid P ns
3 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 4P ns
4 td(RSTL-HIGHIV) Delay time, RESET low to high group invalid P ns
5 td(RSTH-HIGHV) Delay time, RESET high to high group valid 4P ns
6 td(RSTL-LOWIV) Delay time, RESET low to low group invalid P ns
7 td(RSTH-LOWV) Delay time, RESET high to low group valid 4P ns
8 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance P ns
9 td(RSTH-ZV) Delay time, RESET high to Z group valid 4P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
#High group consists of: XFCLK, HOLDA
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RESET TIMING (CONTINUED)
CLKOUT1
9
8
76
54
32
11
10
RESET
CLKOUT2
HIGH GROUP†
LOW GROUP†
Z GROUP†
XD[31:0]‡
1
Boot Configuration
†High group consists of: XFCLK, HOLDA
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA.
‡XD[31:0] are the boot configuration pins during device reset.
Figure 27. Reset Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles† (see Figure 28)
NO. -250
-300 UNITNO. MIN MAX UNIT
2 tw(ILOW) Width of the interrupt pulse low 2P ns
3 tw(IHIGH) Width of the interrupt pulse high 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions during interrupt response
cycles† (see Figure 28)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
1 tR(EINTH – IACKH) Response time, EXT_INTx high to IACK high 9P ns
4 td(CKO2L-IACKV) Delay time, CLKOUT2 low to IACK valid –1.5 10 ns
5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid –2.0 10 ns
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid –2.0 10 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
Interrupt Number
6
5
4
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
Figure 28. Interrupt Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS FIFO TIMING
timing requirements for synchronous FIFO interface (see Figure 29, Figure 30, and Figure 31)
NO. -250
-300 UNITNO. MIN MAX UNIT
5 tsu(XDV-XFCKH) Setup time, read XDx valid before XFCLK high 3 ns
6 th(XFCKH-XDV) Hold time, read XDx valid after XFCLK high 2.5 ns
switching characteristics over recommended operating conditions for synchronous FIFO
interface (see Figure 29, Figure 30, and Figure 31)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
1 td(XFCKH-XCEV) Delay time, XFCLK high to XCEx valid 1.5 4.5 ns
2 td(XFCKH-XAV) Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid†1.5 4.5 ns
3 td(XFCKH-XOEV) Delay time, XFCLK high to XOE valid 1.5 4.5 ns
4 td(XFCKH-XREV) Delay time, XFCLK high to XRE valid 1.5 4.5 ns
7 td(XFCKH-XWEV) Delay time, XFCLK high to XWE/XWAIT‡ valid 1.5 4.5 ns
8 td(XFCKH-XDV) Delay time, XFCLK high to XDx valid 4.5 ns
9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid 1.5 ns
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
44
33
22
11
XFCLK
XCE3†
XBE[3:0]/XA[5:2]‡
XOE
XRE
XWE/XWAIT§
XD[31:0]
†FIFO read (glueless) mode only available in XCE3.
‡XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
§XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 29. FIFO Read Timing (Glueless Read Mode)
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
44
33
22
11
XFCLK
XCEx
XBE[3:0]/XA[5:2]†
XOE
XRE
XWE/XWAIT‡
XD[31:0]
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 30. FIFO Read Timing
XA1 XA2 XA3 XA4
D1 D2 D3 D4
9
8
77
22
11
XFCLK
XCEx
XBE[3:0]/XA[5:2]†
XOE
XRE
XD[31:0]
XWE/XWAIT‡
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 31. FIFO Write Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
timing requirements for asynchronous peripheral cycles†‡§¶ (see Figure 32–Figure 35)
NO. -250
-300 UNITNO. MIN MAX UNIT
3 tsu(XDV-XREH) Setup time, XDx valid before XRE high 4.5 ns
4 th(XREH-XDV) Hold time, XDx valid after XRE high 2.5 ns
6 tsu(XRDYH-XREL) Setup time, XRDY high before XRE low –[(RST – 3) * P – 6] ns
7 th(XREL-XRDYH) Hold time, XRDY high after XRE low (RST – 3) * P + 2 ns
9 tsu(XRDYL-XREL) Setup time, XRDY low before XRE low –[(RST – 3) * P – 6] ns
10 th(XREL-XRDYL) Hold time, XRDY low after XRE low (RST – 3) * P + 2 ns
11 tw(XRDYH) Pulse width, XRDY high 2P ns
15 tsu(XRDYH-XWEL) Setup time, XRDY high before XWE low –[(WST – 3) * P – 6] ns
16 th(XWEL-XRDYH) Hold time, XRDY high after XWE low (WST – 3) * P + 2 ns
18 tsu(XRDYL-XWEL) Setup time, XRDY low before XWE low –[(WST – 3) * P – 6] ns
19 th(XWEL-XRDYL) Hold time, XRDY low after XWE low (WST – 3) * P + 2 ns
†To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous peripheral
cycles‡§¶# (see Figure 32–Figure 35)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN TYP MAX UNIT
1 tosu(SELV-XREL) Output setup time, select signals valid to XRE low RS * P – 2 ns
2 toh(XREH-SELIV) Output hold time, XRE low to select signals invalid RH * P – 2 ns
5 tw(XREL) Pulse width, XRE low RST * P ns
8 td(XRDYH-XREH) Delay time, XRDY high to XRE high 3P 4P + 5 ns
12 tosu(SELV-XWEL) Output setup time, select signals valid to XWE low WS * P – 3 ns
13 toh(XWEH-SELIV) Output hold time, XWE low to select signals invalid WH * P – 2 ns
14 tw(XWEL) Pulse width, XWE low WST * P ns
17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high 3P 4P + 5 ns
‡RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the XBUS XCE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.
#Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an
additional 7P ns following the end of the cycle.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
5
2
1
4
3
21
21
7
6
CLKOUT1
XCEx
XBE[3:0]/
XA[5:2]†
XD[31:0]
XOE
XRE
XWE/XWAIT‡
XRDY§
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 32. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)
Setup = 2 Strobe = 3 Not Ready Hold = 2
8
21
4
3
21
21
11
10
9
CLKOUT1
XCEx
XD[31:0]
XOE
XRE
XBE[3:0]/
XA[5:2]†
XWE/XWAIT‡
XRDY§
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 33. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
Setup = 2 Strobe = 3 Hold = 2
14
1312
1312
1312
16
15
CLKOUT1
XCEx
XD[31:0]
XRE
XBE[3:0]/
XA[5:2]†
XWE/XWAIT‡
XRDY§
XOE
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 34. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)
XOE
Setup = 2 Strobe = 3 Not Ready Hold = 2
17
1312
1312
1312
11
19
18
CLKOUT1
XCEx
XD[31:0]
XRE
XBE[3:0]/
XA[5:2]†
XWE/XWAIT‡
XRDY§
†XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.
‡XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.
§XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.
Figure 35. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as bus master (see Figure 36 and Figure 37)
NO. -250
-300 UNITNO. MIN MAX UNIT
1 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high 3.5 ns
2 th(XCKIH-XCS) Hold time, XCS valid after XCLKIN high 2.8 ns
3 tsu(XAS-XCKIH) Setup time, XAS valid before XCLKIN high 3.5 ns
4 th(XCKIH-XAS) Hold time, XAS valid after XCLKIN high 2.8 ns
5 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high 3.5 ns
6 th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high 2.8 ns
7 tsu(XWR-XCKIH) Setup time, XW/R valid before XCLKIN high†3.5 ns
8 th(XCKIH-XWR) Hold time, XW/R valid after XCLKIN high†2.8 ns
9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high‡3.5 ns
10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN high‡2.8 ns
16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§3.5 ns
17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§2.8 ns
18 tsu(XD-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns
19 th(XCKIH-XD) Hold time, XDx valid after XCLKIN high 2.8 ns
†XW/R input/output polarity selected at boot.
‡XBLAST input polarity selected at boot
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as bus
master¶ (see Figure 36 and Figure 37)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
11 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance 0 ns
12 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 16.5 ns
13 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid 5 ns
14 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance 4P ns
15 td(XCKIH-XRY) Delay time, XCLKIN high to XRDY invalid#5 16.5 ns
20 td(XCKIH-XRYLZ) Delay time, XCLKIN high to XRDY low impedance 5 16.5 ns
21 td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance#2P + 5 3P + 16.5 ns
¶P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
#XRDY operates as active-low ready input/output during host-port accesses.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
D1 D2 D3 D4
15
13
12
11
10
9
10
9
8
7
8
7
6
5
4
3
2
1
XCLKIN
XCS
XAS
XCNTL
XW/R†
XW/R†
XBE[3:0]/XA[5:2]‡
XBLAST§
XBLAST§
XD[31:0]
XRDY¶15
14
20 21
†XW/R input/output polarity selected at boot
‡XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
§XBLAST input polarity selected at boot
¶XRDY operates as active-low ready input/output during host-port accesses.
Figure 36. External Host as Bus Master—Read
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XBE1 XBE2 XBE3 XBE4
D1 D2 D3 D4
19
18
10
9
10
9
17
16
6
5
4
3
2
1
XCLKIN
XCS
XAS
XCNTL
XW/R†
XW/R†
XBLAST§
XBLAST§
XD[31:0]
8
7
8
7
XBE[3:0]/XA[5:2]‡
15
XRDY¶15
20 21
†XW/R input/output polarity selected at boot
‡XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
§XBLAST input polarity selected at boot
¶XRDY operates as active-low ready input/output during host-port accesses.
Figure 37. External Host as Bus Master—Write
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
timing requirements with C62x as bus master (see Figure 38, Figure 39, and Figure 40)
NO. -250
-300 UNITNO. MIN MAX UNIT
9 tsu(XDV-XCKIH) Setup time, XDx valid before XCLKIN high 3.5 ns
10 th(XCKIH-XDV) Hold time, XDx valid after XCLKIN high 2.8 ns
11 tsu(XRY-XCKIH) Setup time, XRDY valid before XCLKIN high†3.5 ns
12 th(XCKIH-XRY) Hold time, XRDY valid after XCLKIN high†2.8 ns
14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high 3.5 ns
15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high 2.8 ns
†XRDY operates as active-low ready input/output during host-port accesses.
switching characteristics over recommended operating conditions with C62x as bus master
(see Figure 38, Figure 39, and Figure 40)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
1 td(XCKIH-XASV) Delay time, XCLKIN high to XAS valid 5 16.5 ns
2 td(XCKIH-XWRV) Delay time, XCLKIN high to XW/R valid‡5 16.5 ns
3 td(XCKIH-XBLTV) Delay time, XCLKIN high to XBLAST valid§5 16.5 ns
4 td(XCKIH-XBEV) Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid¶5 16.5 ns
5 td(XCKIH-XDLZ) Delay time, XCLKIN high to XDx low impedance 0 ns
6 td(XCKIH-XDV) Delay time, XCLKIN high to XDx valid 16.5 ns
7 td(XCKIH-XDIV) Delay time, XCLKIN high to XDx invalid 5 ns
8 td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx high impedance 4P ns
13 td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid#5 16.5 ns
‡XW/R input/output polarity selected at boot.
§XBLAST output polarity is always active low.
¶XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
#XWE/XWAIT operates as XWAIT output signal during host-port accesses.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
BE
AD D1 D2 D3 D4
13
13
1211
10
9
8
7
6
5
44
3
3
22
1
1
XCLKIN
XAS
XW/R†
XW/R†
XBLAST‡
XBE[3:0]/XA[5:2]§
XD[31:0]
XRDY
XWE/XWAIT¶
†XW/R input/output polarity selected at boot
‡XBLAST output polarity is always active low.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
¶XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 38. C62x as Bus Master—Read
Addr D1 D2 D3 D4
13
13
1211
8
7
6
5
44
3
3
22
1
1
XCLKIN
XAS
XW/R†
XW/R†
XBLAST‡
XBE[3:0]/XA[5:2]§
XD[31:0]
XRDY
XWE/XWAIT¶
†XW/R input/output polarity selected at boot
‡XBLAST output polarity is always active low.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
¶XWE/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 39. C62x as Bus Master—Write
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
Addr D1 D2
15
14
12
11
87
6
5
44
22
11
XCLKIN
XAS
XW/R†
XW/R†
XBLAST‡
XD[31:0]
XRDY
XBOFF
XHOLD¶
XHOLDA¶
XHOLD#
XHOLDA#
XBE[3:0]/XA[5:2]§
†XW/R input/output polarity selected at boot
‡XBLAST output polarity is always active low.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
¶Internal arbiter enabled
#External arbiter enabled
|| This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 43 and Figure 44.
Figure 40. C62x as Bus Master—BOFF Operation||
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as asynchronous bus master† (see Figure 41 and
Figure 42)
NO. -250
-300 UNIT
NO. MIN MAX UNIT
1 tw(XCSL) Pulse duration, XCS low 4P ns
2 tw(XCSH) Pulse duration, XCS high 4P ns
3 tsu(XSEL-XCSL) Setup time, expansion bus select signals‡ valid before XCS low 1 ns
4 th(XCSL-XSEL) Hold time, expansion bus select signals‡ valid after XCS low 3.4 ns
10 th(XRYL-XCSL) Hold time, XCS low after XRDY low P + 1.5 ns
11 tsu(XBEV-XCSH) Setup time, XBE[3:0]/XA[5:2] valid before XCS high§1 ns
12 th(XCSH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCS high§3 ns
13 tsu(XDV-XCSH) Setup time, XDx valid before XCS high 1 ns
14 th(XCSH-XDV) Hold time, XDx valid after XCS high 3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡Expansion bus select signals include XCNTL and XR/W.
§XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
switching characteristics over recommended operating conditions with external device as
asynchronous bus master† (see Figure 41 and Figure 42)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
5 td(XCSL-XDLZ) Delay time, XCS low to XDx low impedance 0 ns
6 td(XCSH-XDIV) Delay time, XCS high to XDx invalid 0 12 ns
7 td(XCSH-XDHZ) Delay time, XCS high to XDx high impedance 4P ns
8 td(XRYL-XDV) Delay time, XRDY low to XDx valid –4 1 ns
9 td(XCSH-XRYH) Delay time, XCS high to XRDY high 0 12 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED)
Word
99
7
685
7
685
4
3
4
3
4
3
4
3
4
3
4
3
XCS
XCNTL
XBE[3:0]/XA[5:2]†
XR/W‡
XR/W‡
XD[31:0]
XRDY
10
12110
†XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
‡XW/R input/output polarity selected at boot
Figure 41. External Device as Asynchronous Master—Read
word
99
14
13
14
13
4
3
4
3
4
3
4
3
12
11
12
11
4
3
4
3
10
10
XCS
XCNTL
XBE[3:0]/XA[5:2]†
XR/W‡
XR/W‡
XD[31:0]
XRDY
121
Word
†XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.
‡XW/R input/output polarity selected at boot
Figure 42. External Device as Asynchronous Master—Write
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
XHOLD/XHOLDA TIMING
timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 43)
NO. -250
-300 UNITNO. MIN MAX UNIT
3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for expansion bus arbitration
(internal arbiter enabled)†‡ (see Figure 43)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
1 td(XHDH-XBHZ) Delay time, XHOLD high to XBus high impedance 3P §ns
2 td(XBHZ-XHDAH) Delay time, XBus high impedance to XHOLDA high 0 2P ns
4 td(XHDL-XHDAL) Delay time, XHOLD low to XHOLDA low 3P ns
5 td(XHDAL-XBLZ) Delay time, XHOLDA low to XBus low impedance 0 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
§All pending XBus transactions are allowed to complete before XHOLDA is asserted.
2
DSP Owns Bus External Requestor DSP Owns Bus
C6203 C6203
51
4
3
XHOLD (input)
XHOLDA (output)
Owns Bus
XBus†
†XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 43. Expansion Bus Arbitration—Internal Arbiter Enabled
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
XHOLD/XHOLDA TIMING (CONTINUED)
switching characteristics over recommended operating conditions for expansion bus arbitration
(internal arbiter disabled)† (see Figure 44)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
1 td(XHDAH-XBLZ) Delay time, XHOLDA high to XBus low impedance‡2P 2P + 10 ns
2 td(XBHZ-XHDL) Delay time, XBus high impedance to XHOLD low‡0 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
C6203
1
2
XHOLD (output)
XHOLDA (input)
XBus†
†XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.
Figure 44. Expansion Bus Arbitration—Internal Arbiter Disabled
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 45)
NO. -250
-300 UNITNO. MIN MAX UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–1¶ns
CLKR int 9
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 2ns
CLKR int 6
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3ns
CLKR int 8
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0.5 ns
CLKR int 3
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4.5 ns
CLKX int 9
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 2ns
CLKX int 6
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 4ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger . For example, when running parts at 300 MHz
(P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶The minimum CLKR/X pulse duration is either (P–1) or 4 ns, whichever is larger . For example, when running parts at 300 MHz (P = 3.3 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P–1) = 9 ns as the minimum CLKR/X pulse
duration.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 45)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input 4 16 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2 3 ns
CLKX int –2 3
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 3 9 ns
Disable time, DX high impedance following last data bit from CLKX int –1 5
12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high CLKX ext 2 9 ns
CLKX int –0.5 4
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 211 ns
Delay time, FSX high to DX valid FSX int –1 5
14 td(FXH-DXV) Delay time, FSX high to DX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode. FSX ext 0 10 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger . For example, when running parts at 300 MHz
(P = 3.3 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
#C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
Figure 45. McBSP Timings
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 46)
NO. -250
-300 UNITNO. MIN MAX UNIT
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 46. FSR Timing When GSYNC = 1
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 47)
-250
-300
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 – 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 47)
-250
-300
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T – 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L – 2 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid –3 4 3P + 4 5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low L – 2 L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX
high P + 3 3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 48)
-250
-300
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 48)
-250
-300
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L – 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T – 2 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 4 3P + 4 5P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low –2 4 3P + 3 5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H – 2 H + 4 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 49)
-250
-300
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 – 3P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 49)
-250
-300
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T – 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H – 2 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid –3 4 3P + 4 5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high H – 2 H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high P + 3 3P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 50)
-250
-300
NO. MASTER SLAVE UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 – 3P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 6P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 50)
-250
-300
NO. PARAMETER MASTER§SLAVE UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H – 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T – 2 T + 2 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid –3 4 3P + 4 5P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high –2 4 3P + 3 5P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L – 2 L + 5 2P + 2 4P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics over recommended operating conditions for DMAC outputs†
(see Figure 51)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
1 tw(DMACH) Pulse duration, DMAC high 2P–3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
DMAC[3:0] 1
Figure 51. DMAC Timing
timing requirements for timer inputs† (see Figure 52)
NO. -250
-300 UNITNO. MIN MAX UNIT
1 tw(TINPH) Pulse duration, TINP high 2P ns
2 tw(TINPL) Pulse duration, TINP low 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for timer outputs†
(see Figure 52)
NO. PARAMETER -250
-300 UNITNO. PARAMETER MIN MAX UNIT
3 tw(TOUTH) Pulse duration, TOUT high 2P–3 ns
4 tw(TOUTL) Pulse duration, T OUT low 2P–3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
TINPx
TOUTx
4
3
2
1
Figure 52. Timer Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics over recommended operating conditions for power-down outputs†
(see Figure 53)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
1 tw(PDH) Pulse duration, PD high 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
PD 1
Figure 53. Power-Down Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 54)
NO. -250
-300 UNITNO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 11 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 54)
NO. PARAMETER -250
-300 UNIT
NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid –4.5 13.5 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 54. JTAG Test-Port Timing
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY
25,00 TYP
0,50
AC
W
U
AA
AE
R
N
L
J
G
E
A
C
2622201612 14 1810862
Seating Plane
4
4173516-2/D 01/00
24
1 3 5 7 9 1113151719212325
SQ
26,80
27,20
Y
V
P
H
K
M
F
D
B
T
SQ
24,80
25,20
16,30 NOM
See Note E
0,60
0,40
0,70
0,50
Heat Slug
1,00 NOM
AB
AD
AF
3,50 MAX
0,50
16,30 NOM
1,00
0,15
1,00
M
∅0,10
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL)
D. Flip chip application only
E. Possible protrusion in this area, but within 3,50 max package height specification
F. Falls within JEDEC MO-151/AAL-1
thermal resistance characteristics (S-PBGA package)
NO °C/W Air Flow m/s†
1 RΘJC Junction-to-case 0.47 N/A
2 RΘJA Junction-to-free air 14.2 0.00
3 RΘJA Junction-to-free air 12.3 0.50
4 RΘJA Junction-to-free air 10.9 1.00
5 RΘJA Junction-to-free air 9.3 2.00
†m/s = meters per second
TMS320C6203
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS086E – JANUARY 1999 – REVISED MAY 2001
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
GLS (S-PBGA-N384) PLASTIC BALL GRID ARRAY
0,40 0,80
0,12
0,80
M
0,10
4188959/C 04/00
1,00 NOM
Seating Plane
0,55
0,45
A
1
0,40
16,80 TYP
0,35
0,45
17,90
18,10 SQ
2
B
2,80 MAX
Heat Slug
3579111315171921
4 6 8 10 12 14 16 18 20 22
C
E
G
J
L
N
R
U
W
AA
D
F
H
K
M
P
T
V
Y
AB
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL)
D. Flip chip application only
thermal resistance characteristics (S-PBGA package)
NO °C/W Air Flow m/s†
1 RΘJC Junction-to-case 0.85 N/A
2 RΘJA Junction-to-free air 21.6 0.0
3 RΘJA Junction-to-free air 18.0 0.5
4 RΘJA Junction-to-free air 15.5 1.0
5 RΘJA Junction-to-free air 12.8 2.0
†m/s = meters per second
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Also see: Standard T erms and Conditions of Sale for Semiconductor Products. www .ti.com/sc/docs/stdterms.htm
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