TN1510 N-Channel Enhancement-Mode Vertical DMOS FETs Features General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex's wellproven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Low threshold (2.0V max.) High input impedance Low input capacitance (50pF typ.) Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications Logic level interfaces - ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage 20V Operating and storage temperature -55OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Ordering Information Order Number Device TN1510 BVDSS/ BVDGS RDS(ON) VGS(th) ID(ON) (max) (V) (min) (A) 2.0 2.0 Die* (V) (max) () TN1510NW 100 3.0 * Die in wafer form. 1 TN1510 Electrical Characteristics (T A = 25OC unless otherwise specified) Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 100 - - V VGS= 0V, ID = 1.0mA VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID = 0.5mA O Conditions VGS(th) Change in VGS(th) with temperature - -3.8 -5.0 mV/ C VGS = VDS, ID = 1.0mA IGSS Gate body leakage - 0.1 100 nA VGS = 20V, VDS = 0V VGS =0V, VDS = Max Rating 10 IDSS Zero gate voltage drain current - - A 500 ID(ON) On-state drain current RDS(ON) Static drain-to-source on-state resistance RDS(ON) Change in RDS(ON) with temperature GFS Forward transconductance CISS - 1.4 - - 3.4 - - 2.0 4.5 - 1.6 3.0 A O VDS = 0.8 Max Rating VGS = 0V, TA = 125OC VGS = 5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 250mA VGS = 10V, ID = 500mA - 0.6 1.1 %/ C VGS = 10V, ID = 0.5A 225 400 - mmho VDS = 25V, ID = 500mA Input capacitance - 50 60 COSS Common source output capacitance - 25 35 CRSS Reverse transfer capacitance - 4.0 8.05 td(ON) Turn-on delay time - 2.0 5.0 tr Rise time - 3.0 5.0 td(OFF) Turn-off delay time - 6.0 7.0 tf Fall time - 3.0 6.0 VSD Diode forward voltage drop - 1.0 trr Reverse recovery time - 400 pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD = 25V, ID = 1.0A RGEN = 25 1.5 V VGS = 0V, ISD = 0.5A - ns VGS = 0V, ISD = 0.5A Notes: 1. All D.C. parameters 100% tested at 25C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V PULSE GENERATOR 10% t(ON) td(ON) VDD t(OFF) tr 10% td(OFF) tF D.U.T. 10% OUTPUT 90% OUTPUT RGEN INPUT 0V RL 90% Doc.# DSFP-TN1510 A102907 2