DS1742 DALLAS SEMICONDUCTOR ed DS1742 Nonvolatile Timekeeping RAM FEATURES Integrated NV SRAM, real time clock, crystal, power- fail control circuit and lithium energy source Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations. Century byte register Totally nonvolatile with over 10 years of operation in the absence of power @ Access times of 70 ns, 85 ns, and 100 ns at 5 volt BCD coded century, year, month, date, day, hours, minutes, and seconds with automaticleap year com- pensation valid up to the year 2100 Battery voltage level indicator flag Power-fail write protection allows for +10% Ver power supply tolerance @ Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time * Standard JEDEC bytewide 2K x 8 static RAM pinout Quartz accuracy +1 minute a month @ 25C, factory calibrated DESCRIPTION The DS1742 is a full function, year 2000 compliant (Y2KC), real-time clock/calendar (RTC) and 2K x 8 non-volatile static RAM in a monolithic chip. User access to all registers within the DS1742 is accom- plished with a bytewide interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are PIN ASSIGNMENT ATT] 1 24] Voc ABC] 2 23 AB AST] 3 22 ag AST] 4 217] WE A3[] 5 20 [] OF AZT] 6 19 Ato AIC) 7 ig] CE AQT] 8 17 [Dav bao] 9 16 7] DOB bai [} 10 15 1) Das paz Tj 1 147 Do GND] 12 13 F] Das PIN DESCRIPTION AQA10 Address Input CE Chip Enable OE Output Enable WE Write Enable Vec +5 Volts GND Ground DQ0-DQ7 Data Input/Output double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buff- ered system also prevents time loss as the timekeeping countdown continues unabated by access to time regis- ter data. The DS81742 also contains its own power-fail circuitry which deselects the device when the Ve sup- ply is in an out of tolerance condition. This feature pre- vents loss of data from unpredictable system operation brought on by low Vee as errant access and update cycles are avoided. Copynght 1997 by Dallas Semiconductor Corporaton All Rights Reserved For important Information regarding atents and other intellectual property nghts please refer to allas Semiconductor data books 070787 1/12DS1742 CLOCK OPERATIONS-READING THE CLOCK While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the D81742 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table2. As long asa one remains DS1742 BLOCK DIAGRAM Figure 1 in that position, updating is halted. Aftera haltis issued, the registers reflect the count, thatis day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1742 registers are updated simultaneously af- ter the clock statusis reset. Updating is within a second after the read bitis written to zero. _L| LY | CLOCK 32.768 kHz] ) crock countbown (-__ Esser TT CHAIN, ff j cE WE veo _ = NY SRAM POWER MONITOR, Vear WRITE PROTECTION 2 nao DS1742 TRUTH TABLE Table 1 Veco cE | OF | WE MODE DQ POWER Vin 4 4 DESELECT HIGH-Z STANDBY Vib Xx Vie WRITE DATA IN ACTIVE 5 VOLTS + 10% Veo | Va) Va READ DATA OLIT ACTIVE Vio | Ve | Vin READ HIGH-Z ACTIVE <4.5 VOLTS >Vpat x x x DESELECT HIGH-Z CMOS STANDBY <VBaT x x x DESELECT HIGH-Z DATA RETENTION MODE SETTING THE CLOCK As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS81742 registers. The user can then load them with the correct day, date and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume. 070797 242DS1742 STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To in- crease the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a one stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit of the daybyte is the frequency test bit. When the frequency test bitis settologic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is be- ing read, the DQO line will toggle atthe 512 Hz frequency DS1742 REGISTER MAP Table 2 as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable). CLOCK ACCURACY The 081742 is guaranteed to keep time accuracy to within +1 minute per month at 25C. The clock is cali- brated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS1742 does net require additional calibration and tem- perature deviations will have a negligible effect in most applications. Forthis reason, methods of field clock cal- ibration are not available and not necessary. DATA ADDRESS FUNCTION/RANGE By Bs Bs By Bs Bo By By 7FF 10 YEAR YEAR YEAR 00-99 7FE x x | 10 MO MONTH MONTH 01-12 7FD x x | 10 DATE DATE DATE 01-31 7FC BF FT x x x DAY DAY 01-07 7FB x x | 10 HOUR HOUR HOUR 00-23 7FA x 10 MINUTES MINUTES MINUTES 00-59 7FQ Osc 10 SECONDS SECONDS SECONDS 00-59 7F8 Ww R | 10 CENTURY CENTURY CENTURY 00-39 SC = STOP BIT R = READ BIT FT = FREQUENCY TEST Wo= WRITEBIT X = SEENOTE BELOW BF = BATTERY FLAG NOTE: All indicated X bits are not dedicated to any particular function and can be used as normal RAM bits. RETRIEVING DATA FROM RAM OR CLOCK The DS1742 is in the read mode whenever OE foutput enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple- through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within taa after the last address input is stable, providing that the CE, and OE access times and states are satisfied. If CE, or OE access times and states are not met, valid data will be available at the latter of chip enable access (tcEa) or at output enable access time (toca). The state of the data input/output pins (DQ) is controlled by CE, and OE. Ifthe outputs are activated before taa, the data lines are driven to an intermediate state until ta,. If the address inputs are changed while CE, and OE remain valid, output data will remain valid for output data hold time (toy) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1742is in the write mode whenever WE, and CE areintheir active state. The start of awrite is referenced to the latter occurring transition of WE, on CE. The ad- dresses must be held valid throughout the cycle. CE, or WE must return inactive for a minimum of twp prior to the initiation of another read or write cycle. Datain must be valid tpg prior to the end of write and remain valid for 070787 3/12DS1742 tp afterward. Ina typical application, the OE signal will be high during awrite cycle. However, OE canbe active provided that careis taken with the data bus to avoid bus contention. If OE is low priorto WE transitioning low the data bus can become active with read data defined by the address inputs. Alow transition on WE will then dis- able the outputs twrz after WE goes active. DATA RETENTION MODE When Vcc is within nominal limits (Vcc > Vpr) the DS1742 can be accessed as described above by read or write cycles. However, when Voc is below the pow- erfail point Vpp (point at which write protection occurs) the internal clock registers and RAM is blocked from ac- cess. This is accomplished internally by inhibiting ac- cess via the CE signal. Atthis time the PowerFail Out- put signal (PFO) will be driven low and will remain low until Voc returns to nominal levels and the powerup recovery time tare has expired (The PFO outputis open drain and requires apull-up). When Vcc falls below the level of the internal battery supply, power input is switched from the Vee pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until Vecis returned to nominal level. Except for the open drain PFO signal, all control, data, and address signals must be powered down when Vee is powered down. BATTERY LONGEVITY The D81742 has a lithium power source that is de- signed to provide energy for clock activity, and clock and RAM data retention when the Voc supply is not present. The capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipmentin which itis installed. For specification pur- poses, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of Vee power. Each D31742 is shipped from Dallas Semicon- ductor with its lithium energy source disconnected, guaranteeing full energy capacity. When Vee is first applied at a level greater than Vp, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1742 will be much longer than 10 years since no lithium battery energy is consumed when Vee is present. In fact, in most applications, the life expectancy of the DS1742 will be approximately equal to the shelf life (expected useful life of the lithium battery with no load attached) of the lithium battery, which may prove to be as long as 20 years. BATTERY MONITOR The DS1742 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a one when read. Ifa zerois ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable. 070797 4412DS1742 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground 0.3V to +6.0V Operating Temperature 0G to 70C Storage Temperature 20C to +70C Soldering Temperature 260C for 10 seconds (See Note 7) * Thisis a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specificationis notimplied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (OS to 70C} PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Voltage All Inputs Veco =5V +5%, +10% Vin 2.2 Veco+0.3V V 1 Veo = 3.3V 5%, 110% Vin 2.0 Vee t+0.3V Vv 1 Logic 0 Voltage All Inputs Voce = BV 5%, +10% Vit 0.3 0.8 v i Vee = 3.3V +5%, +10% VIL 0.3 0.6 Vv i Battery Voltage Veat 2.5 3.7 Vv 1 DC ELECTRICAL CHARACTERISTICS (0C to 70C; Veg = 5.0V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current lec Xx 50 mA 2,3 TIL Standby Current leet Xx 3 mA 2,3 (CE = Vin) CMOS Standby Current leee Xx 3 mA 2,3 (CE > Vec0.2V) Input Leakage Current (any input) lit -1 +1 pA Qutput Leakage Current lot -1 +1 pA (any output) Output Logic 1 Voltage Vou 2.4 1 (lout = -1.9 mA) Output Logic 0 Voltage Voi 0.4 1 (lout = +2.1 mA) Write Protection Voltage Veco = 5V 15% Ver 4.45 4.60 4.75 Vv 1 Veco = 5V 210% Ver 4.20 4.35 4.50 Vv 1 Battery Switch Over Voltage Vso VeaT 1,4 070797 5H12DS1742 AC ELECTRICAL CHARACTERISTICS (OC to 70C; Veg = 3.3V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current lee Xx 30 mA 2,3 TIL Standby Current lect 2 mA 2,3 (CE = Vin) x CMOS Standby Current lece 2 mA 2,3 (CE > VCC -0.2V) x Input Leakage Current (any input) lit 1 +1 pA Qutput Leakage Current lo -1 +1 pA (any output) Gutput Logic 1 Voltage Vou 2.4 1 (lout = -1.0 mA) Qutput Logic 0 Voltage VoL 0.4 1 (lout = 2.1 mA) Write Protection Voltage Vee =3.3Vi5% Ver 2.97 3.06 3.14 v 1 Vee =3.3V 10% Vor 2.80 2.88 297 v { Battery Switch Over Voltage Vso VeaT Vv 1,4 READ CYCLE, AC CHARACTERISTICS (OC to 70C; Veg = 5.0V + 10%) 70 ns access | 85ns access | 100 ns access PARAMETER SYMBOL | MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES Read Cycle Time tre 70 85 100 ns Address Access Time TAA 70 85 100 ns CE to DQ Low-Z toe 5 5 5 ns CE Access Time teEA 70 85 100 ns CE Data Off Time tcez 25 30 35 ns OE to DQ Low-Z toEL 5 5 5 ns OE Access Time toEA 35 45 55 ns OE Data Off Time toEz 25 30 35 ns Output Hold from Address tou 5 5 5 ns 070797 BA2DS1742 READ CYCLE, AC CHARACTERISTICS (0C to 70C; Vog = 3.3V + 10%} 200 ns access PARAMETER SYMBOL MIN MAX UNITS NOTES Read Cycle Time the 200 ns Address Access Time tAA 200 ns CE Low to DQ Low-Z toeL 10 ns CE Access Time tcEA 200 ns CE Data Off Time toEz 60 ns OE Low to DQ Low-Z toeEL 10 ns OE Access Time toca 150 ns OE Data Off Time toez 40 ns Qutput Hold from Address tou 10 ns READ CYCLE TIMING DIAGRAM el the = A0A10 <i tna i a a! ton icez jae # _ tcEA CE pai IcEL TOEA Lag icez_ 1 OE * ToEL DQo-Day L Ci VALID AAW 0707987 72DS1742 WRITE CYCLE, AC CHARACTERISTICS (OC to 70C; Veg = 5.0V + 10%) 70 ns access | 85 ns access | 100 ns access PARAMETER SYMBOL | MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES Write Cycle Time twe 70 85 100 ns Address Setup Time tas 0 0 0 ns WE Pulse Width twew 50 60 70 ns CE Pulse Width teew 55 65 75 ns Data Setup Time tos 30 35 40 ns Data Hold Time tpH 0 0 0 ns Address Hold Time taH 0 0 0 ns WE Data Off Time twez 25 30 35 ns Write Recovery Time twrR 5 5 5 ns WRITE CYCLE, AC CHARACTERISTICS (OC to 70C; Veg = 3.3V + 10%) 200 ns access PARAMETER SYMBOL MIN MAX UNITS NOTES Write Cycle Time twe 200 ns Address Setup Time tas 0 ns WE Pulse Width twew 150 ns CE Pulse Width toew 180 ns Data Setup Time tos 100 ns Data Hold Time tou 0 ns Address Hold Time tay 0 ns WE Data Off Time twez 40 ns Write Recovery Time twR 10 ns 070797 B82DS1742 WRITE CYCLE TIMING DIAGRAM,WRITE ENABLE CONTROLLED - two - AO-A10 VALID VALID wite| tas TAH leg ela wl tas c / | \ oat we! las le las _ twey 3t twr WE DQO-DQ7 DATA OUTPUT ips | DATA INPUT WRITE CYCLE TIMING DIAGRAM, CE, CONTROLLED aaa twe aol AOQ-A10 VALID VALID tas TAH beag-am tas CE twrR __ tas Lem Tas WE a IDH OI oo DATA INPUT | BATA INPUT Lg tos 070787 9112DS1742 POWER-UP/DOWN AC CHARACTERISTICS (OC to 70C; Veg = 5.0V, 3.3V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at Vin, tpp Q us Before Power-down Vec Fall Time: Vpp{MAx) to tr 300 ps Vpr (Min) Vee Fall Time: Vpr{MIN) to Veg tre 10 ps Voc Rise Time: VpF{MIN) to tr 0 ps Ver (MAX) Voc Rise Time: Vgq to Vpr(MIN) tRB 1 ps Powerup Recover Time trec 35 ms Expected Data Retention Time tor 10 years 5,6 (Oscillator On) POWER-DOWN/POWER-UP TIMING DIAGRAM Voc Vg (MAX Ver (MIN} Veo TT TR f 7 of lpr / i 7 of INPUTS DON'T CARE RECOGNIZED f f ? i HIGH-Z QUTPUTS 4 # VALID CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Capacitance on all input pins Cin 7 pF Capacitance on all output pins Co 10 pF O70797 10/12DS1742 AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0 Volts Timing Measurement Reference Levels: Input: 1.5 Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1. Voltages are referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Battery switch over occurs at the battery terminal voltage level. 5. Data retention time is at 25C. 6. Each DS1742 has a built-in switch that disconnects the lithium source until Vec is first applied by the user. The expected tp, is defined as a cumulative time in the absence of Ver starting from the time power is first applied by the user. 7. Real-Time Clock Modules can be successfully processed through conventional wavescldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal. o7o7e7 11/12DS1742 DS1742 24-PIN PACKAGE A Leo lhe elo ae HH * BO PKG 24-PIN DIM MIN MAX A IN. 1.270 1.290 MM 37.34 37.85 BIN. 0.875 0.700 MM 17.15 17.78 IN. 0.315 0.335 MM 3.00 8.51 DEIN. 0.075 0.105 MM 1.01 2.67 E IN. 0.015 0.030 MM 0.38 0.76 FIN. 0.140 0.180 MM 3.56 457 G IN. 0.090. 0.110 MM 2.29 279 H_ IN. 0.580, 0.630 MM 14.99 16.00 JIN. 0.010 0.018 MM 0.25 0.45 KIN. 0.015 0.025 MM 0.43 0.53 O7O797 12/12