Precision Micropower, OVP, RRIO
Operational Amplifier
ADA4091-2/ADA4091-4
Rev. F
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FEATURES
Single-supply operation: 3.0 V to 30 V
Wide input voltage range
Rail-to-rail output swing
Low supply current: 200 μA/amplifier
Wide bandwidth: 1.2 MHz
Slew rate: 0.46 V/μs
Low offset voltage: 250 μV maximum
No phase reversal
Overvoltage protection (OVP)
25 V above/below supply rails at ±5 V
12 V above/below supply rails at ±15 V
APPLICATIONS
Industrial process control
Battery-powered instrumentation
Power supply control and protection
Telecommunications
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifiers
GENERAL DESCRIPTION
The ADA4091-2 dual and ADA4091-4 quad are micropower,
single-supply, 1.2 MHz bandwidth amplifiers featuring rail-to-
rail inputs and outputs. They are guaranteed to operate from a
+3.0 V to +30 V single supply as well as from ±1.5 V to ±15 V
dual supplies.
The ADA4091 family features a unique input stage that allows
the input voltage to exceed either supply safely without any phase
reversal or latch-up; this is called overvoltage protection, or OVP.
Applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection,
and interface for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezo-
electric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output enables
designers, for example, to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios (SNR).
The ADA4091 family is specified over the extended industrial
temperature range of −40°C to +125°C. The ADA4091 family is
part of the growing selection of 36 V, low power op amps from
Analog Devices, Inc., (see Table 1).
PIN CONFIGURATIONS
OUTA
1
–INA
2
+INA
3
–V
4
+V
8
OUTB
7
–INB
6
+INB
5
ADA4091-2
TOP VIEW
(Not to Scale)
07671-001
Figure 1. 8-Lead, Narrow-Body SOIC (R-8)
1OUTA
2–INA
3+INA
4–V
7OUTB
8+V
6–INB
5+INB
TOP VIEW
07571-102
ADA4091-2
(Not to Scale)
NOTES
1. IT IS RECOMMENDED TO CONNECT THE
EXPOSED PAD TO V–.
Figure 2. 8-Lead LFCSP (CP-8-9)
07671-101
ADA4091-4
1
2
3
4
5
6
7
–INA
+INA
+V
OUTB
–INB
+INB
OUTA
14
13
12
11
10
9
8
–IND
+IND
–V
OUTC
–INC
+INC
OUTD
TOP VIEW
(Not to Scale)
Figure 3. 14-Lead TSSOP (RU-14)
07671-103
12
11
10
1
3
4
–IND
+IND
V–
9+INC
–INA
V+
2
+INA
+
INB
6
OUTB
5
–INB
7
OUTC
8
–INC
16 NC
15 OUTA
14 OUT
D
13 NC
TOP
VIEW
ADA4091-4
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED TO CONNECT THE
EXPOSED PAD TO V–.
Figure 4. 16-Lead LFCSP (CP-16-17)
The ADA4091-2 is available in 8-lead, plastic SOIC and 8-lead
LFCSP packages. The ADA4091-4 is available in 14–lead TSSOP
and 16-lead LFCSP surface-mount packages.
Table 1. Low Power, 36 V Operational Amplifiers
Family Rail-to-Rail I/O PJFET Low Noise
Single OP1177
Dual ADA4091-2 AD8682 OP2177
Quad ADA4091-4 AD8684 OP4177
ADA4091-2/ADA4091-4
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 14
Input Stage ................................................................................... 14
Output Stage ................................................................................ 14
Input Overvoltage Protection ................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 18
REVISION HISTORY
10/10—Rev. E. to Rev. F
Changes to Features Section and General Description Section . 1
Changes to Outline Dimensions ................................................... 17
5/10—Rev. D. to Rev. E
Changes to Data Sheet Title ............................................................ 1
Changes to Table 2, Input Characteristics, Offset Voltage .......... 3
Changes to Table 3, Input Characteristics, Offset Voltage .......... 4
Changes to Table 4, Input Characteristics, Offset Voltage .......... 5
4/10—Rev. C to Rev. D
Changes to Table 2, Added LFCSP to Input Characteristics ...... 3
Changes to Table 3, Added LFCSP to Input Characteristics ...... 4
Changes to Table 4, Added LFCSP to Input Characteristics ...... 5
10/09—Rev. B to Rev. C
Added 8-Lead LFCSP and 16-Lead LFCSP ..................... Universal
Change to Features Section ............................................................. 1
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 18
7/09—Rev. A to Rev. B
Added New Part ADA4091-4 ........................................... Universal
Changes to Features Section, General Description Section, and
Figure 4 ............................................................................................... 1
Added Figure 2, Renumbered Sequentially ................................... 1
Changes to Table 1 ............................................................................. 1
Changes to Table 2 ............................................................................. 3
Changes to Table 3 ............................................................................. 4
Changes to Table 4 ............................................................................. 5
Changes to Table 5 ............................................................................. 6
Changes to Table 6 ............................................................................. 6
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
7/09—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................. 1
Changes to Features .......................................................................... 1
Changes to Table 2 ............................................................................. 3
Changes to Table 3 ............................................................................. 4
Changes to Table 4 ............................................................................. 5
Added Input Current Parameter, Table 5 ....................................... 6
Added New Figure 12 and Figure 13, Renumbered
Sequentially ........................................................................................ 8
Added New Figure 24 and Figure 25 ........................................... 10
Added New Figure 36 and Figure 37 ........................................... 12
Added New Figure 43 .................................................................... 13
Changes to Input Overvoltage Protection Section ..................... 15
Changes to Ordering Guide .......................................................... 16
10/08—Revision 0: Initial Version
ADA4091-2/ADA4091-4
Rev. F | Page 3 of 20
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VSY = ±1.5 V, VCM = 0.0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS −250 −40 +250 μV
ADA4091-4 LFCSP package −400 −40 +400 μV
−40°C ≤ TA ≤ +125°C −600 +600 μV
Offset Voltage Drift ∆VOS/∆T 2.5 μV/°C
Input Bias Current IB −55 −44 nA
−40°C ≤ TA ≤ +85°C −55 +55 nA
−40°C ≤ TA ≤ +125°C −275 +275 nA
Input Offset Current IOS −3 0.5 +3 nA
−40°C ≤ TA ≤ +85°C −5 +5 nA
−40°C ≤ TA ≤ +125°C −75 +75 nA
Input Voltage Range −1.5 +1.5 V
Common-Mode Rejection Ratio CMRR VCM = −1.35 V to +1.35 V 84 100 dB
−40°C ≤ TA ≤ +125°C 78 dB
Large Signal Voltage Gain AVO RL = 100 kΩ, VO = −1.2 V to +1.2 V 106 113 dB
−40°C ≤ TA ≤ +125°C 101 dB
R
L = 10 kΩ, VO = −1.2 V to +1.2 V 92 94 dB
−40°C ≤ TA ≤ +125°C 85 dB
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 1.490 1.495 V
−40°C ≤ TA ≤ +125°C 1.490 V
R
L = 10 kΩ to GND 1.475 1.485 V
−40°C to +125°C 1.455 V
Output Voltage Low VOL RL = 100 kΩ to GND −1.499 −1.495 V
−40°C ≤ TA ≤ +125°C −1.495 V
R
L = 10 kΩ to GND −1.495 −1.490 V
−40°C ≤ TA ≤ +125°C −1.490 V
Short-Circuit Limit ISC Source/sink ±31 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 102 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 2.7 V to 36 V 108 126 dB
−40°C ≤ TA ≤ +125°C 100 dB
Supply Current per Amplifier ISY IO = 0 mA 165 200 μA
−40°C ≤ TA ≤ +125°C 300 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 100 kΩ, CL = 30 pF 0.46 V/μs
Settling Time tS To 0.01% 22 μs
Gain Bandwidth Product GBP 1.22 MHz
Phase Margin ΦM 69 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 μV p-p
Voltage Noise Density en f = 1 kHz 24 nV/√Hz
ADA4091-2/ADA4091-4
Rev. F | Page 4 of 20
VSY = ±5.0 V, VCM = 0.0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS −250 −45 +250 μV
ADA4091-4 LFCSP package −400 −40 +400 μV
−40°C ≤ TA ≤ +125°C −600 +600 μV
Offset Voltage Drift ∆VOS/∆T 2.5 μV/°C
Input Bias Current IB −60 −50 nA
−40°C ≤ TA ≤ +85°C −80 +80 nA
−40°C ≤ TA ≤ +125°C −350 +350 nA
Input Offset Current IOS −3 0.5 +3 nA
−40°C ≤ TA ≤ +85°C −7 +7 nA
−40°C ≤ TA ≤ +125°C −100 +100 nA
Input Voltage Range −5 +5 V
Common-Mode Rejection Ratio CMRR VCM = −4.85 V to +4.85 V 95 113 dB
−40°C ≤ TA ≤ +125°C 88 dB
Large Signal Voltage Gain AVO RL = 100 kΩ, VO = ±4.7 V 113 117 dB
−40°C ≤ TA ≤ +125°C 106 dB
R
L = 10 kΩ, VO = ±4.7 V 98 100 dB
−40°C ≤ TA ≤ +125°C 90 dB
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 4.980 4.990 V
−40°C ≤ TA ≤ +125°C 4.980 V
R
L = 10 kΩ to GND 4.950 4.960 V
−40°C ≤ TA ≤ +125°C 4.900 V
Output Voltage Low VOL RL = 100 kΩ to GND −4.998 −4.990 V
−40°C ≤ TA ≤ +125°C −4.980 V
R
L = 10 kΩ to GND −4.990 −4.980 V
−40°C ≤ TA ≤ +125°C −4.975 V
Short-Circuit Limit ISC Source/sink ±20 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 77 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 2.7 V to 36 V 108 126 dB
−40°C ≤ TA ≤ +125°C 100 dB
Supply Current per Amplifier ISY IO = 0 mA 180 225 μA
−40°C ≤ TA ≤ +125°C 300 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 100 kΩ, CL = 30 pF 0.46 V/μs
Settling Time tS To 0.01% 22 μs
Gain Bandwidth Product GBP 1.22 MHz
Phase Margin ΦM 70 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 μV p-p
Voltage Noise Density en f = 1 kHz 24 nV/√Hz
ADA4091-2/ADA4091-4
Rev. F | Page 5 of 20
VSY = ±15.0 V, VCM = 0.0 V, VO = 0.0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS −250 −35 +250 μV
ADA4091-4 LFCSP package −400 −40 +400 μV
−40°C ≤ TA ≤ +125°C −600 +600 μV
Offset Voltage Drift ∆VOS/∆T 3.0 μV/°C
Input Bias Current IB −60 −50 nA
−40°C ≤ TA ≤ +85°C −80 +80 nA
−40°C ≤ TA ≤ +125°C −510 +510 nA
Input Offset Current IOS −3 0.5 +3 nA
−40°C ≤ TA ≤ +85°C −10 +10 nA
−40°C ≤ TA ≤ +125°C −140 +140 nA
Input Voltage Range −15 +15 V
Common-Mode Rejection Ratio CMRR VCM = −14.85 V to +14.85 V 104 121 dB
−40°C ≤ TA ≤ +125°C 95 dB
Large Signal Voltage Gain AVO RL = 100 kΩ, VO = ±14.7 V 116 119 dB
−40°C ≤ TA ≤ +125°C 108 dB
R
L = 10 kΩ, VO = ±14.7 V 102 104 dB
−40°C ≤ TA ≤ +125°C 93 dB
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 100 kΩ to GND 14.975 14.980 V
−40°C ≤ TA ≤ +125°C 14.950 V
R
L = 10 kΩ to GND 14.900 14.920 V
−40°C ≤ TA ≤ +125°C 14.800 V
Output Voltage Low VOL RL = 100 kΩ to GND −14.996 −14.990 V
−40°C ≤ TA ≤ +125°C −14.985 V
R
L = 10 kΩ to GND −14.975 −14.950 V
−40°C ≤ TA ≤ +125°C −14.940 V
Short-Circuit Limit ISC Source/sink ±20 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 71 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 2.7 V to 36 V 108 126 dB
−40°C ≤ TA ≤ +125°C 100 dB
Supply Current per Amplifier ISY IO = 0 mA 200 250 μA
−40°C ≤ TA ≤ +125°C 350 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 100 kΩ, CL = 30 pF 0.46 V/μs
Settling Time tS To 0.01% 22 μs
Gain Bandwidth Product GBP 1.27 MHz
Phase Margin ΦM 72 Degrees
Channel Separation CS f = 1 kHz 100 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 μV p-p
Voltage Noise Density en f = 1 kHz 25 nV/√Hz
ADA4091-2/ADA4091-4
Rev. F | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage 36 V
Input Voltage Refer to the Input
Overvoltage Protection
section
Differential Input Voltage1 ±VSY
Input Current ±5 mA
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 Input current should be limited to ±5 mA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device soldered on a 4-layer JEDEC standard
PCB with zero airflow. The exposed pad is soldered to the
application board.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
8-Lead SOIC (R-8) 155 45 °C/W
14-Lead TSSOP (RU-14) 112 35 °C/W
8-Lead LFCSP (CP-8-9) 75 12 °C/W
16-Lead LFCSP (CP-16-17) 55 14 °C/W
ESD CAUTION
ADA4091-2/ADA4091-4
Rev. F | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
07671-034
V
OS
(µV)
NUMBER OF AMPLIFIERS
0
20
40
60
80
100
120
140
160
180
200
–250 –200 –150 –100 –50 0 50 100 150 200 250
ADA4091-2
T
A
= 25°C
V
SY
= ±1.5V
Figure 5. Input Offset Voltage Distribution
07671-035
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
0
50
100
150
200
250
300
ADA4091-2
–40°C T
A
+125°C
V
SY
= ±1.5V
–1012345678
Figure 6. TCVOS Distribution
–150
–100
–50
0
50
100
150
200
250
300
350
–1.5 –1.0 –0.5 0 0.5 1.0 1.5
07671-033
V
CM
(V)
I
B
(nA)
ADA4091-2
V
SY
= ±1.5V
–40°C +25°C
+85°C
+125°C
Figure 7. Input Bias Current vs. Common-Mode Voltage
0.1
0.001 0.01 0.1 1 10 100
1
10
100
10,000
1000
ADA4091-2
V
SY
= ±1.5V
07671-017
LOAD CURRENT (mA)
V
OUT
TO RAIL (mV)
V
OL
– V
SS
V
DD
– V
OH
Figure 8. Dropout Voltage vs. Load Current
–20
0
20
40
60
80
100
–20
0
20
40
60
80
100
GAIN
PHASE
1k 10k 100k 1M 10M
07671-007
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
ADA4091-2
V
SY
= ±1.5V
R
L
= 1M
C
L
= 35pF
Figure 9. Open-Loop Gain and Phase vs. Frequency
–20
–10
0
10
20
30
40
50
10 100 1k 10k 100k 1M 10M
ADA4091-2
VSY = ±1.5V
RL = 1M
CL = 35pF
A
V
= 100
AV = 10
AV = 1
07671-010
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
Figure 10. Closed-Loop Gain vs. Frequency
ADA4091-2/ADA4091-4
Rev. F | Page 8 of 20
AV = 100
AV = 10
AV = 1
ADA4091-2
TA = 25°C
VSY = ±1.5V
0.1
1
10
100
1k
10 100 1k 10k 100k 1M 10M
07671-013
FREQUENCY (Hz)
ZOUT ()
Figure 11. Output Impedance vs. Frequency
07671-025
TIME (µs)
V
OUT
(V)
ADA4091-2
V
SY
= ±1.5V
T
A
= 25°C
R
L
= 100k
C
L
= 100pF
A
V
= +1
0 5 10 15 20 25 30 35 40 45 50
2.0
–2.0
1.5
–1.5
1.0
–1.0
0.5
–0.5
0
Figure 12. Large Signal Transient Response
07671-028
TIME (µs)
V
OUT
(V)
0.06
–0.08
–0.06
0.04
–0.04
0.02
–0.02
0
01234567891011121314151617181920
ADA4091-2
V
SY
= ±1.5V
T
A
= 25°C
R
L
= 100k
C
L
= 100pF
A
V
= +1
Figure 13. Small Signal Transient Response
07671-036
FREQUENCY (Hz)
V
OUT
SWING (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
100 1k 10k 100k 1M
ADA4091-2
V
SY
= ±1.5V
V
IN
= 2.8V p-p
R
L
= 100k
Figure 14. Output Swing vs. Frequency
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0 102030405060708090
TIME (µs)
OUTPUT VOLTAGE (V)
07671-051
ADA4091-2
T
A
= 25°C
V
SY
= ±1.5V
Figure 15. Positive Overload Recovery
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
0 10203040 5060 708090
TIME (µs)
OUTPUT VOLTAGE (V)
07671-045
ADA4091-2
T
A
= 25°C
V
SY
= ±1.5V
Figure 16. Negative Overload Recovery
ADA4091-2/ADA4091-4
Rev. F | Page 9 of 20
0
25
50
75
100
125
150
175
200
225
07671-037
V
OS
(µV)
NUMBER OF AMPLIFIERS
–250 –200 –150 –100 –50 0 50 100 150 200 250
ADA4091-2
T
A
= 25°C
V
SY
= ±5V
Figure 17. Input Offset Voltage Distribution
07671-038
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
0
50
100
150
200
300
250
350
400
ADA4091-2
–40°C T
A
+125°C
V
SY
= ±5V
–1012345678
Figure 18. TCVOS Distribution
07671-026
ADA4091-2
V
SY
= ±5V
T
A
= 25°C
R
L
= 100k
C
L
= 100pF
A
V
= +1
TIME (µs)
V
OUT
(V)
0 5 10 15 20 25 30 35 40 45 50
6
–6
–4
4
–2
2
0
Figure 19. Large Signal Transient Response
01234567891011121314151617181920
07671-029
TIME (µs)
V
OUT
(V)
0.06
–0.08
–0.06
0.04
–0.04
0.02
–0.02
0ADA4091-2
V
SY
= ±5V
T
A
= 25°C
R
L
= 100k
C
L
= 100pF
A
V
= +1
Figure 20. Small Signal Transient Response
–5 –4 –3 –2 –1 0 3214
07671-032
V
CM
(V)
I
B
(nA)
5
–40°C
+85°C
+125°C
ADA4091-2
V
SY
= ±5V
–200
–100
0
100
200
300
400
500
+25°C
Figure 21. Input Bias Current vs. Common-Mode Voltage
GAIN
PHASE
1k 10k 100k 1M 10M
07671-005
FREQUENCY (Hz)
ADA4091-2
V
SY
= ±5V
R
L
= 1M
C
L
= 35pF
–20
0
20
40
60
80
100
–20
0
20
40
60
80
100
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
Figure 22. Open-Loop Gain and Phase vs. Frequency
ADA4091-2/ADA4091-4
Rev. F | Page 10 of 20
A
V
= 100
A
V
= 10
A
V
= 1 ADA4091-2
T
A
= 25°C
V
SY
= ±5V
0.1
1
10
100
1k
10 100 1k 10k 100k 1M 10M
07671-012
FREQUENCY (Hz)
Z
OUT
()
Figure 23. Output Impedance vs. Frequency
0
1
2
3
4
5
6
7
8
9
10
100 1k 10k 100k 1M
07671-015
FREQUENCY (Hz)
V
OUT
SWING (V)
ADA4091-2
V
SY
= ±5V
V
IN
= 9.8V p-p
R
L
= 100k
Figure 24. Output Voltage Swing vs. Frequency
0.1
0.001 0.01 0.1 1 10 100
1
10
100
10,000
1000
ADA4091-2
V
SY
= ±5V
07671-018
LOAD CURRENT (mA)
V
OUT
TO RAIL (mV)
V
OL
– V
SS
V
DD
– V
OH
Figure 25. Dropout Voltage vs. Load Current
–20
–10
0
10
20
30
40
50
10 100 1k 10k 100k 1M 10M
ADA4091-2
V
SY
= ±5V
R
L
= 1M
C
L
= 35pF
A
V
= 100
A
V
= 10
A
V
= 1
07671-009
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
Figure 26. Closed-Loop Gain vs. Frequency
6
5
4
3
2
1
0
0 102030405060708090
TIME (µs)
OUTPUT VOLTAGE (V)
07671-046
ADA4091-2
T
A
= 25°C
V
SY
= ±5V
Figure 27. Positive Overload Recovery
1
0
–1
–2
–3
–4
–5
–6
010 20 30 40 50 60 70 80
TIME (µs)
OUTPUT VOLTAGE (V)
07671-047
ADA4091-2
T
A
= 25°C
V
SY
= ±5V
Figure 28. Negative Overload Recovery
ADA4091-2/ADA4091-4
Rev. F | Page 11 of 20
0
50
100
150
200
250
07671-041
V
OS
(µV)
NUMBER OF AMPLIFIERS
–250 –200 –150 –100 –50 0 50 100 150 200 250
ADA4091-2
T
A
= 25°C
V
SY
= ±15V
Figure 29. Input Offset Voltage Distribution
0
50
100
150
200
250
300
350
07671-042
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
ADA4091-2
–40°C T
A
+125°C
V
SY
= ±15V
–1012345678
Figure 30. TCVOS Distribution
–300
–200
–100
0
100
200
300
400
500
600
700
–15 –10 –5 0 5 10 15
07671-031
V
CM
(V)
I
B
(nA)
ADA4091-2
V
SY
= ±15V
–40°C
+25°C
+85°C
+125°C
Figure 31. Input Bias Current vs. Common-Mode Voltage
GAIN
PHASE
1k 10k 100k 1M 10M
07671-006
FREQUENCY (Hz)
ADA4091-2
V
SY
= ±15V
R
L
= 1M
C
L
= 35pF
–20
0
20
40
60
80
100
–20
0
20
40
60
80
100
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
Figure 32. Open-Loop Gain and Phase vs. Frequency
07671-027
ADA4091-2
VSY = ±15V
TA = 25°C
RL = 100k
CL = 100pF
AV = +1
TIME (µs)
VOUT (V)
–25 0 25 50 75 100 125 150 175 200
20
–20
15
–15
10
–10
5
–5
0
Figure 33. Large Signal Transient Response
01234567891011121314151617181920
07671-030
TIME (µs)
V
OUT
(V)
0.06
–0.08
–0.06
0.04
–0.04
0.02
–0.02
0ADA4091-2
V
SY
= ±15V
T
A
= 25°C
R
L
= 100k
C
L
= 100pF
A
V
= +1
Figure 34. Small Signal Transient Response
ADA4091-2/ADA4091-4
Rev. F | Page 12 of 20
0
5
10
15
20
25
30
35
100 1k 10k 100k 1M
07671-016
FREQUENCY (Hz)
V
OUT
SWING (V)
ADA4091-2
V
SY
= ±15V
V
IN
= 29.8V p-p
R
L
= 100k
Figure 35. Output Voltage Swing vs. Frequency
0.1
0.001 0.01 0.1 1 10 100
1
10
100
10,000
1000
ADA4091-2
V
SY
= ±15V
07671-019
LOAD CURRENT (mA)
V
OUT
TO RAIL (mV)
V
OL
– V
SS
V
DD
– V
OH
Figure 36. Dropout Voltage vs. Load Current
0.1
1
10
100
1k
A
V
= 100
A
V
= 10
A
V
= 1 ADA4091-2
T
A
= 25°C
V
SY
= ±15V
10 100 1k 10k 100k 1M 10M
07671-011
FREQUENCY (Hz)
Z
OUT
()
Figure 37. Output Impedance vs. Frequency
–30
–20
–10
0
10
20
30
40
50
10 100 1k 10k 100k 1M 10M
ADA4091-2
V
SY
= ±15V
R
L
= 1M
C
L
= 35pF
A
V
= 100
A
V
= 10
A
V
= 1
07671-008
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
Figure 38. Closed-Loop Gain vs. Frequency
16
14
12
10
8
6
4
2
0
–2
0 102030405060708090
TIME (µs)
OUTPUT VOLTAGE (V)
07671-048
ADA4091-2
T
A
= 25°C
V
SY
= ±15V
Figure 39. Positive Overload Recovery
2
0
–2
–4
–6
–8
–10
–12
–14
–16
01020304050607080
TIME (µs)
OUTPUT VOLTAGE (V)
07671-049
ADA4091-2
T
A
= 25°C
V
SY
= ±15V
Figure 40. Negative Overload Recovery
ADA4091-2/ADA4091-4
Rev. F | Page 13 of 20
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
012345678910
ADA4091-2
V
SY
= ±15V
07671-043
TIME (Seconds)
NOISE (µV p-p)
Figure 41.Peak-to-Peak Voltage Noise
–130
–120
–110
–100
–90
–80
–70
–
60
100
07671-044
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
10 1k 10k 100k
ADA4091-2
V
SY
= ±15V
Figure 42. Channel Separation vs. Frequency
V
SY
= ±5V, ±15V
0
10
20
30
40
50
60
70
80
90
100
110
100 1k 10k 100k 1M 10M
ADA4091-2
07671-002
FREQUENCY (Hz)
CMRR (dB)
V
SY
= ±1.5V
Figure 43. CMRR vs. Frequency
–20
0
20
40
60
80
100
PSRR– PSRR+
100 1k 10k 100k 1M 10M
07671-003
FREQUENCY (Hz)
PSRR (dB)
ADA4091-2
V
SY
= ±1.5V, ±5V, ±15V
Figure 44. PSRR vs. Frequency
0
50
100
150
200
250
300
350
400
450
500
0 5 10 15 20 25 30 35
07671-004
V
SY
(V)
I
SY
(µA)
ADA4091-2
T
A
= 25°C
Figure 45. Supply Current vs. Supply Voltage
1k
100
10
0.01 0.1 1 10 100 1k
FREQUENCY (Hz)
VOLTAGE NOISE (nV/ Hz)
07671-050
ADA4091-2
T
A
= 25°C
V
SY
= ±5V
Figure 46. Voltage Noise Density
ADA4091-2/ADA4091-4
Rev. F | Page 14 of 20
THEORY OF OPERATION
The ADA4091 family is a single-supply, micropower amplifier
featuring rail-to-rail inputs and outputs. To achieve wide input
and output ranges, these amplifiers employ unique input and
output stages.
INPUT STAGE
In Figure 47, the input stage comprises two differential pairs, a
PNP pair (PNP input stage) and an NPN pair (NPN input
stage). These input stages do not work in parallel. Instead, only
one stage is on for any given input common-mode signal level.
The PNP stage (Transistor Q1 and Transistor Q2) is required to
ensure that the amplifier remains in the linear region when the
input voltage approaches and reaches the negative rail. Alter-
natively, the NPN stage (Transistor Q5 and Transistor Q6) is
needed for input voltages up to, and including, the positive rail.
For the majority of the input common-mode range, the PNP
stage is active, as shown in Figure 7, Figure 21, and Figure 31.
Notice that the bias current switches direction at approximately
1.5 V below the positive rail. At voltages below this level, the
bias current flows out of the ADA4091-x input, from the PNP
input stage. Above this voltage, however, the bias current enters
the device, due to the NPN stage. The actual mechanism within
the amplifier for switching between the input stages comprises
Transistor Q3, Transistor Q4, and Transistor Q7. As the input
common-mode voltage increases, the emitters of Q1 and Q2
follow that voltage plus a diode drop. Eventually, the emitters of
Q1 and Q2 are high enough to turn on Q3, which diverts the
tail current away from the PNP input stage, turning it off. The
tail current of the PNP pair is diverted to the Q4/Q7 current
mirror to activate the NPN input stage.
A common practice in bipolar amplifiers to protect the input
transistors from large differential voltages is to include series
resistors and differential diodes. See Figure 48 for the full input
protection circuitry. These diodes turn on whenever the diffe-
rential voltage exceeds approximately 0.6 V. In this condition,
current flows between the input pins, limited only by the two
5 kΩ resistors. Evaluate each application carefully to make sure
that the increase in current does not affect performance.
OUTPUT STAGE
The output stage in the ADA4091-x device uses a PNP and
an NPN transistor, as do most output stages. However, Q32
and Q33, the output transistors, connect with their collectors
to the output pin to achieve the rail-to-rail output swing.
As the output voltage approaches either the positive or negative
rail, these transistors begin to saturate. Thus, the final limit
on output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage has inherent gain arising
from the transistor output impedance, as well as any external load
impedance; consequently, the open-loop gain of the op amp is
dependent on the load resistance and decreases when the output
voltage is close to either rail.
07671-024
Q1
Q3
–IN
Q5 Q6
Q11
Q10Q8
Q7
Q4
Q13 Q15
Q14Q12
Q9
Q16 Q17
Q18 Q19
Q32
OUT
Q33
+IN Q2
Figure 47. Simplified Schematic Without Input Protection (see Figure 48)
ADA4091-2/ADA4091-4
Rev. F | Page 15 of 20
INPUT OVERVOLTAGE PROTECTION
The ADA4091-x has two different ESD circuits for enhanced
protection, as shown in Figure 48.
07671-023
D4
D3 D1
+V
–V
D2
D8
D7 R2 D5
R1
D6
Figure 48. Complete Input Protection Network
One circuit is a series resistor of 5 k to the internal inputs and
diodes (D1 and D2 or D5 and D6) from the internal inputs to
the supply rails. The other protection circuit is a circuit with
two DIACs (D3 and D4 or D7 and D8) to the supply rails. A
DIAC can be considered a bidirectional Zener diode with a
transfer characteristic, as shown in Figure 49.
–3
–2
–1
0
1
2
3
4
5
–40–50 –20 0 20 30–30 10–10 40 50
07671-100
VOLTAGE (V)
CURRENT (mA)
Figure 49. DIAC Transfer Characteristic
For a worst-case design analysis, consider two cases. The
ADA4091-x has a normal ESD structure from the internal op
amp inputs to the supply rails. In addition, it has 42 V DIACs
from the external inputs to the rails, as shown in Figure 47.
Therefore, two conditions need to be considered to determine
which case is the limiting factor.
• Condition 1. Consider, for example, that when operating
on ±15 V, the inputs can go +42 V above the negative
supply rail. With the −V pin equal to −15 V, +42 V above
this supply (the negative supply) is +27 V.
• Condition 2. There is a restriction on the input current of
5 mA through a 5 k resistor to the ESD structure to the
positive rail. In Condition 1, +27 V through the 5 k
resistor to +15 V gives a current of 2.4 mA. Thus, the
DIAC is the limiting factor. If the ADA4091-x supply
voltages are changed to ±5 V, then −5 V + 42 V = +37 V.
However, +5 V + (5 k × 5 mA) = 30 V. Thus, the normal
resistor diode structure is the limitation when running on
lower supply voltages.
Additional resistance can be added externally in series with
each input to protect against higher peak voltages; however, the
additional thermal noise of the resistors must be considered.
The flatband voltage noise of the ADA4091-x is approximately
24 nV/√Hz, and a 5 k resistor has a noise of 9 nV/√Hz. Adding
an additional 5 k resistor increases the total noise by less than
15% root sum square (rss). Therefore, maintain resistor values
below this value (5 k) when overall noise performance is critical.
Note that this represents input protection under abnormal con-
ditions only. The correct amplifier operation input voltage range
(IVR) is specified in Table 2, Table 3, and Table 4.
ADA4091-2/ADA4091-4
Rev. F | Page 16 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
051909-A
1
EXPOSED
PAD
BOTTOM VIEW
0.50
BSC
PIN 1
INDICATOR
0.50
0.40
0.30
TOP VIEW
12° MAX 0.70 MAX
0.65 TYP
0.90 MAX
0.85 NOM 0.05 MAX
0.01 NOM
0.20 REF
2.23
2.13
2.03
4
1.60
1.50
1.40
3.25
3.00 SQ
2.75
2.95
2.75 SQ
2.55
58
PIN 1
INDICATOR
SEATING
PLANE
0.30
0.23
0.18
0.60 MAX
0.60 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-9)
Dimensions shown in millimeters
ADA4091-2/ADA4091-4
Rev. F | Page 17 of 20
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
2.70
2.60 SQ
2.50
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
012909-B
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDI
C
ATOR
0.35
0.30
0.25
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions are millimeters
ADA4091-2/ADA4091-4
Rev. F | Page 18 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADA4091-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADA4091-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADA4091-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADA4091-2ACPZ-R2 −40°C to +125°C 8-Lead Frame Chip Scale Package (LFCSP_VD) CP-8-9 A1Z
ADA4091-2ACPZ-R7 −40°C to +125°C 8-Lead Frame Chip Scale Package (LFCSP_VD) CP-8-9 A1Z
ADA4091-2ACPZ-RL −40°C to +125°C 8-Lead Frame Chip Scale Package (LFCSP_VD) CP-8-9 A1Z
ADA4091-4ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
ADA4091-4ARUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14
ADA4091-4ACPZ-R2 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-17
ADA4091-4ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-17
ADA4091-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-16-17
1 Z = RoHS Compliant Part.
ADA4091-2/ADA4091-4
Rev. F | Page 19 of 20
NOTES
ADA4091-2/ADA4091-4
Rev. F | Page 20 of 20
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07671-0-10/10(F)
