Low Voltage CTCSS Encoder/Decoder 4 MX465
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2 Signal List
Pin No. Signal Type Description
1 VDD power Positive supply. This pin should be bypassed to VSS by
a capacitor mounted close to the device pins.
2 XTAL/CLOCK input Input to the on-chip inverter used with a 4 MHz Xtal or
external clock source.
3
output Output of the on-chip inverter (clock output).
4 LATCH/LOAD input Controls 8 on-chip latches. It is used to latch
,
PTL, and D0-D5. A logic 1 applied to this input places
the 8 latches in the ‘transparent’ mode. A logic 0 applied
to this input places the 8 latches in the ‘latched’ mode. In
Parallel Mode, data is loaded and latched by a logic 1-0
transition (see Figure 4). In Serial Mode, data is loaded
and latched by a 0-1-0 strobe pulse on this pin (see
Figure 5). Internally pulled to VDD
5 D5 / SERIAL ENABLE 1 input Data input D5 (Parallel Mode). A logic 1 applied to this
input together with a logic 0 applied to
will place the device in Serial
Mode (see Figure 5). Internally pulled to VDD.
6 D4/SERIAL ENABLE 2 input Data input D4 (Parallel Mode). A logic 0 applied to this
input together with a logic 1 applied to D5 / SERIAL
ENABLE 1 will place the device in Serial Mode
(see Figure 5). Internally pulled to VDD.
7 D3 / SERIAL DATA IN input Data input D3 (Parallel Mode). In Serial Mode this pin
becomes the serial data input for D5-D0, TXRX/ and
PTL (see Figure 5). D5 is clocked first and PTL last.
Internally pulled to VDD.
8 D2 / SERIAL CLOCK input Data input D2 (Parallel Mode). In Serial Mode this pin
becomes the SERIAL CLOCK input. Data is clocked on
the positive going edge (see Figure 5). Internally pulled
to VDD.
9 D1 input Data input D1 (Parallel Mode). Internally pulled to VDD.
10 D0 input Data input D0 (Parallel Mode). Internally pulled to VDD.
11 VSS power Negative supply.
12 DECODE COMPARATOR
REF. input Internally biased to VDD/3 or 2 VDD/3 via 1M resistors
depending on the logic state of the
pin.
= 1 will
bias this input 2 VDD/3; a logic 0 will bias this input VDD
This input provides the DECODE COMPARATOR
REFERENCE voltage, and the switching of bias voltages
provides hysteresis to reduce ‘chatter’ under marginal
conditions.
13 RX TONE DECODE output Gated output of the decode comparator. This output is
used to gate the RX Audio path. A logic 0 on this pin
indicates a successful decode and the DECODE
COMPARATOR IN pin is more positive than the
DECODE COMPARATOR REF. input (see Table 3).
14 DECODE COMPARATOR IN input Inverting input of the DECODE COMPARATOR. This pin
is normally connected to the integrated output of the RX
TONE DETECT line.