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FEATURES
APPLICATIONS
DESCRIPTION
PC
DVD Player
STB
Digital TV
or
Game
Machine
TMDS
341A
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
3-TO-1 DVI/HDMI SWITCH
Exceeds 5 kV•Compatible with HDMI 1.3a •3.3-V Supply Operation•Supports 2.25 Gbps Signaling Rate for 480i/p, •80-Pin TQFP Package720i/p, and 1080i/p Resolutions up to 12-Bit
•ROHS Compatible and 260 °C Reflow RatedColor Depth•Each Port Supports HDMI or DVI Inputs
•Switching From Three Digital-Video (DVI) or•Isolated Digital Display Control (DDC) Bus for
Digital-Audio Visual (HDMI) SourcesUnused Ports
•Digital TV•5-V Tolerance to all DDC and HPD_SINK
•Digital ProjectorInputs
•Audio Video Receiver•Integrated Receiver Termination•Inter-Pair Output Skew < 100 ps•Intra-Pair Skew < 50 ps•8-dB Receiver Equalization to Compensate for5-m DVI Cable Losses•High Impedance Outputs When Disabled•TMDS Inputs HBM ESD Protection
The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch thatallows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plugdetector, and an I
2
C interface are supported on each port. Each TMDS channel allows signaling rates up to 2.25Gbps.
The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs fromeach port are switched through a 3-to-1 multiplexer. The I
2
C interface of the selected input port is linked to theI
2
C interface of the output port, and the hot plug detector (HPD) of the selected input port is output toHPD_SINK. For the unused ports, the I
2
C interfaces are isolated, and the HPD pins are kept low.
Termination resistors (50- Ω), pulled up to V
CC
, are integrated at each receiver input pin. External terminationsare not required. A precision resistor is connected externally from the VSADJ pin to ground for setting thedifferential output voltage to be compliant with the TMDS standard. When the output is connected to a standardTMDS termination and OE is high, the output is high impedance.
The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimizesystem performance through 5-meter or longer DVI compliant cables. The device is characterized for operationfrom 0 °C to 70 °C.
Typical Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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PRE
VSADJ
Y4
Z4
Y3
Z3
Y2
Z2
Y1
Z1
S1
S2
S3
HPD_SINK
SCL_SINK
SDA_SINK
SDA3
SCL3
SDA2
SCL2
SDA1
SCL1
HPD3
HPD2
HPD1
B31
A31
B32
A32
B33
A33
B34
A34
B21
A21
B22
A22
B23
A23
B24
A24 Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Control Logic
3−to−1 MUX TMDS
Drive
TMDS
Drive
TMDS
Drive
TMDS
Drive
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
Rx w/
EQ
VCC (3.3 V)
VCC
VCC
VCC
VCC
VCC
VCC
VCC (3.3 V)
VCC (3.3 V)
A11
B11
A12
B12
A13
B13
A14
B14
RINT
RINT
RINT
RINT
RINT
RINT
RINT
RINT
RINT
RINT
RINT
RINT
OE
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
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HPD2
SDA2
SCL2
GND
GND
B21
A21
B22
A22
GND
B23
A23
V
B24
A24
GND
HPD1
NC
OE
HPD3
SDA3
SCL3
GND
B31
A31
B32
A32
GND
B33
A33
B34
A34
GND
NC
HPD_SINK
SDA_SINK
SCL_SINK
GND
GND
Z1
Y1
Z2
Y2
GND
Z3
Y3
Z4
Y4
GND
S3
S2
S1
N C
PRE
V
G N D
A14
B14
A13
B13
A12
B12
A11
B11
GN D
SC L 1
SD A 1
CC
VCC
VCC
VCC
VCC
VCC
CC
VCC
VC C
VCC
VSADJ
2 3 4 5 6 7 8 9 10 11 12 131 14 15 16 17 18 19 20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
59 58 57 56 5560 54 52 51 5053 49 48 47 46 45 44 43 42 41
VCC
VCC
N C
G N D
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
PFC PACKAGE
(TOP VIEW)
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TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
A11, A12, A13, A14 6, 9, 12, 15 I Port 1 TMDS positive inputsA21, A22, A23, A24 68, 71, 74, 77 I Port 2 TMDS positive inputsA31, A32, A33, A34 49, 52, 55, 58 I Port 3 TMDS positive inputsB11, B12, B13, B14 5, 8, 11, 14 I Port 1 TMDS negative inputsB21, B22, B23, B24 67, 70, 73, 76 I Port 2 TMDS negative inputsB31, B32, B33, B34 48, 51, 54, 57 I Port 3 TMDS negative inputs4, 10, 16 24, 30,GND 36, 37, 47, 53, Ground59, 65, 66, 72, 78HPD1 80 O Port 1 hot plug detector outputHPD2 62 O Port 2 hot plug detector outputHPD3 44 O Port 3 hot plug detector outputSink side hot plug detector inputHPD_SINK 40 I High: 5-V power signal asserted from source to sink and EDID is readyLow: No 5-V power signal asserted from source to sink, or EDID is not readyNC 1, 20, 41,60 No connectOE 42 I Output enable, active lowOutput de-emphasis adjustmentPRE 19 I High: 3 dBLow: 0 dBSCL1 3 I/O Port 1 DDC bus clock lineSCL2 64 I/O Port 2 DDC bus clock lineSCL3 46 I/O Port 3 DDC bus clock lineSCL_SINK 38 I/O Sink side DDC bus clock lineSDA1 2 I/O Port 1 DDC bus data lineSDA2 63 I/O Port 2 DDC bus data lineSDA3 45 I/O Port 3 DDC bus data lineSDA_SINK 39 I/O Sink side DDC bus data lineS1, S2, S3 21, 22, 23 I Source selector input7, 13, 17 27, 33,V
CC
43, 50, 56 61, 69, Power supply75, 79VSADJ 18 I TMDS compliant voltage swing controlY1, Y2, Y3, Y4 34, 31, 28, 25 O TMDS positive outputsZ1, Z2, Z3, Z4 35, 32, 29, 26 O TMDS negative outputs
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TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
Table 1. Source Selection Lookup
(1)
CONTROL PINS I/O SELECTED HOT PLUG DETECT STATUS
SCL_SINKS1 S2 S3 Y/Z HPD1 HPD2 HPD3SDA_SINK
SCL1H x x A1/B1 HPD_SINK L LSDA1
SCL2L H x A2/B2 L HPD_SINK LSDA2
SCL3L L H A3/B3 L L HPD_SINKSDA3L L L None (Z) None (Z) L L L
(1) H: Logic high; L: Logic low; X: Don't care; Z: High impedance
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Z
TMDS Output Stage
Y
HPD output stageControl Input Stage
OE
HPD_SINK
PRE
S1, S2, S3
Vcc
HPD1
HPD2
HPD3
Vcc
TMDS Input Stage
25Ω
A B
Vcc
50Ω50Ω
25Ω
10 mA
400Ω
Vcc
SCL/SCA
Source SCL/SCA
Sink
DDC pass gate
8V 8V
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
ORDERING INFORMATION
(1)
PART NUMBER PART MARKING PACKAGE
TMDS341APFC TMDS341A 80-PIN TQFPTMDS341APFCR TMDS341A 80-PIN TQFP Tape/Reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range, V
CC
(2)
–0.5 V to 4 VAnm
(3)
, Bnm 2.5 V to 4 VVoltage range Ym, Zm, VSADJ, PRE, Sn, OE, HPDn –0.5V to 4 VSCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK –0.5 V to 6 VAnm, Bnm 5 kVHuman body model
(4)
All pins 4 kVElectrostatic
discharge
Charged-device model
(5)
(all pins) 1000 VMachine model
(6)
(all pins) 250 VSee Dissipation RatingContinuous power dissipation
Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) n = 1, 2, 3; m = 1, 2, 3, 4(4) Tested in accordance with JEDEC Standard 22, Test Method A114-B(5) Tested in accordance with JEDEC Standard 22, Test Method C101-A(6) Tested in accordance with JEDEC Standard 22, Test Method A115-A
DERATING FACTOR
(1)
T
A
= 70 °CPACKAGE T
A
≤25 °C
ABOVE T
A
= 25 °C POWER RATING
80-TQFP 1342 mW 13.42 mW/ °C 738 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VT
A
Operating free-air temperature 0 70 °C
TMDS DIFFERENTIAL PINS (A/B)
V
ID
Receiver peak-to-peak differential input voltage 150 1560 mVp-pV
IC
Input common mode voltage V
CC
–0.4 V
CC
+0.01 VR
VSADJ
Resistor for TMDS compliant voltage swing range 4.6 4.64 4.68 k ΩAV
CC
TMDS output termination voltage, see Figure 1 3 3.3 3.6 VR
T
Termination resistance, see Figure 1 45 50 55 ΩSignaling rate 0 2.25 Gbps
CONTROL PINS (PRE; S, OE)
V
IH
LVTTL High-level input voltage 2 V
CC
VV
IL
LVTTL Low-level input voltage GND 0.8 V
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
V
I(DDC)
Input voltage GND 5.5 V
STATUS PINS (HPD_SINK)
V
IH
LVTTL High-level input voltage 2 5.3 VV
IL
LVTTL Low-level input voltage GND 0.8 V
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ELECTRICAL CHARACTERISTICS
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IH
= V
CC
, V
IL
= V
CC
– 0.4 V, R
VSADJ
= 4.64 k Ω,R
T
= 50 Ω, AV
CC
= 3.3 VI
CC
Supply current 190 230 mAAm/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4A1/B1 = 165 MHz clock
V
IH
= V
CC
, V
IL
= V
CC
– 0.4 V, R
VSADJ
= 4.64 k Ω,R
T
= 50 Ω, AV
CC
= 3.3 VP
D
Power dissipation 394 657 mWAm/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4A1/B1 = 165 MHz clock
TMDS DIFFERENTIAL PINS (A/B; Y/Z)
V
OH
Single-ended high-level output voltage AV
CC
–10 AV
CC
+10 mV
V
OL
Single-ended low-level output voltage AV
CC
–600 AV
CC
–400 mV
V
swing
Single-ended output swing voltage 400 600 mVSee Figure 2 , AV
CC
= 3.3 V,V
OD(O)
Overshoot of output differential voltage 6% 15% 2 ×V
swingR
T
= 50 Ω, PRE = 0 VV
OD(U)
Undershoot of output differential voltage 12% 25% 2 ×V
swing
Change in steady-state common-mode∆V
OC(SS)
0.5 5 mVoutput voltage between logic states
0 V ≤V
CC
≤1.5 V,I
(O)OFF
Single-ended standby output current –10 10 µAAV
CC
= 3.3 V, R
T
= 50 Ω
|I
(OS)
| Short circuit output current See Figure 3 12 mA
Steady state output differential voltage with
See Figure 4 , PRE = V
CC
,V
ODE(SS)
560 840 mVp-pde-emphasis
Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4A1/B1 = 25 MHz clockV
ODE(pp)
Peak-to-peak output differential voltage 800 1200 mVp-p
Single-ended input voltage under highV
I(open)
I
I
= 10 µA V
CC
–10 V
CC
+10 mVimpedance input or open input
R
INT
Input termination resistance V
IN
= 2.9 V 45 50 55 Ω
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
|I
lkg
| Input leakage current V
I
= 0.1 V
CC
to 0.9 V
CC
to isolated DDC ports 0.1 2 µA
C
IO
Input/output capacitance V
I
= 0 V 7.5 pF
R
ON
Switch resistance I
O
= 3 mA, V
O
= 0.4 V 25 50 Ω
V
PASS
Switch output voltage V
I
= 3.3 V, I
O
= 100 µA 1.5
(2)
2.0 2.5
(3)
V
STATUS PINS (HPD)
V
OH(TTL)
TTL High-level output voltage I
OH
= –8 mA 2.4 V
V
OL(TTL)
TTL Low-level output voltage I
OL
= 8 mA 0.4 V
CONTROL PINS (PRE, S, OE)
|I
IH
| High-level digital input current V
IH
= 2 V or V
CC
0.1 2 µA
|I
IL
| Low-level digital input current V
IL
= GND or 0.8 V 0.1 2 µA
STATUS PINS (HPD_SINK)
V
IH
= 5.3 V 23 100|I
IH
| High-level digital input current µAV
IH
= 2 V or V
CC
0.1 2
|I
IL
| Low-level digital input current V
IL
= GND or 0.8 V 0.1 2 µA
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) The value is tested in full temperature range at 3.0 V.(3) The value is tested in full temperature range at 3.6 V.
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SWITCHING CHARACTERISTICS
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
TMDS DIFFERENTIAL PINS (Y/Z)
t
PLH
Propagation delay time, low-to-high-level output 250 800 ps
t
PHL
Propagation delay time, high-to-low-level output 250 800 ps
t
r
Differential output signal rise time (20% - 80%) 75 240 ps
t
f
Differential output signal fall time (20% - 80%) 75 240 psSee Figure 2 , AV
CC
= 3.3 V,R
T
= 50 Ω, PRE = 0 Vt
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) 7 50 ps
t
sk(D)
Intra-pair differential skew, see Figure 5 23 50 ps
t
sk(o)
Inter-pair channel-to-channel output skew
(2)
100 ps
t
sk(pp)
Part-to-part skew (3)
200 ps
t
jit(pp)
Peak-to-peak output jitter from Y/Z(1) residual jitter See Figure 8 , PRE = 0 V 15 30 psAm/Bm = 1.65 Gbps HDMI data pattern,m = 2, 3, 4t
jit(pp)
Peak-to-peak output jitter from Y/Z(2:4) residual jitter 18 50 psA1/B1 = 165 MHz clock
t
jit(pp)
Peak-to-peak output jitter from Y/Z(1) residual jitter See Figure 8 , PRE = 0 V 20 22 psAm/Bm = 2.25 Gbps HDMI data pattern,m = 2, 3, 4t
jit(pp)
Peak-to-peak output jitter from Y/Z(2:4) residual jitter 38 78 psA1/B1 = 225 MHz clock
See Figure 4 , PRE = V
CCAm/Bm = 250 Mbps HDMI data pattern,t
PRE
De-emphasis duration 240
(4)
psm = 2, 3, 4A1/B1 = 25 MHz clock
t
SX
Select to switch output 6 10 ns
t
en
Enable time See Figure 6 6 10 ns
t
dis
Disable time 6 10 ns
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
Propagation delay from SCLn to SCL_SINK or SDAn tot
pd(DDC)
See Figure 7 , C
L
= 10 pF 0.4 2.5 nsSDA_SINK or SDA_SINK to SDAn
CONTROL AND STATUS PINS (S, HPD_SINK, HPD)
t
pd(HPD)
Propagation delay (from HPD_SINK to the active port of HPD) 2 6.0 nsSee Figure 7 , C
L
= 10 pFt
sx(HPD)
Switch time (from port select to the latest valid status of HPD) 3 6.5 ns
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) t
sk(o)
is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device wheninputs are tied together.(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, orbetween channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the sametemperature, and have identical packages and test circuits.(4) The typical value is ensured by simulation.
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PARAMETER MEASUREMENT INFORMATION
TMDS
Driver
AVcc
RTRT
TMDS
Receiver
ZO = RT
ZO = RT
VOC(SS)
VOC
tPHL tPLH
100%
0V Differential
0%
80%
20%
tftr
VID 0.4 V
0 V
−0.4 V
VOD(O)
VOD(U)
VOD(pp)
VID
VID(pp)
Vcc
RINT RINT
TMDS
Receiver TMDS
Driver
Y
Z
A
B
AVcc
RT
RT
VID
VB
VAVY
VZ
CL
0.5 pF
VA
VB
Vcc
Vcc−0.4 V
VYVZ
swing = −
V
VID = −
V VBA
n
DC Coupled Vcc+0.2 V
Vcc−0.2 V
AC Coupled
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
Figure 1. Termination for TMDS Output Driver
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
< 100 ps, 100 MHz fromAgilent 81250. C
L
includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurementequipment provides a bandwidth of 20 GHz minimum.
Figure 2. Timing Test Circuit and Definitions
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VOD(pp) V
ODE(SS)
20%
80%
tPRE
1 bit 1 to N bit
50%
VOL
tsk(D)
VY
VZ
VOH
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Short Circuit Output Current Test Circuit
Figure 4. De-Emphasis Output Voltage Waveforms and Duration Measurement Definitions
Figure 5. Definition of Intra-Pair Differential Skew
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Input−1
Kept
High
Input−2/Input−3
Kept Low
A
B
A
B
S1 Clocking
S2 or S3
Kept High
Y
Z
Output
OE
tsx
tdis ten
tsx
Hi−Z75 mV
−75 mV 75 mV
−75 mV
3.3 V
0 V
VCC
2
0 V
VCC
2
3.3 V
tpd(HPD) tpd(HPD)
tsx(HPD)
tpd(DDC) tpd(DDC)
0 V
VCC
2
VCC
2
VCC
2
0 V
2.4 V
0.4 V
VCC
2
VCC
2
HPD_SINK
HPD1
HPD2
HPD3
S1
S2
S3
SDA_SINK
SDA1
SDA2
SDA3
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. TMDS Outputs Control Timing Definitions
Figure 7. HPD Timing Definitions
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Data +
Data −
Clk+
Clk−
Video Patterm
Generator
1000 mVpp
Differential
Coax
Coax
Coax
Coax
Coax
Coax
Coax
Coax
<2” 50 Ω
Transmission Line
5m 28AWG
HDMI Cable TMDS341A
RX
+
EQ
M
U
X
OUT
0dB
RX
+
EQ
M
U
X
OUT
0dB
<2” 50Ω
Transmission Line
<2” 50 Ω
Transmission Line
<2” 50 Ω
Transmission Line
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
AVcc
RTRT
AVcc
RTRT
Jitter Test
Instrument
Jitter Test
Instrument
TP3TP2TP1
TMDS341 input equalization gain vs. 5m DVI/HDMI cable response
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
f − Frequency − MHz
Gain − dB
Inversed TMDS341 EQ Gain
28 AWG 5m HDMI Cable
28 AWG 5m DVI Cable
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A. All jitters are measured in BER of 10
-12
B. The residual jitter reflects the total jitter measured at the TMDS341A output, TP3, subtract the total jitter from thesignal generator, TP1
Figure 8. Jitter Test Circuit
Figure 9 shows the frequency loss response from a 5m 28AWG HDMI cable and a 5m 28AWG DVI cable. TheTMDS341A built-in passive input equalizer compensates for ISI. For an 8-dB loss HDMI cable, the TMDS341Atypically reduces jitter by 60 ps from the device input to the device output.
Figure 9. S-Parameter Plots of 5-m DVI and HDMI Cables
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TYPICAL CHARACTERISTICS
185
187
189
191
193
195
0 10 20 30 40 50 60 70
I -SupplyCurrent-mA
CC
T -Free-AirTemperature-C
A
V = AV =3.3V,
TP1V =800mV,R =4.64K
Input(2:4)2.2 HDMIDataPattern
Input(1)165MHz
CC CC
ID(PP) VSADJ W
5Gbps
Clock
160
170
180
190
200
210
220
230
25 45 65 75 85 105 145 165
f-Frequency-MHz
I -SupplyCurrent-mA
CC
V = AV =3.3V,T =25C,
TP1V =800mV ,R =4.64K
PRE= =Low
Input(2:4)HDMIDataPattern,250Mbps-2.25Gbps
Input(1)Clock,25MHz-165Mhz
CC CC
ID(PP) p-p VSADJ
A
W
OE
0
2
4
6
8
200 250 450 650 750 850 1050 1250 1450 1650
DataRate-Mbps
ResidualDeterministicJitter-%UnitInterval
1mHDMICable
3mHDMICable
5mHDMICable
V = AV =3.3V,T =25°C,
TP1V =800mV,R =4.64K
PRE= =Low,Sourcejitter=180ps
CC CC
ID(PP) VSADJ
A
W
OE
0
1
2
3
20 25 45 65 75 85 105 125 145 165
ClockFrequency-MHz
ResidualPeak-PeakJitter-%UnitInterval
5mHDMICable
1mHDMICable
3mHDMICable
V = AV =3.3V,T =25°C,
TP1V =800mV ,R =4.64K
PRE= =Low,Sourcejitter=150ps
CC CC
ID(PP) p-p VSADJ
A
W
OE
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
SUPPLY CURRENT SUPPLY CURRENTvs vsFREQUENCY FREE-AIR TEMPERATURE
Figure 10. Figure 11.
RESIDUAL DETERMINISTIC JITTER RESIDUAL PEAK-TO-PEAK JITTERvs vsDATA RATE CLOCK FREQUENCY
Figure 12. Figure 13.
14
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-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
Peak-to-PeakDifferentialInputVoltage-mVp-p
ResidualPeak-PeakJitter-%UnitInterval
74.25MHz
148.5MHz
150 350 550 750 950 1150 15501350
27MHz
V = AV =3.3V,T =25°C,
R =4.64K PRE= =Low
CC CC
VSADJ
A
W, OE
-3
-2
-1
1
0
2
3
4
5
6
7
8
9
10
150 350 550 750 950 1150 1350 1550
Peak-to-PeakDifferentialInputVoltage-mVp-p
ResidualDeterministicJitter-%UnitInterval
1485Mbps
742.5Mbps
270Mbps
V = AV =3.3V,T =25°C,
R =4.64K PRE= =Low
CC CC
VSADJ
A
W, OE
ResidualDeterministicJitter-%UnitInterval
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5 7 11 15 19
FR4PCBTrace-Inch
270Mbps
742.5Mbps
1485Mbps
V = AV =3.3V,T =25°C,
TP1V =800mV,R =4.64K
PRE=High, =Low,
5-m28 AWGHDMICable
CC CC
ID(PP) VSADJ
A
W
OE
0
ResidualPeak-PeakJitter-%UnitInterval
0
0.5
2.0
2.5
3.5
4
5711 15 19
FR4PCBTrace-Inch
27MHz
74.25MHz
148.5MHz
V = AV =3.3V,T =25°C,
TP1V =800mV,R =4.64K
PRE=High, =Low,5-m28 AWGHDMICable
CC CC
ID(PP) VSADJ
A
W
OE
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
RESIDUAL DETERMINISTIC JITTER RESIDUAL PEAK-TO-PEAK JITTERvs vsDIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE
Figure 14. Figure 15.
RESIDUAL DETERMINISTIC JITTER RESIDUAL PEAK-TO-PEAK JITTERvs vsFR4 PCB TRACE (at 3dB Pre-Emphasis) FR4 PCB TRACE (at 3dB Pre-Emphasis)
Figure 16. Figure 17.
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0
4
8
12
16
20
750 950 1150 1485 1650 1850 2250
Clock Frequency - MHz
ResidualPeak-PeakJitter-%UnitInterval
3m30 AWG
5m28 AWG
Channels2,3,4,
V = AV =3.3V,T =25°C,
Tp1V =1000mV ,
720p/1080i8-Bit=742.5Mbps,
720p/1080i12-Bit=1113.75Mbps,
1080p8-Bit=1485Mbps,
1080p12-Bit=2227.5Mbps
CC CC
ID(PP) p-p
AR =4.64K
PRE= =Low,
VSADJ W,
OE
0
1
2
3
4
5
75 95 115 148.5 165 185 225
Clock Frequency - MHz
ResidualPeak-PeakJitter-%UnitInterval
5m28 AWG
3m30 AWG
Channel1,
V = AV =3.3V,T =25°C,
Tp1V =1000mV
CC CC
ID(PP) p-p
AR =4.64K
PRE= =Low,
VSADJ W,
OE
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
RESIDUAL PEAK-TO-PEAK JITTER RESIDUAL PEAK-TO-PEAK JITTER(Data Channels) (Clock Channel)vs vsCLOCK FREQUENCY CLOCK FREQUENCY
Figure 18. Figure 19.
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HDMI Cables Running at 165-MHz Pixel Clock
Video
Format
Generator
TMDS341A TestBoard
TMDS
341A
TP1 TP2 TP3
28 AWGHDMICable
1-m Cable Length Eye Patterns
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Figure 20. 1-m and 5-m HDMI Cable Test Point Configuration
Figure 21. Clock at TP1 Figure 22. Clock at TP2 Figure 23. Clock at TP3
Figure 24. Data at TP1 Figure 25. Data at TP2 Figure 26. Data at TP3
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5-m Cable Length Eye Patterns
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Figure 27. Clock at TP1 Figure 28. Clock at TP2 Figure 29. Clock at TP3
Figure 30. Data at TP1 Figure 31. Data at TP2 Figure 32. Data at TP3(DC-Coupled Input)
Figure 33. Data at TP3(AC-Coupled Input)
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APPLICATION INFORMATION
Supply Voltage
TMDS Inputs
TMDS Input Fail-Safe
VCC
RINT
RINT
TMDS
Receiver TMDS
Driver
RT
RT
Y
Z
A
B
AVCC
TMDS341A
TMDS Outputs
TMDS341A
VCC
GND
TMDS
Driver
AVCC
ZO = RT
ZO = RT
RT
RT
TMDS
Receiver
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
All V
CC
pins can be tied to a single 3.3-V power source. A 0.01-µF capacitor is connected from each V
CC
pindirectly to ground to filter supply noise.
Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Eachinput channel contains an 8-dB equalization circuit to compensate for cable losses. The voltage at the TMDSinput pins must be limited per the absolute maximum ratings. An unused input should not be connected toground as this would result in excessive current flow damaging the device.
TMDS input pins do not incorporate fail-safe circuits. An unused input channel can be externally biased toprevent output oscillation. One pin can be left open with the other grounded through a 1-k Ωresistor as shown inFigure 34 .
Figure 34. TMDS Input Fail-Safe Recommendation
A 1% precision resister, 4.64-k Ω, connected from VSADJ to ground is recommended to allow the differentialoutput swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA currentsink capability, which provides a typical 500-mV voltage drop across a 50- Ωtermination resistor.
Figure 35. TMDS Driver and Termination Circuit
As shown in Figure 35 , if V
CC
(TMDS341A supply) and AV
CC
(sink termination supply) are powered, the TMDSoutput signals are high impedance when OE is high. Normal operation is with both supplies active.
Also shown in Figure 35 , if V
CC
is on and AV
CC
is off, the TMDS outputs source a typical 5-mA current througheach termination resistor to ground. The terminations consume a total of 10 mW of power independent of theOE logical selection. When AV
CC
is powered on, normal operation ( OE controls output impedance) is resumed.
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HPD Pins
DDC Channels
Configuring the TMDS341A as a 2:1 Switch
Layout Considerations
Connecting Cables Longer Than 5 m
TMDS Signal Path
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
APPLICATION INFORMATION (continued)When the power source of the device, V
CC
, is off and the power source to termination, AV
CC
, is on, the outputleakage current (I
o(off)
) specification ensures leakage current is limited to 10-µA or less.
The PRE pin provides 3-dB de-emphasis, allowing output signal pre-conditioning to offset interconnect lossesfrom the TMDS341A outputs to a TMDS receiver. PRE is recommended to be low to the circuit design of astand-alone switch box.
The input of the HPD_SINK is 5-V tolerant, allowing direct connection to 5-V signals. The HPD pin outputresistance is 35- Ωtypically. A 1-k Ω10% resistor is recommended to be connected from an HPD pin at theTMDS341A to the HPD pin of the HDMI connector.
The DDC channels are designed with a bi-directional pass gate, providing 5-V signal tolerance. The 5-Vtolerance allows direct connection to a standard I
2
C bus. The level shifter between 3.3 V and 5 V I
2
C interfacecan be eliminated.
The TMDS341A can be configured as a 2-to-1 switch by pulling the source selector pin (S1, S2, S3) of thenon-active port low and leaving the corresponding TMDS inputs, SCL, SDA, and HPD pins open.
The high-speed TMDS inputs are the most critical paths for the TMDS341A. There are several considerations tominimize discontinuities on these transmission lines between the connectors and the device:•Maintain 100- Ωdifferential transmission line impedance into and out of the TMDS341A•Keep an uninterrupted ground plane beneath the high-speed I/Os•Keep the ground-path vias to the device as close as possible to allow the shortest return current path•Layout of the TMDS differential inputs should be with the shortest stubs from the connectors
When using the TMDS341A with cables longer than 5 m, the impact to the TMDS signal path as well as theDDC signal path must be considered.
The TMDS341A receiver equalization circuit provides the capability of compensating inter-symbol interference(ISI) losses in a 5-m 28-AWG DVI cable. Typical cable measurements indicate that the TMDS341A can drive a5-m 28-AWG HDMI cable and pass the eye mask at the output of a HDMI source (TP1) and a 10-m 28-AWGHDMI cable and pass the eye mask at the input of a HDMI sink (TP2). Figure 36 through Figure 39 show theeye mask measurement results.
Figure 36. Eye Diagram at Output 5-m 28-AWG Cable vs Figure 37. Eye Diagram Recovered by TMDS341A vs TP1TP1 Eye Mask Eye Mask
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DDC Signal Path
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
APPLICATION INFORMATION (continued)
Figure 38. Eye Diagram at Output 10-m 28-AWG Cable Figure 39. Eye Diagram Recovered by TMDS341A vs TP2vs TP2 Eye Mask Eye Mask
Observed I
2
C bus voltage is dependent on bus resistance, capacitance, and time. The transient bus voltage,when charging from a low state to a high state, can be calculated using equation (1).
V(t) = V
DD
(1 – e
–t/RC
) (1)
Where:
t is the time since the charging startedV
DD
is the pull-up termination voltageR is the total resistance on the I
2
C linkC is the total capacitance on the I
2
C link
In the I
2
C bus specification, version 2.1, the high-level threshold voltage is V
IH
= 0.7 V
DD
, and the low-levelthreshold voltage is V
IL
= 0.3 V
DD
.
From equation (1), the times to charge from a bus voltage of 0 V to the V
IH
and V
IL
levels are:
t
IH
= 1.204 × RCt
IL
= 0.357 × RC
The bus rise time (from 0.3 V
DD
to 0.7 V
DD
) is then given by equation (2):
t
r(30-70)
= t
IH
– t
IL
= 0.847 × RC (2)
The TMDS341A can be easily applied in stand-alone switch boxes and digital displays. The following sectionsshow the bus lengths that can be supported in each case.
Maximum Bus Lengths for Switch Applications
Figure 40 shows the TMDS341A being used as a stand-alone switch. Both pull-up resistors are decided by thesource and sink equipment. A 1.5-k Ωresistor at the source and a 47-k Ωresistor at the sink are recommended.
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SDAn
Switch Box
TMDS341A
SDA_Sink
VDDsink
Rupsink
Csink
Ccable2
CO
CI
Ccable1
Csource
VDDsource
Rupsource
Source Sink
Csource
Sink
TMDS341A
SDA_SinkSDAn
Source
Ccable Csink
DVI/HDMI RX
VDDsource
Rupsource
VDDsink
Rupsink
TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
APPLICATION INFORMATION (continued)
Figure 40. DDC Link from Source to Sink With External Switch Box
R
upsource
= 1.5-k Ωpull-up to 5 VR
upsink
= 47-k Ωpull-up to 5 VR
total
= R
upsource
// R
upsink
= 1.45 k ΩC
total
= C
source
// C
cable1
// C
i
// C
o
// C
cable2
// C
sink
For standard mode I
2
C, the frequency is at 100 kHz, and the transition time must be less than 1 µs. The totalallowable capacitance, C
total
, is then 814-pF. C
source
and C
sink
are limited by the HDMI specification to 50 pF.C
i/o
for the TMDS341A is 10 pF max. The total capacitance from DVI or HDMI cables, C
cable1
and C
cable2
,should then be less than 704 pF.Typical capacitance is 200 pF for a 28-AWG 5-m HDMI cable and 300 pF for a 28-AWG 5-m DVI cable. Therecommended total cable length is the length of cable 1, Lcable1, plus the length of cable 2, Lcable2. For a28-AWG DVI cable, the total cable length is 11 m; and for a 28-AWG HDMI cable, the total cable length is 17m.
This calculation is applicable to V
IH
≤V
pass
.
Maximum Bus Lengths for DTV Applications
Figure 41 shows the TMDS341A being used as a switch in a DTV and being placed on the same PCB board asthe DVI/HDMI receiver. Unlike Figure 40 , the output connector of the TMDS341A stand-alone switch and theinput connector of the sink are removed, which results in a lower capacitance in the DDC link and eliminates theimpedance discontinuity. However, the capacitance of the removed connectors is relatively small, relative to thetotal allowable capacitance. The results from the previous section Maximum Bus Lengths for Switch Applicationscan be reused if the pull-up resistors and capacitances have the same values. The recommended total cablelength is the length from source to sink.
Figure 41. DDC Link From Source to Sink Without External Switch Box
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TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
APPLICATION INFORMATION (continued)Table 2 summarizes the recommended cable lengths based on threshold voltages V
IH
= 0.7 V
DD
and V
IL
= 0.3V
DD
.
Table 2. Recommended Cable Lengths Under General Threshold Voltages, 0.7 V
DD
and 0.3 V
DD
, of a DDCInterface
DDC THRESHOLD VOLTAGE, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
TOTAL CABLE LENGTH (m)
SUGGESTED PULL-UP RESISTANCE (k Ω) CABLE TYPE SWITCH BOX Lcable1 + Lcable2 DIGITAL DISPLAY Lcable
28-AWG DVI 11 11R
upsource
= 1.5 k ΩR
upsink
= 47 k Ω
28-AWG HDMI 17 17
Applying the same methodology to the case of V
IH
= 1.9 V and V
IL
= 0.7 V, Table 3 summarizes therecommended cable lengths to meet the timing requirement of the DDC interface.
Table 3. Recommended Cable Lengths Under General Threshold Voltages, 1.9 V and 0.7 V, of a DDCInterface
DDC THRESHOLD VOLTAGE, V
IH
= 1.9 V, V
IL
= 0.7 V TOTAL CABLE LENGTH (m)
SUGGESTED PULL-UP RESISTANCE (k Ω) CABLE TYPE SWITCH BOX Lcable1 + Lcable2 DIGITAL DISPLAY Lcable
28-AWG DVI 16 16R
upsource
= 1.5 k ΩR
upsink
= 47 k Ω
28-AWG HDMI 24 24
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TMDS341A
SLLS702B – MAY 2006 – REVISED MARCH 2007
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (November 2006) to B Revision .......................................................................................... Page
•Changed signaling rate from 1.65 Gbps to 2.25 Gbps and color depth from 8-bit to 12-bit ............................................... 1•Changed 1.65 Gbps to 2.25 Gbps ........................................................................................................................................ 1•Changed from 1.65 Gbps to 2.25 Gbps ................................................................................................................................ 7•Added data channels residual peak-to-peak jitter curves ................................................................................................... 16•Added clock channel residual peak-to-peak jitter curves ................................................................................................... 16•Added A to the device on test board .................................................................................................................................. 17
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TMDS341APFC ACTIVE TQFP PFC 80 96 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMDS341APFCG4 ACTIVE TQFP PFC 80 96 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMDS341APFCR ACTIVE TQFP PFC 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMDS341APFCRG4 ACTIVE TQFP PFC 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Feb-2007
Addendum-Page 1
MECHANICAL DATA
MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK
4073177/B 11/96
40
21 0,13 NOM
0,25
0,75
0,45
Seating Plane
0,05 MIN
Gage Plane
0,27
41
0,17
20
60
1
61
80
SQ
SQ
12,20
13,80
14,20
11,80
9,50 TYP
1,05
1,20 MAX
0,95
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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