v1.5 IGLOO PLUS Low-Power Flash FPGAs (R) with Flash*Freeze Technology Features and Benefits Low Power * * * * * 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 W Power Consumption in Flash*Freeze Mode Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content * Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode * Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode Feature Rich * 30 k to 125 k System Gates * Up to 36 kbits of True Dual-Port SRAM * Up to 212 User I/Os Reprogrammable Flash Technology * * * * 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy * Segmented, Hierarchical Routing and Clock Structure Advanced I/O * 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--4 Banks per Chip on All IGLOO(R) PLUS Devices * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V * Selectable Schmitt Trigger Inputs * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Small-Footprint Packages across the IGLOO PLUS Family Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, One with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x18) Table 1-1 * IGLOO PLUS Product Family IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 System Gates 30 k 60 k 125 k Typical Equivalent Macrocells 256 512 1,024 VersaTiles (D-flip-flops) 792 1,584 3,120 Flash*Freeze Mode (typical, W) 5 10 16 RAM kbits (1,024 bits) - 18 36 4,608-Bit Blocks - 4 8 Secure (AES) ISP - Yes Yes 1k 1k 1k - 1 1 6 18 18 4 4 4 120 157 212 CS201, CS289 VQ128 CS201, CS289 VQ176 CS281, CS289 FlashROM Bits Integrated PLL in CCCs VersaNet Globals 1 2 I/O Banks Maximum User I/Os Package Pins CS VQ Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. The AGLP030 device does not support this feature. April 2009 (c) 2009 Actel Corporation I IGLOO PLUS Low-Power Flash FPGAs I/Os Per Package 1 IGLOO PLUS Devices AGLP030 AGLP060 Package AGLP125 Single-Ended I/Os CS201 120 157 - CS281 - - 212 CS289 120 157 212 VQ128 101 - - VQ176 - 137 - Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. Table 1-2 * Package Dimensions Package CS201 CS281 CS289 VQ128 VQ176 8x8 10 x 10 14 x 14 14 x 14 20 x 20 64 100 196 196 400 Pitch (mm) 0.5 0.5 0.8 0.4 0.4 Height (mm) 0.89 1.05 1.20 1.0 1.0 Length x Width (mm/mm) Nominal Area (mm II 2) v1.5 IGLOO PLUS Low-Power Flash FPGAs IGLOO PLUS Ordering Information AGLP125 V2 _ CS G 289 I Application (Temperature Range) Blank = Commercial (0C to +70C ambient temperature) I = Industrial (-40C to +85C ambient temperature) PP = Pre-Production ES = Engineering Sample (room temperature only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type CS = Chip Scale Package (0.5 mm and 0.8 mm pitches) VQ = Very Thin Quad Flat Pack (0.4 mm pitch) Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number AGLP030 = 30,000 System Gates AGLP060 = 60,000 System Gates AGLP125 = 125,000 System Gates Notes: 1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly. 2. "G" indicates RoHS-compliant packages. v1.5 III IGLOO PLUS Low-Power Flash FPGAs Temperature Grade Offerings Package AGLP030 AGLP060 AGLP125 CS201 C, I C, I - CS281 - - C, I CS289 C, I C, I C, I VQ128 C, I - - VQ176 - C, I - Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/company/contact/default.aspx. IV v1.5 1 - IGLOO PLUS Device Family Overview General Description The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultralow-power mode that consumes as little as 5 W while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low-power consumption while the IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, lowpower, single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212 user I/Os. The AGLP030 devices have no PLL or RAM support. Flash*Freeze Technology The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode. IGLOO PLUS devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state, tristate, or set as HIGH or LOW. The availability of low-power modes, combined with reprogrammability, a single-chip and singlevoltage solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS devices the best fit for portable electronics. Flash Advantages Low Power IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA. v1.5 1-1 IGLOO PLUS Device Family Overview Security The nonvolatile, flash-based IGLOO PLUS devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO PLUS devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO PLUS devices (except AGLP030) utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO PLUS devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO PLUS devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO PLUS devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO PLUS device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOO PLUS family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO PLUS family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOO PLUS device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO PLUS FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. The IGLOO PLUS devices can be operated with a 1.2 V or 1.5 V single-voltage supply for core and I/Os, eliminating the need for additional supplies while minimizing total power consumption. Live at Power-Up The Actel flash-based IGLOO PLUS devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO PLUS devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO PLUS device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO PLUS devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO PLUS flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 s), and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from external memory components; instead, it retains all necessary information to resume operation immediately. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based IGLOO PLUS devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field 1 -2 v1.5 IGLOO PLUS Low-Power Flash FPGAs upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO PLUS family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO PLUS family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO PLUS flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO PLUS FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO PLUS family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130 nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO PLUS family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO PLUS architecture provides granularity comparable to standard-cell ASICs. The IGLOO PLUS device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4): * Flash*Freeze technology * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO PLUS core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generationarchitecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface. The AGLP030 device does not support PLL or SRAM. v1.5 1-3 IGLOO PLUS Device Family Overview Bank 0 CCC* Bank 3 Bank 1 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os Bank 1 Bank 3 VersaTile ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 2 * Not supported by AGLP030 devices Figure 1-1 * IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and AGLP125) Flash*Freeze Technology The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 W in this mode. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of 1 -4 v1.5 IGLOO PLUS Low-Power Flash FPGAs entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned. Actel IGLOO PLUS FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-2 * IGLOO PLUS Flash*Freeze Mode VersaTiles The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOO PLUS VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 D-Flip-Flop with Clear or Set Y Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 1-3 * VersaTile Configurations User Nonvolatile FlashROM Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in AGLP030 devices), as in security keys stored in the FlashROM for a user design. v1.5 1-5 IGLOO PLUS Device Family Overview The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOO PLUS development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL. The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis (for PLL only) Additional CCC specifications: * 1 -6 Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) * Maximum acquisition time is 300 s (for PLL only) v1.5 IGLOO PLUS Low-Power Flash FPGAs * Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns (for PLL only) * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC (for PLL only) Global Clocking IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO PLUS FPGAs support many different I/O standards. The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and output enable registers. Wide Range I/O Support Actel IGLOO PLUS devices support JEDEC-defined wide range I/O operation. IGLOO PLUS devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. v1.5 1-7 IGLOO PLUS Device Family Overview Part Number and Revision Date Part Number 51700102-001-5 Revised April 2009 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.5) Page v1.4 (February 2009) The -F speed grade is no longer offered for IGLOO PLUS devices. The speed grade column and note regarding -F speed grade were removed from "IGLOO PLUS Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. III, IV v1.3 (December 2008) The "Advanced I/O" section was revised to add two bullets regarding support of wide range power supply voltage. I The "I/Os with Advanced I/O Standards" section was revised to add 3.0 V wide range to the list of supported voltages. The "Wide Range I/O Support" section is new. 1-7 A note was added to Table 1-1 * IGLOO PLUS Product Family: "AGLP060 in CS201 does not support the PLL." I Table 1-2 * Package Dimensions was updated to change the nominal size of VQ176 from 100 to 400 mm2. II v1.1 (July 2008) The VQ128 and VQ176 packages were added to Table 1-1 * IGLOO PLUS Product Family, the "I/Os Per Package 1" table, Table 1-2 * Package Dimensions, "IGLOO PLUS Ordering Information", and the "Temperature Grade Offerings" table. I to IV v1.0 (March 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A v1.2 (August 2008) 1 -8 v1.5 IGLOO PLUS Low-Power Flash FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v1.5 1-9 2 - IGLOO PLUS DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Symbol Absolute Maximum Ratings Parameter Limits Units VCC DC core supply voltage -0.3 to 1.65 V VJTAG JTAG DC voltage -0.3 to 3.75 V VPUMP Programming voltage -0.3 to 3.75 V VCCPLL Analog power supply (PLL) -0.3 to 1.65 V VCCI DC I/O buffer supply voltage -0.3 to 3.75 V VI I/O input voltage -0.3 V to 3.6 V (when I/O hot insertion mode is enabled) V -0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 Storage temperature -65 to +150 C 2 Junction temperature +125 C TJ Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. A dv a n c e v 0. 5 2-1 IGLOO PLUS DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions 4 Symbol Parameter Commercial 6 Industrial C TA Ambient temperature 0 to +70 TJ Junction temperature 8 0 to + 85 -40 to +100 C 1.425 to 1.575 1.425 to 1.575 V 1.14 to 1.575 1.14 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.45 0 to 3.45 V 1.4 to 1.6 1.4 to 1.6 V 1.14 to 1.575 1.14 to 1.575 V 1.14 to 1.26 1.14 to 1.26 V 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V VCC 3 1.5 V DC core supply voltage 1 1.2 V-1.5 V wide range core voltage VJTAG 2 JTAG DC voltage VPUMP 5 Programming voltage Programming mode Operation VCCPLL 9 1 Analog power supply (PLL) 1.5 V DC core supply voltage 1.2 V-1.5 V wide range core voltage 2 VCCI 1.2 V DC supply voltage 2 -40 to +85 Units 7 Notes: 1. For IGLOO(R) PLUS V5 devices 2. For IGLOO PLUS V2 devices only, operating at VCCI VCC 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-20 on page 2-19. VCCI should be at the same voltage within a given I/O bank. 4. All parameters representing voltages are measured with respect to GND unless otherwise specified. 5. VPUMP can be left floating during operation (not programming mode). 6. Maximum TJ = 85C. 7. Maximum TJ = 100C. 8. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel's timing and power simulation tools. 9. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information. Table 2-3 * Flash Programming Limits - Retention, Storage, and Operating Temperature 1 Program Retention Maximum Storage Maximum Operating Junction Product Grade Programming Cycles (biased/unbiased) Temperature TSTG (C) 2 Temperature TJ (C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2 -2 A dv a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Table 2-4 * Overshoot and Undershoot Limits 1 Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 2.7 V or less 10% 1.4 V 5% 1.49 V 3V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V VCCI 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOO PLUS device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. IGLOO PLUS I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on page 2-5). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * During programming, I/Os become tristated and weakly pulled up to VCCI. * JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. A dv a n c e v 0. 5 2-3 IGLOO PLUS DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V for V5 devices, and 0.75 V 0.2 V for V2 devices), the PLL output lock signal goes LOW and/or the output clock is lost. Refer to the "Brownout Voltage" section in the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V Figure 2-1 * V5 Devices - I/O State as a Function of VCCI and VCC Voltage Levels 2 -4 A dv a n c e v 0. 5 VCCI IGLOO PLUS DC and Switching Characteristics VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.2 V Deactivation trip point: Vd = 0.75 V 0.2 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V 0.15 V Deactivation trip point: Vd = 0.8 V 0.15 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI Figure 2-2 * V2 Devices - I/O State as a Function of VCCI and VCC Voltage Levels A dv a n c e v 0. 5 2-5 IGLOO PLUS DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 2-1 where: TA = Ambient temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction temperature is 100C. EQ 2-2 shows a sample calculation of the maximum operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. 100C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.46 W 20.5C/W ja (C/W) EQ 2-2 Table 2-5 * Package Thermal Resistivities ja Package Type Chip Scale Package (CSP) Pin Count jc Still Air 200 ft./ min. 500 ft./ min. Units 201 TBD TBD TBD TBD C/W 281 TBD TBD TBD TBD C/W 289 TBD TBD TBD TBD C/W Temperature and Voltage Derating Factors Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.425 V) For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Array Voltage VCC (V) Junction Temperature (C) -40C 0C 25C 70C 85C 110C 1.425 0.95 0.97 0.98 1.00 1.01 1.02 1.5 0.87 0.89 0.90 0.92 0.93 0.94 1.575 0.81 0.83 0.84 0.86 0.87 0.87 2 -6 A dv a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Table 2-7 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.14 V) For IGLOO PLUS V2, 1.2 V DC Core Supply Voltage Array Voltage VCC (V) Junction Temperature (C) -40C 0C 25C 70C 85C 110C 1.14 0.97 0.98 0.99 1.00 1.01 1.01 1.2 0.86 0.87 0.88 0.89 0.89 0.90 1.26 0.79 0.80 0.81 0.81 0.82 0.82 Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage. Actel recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* Typical (25C) Core Voltage AGLP030 AGLP060 AGLP125 Units 1.2 V 1.5 V 4 8 13 A 6 10 18 A * IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Table 2-9 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode (VCC = 0 V)* Core Voltage AGLP030 AGLP060 AGLP125 Units VCCI/VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V 1.7 1.7 1.7 A VCCI/VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.8 1.8 1.8 A VCCI/VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.9 1.9 1.9 A VCCI/VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.2 2.2 2.2 A VCCI/VJTAG = 3.3 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.5 2.5 2.5 A * IDD includes VCC, VPUMP, and VCCPLL currents. Table 2-10 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode (VCC, VCCI = 0 V)* Typical (25C) Core Voltage AGLP030 AGLP060 AGLP125 Units 1.2 V / 1.5 V 0 0 0 A * IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. A dv a n c e v 0. 5 2-7 IGLOO PLUS DC and Switching Characteristics Table 2-11 * Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 Core Voltage AGLP030 AGLP060 AGLP125 Units 1.2 V 6 10 13 A 1.5 V 16 20 28 A VCCI / VJTAG = 1.2 V (per bank) Typical (25C) 1.2 V 1.7 1.7 1.7 A VCCI / VJTAG = 1.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.8 1.8 1.8 A VCCI / VJTAG = 1.8 V (per bank) Typical (25C) 1.2 V / 1.5 V 1.9 1.9 1.9 A VCCI / VJTAG = 2.5 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.2 2.2 2.2 A VCCI / VJTAG = 3.3 V (per bank) Typical (25C) 1.2 V / 1.5 V 2.5 2.5 2.5 A ICCA Current 2 Typical (25C) ICCI or IJTAG Current 3 Notes: 1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution. 2. Includes VCC , VCCPLL, and VPUMP currents. 3. Per VCCI or VJTAG bank Power per I/O Pin Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings VCCI (V) Dynamic Power PAC9 (W/MHz) 1 3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.88 3.3 V LVTTL / 3.3 V LVCMOS - Schmitt Trigger 3.3 19.54 2.5 V LVCMOS 2.5 5.20 2.5 V LVCMOS - Schmitt Trigger 2.5 6.60 1.8 V LVCMOS 1.8 2.22 1.8 V LVCMOS - Schmitt Trigger 1.8 2.29 1.5 V LVCMOS (JESD8-11) 1.5 1.57 1.5 V LVCMOS (JESD8-11) - Schmitt Trigger 1.5 1.49 1.2 V LVCMOS 2 1.2 0.55 2 1.2 0.47 Single-Ended 1.2 V LVCMOS - Schmitt Trigger Notes: 1. PAC9 is the total dynamic power measured on VCCI. 2. Applicable to IGLOO PLUS V2 devices only. 2 -8 A dv a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Table 2-13 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 CLOAD (pF) VCCI (V) Dynamic Power PAC10 (W/MHz)2 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 128.60 2.5 V LVCMOS 5 2.5 72.14 1.8 V LVCMOS 5 1.8 36.94 5 1.5 25.65 5 1.2 15.22 Single-Ended 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PAC10 is the total dynamic power measured on VCCI. 3. Applicable for IGLOO PLUS V2 devices only. Power Consumption of Various Internal Resources Table 2-14 * Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Device Specific Dynamic Power (W/MHz) Parameter Definition AGLP125 AGLP060 AGLP030 PAC1 Clock contribution of a Global Rib 11.03 9.3 9.3 PAC2 Clock contribution of a Global Spine 0.81 0.81 0.41 PAC3 Clock contribution of a VersaTile row 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.11 PAC5 First contribution of a VersaTile used as a sequential module 0.057 PAC6 Second contribution of a VersaTile used as a sequential module 0.207 PAC7 Contribution of a VersaTile used as a combinatorial module 0.17 PAC8 Average contribution of a routing net 0.7 PAC9 Contribution of an I/O input pin (standard-dependent) PAC10 Contribution of an I/O output pin (standard-dependent) PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.70 A dv a n c e v 0. 5 See Table 2-12 on page 2-8. See Table 2-13. 2-9 IGLOO PLUS DC and Switching Characteristics Table 2-15 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Device -Specific Static Power (mW) Parameter Definition AGLP125 AGLP060 AGLP030 PDC1 Array static power in Active mode See Table 2-11 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-8 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7 PDC3 PDC4 2 PDC5 Static PLL contribution 1.84 Bank quiescent power (VCCI -dependent) See Table 2-11 on page 2-8 Notes: 1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or the SmartPower tool in Actel Libero(R) Integrated Design Environment (IDE). 2. Minimum contribution of the PLL when running at lowest frequency. Table 2-16 * Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Device-Specific Dynamic Power (W/MHz) Parameter Definition AGLP125 AGLP060 AGLP030 PAC1 Clock contribution of a Global Rib 7.07 5.96 5.96 PAC2 Clock contribution of a Global Spine 0.52 0.52 0.26 PAC3 Clock contribution of a VersaTile row 0.52 PAC4 Clock contribution of a VersaTile used as a sequential module 0.07 PAC5 First contribution of a VersaTile used as a sequential module 0.045 PAC6 Second contribution of a VersaTile used as a sequential module 0.186 PAC7 Contribution of a VersaTile used as a combinatorial module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-12 on page 2-8 PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-13 on page 2-9 PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.10 2 -1 0 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Table 2-17 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Device-Specific Static Power (mW) Parameter Definition AGLP125 AGLP060 AGLP030 PDC1 Array static power in Active mode See Table 2-11 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-8 on page 2-7 PDC4 2 Static PLL contribution PDC5 Bank quiescent power (VCCI -dependent) 0.90 See Table 2-11 on page 2-8 Notes: 1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or the SmartPower tool in Actel Libero IDE. 2. Minimum contribution of the PLL when running at lowest frequency. A dv a n c e v 0. 5 2 - 11 IGLOO PLUS DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * The number of PLLs as well as the number and the frequency of each output clock generated * The number of combinatorial and sequential cells used in the design * The internal clock frequencies * The number and the standard of I/O pins used in the design * The number of RAM blocks used in the design * Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-18 on page 2-14. * Enable rates of output buffers--guidelines are provided for typical applications in Table 2-19 on page 2-14. * Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-19 on page 2-14. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption--PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption--PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption--PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution--PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-18 on page 2-14. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-18 on page 2-14. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution--PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-18 on page 2-14. FCLK is the global clock signal frequency. 2 -1 2 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Combinatorial Cells Contribution--PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-18 on page 2-14. FCLK is the global clock signal frequency. Routing Net Contribution--PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-18 on page 2-14. FCLK is the global clock signal frequency. I/O Input Buffer Contribution--PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-18 on page 2-14. FCLK is the global clock signal frequency. I/O Output Buffer Contribution--POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate--guidelines are provided in Table 2-18 on page 2-14. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. RAM Contribution--PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations--guidelines are provided in Table 2-19 on page 2-14. PLL Contribution--PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. A dv a n c e v 0. 5 2 - 13 IGLOO PLUS DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. * The average toggle rate of an 8-bit counter is 25%: - Bit 0 (LSB) = 100% - Bit 1 = 50% - Bit 2 = 25% - ... - Bit 7 (MSB) = 0.78125% - Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-18 * Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-19 * Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 2 -1 4 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVCMOS 2.5V Output Drive Strength = 12 mA High Slew Rate Y tPD = 1.40 ns tPD = 0.89 ns tDP = 1.62 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output drive strength = 12 mA High slew rate tDP = 1.62 ns tPD = 1.98 ns Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Y LVTTL Output drive strength = 8 mA High slew rate tPY = 1.06 ns Input LVCMOS 2.5 V D tDP = 1.70 ns tPD = 1.24 ns Q Combinational Cell I/O Module (Non-Registered) Y tICLKQ = 0.63 ns tISUD = 0.18 ns LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 2.07 ns tPD = 0.86 ns Input LVTTL Clock Register Cell tPY = 0.85 ns D Combinational Cell Y Q I/O Module (Non-Registered) tPY = 1.15 ns D Q D tPD = 0.87 ns tCLKQ = 0.80 ns tSUD = 0.84 ns LVCMOS 1.5 V I/O Module (Registered) Register Cell Q tDP = 1.62 ns tCLKQ = 0.80 ns tSUD = 0.84 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.85 ns tPY = 0.85 ns LVTTL 3.3 V Output drive strength = 12 mA High slew rate tOCLKQ = 0.89 ns tOSUD = 0.18 ns Figure 2-3 * Timing Model Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices A dv a n c e v 0. 5 2 - 15 IGLOO PLUS DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (R) tPY (F) VCC 50% DIN GND 50% tDOUT tDOUT (R) (F) Figure 2-4 * Input Buffer Timing Model and Delays (example) 2 -1 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT tDOUT (R) D 50% VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) tDP (F) Figure 2-5 * Output Buffer Model and Delays (example) A dv a n c e v 0. 5 2 - 17 IGLOO PLUS DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% E 50% tEOUT (F) tEOUT (R) VCC 50% 50% EOUT tZL 50% tZH tHZ Vtrip VCCI 90% VCCI PAD Vtrip VOL VCC D VCC E 50% 50% tEOUT (R) tEOUT (F) VCC EOUT 50% 50% tZLS VOH PAD Vtrip 50% tZHS Vtrip VOL Figure 2-6 * Tristate Output Buffer Timing Model and Delays (example) 2 -1 8 A d v a n c e v 0. 5 50% tLZ 10% VCCI IGLOO PLUS DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels - Default I/O Software Settings Table 2-20 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings VIH VIL Drive Slew Max, V Strength Rate Min, V I/O Standard VOL VOH Min, V Max, V Max, V Min, V IOL IOH mA mA 3.3 V LVTTL / 3.3 V LVCMOS 12 mA High -0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 V LVCMOS 12 mA High -0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 V LVCMOS 8 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 4 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 2 mA High -0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 2 2 1.5 V LVCMOS 1.2 V LVCMOS 2 Notes: 1. Currents are measured at 85C junction temperature. 2. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC Table 2-21 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL IIH IIL IIH DC I/O Standards A A A A 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 1.2 V LVCMOS3 10 10 15 15 Notes: 1. Commercial range (0C < TA < 70C) 2. Industrial range (-40C < TA < 85C) 3. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC A dv a n c e v 0. 5 2 - 19 IGLOO PLUS DC and Switching Characteristics Summary of I/O Timing Characteristics - Default I/O Software Settings Table 2-22 * Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 1.2 V LVCMOS 0.60 V Table 2-23 * I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer--HIGH to Z tZH Enable to Pad delay through the Output Buffer--Z to HIGH tLZ Enable to Pad delay through the Output Buffer--LOW to Z tZL Enable to Pad delay through the Output Buffer--Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable--Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable--Z to LOW 2 -2 0 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics - 0.97 1.62 0.18 1.06 1.22 0.66 1.65 1.34 2.22 2.56 ns 1.8 V LVCMOS 8 mA High 5 pF - 0.97 1.82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns 1.5 V LVCMOS 4 mA High 5 pF - 0.97 2.07 0.18 1.15 1.62 0.66 2.10 1.71 2.37 2.57 ns Units 5 pF tHZ High tLZ 12 mA tZH 2.5 V LVCMOS tZL ns tE OUT 0.97 1.62 0.18 0.85 1.14 0.66 1.65 1.27 2.20 2.64 tPYS - tPY 5 pF tDIN External Resistor () High tDP Capacitive Load (pF) 12 mA tDOUT Slew Rate 3.3 V LVTTL / 3.3 V LVCMOS I/O Standard Drive Strength (mA) Table 2-24 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Units tHZ tLZ tZH tZL tE OU T tPYS tPY) tDIN tDP tDOUT External Resistor () Capacitive Load (pF) Slew Rate Drive Strength (mA) I/O Standard Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V 3.3 V LVTTL / 3.3 V LVCMOS 12 mA High 5 pF - 0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns 2.5 V LVCMOS 12 mA High 5 pF - 0.98 2.13 0.19 1.20 1.40 0.67 2.17 1.77 2.65 3.25 ns 1.8 V LVCMOS 8 mA High 5 pF - 0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns 1.5 V LVCMOS 4 mA High 5 pF - 0.98 2.48 0.19 1.26 1.79 0.67 2.52 2.10 2.77 3.14 ns 2 mA High 5 pF - 0.98 2.68 0.19 1.56 2.34 0.67 2.73 2.24 2.53 2.67 ns 1.2 V LVCMOS2 Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC. A dv a n c e v 0. 5 2 - 21 IGLOO PLUS DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-26 * Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 2-27 * I/O Output Buffer Maximum Resistances 1 Standard 3.3 V LVTTL LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS / 3.3V Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8m A 50 150 12 mA 25 75 16 mA 25 75 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 12 mA 25 50 2 mA 200 225 4 mA 100 112 6 mA 50 56 8 mA 50 56 2 mA 200 224 4 mA 100 112 2 mA TBD TBD Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHs pe c 2 -2 2 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Table 2-28 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 k 45 k 10 k 45 k 2.5 V 11 k 55 k 12 k 74 k 1.8 V 18 k 70 k 17 k 110 k 1.5 V 19 k 90 k 19 k 140 k 1.2 V TBD TBD TBD TBD Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) Table 2-29 * I/O Short Currents IOSH/IOSL 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 103 109 2 mA 16 18 4 mA 16 18 6 mA 32 37 8 mA 32 37 12 mA 65 74 2 mA 9 11 4 mA 17 22 6 mA 35 44 8 mA 35 44 2 mA 13 16 4 mA 25 33 2 mA TBD TBD * TJ = 100C A dv a n c e v 0. 5 2 - 23 IGLOO PLUS DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-30 * Duration of Short Circuit Event before Failure Temperature Time before Failure -40C > 20 years 0C > 20 years 25C > 20 years 70C 5 years 85C 2 years 100C 6 months 110C 3 months Table 2-31 * Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL/LVCMOS (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV Table 2-32 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (100C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis. 20 years (100C) Input Buffer * The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -2 4 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-33 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA -0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA -0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA -0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 mA -0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 mA -0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-7 * AC Loading Table 2-34 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 5 * Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points. A dv a n c e v 0. 5 2 - 25 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-35 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.97 3.33 0.18 0.85 1.14 0.66 3.39 2.95 1.82 1.87 ns 6 mA STD 0.97 2.83 0.18 0.85 1.14 0.66 2.88 2.65 2.04 2.27 ns 8 mA STD 0.97 2.83 0.18 0.85 1.14 0.66 2.88 2.65 2.04 2.27 ns 12 mA STD 0.97 2.48 0.18 0.85 1.14 0.66 2.52 2.38 2.20 2.53 ns 16 mA STD 0.97 2.48 0.18 0.85 1.14 0.66 2.52 2.38 2.20 2.53 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-36 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.97 1.84 0.18 0.85 1.14 0.66 1.88 1.43 1.81 1.98 ns 6 mA STD 0.97 1.70 0.18 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns 8 mA STD 0.97 1.70 0.18 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns 12 mA STD 0.97 1.62 0.18 0.85 1.14 0.66 1.65 1.27 2.20 2.64 ns 16 mA STD 0.97 1.62 0.18 0.85 1.14 0.66 1.65 1.27 2.20 2.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -2 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-37 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 3.92 0.19 0.99 1.37 0.67 3.99 3.47 2.25 2.56 ns 6 mA STD 0.98 3.40 0.19 0.99 1.37 0.67 3.47 3.15 2.48 2.97 ns 8 mA STD 0.98 3.40 0.19 0.99 1.37 0.67 3.47 3.15 2.48 2.97 ns 12 mA STD 0.98 3.04 0.19 0.99 1.37 0.67 3.10 2.88 2.64 3.24 ns 16 mA STD 0.98 3.04 0.19 0.99 1.37 0.67 3.10 2.88 2.64 3.24 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-38 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 2.39 0.19 0.99 1.37 0.67 2.43 1.91 2.24 2.68 ns 6 mA STD 0.98 2.24 0.19 0.99 1.37 0.67 2.28 1.80 2.48 3.10 ns 8 mA STD 0.98 2.24 0.19 0.99 1.37 0.67 2.28 1.80 2.48 3.10 ns 12 mA STD 0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns 16 mA STD 0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 27 IGLOO PLUS DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V-tolerant input buffer and push-pull output buffer. Table 2-39 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH IOSL Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 IOSH IIL IIH Max., mA1 A2 A2 2 mA -0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10 4 mA -0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 6 mA -0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10 8 mA -0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 mA -0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 * AC Loading Table 2-40 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 5 * Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points. 2 -2 8 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-41 * 2.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.97 3.80 0.18 1.06 1.22 0.66 3.87 3.47 1.80 1.70 ns 6 mA STD 0.97 3.21 0.18 1.06 1.22 0.66 3.27 3.11 2.05 2.17 ns 8 mA STD 0.97 3.21 0.18 1.06 1.22 0.66 3.27 3.11 2.05 2.17 ns 12 mA STD 0.97 2.80 0.18 1.06 1.22 0.66 2.85 2.79 2.22 2.48 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-42 * 2.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.97 1.90 0.18 1.06 1.22 0.66 1.93 1.57 1.79 1.77 ns 6 mA STD 0.97 1.73 0.18 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns 8 mA STD 0.97 1.73 0.18 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns 12 mA STD 0.97 1.62 0.18 1.06 1.22 0.66 1.65 1.34 2.22 2.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 29 IGLOO PLUS DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-43 * 2.5 LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 4.37 0.19 1.20 1.40 0.67 4.45 3.95 2.21 2.35 ns 6 mA STD 0.98 3.76 0.19 1.20 1.40 0.67 3.83 3.59 2.47 2.83 ns 8 mA STD 0.98 3.76 0.19 1.20 1.40 0.67 3.83 3.59 2.47 2.83 ns 12 mA STD 0.98 3.34 0.19 1.20 1.40 0.67 3.41 3.26 2.65 3.15 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-44 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 4 mA STD 0.98 2.42 0.19 1.20 1.40 0.67 2.46 2.01 2.21 2.44 ns 6 mA STD 0.98 2.24 0.19 1.20 1.40 0.67 2.28 1.85 2.46 2.93 ns 8 mA STD 0.98 2.24 0.19 1.20 1.40 0.67 2.28 1.85 2.46 2.93 ns 12 mA STD 0.98 2.13 0.19 1.20 1.40 0.67 2.17 1.77 2.65 3.25 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 0 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-45 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL Drive Strength Min., V Max., V VIH Min., V VOL VOH Max., V Max., V IOL IOH Min., V IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 2 2 9 11 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 4 4 17 22 10 10 6 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 6 6 35 44 10 10 8 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI - 0.45 8 8 35 44 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 * AC Loading Table 2-46 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 5 * Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points. A dv a n c e v 0. 5 2 - 31 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-47 * 1.8 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 5.11 0.18 0.99 1.43 0.66 5.20 4.48 1.78 1.30 ns 4 mA STD 0.97 4.31 0.18 0.99 1.43 0.66 4.39 4.04 2.08 2.07 ns 6 mA STD 0.97 3.78 0.18 0.99 1.43 0.66 3.85 3.63 2.29 2.46 ns 8 mA STD 0.97 3.78 0.18 0.99 1.43 0.66 3.85 3.63 2.29 2.46 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-48 * 1.8 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 2.21 0.18 0.99 1.43 0.66 2.25 1.86 1.78 1.35 ns 4 mA STD 0.97 1.97 0.18 0.99 1.43 0.66 2.01 1.64 2.08 2.15 ns 6 mA STD 0.97 1.82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns 8 mA STD 0.97 1.82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 2 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-49 * 1.8 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 5.61 0.19 1.12 1.60 0.67 5.71 4.96 2.18 1.87 ns 4 mA STD 0.98 4.80 0.19 1.12 1.60 0.67 4.89 4.50 2.49 2.67 ns 6 mA STD 0.98 4.25 0.19 1.12 1.60 0.67 4.33 4.09 2.71 3.06 ns 8 mA STD 0.98 4.25 0.19 1.12 1.60 0.67 4.33 4.09 2.71 3.06 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-50 * 1.8 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 2.66 0.19 1.12 1.60 0.67 2.71 2.27 2.18 1.92 ns 4 mA STD 0.98 2.41 0.19 1.12 1.60 0.67 2.46 2.04 2.49 2.75 ns 6 mA STD 0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns 8 mA STD 0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 33 IGLOO PLUS DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-51 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL Drive Min., Strength V Max., V VIH Min., V Max., V VOL VOH IOL IOH Max., V Min., V IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10 4 mA -0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 4 25 33 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-10 * AC Loading Table 2-52 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 5 * Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points. 2 -3 4 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-53 * 1.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 5.47 0.18 1.15 1.62 0.66 5.57 4.89 2.13 2.02 ns 4 mA STD 0.97 4.82 0.18 1.15 1.62 0.66 4.91 4.42 2.37 2.47 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-54 * 1.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 2.27 0.18 1.15 1.62 0.66 2.31 1.85 2.13 2.11 ns 4 mA STD 0.97 2.07 0.18 1.15 1.62 0.66 2.10 1.71 2.37 2.57 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 35 IGLOO PLUS DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-55 * 1.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 5.94 0.19 1.26 1.79 0.67 6.05 5.36 2.53 2.58 ns 4 mA STD 0.98 5.28 0.19 1.26 1.79 0.67 5.38 4.88 2.78 3.04 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-56 * 1.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.98 2.68 0.19 1.26 1.79 0.67 2.73 2.24 2.53 2.67 ns 4 mA STD 0.98 2.48 0.19 1.26 1.79 0.67 2.52 2.10 2.77 3.14 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-57 * Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS VIL Drive Min., Strength V 2 mA Max., V VIH Min., V -0.3 0.35 * VCCI 0.65 * VCCI Max., V 1.26 VOL VOH IOL IOH Max., V Min., V 0.25 * VCCI 0.75 * VCCI IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 A2 A2 2 2 TBD TBD 10 10 Notes: 1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature. 3. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-11 * AC Loading Table 2-58 * AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.2 0.6 5 * Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points. A dv a n c e v 0. 5 2 - 37 IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-59 * 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.98 8.28 0.19 1.56 2.34 0.67 3.24 2.76 3.00 3.25 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-60 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.98 2.68 0.19 1.56 2.34 0.67 2.73 2.24 2.53 2.67 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 8 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Asynchronous Preset INBUF Preset L DOUT Data_out D C Q E PRE F Y Core Array DFN1P1 D Q DFN1P1 TRIBUF PRE INBUF Data Pad Out D EOUT CLKBUF CLK H I A PRE J D Q DFN1P1 CLKBUF INBUF CLK D_Enable Data Input I/O Register with: Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Preset Postive-Edge Triggered Figure 2-12 * Timing Model of Registered I/O Buffers with Asynchronous Preset A dv a n c e v 0. 5 2 - 39 IGLOO PLUS DC and Switching Characteristics Table 2-61 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A * See Figure 2-12 on page 2-39 for more information. 2 -4 0 A d v a n c e v 0. 5 H, DOUT L, DOUT H, EOUT I, EOUT IGLOO PLUS DC and Switching Characteristics Fully Registered I/O Buffers with Asynchronous Clear Y D CC Q DFN1C1 EE Core Array D Q DFN1C1 TRIBUF INBUF Data Pad Out DOUT Data_out FF EOUT CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ D DD Q DFN1C1 Data Input I/O Register with Active High Clear Positive-Edge Triggered INBUF CLKBUF D_Enable CLK CLR Data Output Register and Enable Output Register with Active High Clear Positive-Edge Triggered Figure 2-13 * Timing Model of the Registered I/O Buffers with Asynchronous Clear A dv a n c e v 0. 5 2 - 41 IGLOO PLUS DC and Switching Characteristics Table 2-62 * Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA * See Figure 2-13 on page 2-41 for more information. 2 -4 2 A d v a n c e v 0. 5 HH, DOUT LL, DOUT HH, EOUT II, EOUT IGLOO PLUS DC and Switching Characteristics Input Register tICKMPWH tICKMPWL CLK 50% 50% 1 50% 50% 50% 0 tIREMPRE tIRECPRE tIWPRE Preset 50% 50% tIHD tISUD Data 50% 50% 50% 50% 50% tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 2-14 * Input Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-63 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units 0.63 ns tICLKQ Clock-to-Q of the Input Data Register tISUD Data Setup Time for the Input Data Register 0.18 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.46 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.46 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.23 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.23 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.28 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 43 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-64 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units 0.99 ns tICLKQ Clock-to-Q of the Input Data Register tISUD Data Setup Time for the Input Data Register 0.29 ns tIHD Data Hold Time for the Input Data Register 0.00 ns 0.68 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.68 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.28 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2 -4 4 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD Data_out 1 50% 50% 0 tOWPRE Preset tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tORECCLR tOREMCLR 50% 50% tOPRE2Q 50% DOUT 50% tOCLR2Q 50% tOCLKQ Figure 2-15 * Output Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-65 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.89 ns tOSUD Data Setup Time for the Output Data Register 0.18 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.72 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.78 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.23 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.23 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.28 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 45 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-66 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 1.37 ns tOSUD Data Setup Time for the Output Data Register 0.22 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.05 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.14 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.28 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2 -4 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK tOESUD tOEHD D_Enable 1 50% 0 50% tOEWPRE 50% tOEREMPRE tOERECPRE 50% 50% Preset tOEWCLR tOERECCLR 50% tOEREMCLR 50% 50% Clear EOUT 50% tOEPRE2Q tOECLR2Q 50% 50% tOECLKQ Figure 2-16 * Output Enable Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-67 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.91 ns tOESUD Data Setup Time for the Output Enable Register 0.18 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.74 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.81 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.23 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.23 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.28 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 47 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-68 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units 1.40 ns tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register 0.22 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.08 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.19 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.28 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.31 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2 -4 8 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/ E Macro Library Guide. A A A OR2 NOR2 Y A AND2 A Y NAND2 B Y B A B C A XOR2 Y A A B C Y B B B Y INV NAND3 Y A MAJ3 B XOR3 0 Y MUX2 B Y 1 C S Figure 2-17 * Sample of Combinatorial Cells A dv a n c e v 0. 5 2 - 49 IGLOO PLUS DC and Switching Characteristics tPD Fanout = 4 A Net NAND2 or Any Combinatorial Logic Length = 1 VersaTile B A Net Length = 1 VersaTile B Y NAND2 or Any Combinatorial Logic tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell A Net Length = 1 VersaTile B Y NAND2 or Any Combinatorial Logic A Net Length = 1 VersaTile B Y NAND2 or Any Combinatorial Logic VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) tPD OUT (FR) 50% tPD (RF) GND Figure 2-18 * Timing Model and Waveforms 2 -5 0 A d v a n c e v 0. 5 Y 50% IGLOO PLUS DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-69 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 0.72 ns Y=A*B tPD 0.86 ns Y = !(A * B) tPD 0.87 ns Y=A+B tPD 0.89 ns NOR2 Y = !(A + B) tPD 0.90 ns XOR2 Y=AB tPD 1.35 ns MAJ3 Y = MAJ(A, B, C) tPD 1.33 ns XOR3 Y=ABC tPD 1.98 ns MUX2 Y = A !S + B S tPD 1.24 ns AND3 Y=A*B*C tPD 1.40 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-70 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 1.27 ns Y=A*B tPD 1.47 ns Y = !(A * B) tPD 1.52 ns Y=A+B tPD 1.51 ns NOR2 Y = !(A + B) tPD 1.57 ns XOR2 Y=AB tPD 2.28 ns MAJ3 Y = MAJ(A, B, C) tPD 2.39 ns XOR3 Y=ABC tPD 3.50 ns MUX2 Y = A !S + B S tPD 2.21 ns AND3 Y=A*B*C tPD 2.50 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. A dv a n c e v 0. 5 2 - 51 IGLOO PLUS DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOO PLUS library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Data D Q Out Data Out D En DFN1 CLK Q DFN1E1 CLK PRE Data D Q Out DFN1C1 En CLK CLK CLR Figure 2-19 * Sample of Sequential Cells 2 -5 2 Data A d v a n c e v 0. 5 D Q DFI1E1P1 Out IGLOO PLUS DC and Switching Characteristics tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data 50% 50% 50% 50% 50% tHD 50% 0 EN 50% PRE tRECPRE tWPRE tSUE tHE 50% tREMPRE 50% 50% 50% CLR tPRE2Q 50% Out tREMCLR tRECCLR tWCLR 50% 50% tCLR2Q 50% 50% tCLKQ Figure 2-20 * Timing Model and Waveforms Timing Characteristics 1.5 V DC Core Voltage Table 2-71 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Std. Units tCLKQ Clock-to-Q of the Core Register Description 0.80 ns tSUD Data Setup Time for the Core Register 0.84 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 0.73 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.62 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.60 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.23 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 53 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-72 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 1.40 ns tSUD Data Setup Time for the Core Register 1.35 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 1.29 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.89 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.87 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.46 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.46 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.95 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.95 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2 -5 4 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Global Resource Characteristics AGLP125 Clock Tree Topology Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing. The global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-21 * Example of Global Tree Use in an AGLP125 Device for Clock Routing A dv a n c e v 0. 5 2 - 55 IGLOO PLUS DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-59. Table 2-73 to Table 2-78 on page 2-58 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.5 V DC Core Voltage Table 2-73 * AGLP030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 1.21 1.42 ns tRCKH Input HIGH Delay for Global Clock 1.23 1.49 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.27 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-74 * AGLP060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 1.32 1.52 ns tRCKH Input HIGH Delay for Global Clock 1.34 1.59 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.26 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -5 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Table 2-75 * AGLP125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 1.31 1.66 ns tRCKH Input HIGH Delay for Global Clock 1.29 1.72 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.43 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-76 * AGLP030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 1.80 2.09 ns tRCKH Input HIGH Delay for Global Clock 1.88 2.27 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.39 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. A dv a n c e v 0. 5 2 - 57 IGLOO PLUS DC and Switching Characteristics Table 2-77 * AGLP060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 2.02 2.30 ns tRCKH Input HIGH Delay for Global Clock 2.09 2.46 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.37 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-78 * AGLP125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter Description 1 Min. Max.2 Units tRCKL Input LOW Delay for Global Clock 2.08 2.54 ns tRCKH Input HIGH Delay for Global Clock 2.15 2.77 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock FRMAX Maximum Frequency for Global Clock 0.62 ns MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2 -5 8 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-79 * IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Max. Units 1.5 250 MHz 0.75 250 MHz Delay Increments in Programmable Delay Blocks 1, 2 Typ. 360 Number of Programmable Values in Each Programmable Delay Block ps 32 Input Cycle-to-Cycle Jitter (peak magnitude) CCC Output Peak-to-Peak Period Jitter FCCC_OUT 100 MHz 1 ns Max Peak-to-Peak Period Jitter 0.75 MHz to 24 MHz 1 Global Network Used 24 MHz to 100 MHz 0.50% 0.75% 0.70% 100 MHz to 250 MHz 1.00% 1.50% 1.20% 2.50% 3.75% 2.75% Acquisition Time External 3 Global FB Used Networks Used LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 2.5 LockControl = 1 1.5 ns Tracking Jitter Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2, 3 1.25 15.65 ns Delay Range in Block: Programmable Delay 2 1, 2, 3 0.025 15.65 ns Delay Range in Block: Fixed Delay 1, 2 3.5 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in IGLOO and ProASIC3 Devices chapter of the handbook. 4. The AGLP030 device does not support PLL. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. A dv a n c e v 0. 5 2 - 59 IGLOO PLUS DC and Switching Characteristics Table 2-80 * IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Max. Units 1.5 160 MHz 0.75 160 MHz 1, 2 Typ. 580 ps Number of Programmable Values in Each Programmable Delay Block 32 Input Cycle-to-Cycle Jitter (peak magnitude) 60 MHz Max Peak-to-Peak Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT 1 Global Network Used External FB Used 3 Global Networks Used 0.75 MHz to 24 MHz 0.50% 0.75% 0.70% 24 MHz to 100 MHz 1.00% 1.50% 1.20% 100 MHz to 160 MHz 2.50% 3.75% 2.75% Acquisition Time LockControl = 0 300 s LockControl = 1 6.0 ms LockControl = 0 4 ns LockControl = 1 3 ns Tracking Jitter Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2, 3 2.3 20.86 ns Delay Range in Block: Programmable Delay 2 1, 2, 3 0.025 20.86 ns Delay Range in Block: Fixed Delay 1, 2 5.7 ns Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25C, VCC = 1.2 V 3. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in IGLOO and ProASIC3 Devices chapter of the handbook. 4. The AGLP030 device does not support PLL. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-22 * Peak-to-Peak Jitter Definition 2 -6 0 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM4K9 RAM512X18 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-23 * RAM Models A dv a n c e v 0. 5 2 - 61 IGLOO PLUS DC and Switching Characteristics Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tCKQ1 DO Dn D0 D1 D2 tDOH1 Figure 2-24 * RAM Read for Pass-Through Output tCYC tCKH tCKL CLK t AS tAH A1 A0 ADD A2 tBKS tBKH BLK_B tENH tENS WEN_B tCKQ2 DO Dn D0 D1 tDOH2 Figure 2-25 * RAM Read for Pipelined Output 2 -6 2 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS tENH WEN_B tDS DI0 DI tDH DI1 D2 Dn DO Figure 2-26 * RAM Write, Output Retained (WMODE = 0) tCYC tCKH tCKL CLK tAS tAH A0 ADD A1 A2 tBKS tBKH BLK_B tENS WEN_B tDS DI0 DI DO (pass-through) DO (pipelined) tDH DI1 Dn DI2 DI0 DI1 DI0 Dn DI1 Figure 2-27 * RAM Write, Output as Write Data (WMODE = 1) A dv a n c e v 0. 5 2 - 63 IGLOO PLUS DC and Switching Characteristics CLK1 tAS tAH A1 A3 tDS A0 tDH D1 D2 D3 ADD1 DI1 tCCKH CLK2 WEN_B1 WEN_B2 tAS ADD2 A0 DI2 D0 tAH A0 A4 D4 tCKQ1 DO2 (pass-through) Dn D0 tCKQ2 DO2 (pipelined) Dn D0 Figure 2-28 * Write Access after Write onto Same Address 2 -6 4 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics CLK1 tAS tAH ADD1 DI1 A0 tDS tDH D0 tWRO A2 A3 D2 D3 CLK2 WEN_B1 WEN_B2 tAS tAH A0 ADD2 A1 A4 tCKQ1 DO2 (pass-through) DO2 (pipelined) Dn D0 D1 tCKQ2 Dn D0 Figure 2-29 * Read Access after Write onto Same Address A dv a n c e v 0. 5 2 - 65 IGLOO PLUS DC and Switching Characteristics CLK1 tAS tAH A0 ADD1 A1 A0 WEN_B1 tCKQ1 DO1 (pass-through) tCKQ1 D0 Dn D1 tCKQ2 DO1 (pipelined) D0 Dn tCCKH CLK2 tAS tAH ADD2 A0 A1 A3 DI2 D1 D2 D3 WEN_B2 Figure 2-30 * Write Access after Read onto Same Address tCYC tCKH tCKL CLK RESET_B tRSTBQ DO Dm Dn Figure 2-31 * RAM Reset 2 -6 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-81 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.83 ns tAH Address hold time 0.16 ns tENS REN_B, WEN_B setup time 0.81 ns tENH REN_B, WEN_B hold time 0.16 ns tBKS BLK_B setup time 1.65 ns tBKH BLK_B hold time 0.16 ns tDS Input data (DI) setup time 0.71 ns tDH Input data (DI) hold time 0.36 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 3.53 ns Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 3.06 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 1.81 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same address TBD ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on same TBD address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 2.06 ns RESET_B LOW to data out LOW on DO (pipelined) 2.06 ns tREMRSTB RESET_B removal 0.61 ns tRECRSTB RESET_B recovery 3.21 ns tMPWRSTB RESET_B minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 67 IGLOO PLUS DC and Switching Characteristics Table 2-82 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.83 ns tAH Address hold time 0.16 ns tENS REN_B, WEN_B setup time 0.73 ns tENH REN_B, WEN_B hold time 0.08 ns tDS Input data (DI) setup time 0.71 ns tDH Input data (DI) hold time 0.36 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 4.21 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 1.71 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same address TBD ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on same TBD address ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 2.06 ns RESET_B LOW to data out LOW on DO (pipelined) 2.06 ns tREMRSTB RESET_B removal 0.61 ns tRECRSTB RESET_B recovery 3.21 ns tMPWRSTB RESET_B minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -6 8 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-83 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tAS Address setup time 1.53 ns tAH Address hold time 0.29 ns tENS REN_B, WEN_B setup time 1.50 ns tENH REN_B, WEN_B hold time 0.29 ns tBKS BLK_B setup time 3.05 ns tBKH BLK_B hold time 0.29 ns tDS Input data (DI) setup time 1.33 ns tDH Input data (DI) hold time 0.66 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 6.61 ns Clock HIGH to new data valid on DO (flow-through, WMODE = 1) 5.72 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 3.38 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same address TBD ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on same address TBD ns tRSTBQ RESET_B LOW to data out LOW on DO (flow-through) 3.86 ns RESET_B LOW to data out LOW on DO (pipelined) 3.86 ns tREMRSTB RESET_B removal 1.12 ns tRECRSTB RESET_B recovery 5.93 ns tMPWRSTB RESET_B minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. A dv a n c e v 0. 5 2 - 69 IGLOO PLUS DC and Switching Characteristics Table 2-84 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Std. Units tAS Address setup time Description 1.53 ns tAH Address hold time 0.29 ns tENS REN_B, WEN_B setup time 1.36 ns tENH REN_B, WEN_B hold time 0.15 ns tDS Input data (DI) setup time 1.33 ns tDH Input data (DI) hold time 0.66 ns tCKQ1 Clock HIGH to new data valid on DO (output retained, WMODE = 0) 7.88 ns tCKQ2 Clock HIGH to new data valid on DO (pipelined) 3.20 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same address TBD ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on same address TBD ns tRSTBQ RESET_B LOW to data out LOW on DO (flow through) 3.86 ns RESET_B LOW to data out LOW on DO (pipelined) 3.86 ns tREMRSTB RESET_B removal 1.12 ns tRECRSTB RESET_B recovery 5.93 ns tMPWRSTB RESET_B minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2 -7 0 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-32 * FIFO Model A dv a n c e v 0. 5 2 - 71 IGLOO PLUS DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB tRSTCK RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-33 * FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Figure 2-34 * FIFO EMPTY Flag and AEMPTY Flag Assertion 2 -7 2 A d v a n c e v 0. 5 Dist = AEF_TH MATCH (EMPTY) IGLOO PLUS DC and Switching Characteristics tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-35 * FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) RCLK MATCH (EMPTY) NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-36 * FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-37 * FIFO FULL Flag and AFULL Flag Deassertion A dv a n c e v 0. 5 2 - 73 IGLOO PLUS DC and Switching Characteristics Timing Characteristics 1.5 V DC Core Voltage Table 2-85 * FIFO Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description Std. Units tENS REN_B, WEN_B Setup Time 1.99 ns tENH REN_B, WEN_B Hold Time 0.16 ns tBKS BLK_B Setup Time 0.30 ns tBKH BLK_B Hold Time 0.00 ns tDS Input Data (DI) Setup Time 0.76 ns tDH Input Data (DI) Hold Time 0.25 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 3.33 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 1.80 ns tRCKEF RCLK HIGH to Empty Flag Valid 3.53 ns tWCKFF WCLK HIGH to Full Flag Valid 3.35 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 12.85 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 3.48 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 12.72 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 2.02 ns RESET_B LOW to Data Out LOW on DO (pipelined) 2.02 ns tREMRSTB RESET_B Removal 0.61 ns tRECRSTB RESET_B Recovery 3.21 ns tMPWRSTB RESET_B Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency for FIFO 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -7 4 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-86 * FIFO Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter Description Std. Units tENS REN_B, WEN_B Setup Time 4.13 ns tENH REN_B, WEN_B Hold Time 0.31 ns tBKS BLK_B Setup Time 0.30 ns tBKH BLK_B Hold Time 0.00 ns tDS Input Data (DI) Setup Time 1.56 ns tDH Input Data (DI) Hold Time 0.49 ns tCKQ1 Clock HIGH to New Data Valid on DO (flow-through) 6.80 ns tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 3.62 ns tRCKEF RCLK HIGH to Empty Flag Valid 7.23 ns tWCKFF WCLK HIGH to Full Flag Valid 6.85 ns tCKAF Clock HIGH to Almost Empty/Full Flag Valid 26.61 ns tRSTFG RESET_B LOW to Empty/Full Flag Valid 7.12 ns tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 26.33 ns tRSTBQ RESET_B LOW to Data Out LOW on DO (flow-through) 4.09 ns RESET_B LOW to Data Out LOW on DO (pipelined) 4.09 ns tREMRSTB RESET_B Removal 1.23 ns tRECRSTB RESET_B Recovery 6.58 ns tMPWRSTB RESET_B Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency for FIFO 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. A dv a n c e v 0. 5 2 - 75 IGLOO PLUS DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-38 * Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-87 * Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter Description Std. Units tSU Address Setup Time 0.57 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 33.14 ns FMAX Maximum Clock Frequency 15 MHz Std. Units 1.2 V DC Core Voltage Table 2-88 * Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter Description tSU Address Setup Time 0.59 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 52.04 ns FMAX Maximum Clock Frequency 10 MHz 2 -7 6 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details. Timing Characteristics 1.5 V DC Core Voltage Table 2-89 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.00 ns tDIHD Test Data Input Hold Time 2.00 ns tTMSSU Test Mode Select Setup Time 1.00 ns tTMDHD Test Mode Select Hold Time 2.00 ns tTCK2Q Clock to Q (data out) 8.00 ns tRSTB2Q Reset to Q (data out) 25.00 ns FTCKMAX TCK Maximum Frequency 15 MHz tTRSTREM ResetB Removal Time 0.58 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-90 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.50 ns tDIHD Test Data Input Hold Time 3.00 ns tTMSSU Test Mode Select Setup Time 1.50 ns tTMDHD Test Mode Select Hold Time 3.00 ns tTCK2Q Clock to Q (data out) 11.00 ns tRSTB2Q Reset to Q (data out) 30.00 ns FTCKMAX TCK Maximum Frequency 9.00 MHz tTRSTREM ResetB Removal Time 1.18 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. A dv a n c e v 0. 5 2 - 77 IGLOO PLUS DC and Switching Characteristics Part Number and Revision Date Part Number 51700102-002-4 Revised April 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (Advance v0.5) Page Advance v0.4 (October 2008) Reference to the -F speed grade was removed from this document, since it is no longer offered for IGLOO PLUS devices. 2-1 Advance v0.3 (July 2008) Data was revised significantly in the following tables: Table 2-24 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, 2-21, 2-30 Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Table 2-43 * 2.5 LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Table 2-44 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Advance v0.2 (March 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A Advance v0.1 (January 2008) Tables have been updated to reflect default values in the software. The default I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O set. N/A Table note 3 was updated in Table 2-2 * Recommended Operating Conditions 4 to add the sentence, "VCCI should be at the same voltage within a given I/O bank." References to table notes 5, 6, 7, and 8 were added. Reference to table note 3 was removed from VPUMP Operation and placed next to VCC. 2-2 Table 2-4 * Overshoot and Undershoot Limits 1 was revised to remove "as measured on quiet I/Os" from the title. Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. 2-3 The table note for Table 2-8 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values do not include I/O static contribution. 2-7 The table note for Table 2-9 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode (VCC = 0 V)* was updated to remove VJTAG and VCCI and the statement that values do not include I/O static contribution. 2-7 The table note for Table 2-10 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode (VCC, VCCI = 0 V)* was updated to remove the statement that values do not include I/O static contribution. 2-7 Note 2 of Table 2-11 * Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 was updated to include VCCPLL. Table note 4 was deleted. 2-8 Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings and Table 2-13 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 were updated to remove static power. The table notes were updated to reflect that power was measured on VCCI. Table note 2 was added to Table 2-12 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings. 2-8, 2-9 2 -7 8 A d v a n c e v 0. 5 IGLOO PLUS DC and Switching Characteristics Previous Version Advance v0.1 (continued) Changes in Current Version (Advance v0.5) Page Table 2-15 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-17 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices were updated to change the definition for PDC5 from bank static power to bank quiescent power. Table subtitles were added for Table 2-15 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices, Table 2-16 * Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices, and Table 2-17 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices. 2-10, 2-11 The "Total Static Power Consumption--PSTAT" section was revised. 2-12 Table 2-31 * Schmitt Trigger Input Hysteresis is new. 2-24 Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. A dv a n c e v 0. 5 2 - 79 IGLOO PLUS Packaging 3 - Package Pin Assignments 128-Pin VQFP 128 1 128-Pin VQFP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.5 3-1 Package Pin Assignments 128-Pin VQFP 128-Pin VQFP 128-Pin VQFP Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function 1 IO119RSB3 37 IO86RSB2 73 GND 2 IO118RSB3 38 IO84RSB2 74 IO55RSB1 3 IO117RSB3 39 IO83RSB2 75 IO54RSB1 4 IO115RSB3 40 GND 76 IO53RSB1 5 IO116RSB3 41 VCCIB2 77 IO52RSB1 6 IO113RSB3 42 IO82RSB2 78 IO51RSB1 7 IO114RSB3 43 IO81RSB2 79 IO50RSB1 8 GND 44 IO79RSB2 80 IO49RSB1 9 VCCIB3 45 IO78RSB2 81 VCC 10 IO112RSB3 46 IO77RSB2 82 GDB0/IO48RSB1 11 IO111RSB3 47 IO75RSB2 83 GDA0/IO47RSB1 12 IO110RSB3 48 IO74RSB2 84 GDC0/IO46RSB1 13 IO109RSB3 49 VCC 85 IO45RSB1 14 GEC0/IO108RSB3 50 IO73RSB2 86 IO44RSB1 15 GEA0/IO107RSB3 51 IO72RSB2 87 IO43RSB1 16 GEB0/IO106RSB3 52 IO70RSB2 88 IO42RSB1 17 VCC 53 IO69RSB2 89 VCCIB1 18 IO104RSB3 54 IO68RSB2 90 GND 19 IO103RSB3 55 IO66RSB2 91 IO40RSB1 20 IO102RSB3 56 IO65RSB2 92 IO41RSB1 21 IO101RSB3 57 GND 93 IO39RSB1 22 IO100RSB3 58 VCCIB2 94 IO38RSB1 23 IO99RSB3 59 IO63RSB2 95 IO37RSB1 24 GND 60 IO61RSB2 96 IO36RSB1 25 VCCIB3 61 IO59RSB2 97 IO35RSB0 26 IO97RSB3 62 TCK 98 IO34RSB0 27 IO98RSB3 63 TDI 99 IO33RSB0 28 IO95RSB3 64 TMS 100 IO32RSB0 29 IO96RSB3 65 VPUMP 101 IO30RSB0 30 IO94RSB3 66 TDO 102 IO28RSB0 31 IO93RSB3 67 TRST 103 IO27RSB0 32 IO92RSB3 68 IO58RSB1 104 VCCIB0 33 IO91RSB2 69 VJTAG 105 GND 34 FF/IO90RSB2 70 IO56RSB1 106 IO26RSB0 35 IO89RSB2 71 IO57RSB1 107 IO25RSB0 36 IO88RSB2 72 VCCIB1 108 IO23RSB0 3 -2 v1.5 IGLOO PLUS Packaging 128-Pin VQFP Pin Number AGLP030 Function 109 IO22RSB0 110 IO21RSB0 111 IO19RSB0 112 IO18RSB0 113 VCC 114 IO17RSB0 115 IO16RSB0 116 IO14RSB0 117 IO13RSB0 118 IO12RSB0 119 IO10RSB0 120 IO09RSB0 121 VCCIB0 122 GND 123 IO07RSB0 124 IO05RSB0 125 IO03RSB0 126 IO02RSB0 127 IO01RSB0 128 IO00RSB0 v1.5 3-3 Package Pin Assignments 176-Pin VQFP 1176 176-Pin VQFP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -4 v1.5 IGLOO PLUS Packaging 176-Pin VQFP 176-Pin VQFP 176-Pin VQFP Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function 1 GAA2/IO156RSB3 37 GND 72 IO87RSB2 2 IO155RSB3 38 VCCIB3 73 IO86RSB2 3 GAB2/IO154RSB3 39 GEC1/IO116RSB3 74 IO85RSB2 4 IO153RSB3 40 GEB1/IO114RSB3 75 IO84RSB2 5 GAC2/IO152RSB3 41 GEC0/IO115RSB3 76 GND 6 GND 42 GEB0/IO113RSB3 77 VCCIB2 7 VCCIB3 43 GEA1/IO112RSB3 78 IO83RSB2 8 IO149RSB3 44 GEA0/IO111RSB3 79 IO82RSB2 9 IO147RSB3 45 GEA2/IO110RSB2 80 GDC2/IO80RSB2 10 IO145RSB3 46 NC 81 IO81RSB2 11 IO144RSB3 47 82 GDA2/IO78RSB2 12 IO143RSB3 FF/GEB2/IO109RSB 2 83 GDB2/IO79RSB2 48 GEC2/IO108RSB2 84 NC 49 IO106RSB2 85 NC 50 IO107RSB2 86 TCK 51 IO104RSB2 87 TDI 52 IO105RSB2 88 TMS 53 IO102RSB2 89 VPUMP 54 IO103RSB2 90 TDO 55 GND 91 TRST 56 VCCIB2 92 VJTAG 57 IO101RSB2 93 GDA1/IO76RSB1 58 IO100RSB2 94 GDC0/IO73RSB1 59 IO99RSB2 95 GDB1/IO74RSB1 60 IO98RSB2 96 GDC1/IO72RSB1 61 IO97RSB2 97 VCCIB1 62 IO96RSB2 98 GND 63 IO95RSB2 99 IO70RSB1 64 IO94RSB2 100 IO69RSB1 65 IO93RSB2 101 IO67RSB1 66 VCC 102 IO66RSB1 67 IO92RSB2 103 IO65RSB1 68 IO91RSB2 104 IO63RSB1 69 IO90RSB2 105 IO62RSB1 70 IO89RSB2 106 IO61RSB1 71 IO88RSB2 107 GCC2/IO60RSB1 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VCC IO141RSB3 GFC1/IO140RSB3 GFB1/IO138RSB3 GFB0/IO137RSB3 VCOMPLF GFA1/IO136RSB3 VCCPLF GFA0/IO135RSB3 GND VCCIB3 GFA2/IO134RSB3 GFB2/IO133RSB3 GFC2/IO132RSB3 IO131RSB3 IO130RSB3 IO129RSB3 IO127RSB3 IO126RSB3 IO125RSB3 IO123RSB3 IO122RSB3 IO121RSB3 IO119RSB3 v1.5 3-5 Package Pin Assignments 176-Pin VQFP 176-Pin VQFP Pin Number AGLP060 Function Pin Number AGLP060 Function 108 GCB2/IO59RSB1 144 IO27RSB0 109 GCA2/IO58RSB1 145 VCCIB0 110 GCA0/IO57RSB1 146 GND 111 GCA1/IO56RSB1 147 IO26RSB0 112 VCCIB1 148 IO25RSB0 113 GND 149 IO24RSB0 114 GCB0/IO55RSB1 150 IO23RSB0 115 GCB1/IO54RSB1 151 IO22RSB0 116 GCC0/IO53RSB1 152 IO21RSB0 117 GCC1/IO52RSB1 153 IO20RSB0 118 IO51RSB1 154 IO19RSB0 119 IO50RSB1 155 IO18RSB0 120 VCC 156 VCC 121 IO48RSB1 157 IO17RSB0 122 IO47RSB1 158 IO16RSB0 123 IO45RSB1 159 IO15RSB0 124 IO44RSB1 160 IO14RSB0 125 IO43RSB1 161 IO13RSB0 126 VCCIB1 162 IO12RSB0 127 GND 163 IO11RSB0 128 GBC2/IO40RSB1 164 IO10RSB0 129 IO39RSB1 165 IO09RSB0 130 GBB2/IO38RSB1 166 VCCIB0 131 IO37RSB1 167 GND 132 GBA2/IO36RSB1 168 IO07RSB0 133 GBA1/IO35RSB0 169 IO08RSB0 134 NC 170 GAC1/IO05RSB0 135 GBA0/IO34RSB0 171 IO06RSB0 136 NC 172 GAB1/IO03RSB0 137 GBB1/IO33RSB0 173 GAC0/IO04RSB0 138 NC 174 GAB0/IO02RSB0 139 GBC1/IO31RSB0 175 GAA1/IO01RSB0 140 GBB0/IO32RSB0 176 GAA0/IO00RSB0 141 GBC0/IO30RSB0 142 IO29RSB0 143 IO28RSB0 3 -6 v1.5 IGLOO PLUS Packaging 201-Pin CSP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v1.5 3-7 Package Pin Assignments 201-Pin CSP 201-Pin CSP 201-Pin CSP Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function A1 NC C7 IO23RSB0 F6 GND A2 IO04RSB0 C8 IO19RSB0 F7 VCC A3 IO06RSB0 C9 IO28RSB0 F8 VCCIB0 A4 IO09RSB0 C10 IO32RSB0 F9 VCCIB0 A5 IO11RSB0 C11 IO35RSB0 F10 VCCIB0 A6 IO13RSB0 C12 NC F12 NC A7 IO17RSB0 C13 GND F13 NC A8 IO18RSB0 C14 IO41RSB1 F14 IO40RSB1 A9 IO24RSB0 C15 IO37RSB1 F15 IO38RSB1 A10 IO26RSB0 D1 IO117RSB3 G1 NC A11 IO27RSB0 D2 IO118RSB3 G2 IO112RSB3 A12 IO31RSB0 D3 NC G3 IO110RSB3 A13 NC D4 GND G4 IO109RSB3 A14 NC D5 IO01RSB0 G6 VCCIB3 A15 NC D6 IO03RSB0 G7 GND B1 NC D7 IO10RSB0 G8 VCC B2 NC D8 IO21RSB0 G9 GND B3 IO08RSB0 D9 IO25RSB0 G10 GND B4 IO05RSB0 D10 IO30RSB0 G12 NC B5 IO07RSB0 D11 IO33RSB0 G13 NC B6 IO15RSB0 D12 GND G14 IO42RSB1 B7 IO14RSB0 D13 NC G15 IO44RSB1 B8 IO16RSB0 D14 IO36RSB1 H1 NC B9 IO20RSB0 D15 IO39RSB1 H2 GEB0/IO106RSB3 B10 IO22RSB0 E1 IO115RSB3 H3 GEC0/IO108RSB3 B11 IO34RSB0 E2 IO114RSB3 H4 NC B12 IO29RSB0 E3 NC H6 VCCIB3 B13 NC E4 NC H7 GND B14 NC E12 NC H8 VCC B15 NC E13 NC H9 GND C1 NC E14 GDC0/IO46RSB1 H10 VCCIB1 C2 NC E15 GDB0/IO48RSB1 H12 IO54RSB1 C3 GND F1 IO113RSB3 H13 GDA0/IO47RSB1 C4 IO00RSB0 F2 IO116RSB3 H14 IO45RSB1 C5 IO02RSB0 F3 IO119RSB3 H15 IO43RSB1 C6 IO12RSB0 F4 IO111RSB3 J1 GEA0/IO107RSB3 3 -8 v1.5 IGLOO PLUS Packaging 201-Pin CSP 201-Pin CSP 201-Pin CSP Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function J2 IO105RSB3 M4 GND P10 IO73RSB2 J3 IO104RSB3 M5 NC P11 IO76RSB2 J4 IO102RSB3 M6 IO79RSB2 P12 IO67RSB2 J6 VCCIB3 M7 IO77RSB2 P13 IO64RSB2 J7 GND M8 IO72RSB2 P14 VPUMP J8 VCC M9 IO70RSB2 P15 TRST J9 GND M10 IO61RSB2 R1 NC J10 VCCIB1 M11 IO59RSB2 R2 NC J12 NC M12 GND R3 IO91RSB2 J13 NC M13 NC R4 FF/IO90RSB2 J14 IO52RSB1 M14 IO55RSB1 R5 IO89RSB2 J15 IO50RSB1 M15 IO56RSB1 R6 IO83RSB2 K1 IO103RSB3 N1 NC R7 IO82RSB2 K2 IO101RSB3 N2 NC R8 IO85RSB2 K3 IO99RSB3 N3 GND R9 IO78RSB2 K4 IO100RSB3 N4 NC R10 IO69RSB2 K6 GND N5 IO88RSB2 R11 IO62RSB2 K7 VCCIB2 N6 IO81RSB2 R12 IO60RSB2 K8 VCCIB2 N7 IO75RSB2 R13 TMS K9 VCCIB2 N8 IO68RSB2 R14 TDI K10 VCCIB1 N9 IO66RSB2 R15 TCK K12 NC N10 IO65RSB2 K13 IO57RSB1 N11 IO71RSB2 K14 IO49RSB1 N12 IO63RSB2 K15 IO53RSB1 N13 GND L1 IO96RSB3 N14 TDO L2 IO98RSB3 N15 VJTAG L3 IO95RSB3 P1 NC L4 IO94RSB3 P2 NC L12 NC P3 NC L13 NC P4 NC L14 IO51RSB1 P5 IO87RSB2 L15 IO58RSB1 P6 IO86RSB2 M1 IO93RSB3 P7 IO84RSB2 M2 IO92RSB3 P8 IO80RSB2 M3 IO97RSB3 P9 IO74RSB2 v1.5 3-9 Package Pin Assignments 201-Pin CSP 201-Pin CSP 201-Pin CSP Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function A1 IO150RSB3 C7 IO16RSB0 F6 GND A2 GAA0/IO00RSB0 C8 IO21RSB0 F7 VCC A3 GAC0/IO04RSB0 C9 IO28RSB0 F8 VCCIB0 A4 IO08RSB0 C10 GBB1/IO33RSB0 F9 VCCIB0 A5 IO11RSB0 C11 GBA1/IO35RSB0 F10 VCCIB0 A6 IO15RSB0 C12 GBB2/IO38RSB1 F12 IO47RSB1 A7 IO17RSB0 C13 GND F13 IO45RSB1 A8 IO18RSB0 C14 IO48RSB1 F14 GCC1/IO52RSB1 A9 IO22RSB0 C15 IO39RSB1 F15 GCA1/IO56RSB1 A10 IO26RSB0 D1 IO146RSB3 G1* VCOMPLF A11 IO29RSB0 D2 IO144RSB3 G2 GFB0/IO137RSB3 A12 GBC1/IO31RSB0 D3 IO148RSB3 G3 GFC0/IO139RSB3 A13 GBA2/IO36RSB1 D4 GND G4 IO143RSB3 A14 IO41RSB1 D5 GAB0/IO02RSB0 G6 VCCIB3 A15 NC D6 GAC1/IO05RSB0 G7 GND B1 IO151RSB3 D7 IO14RSB0 G8 VCC B2 GAB2/IO154RSB3 D8 IO19RSB0 G9 GND B3 IO06RSB0 D9 GBC0/IO30RSB0 G10 GND B4 IO09RSB0 D10 GBB0/IO32RSB0 G12 IO50RSB1 B5 IO13RSB0 D11 GBA0/IO34RSB0 G13 GCB1/IO54RSB1 B6 IO10RSB0 D12 GND G14 GCC2/IO60RSB1 B7 IO12RSB0 D13 GBC2/IO40RSB1 G15 GCA2/IO58RSB1 B8 IO20RSB0 D14 IO51RSB1 H1* VCCPLF B9 IO23RSB0 D15 IO44RSB1 H2 GFA1/IO136RSB3 B10 IO25RSB0 E1 IO142RSB3 H3 GFB1/IO138RSB3 B11 IO24RSB0 E2 IO149RSB3 H4 NC B12 IO27RSB0 E3 IO153RSB3 H6 VCCIB3 B13 IO37RSB1 E4 GAC2/IO152RSB3 H7 GND B14 IO46RSB1 E12 IO43RSB1 H8 VCC B15 IO42RSB1 E13 IO49RSB1 H9 GND C1 IO155RSB3 E14 GCC0/IO53RSB1 H10 VCCIB1 C2 GAA2/IO156RSB3 E15 GCB0/IO55RSB1 H12 GCB2/IO59RSB1 C3 GND F1 IO141RSB3 H13 GCA0/IO57RSB1 C4 GAA1/IO01RSB0 F2 GFC1/IO140RSB3 H14 IO64RSB1 C5 GAB1/IO03RSB0 F3 IO145RSB3 H15 IO62RSB1 C6 IO07RSB0 F4 IO147RSB3 J1 GFA2/IO134RSB3 * Pin numbers G1 and H1 must be connected to ground because a PLL is not supported for AGLP060-CS/G201. 3 -1 0 v1.5 IGLOO PLUS Packaging 201-Pin CSP 201-Pin CSP 201-Pin CSP Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function J2 GFA0/IO135RSB3 M4 GND P10 IO92RSB2 J3 GFB2/IO133RSB3 M5 IO125RSB3 P11 IO95RSB2 J4 IO131RSB3 M6 IO98RSB2 P12 IO86RSB2 J6 VCCIB3 M7 IO96RSB2 P13 IO83RSB2 J7 GND M8 IO91RSB2 P14 VPUMP J8 VCC M9 IO89RSB2 P15 TRST J9 GND M10 IO82RSB2 R1 IO118RSB3 J10 VCCIB1 M11 GDA2/IO78RSB2 R2 GEB0/IO113RSB3 J12 IO61RSB1 M12 GND R3 GEA2/IO110RSB2 J13 IO63RSB1 M13 GDA1/IO76RSB1 R4 J14 IO68RSB1 M14 GDA0/IO77RSB1 FF/GEB2/IO109RSB 2 J15 IO66RSB1 M15 GDB0/IO75RSB1 R5 GEC2/IO108RSB2 K1 IO130RSB3 N1 IO117RSB3 R6 IO102RSB2 K2 GFC2/IO132RSB3 N2 IO120RSB3 R7 IO101RSB2 K3 IO127RSB3 N3 GND R8 IO104RSB2 K4 IO129RSB3 N4 GEB1/IO114RSB3 R9 IO97RSB2 K6 GND N5 IO107RSB2 R10 IO88RSB2 K7 VCCIB2 N6 IO100RSB2 R11 IO81RSB2 K8 VCCIB2 N7 IO94RSB2 R12 GDB2/IO79RSB2 K9 VCCIB2 N8 IO87RSB2 R13 TMS K10 VCCIB1 N9 IO85RSB2 R14 TDI K12 IO65RSB1 N10 GDC2/IO80RSB2 R15 TCK K13 IO67RSB1 N11 IO90RSB2 K14 IO69RSB1 N12 IO84RSB2 K15 IO70RSB1 N13 GND L1 IO126RSB3 N14 TDO L2 IO128RSB3 N15 VJTAG L3 IO121RSB3 P1 GEC0/IO115RSB3 L4 IO123RSB3 P2 GEC1/IO116RSB3 L12 GDB1/IO74RSB1 P3 GEA0/IO111RSB3 L13 GDC1/IO72RSB1 P4 GEA1/IO112RSB3 L14 IO71RSB1 P5 IO106RSB2 L15 GDC0/IO73RSB1 P6 IO105RSB2 M1 IO122RSB3 P7 IO103RSB2 M2 IO124RSB3 P8 IO99RSB2 M3 IO119RSB3 P9 IO93RSB2 v1.5 3 - 11 Package Pin Assignments 281-Pin CSP 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx 3 -1 2 v1.5 IGLOO PLUS Packaging 281-Pin CSP 281-Pin CSP 281-Pin CSP Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function A1 GND B18 VCCIB1 E13 IO48RSB0 A2 GAB0/IO02RSB0 B19 IO64RSB1 E14 GBB1/IO60RSB0 A3 GAC1/IO05RSB0 C1 GAB2/IO209RSB3 E15 IO53RSB0 A4 IO09RSB0 C2 IO210RSB3 E16 IO69RSB1 A5 IO13RSB0 C6 IO12RSB0 E18 IO68RSB1 A6 IO15RSB0 C14 IO47RSB0 E19 IO71RSB1 A7 IO18RSB0 C18 IO54RSB0 F1 IO198RSB3 A8 IO23RSB0 C19 GBB2/IO65RSB1 F2 GND A9 IO25RSB0 D1 IO206RSB3 F3 IO201RSB3 A10 VCCIB0 D2 IO208RSB3 F4 IO204RSB3 A11 IO33RSB0 D4 GAA0/IO00RSB0 F5 IO16RSB0 A12 IO41RSB0 D5 GAA1/IO01RSB0 F15 IO50RSB0 A13 IO43RSB0 D6 IO10RSB0 F16 IO74RSB1 A14 IO46RSB0 D7 IO17RSB0 F17 IO72RSB1 A15 IO55RSB0 D8 IO24RSB0 F18 GND A16 IO56RSB0 D9 IO27RSB0 F19 IO73RSB1 A17 GBC1/IO58RSB0 D10 GND G1 IO195RSB3 A18 GBA0/IO61RSB0 D11 IO31RSB0 G2 IO200RSB3 A19 GND D12 IO40RSB0 G4 IO202RSB3 B1 GAA2/IO211RSB3 D13 IO49RSB0 G5 IO08RSB0 B2 VCCIB0 D14 IO45RSB0 G7 GAC2/IO207RSB3 B3 GAB1/IO03RSB0 D15 GBB0/IO59RSB0 G8 VCCIB0 B4 GAC0/IO04RSB0 D16 GBA2/IO63RSB1 G9 IO26RSB0 B5 IO11RSB0 D18 GBC2/IO67RSB1 G10 IO35RSB0 B6 GND D19 IO66RSB1 G11 IO44RSB0 B7 IO21RSB0 E1 IO203RSB3 G12 VCCIB0 B8 IO22RSB0 E2 IO205RSB3 G13 IO51RSB0 B9 IO28RSB0 E4 IO07RSB0 G15 IO70RSB1 B10 IO32RSB0 E5 IO06RSB0 G16 IO75RSB1 B11 IO36RSB0 E6 IO14RSB0 G18 GCC0/IO80RSB1 B12 IO39RSB0 E7 IO20RSB0 G19 GCB1/IO81RSB1 B13 IO42RSB0 E8 IO29RSB0 H1 GFB0/IO191RSB3 B14 GND E9 IO34RSB0 H2 IO196RSB3 B15 IO52RSB0 E10 IO30RSB0 H4 GFC1/IO194RSB3 B16 GBC0/IO57RSB0 E11 IO37RSB0 H5 GFB1/IO192RSB3 B17 GBA1/IO62RSB0 E12 IO38RSB0 H7 VCCIB3 v1.5 3 - 13 Package Pin Assignments 281-Pin CSP 281-Pin CSP 281-Pin CSP Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function H8 VCC K15 IO89RSB1 N4 IO182RSB3 H9 VCCIB0 K16 GND N5 IO161RSB2 H10 VCC K18 IO88RSB1 N7 GEA2/IO164RSB2 H11 VCCIB0 K19 VCCIB1 N8 VCCIB2 H12 VCC L1 GFB2/IO187RSB3 N9 IO137RSB2 H13 VCCIB1 L2 IO185RSB3 N10 IO135RSB2 H15 IO77RSB1 L4 GFC2/IO186RSB3 N11 IO131RSB2 H16 GCB0/IO82RSB1 L5 IO184RSB3 N12 VCCIB2 H18 GCA1/IO83RSB1 L7 IO199RSB3 N13 VPUMP H19 GCA2/IO85RSB1 L8 VCCIB3 N15 IO117RSB2 J1 VCOMPLF L9 GND N16 IO96RSB1 J2 GFA0/IO189RSB3 L10 GND N18 IO98RSB1 J4 VCCPLF L11 GND N19 IO94RSB1 J5 GFC0/IO193RSB3 L12 VCCIB1 P1 IO174RSB3 J7 GFA2/IO188RSB3 L13 IO95RSB1 P2 GND J8 VCCIB3 L15 IO91RSB1 P3 IO176RSB3 J9 GND L16 NC P4 IO177RSB3 J10 GND L18 IO90RSB1 P5 GEA0/IO165RSB3 J11 GND L19 NC P15 IO111RSB2 J12 VCCIB1 M1 IO180RSB3 P16 IO108RSB2 J13 GCC1/IO79RSB1 M2 IO179RSB3 P17 GDC1/IO99RSB1 J15 GCA0/IO84RSB1 M4 IO181RSB3 P18 GND J16 GCB2/IO86RSB1 M5 IO183RSB3 P19 IO97RSB1 J18 IO76RSB1 M7 VCCIB3 R1 IO173RSB3 J19 IO78RSB1 M8 VCC R2 IO172RSB3 K1 VCCIB3 M9 VCCIB2 R4 GEC1/IO170RSB3 K2 GFA1/IO190RSB3 M10 VCC R5 GEB1/IO168RSB3 K4 GND M11 VCCIB2 R6 IO154RSB2 K5 IO19RSB0 M12 VCC R7 IO149RSB2 K7 IO197RSB3 M13 VCCIB1 R8 IO146RSB2 K8 VCC M15 IO122RSB2 R9 IO138RSB2 K9 GND M16 IO93RSB1 R10 IO134RSB2 K10 GND M18 IO92RSB1 R11 IO132RSB2 K11 GND M19 NC R12 IO130RSB2 K12 VCC N1 IO178RSB3 R13 IO118RSB2 K13 GCC2/IO87RSB1 N2 IO175RSB3 R14 IO112RSB2 3 -1 4 v1.5 IGLOO PLUS Packaging 281-Pin CSP 281-Pin CSP Pin Number AGLP125 Function Pin Number AGLP125 Function R15 IO109RSB2 V10 IO133RSB2 R16 GDA1/IO103RSB1 V11 IO127RSB2 R18 GDB0/IO102RSB1 V12 IO123RSB2 R19 GDC0/IO100RSB1 V13 IO120RSB2 T1 IO171RSB3 V14 GND T2 GEC0/IO169RSB3 V15 IO113RSB2 T4 GEB0/IO167RSB3 V16 GDA2/IO105RSB2 T5 IO157RSB2 V17 TDI T6 IO158RSB2 V18 VCCIB2 T7 IO148RSB2 V19 TDO T8 IO145RSB2 W1 GND T9 IO143RSB2 W2 FF/GEB2/IO163RSB2 T10 GND W3 IO155RSB2 T11 IO129RSB2 W4 IO152RSB2 T12 IO126RSB2 W5 IO150RSB2 T13 IO125RSB2 W6 IO147RSB2 T14 IO116RSB2 W7 IO142RSB2 T15 GDC2/IO107RSB2 W8 IO139RSB2 T16 TMS W9 IO136RSB2 T18 VJTAG W10 VCCIB2 T19 GDB1/IO101RSB1 W11 IO128RSB2 U1 IO160RSB2 W12 IO124RSB2 U2 GEA1/IO166RSB3 W13 IO119RSB2 U6 IO151RSB2 W14 IO115RSB2 U14 IO121RSB2 W15 IO114RSB2 U18 TRST W16 IO110RSB2 U19 GDA0/IO104RSB1 W17 GDB2/IO106RSB2 V1 IO159RSB2 W18 TCK V2 VCCIB3 W19 GND V3 GEC2/IO162RSB2 V4 IO156RSB2 V5 IO153RSB2 V6 GND V7 IO144RSB2 V8 IO141RSB2 V9 IO140RSB2 v1.5 3 - 15 Package Pin Assignments 289-Pin CSP A1 Ball Pad Corner 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx . 3 -1 6 v1.5 IGLOO PLUS Packaging 289-Pin CSP 289-Pin CSP 289-Pin CSP Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function A1 IO03RSB0 C5 VCCIB0 E9 IO22RSB0 A2 NC C6 IO09RSB0 E10 IO26RSB0 A3 NC C7 IO13RSB0 E11 VCCIB0 A4 GND C8 IO15RSB0 E12 NC A5 IO10RSB0 C9 IO21RSB0 E13 IO33RSB0 A6 IO14RSB0 C10 GND E14 IO36RSB1 A7 IO16RSB0 C11 IO29RSB0 E15 IO38RSB1 A8 IO18RSB0 C12 NC E16 VCCIB1 A9 GND C13 NC E17 NC A10 IO23RSB0 C14 NC F1 IO111RSB3 A11 IO27RSB0 C15 GND F2 NC A12 NC C16 IO34RSB0 F3 IO116RSB3 A13 NC C17 NC F4 VCCIB3 A14 GND D1 NC F5 IO117RSB3 A15 NC D2 IO119RSB3 F6 NC A16 NC D3 GND F7 NC A17 IO30RSB0 D4 IO02RSB0 F8 IO08RSB0 B1 IO01RSB0 D5 NC F9 IO12RSB0 B2 GND D6 NC F10 NC B3 NC D7 NC F11 NC B4 NC D8 GND F12 NC B5 IO07RSB0 D9 IO20RSB0 F13 NC B6 NC D10 IO25RSB0 F14 GND B7 VCCIB0 D11 NC F15 NC B8 IO17RSB0 D12 NC F16 IO37RSB1 B9 IO19RSB0 D13 GND F17 IO41RSB1 B10 IO24RSB0 D14 IO32RSB0 G1 IO110RSB3 B11 IO28RSB0 D15 IO35RSB0 G2 GND B12 VCCIB0 D16 NC G3 IO113RSB3 B13 NC D17 NC G4 NC B14 NC E1 VCCIB3 G5 NC B15 NC E2 IO114RSB3 G6 NC B16 IO31RSB0 E3 IO115RSB3 G7 GND B17 GND E4 IO118RSB3 G8 GND C1 NC E5 IO05RSB0 G9 VCC C2 IO00RSB0 E6 NC G10 GND C3 IO04RSB0 E7 IO06RSB0 G11 GND C4 NC E8 IO11RSB0 G12 IO40RSB1 v1.5 3 - 17 Package Pin Assignments 289-Pin CSP 289-Pin CSP 289-Pin CSP Pin Number AGLP030 Function Pin Number AGLP030 Function Pin Number AGLP030 Function G13 NC J17 GDA0/IO47RSB1 M4 IO98RSB3 G14 IO39RSB1 K1 GND M5 IO93RSB3 G15 IO44RSB1 K2 GEB0/IO106RSB3 M6 IO97RSB3 G16 NC K3 IO102RSB3 M7 NC G17 GND K4 IO104RSB3 M8 NC H1 NC K5 IO99RSB3 M9 IO71RSB2 H2 GEC0/IO108RSB3 K6 NC M10 NC H3 NC K7 GND M11 IO63RSB2 H4 IO112RSB3 K8 GND M12 NC H5 NC K9 GND M13 IO57RSB1 H6 IO109RSB3 K10 GND M14 NC H7 GND K11 GND M15 NC H8 GND K12 NC M16 NC H9 GND K13 NC M17 VCCIB1 H10 GND K14 NC N1 NC H11 GND K15 IO53RSB1 N2 NC H12 NC K16 GND N3 IO95RSB3 H13 NC K17 IO49RSB1 N4 IO96RSB3 H14 IO45RSB1 L1 IO103RSB3 N5 GND H15 VCCIB1 L2 IO101RSB3 N6 NC H16 GDB0/IO48RSB1 L3 NC N7 IO85RSB2 H17 IO42RSB1 L4 GND N8 IO79RSB2 J1 NC L5 NC N9 IO77RSB2 J2 GEA0/IO107RSB3 L6 NC N10 VCCIB2 J3 VCCIB3 L7 GND N11 NC J4 IO105RSB3 L8 GND N12 NC J5 NC L9 VCC N13 IO59RSB2 J6 NC L10 GND N14 NC J7 VCC L11 GND N15 GND J8 GND L12 IO58RSB1 N16 IO56RSB1 J9 GND L13 IO54RSB1 N17 IO55RSB1 J10 GND L14 VCCIB1 P1 IO94RSB3 J11 VCC L15 NC P2 NC J12 IO50RSB1 L16 NC P3 GND J13 IO43RSB1 L17 NC P4 NC J14 IO51RSB1 M1 NC P5 NC J15 IO52RSB1 M2 VCCIB3 P6 IO87RSB2 J16 GDC0/IO46RSB1 M3 IO100RSB3 P7 IO80RSB2 3 -1 8 v1.5 IGLOO PLUS Packaging 289-Pin CSP 289-Pin CSP Pin Number AGLP030 Function Pin Number AGLP030 Function P8 GND T12 IO64RSB2 P9 IO72RSB2 T13 NC P10 IO67RSB2 T14 GND P11 IO61RSB2 T15 NC P12 NC T16 TDI P13 VCCIB2 T17 TDO P14 NC U1 FF/IO90RSB2 P15 IO60RSB2 U2 GND P16 IO62RSB2 U3 NC P17 VJTAG U4 IO88RSB2 R1 GND U5 IO86RSB2 R2 IO91RSB2 U6 IO82RSB2 R3 NC U7 GND R4 NC U8 IO75RSB2 R5 NC U9 IO73RSB2 R6 VCCIB2 U10 IO68RSB2 R7 IO83RSB2 U11 IO66RSB2 R8 IO78RSB2 U12 GND R9 IO74RSB2 U13 NC R10 IO70RSB2 U14 NC R11 GND U15 NC R12 NC U16 TCK R13 NC U17 VPUMP R14 NC R15 NC R16 TMS R17 TRST T1 IO92RSB3 T2 IO89RSB2 T3 NC T4 GND T5 NC T6 IO84RSB2 T7 IO81RSB2 T8 IO76RSB2 T9 VCCIB2 T10 IO69RSB2 T11 IO65RSB2 v1.5 3 - 19 Package Pin Assignments 289-Pin CSP 289-Pin CSP 289-Pin CSP Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function A1 GAB1/IO03RSB0 C5 VCCIB0 E9 IO22RSB0 A2 NC C6 IO09RSB0 E10 IO26RSB0 A3 NC C7 IO13RSB0 E11 VCCIB0 A4 GND C8 IO15RSB0 E12 NC A5 IO10RSB0 C9 IO21RSB0 E13 GBB1/IO33RSB0 A6 IO14RSB0 C10 GND E14 GBA2/IO36RSB1 A7 IO16RSB0 C11 IO29RSB0 E15 GBB2/IO38RSB1 A8 IO18RSB0 C12 NC E16 VCCIB1 A9 GND C13 NC E17 IO44RSB1 A10 IO23RSB0 C14 NC F1 GFC1/IO140RSB3 A11 IO27RSB0 C15 GND F2 IO142RSB3 A12 NC C16 GBA0/IO34RSB0 F3 IO149RSB3 A13 NC C17 IO39RSB1 F4 VCCIB3 A14 GND D1 IO150RSB3 F5 GAB2/IO154RSB3 A15 NC D2 IO151RSB3 F6 IO153RSB3 A16 NC D3 GND F7 NC A17 GBC0/IO30RSB0 D4 GAB0/IO02RSB0 F8 IO08RSB0 B1 GAA1/IO01RSB0 D5 NC F9 IO12RSB0 B2 GND D6 NC F10 NC B3 NC D7 NC F11 NC B4 NC D8 GND F12 NC B5 IO07RSB0 D9 IO20RSB0 F13 GBC2/IO40RSB1 B6 NC D10 IO25RSB0 F14 GND B7 VCCIB0 D11 NC F15 IO43RSB1 B8 IO17RSB0 D12 NC F16 IO46RSB1 B9 IO19RSB0 D13 GND F17 IO45RSB1 B10 IO24RSB0 D14 GBB0/IO32RSB0 G1 GFC0/IO139RSB3 B11 IO28RSB0 D15 GBA1/IO35RSB0 G2 GND B12 VCCIB0 D16 IO37RSB1 G3 IO144RSB3 B13 NC D17 IO42RSB1 G4 IO145RSB3 B14 NC E1 VCCIB3 G5 IO146RSB3 B15 NC E2 IO147RSB3 G6 IO148RSB3 B16 GBC1/IO31RSB0 E3 GAC2/IO152RSB3 G7 GND B17 GND E4 GAA2/IO156RSB3 G8 GND C1 IO155RSB3 E5 GAC1/IO05RSB0 G9 VCC C2 GAA0/IO00RSB0 E6 NC G10 GND C3 GAC0/IO04RSB0 E7 IO06RSB0 G11 GND C4 NC E8 IO11RSB0 G12 IO48RSB1 3 -2 0 v1.5 IGLOO PLUS Packaging 289-Pin CSP 289-Pin CSP 289-Pin CSP Pin Number AGLP060 Function Pin Number AGLP060 Function Pin Number AGLP060 Function G13 IO41RSB1 J17 GCA1/IO56RSB1 M4 IO122RSB3 G14 IO47RSB1 K1 GND M5 GEB0/IO113RSB3 G15 IO49RSB1 K2 GFA0/IO135RSB3 M6 GEB1/IO114RSB3 G16 IO50RSB1 K3 GFB2/IO133RSB3 M7 NC G17 GND K4 IO128RSB3 M8 NC H1 VCOMPLF K5 IO123RSB3 M9 IO90RSB2 H2 GFB0/IO137RSB3 K6 IO125RSB3 M10 NC H3 NC K7 GND M11 IO83RSB2 H4 IO141RSB3 K8 GND M12 NC H5 IO143RSB3 K9 GND M13 GDA1/IO76RSB1 H6 GFB1/IO138RSB3 K10 GND M14 GDA0/IO77RSB1 H7 GND K11 GND M15 IO71RSB1 H8 GND K12 IO64RSB1 M16 IO69RSB1 H9 GND K13 IO61RSB1 M17 VCCIB1 H10 GND K14 IO66RSB1 N1 IO119RSB3 H11 GND K15 IO65RSB1 N2 IO120RSB3 H12 GCC1/IO52RSB1 K16 GND N3 GEC0/IO115RSB3 H13 IO51RSB1 K17 GCC2/IO60RSB1 N4 GEA0/IO111RSB3 H14 GCA0/IO57RSB1 L1 GFA2/IO134RSB3 N5 GND H15 VCCIB1 L2 GFC2/IO132RSB3 N6 NC H16 GCA2/IO58RSB1 L3 IO127RSB3 N7 IO104RSB2 H17 GCC0/IO53RSB1 L4 GND N8 IO98RSB2 J1 VCCPLF L5 IO121RSB3 N9 IO96RSB2 J2 GFA1/IO136RSB3 L6 GEC1/IO116RSB3 N10 VCCIB2 J3 VCCIB3 L7 GND N11 NC J4 IO131RSB3 L8 GND N12 NC J5 IO130RSB3 L9 VCC N13 GDB2/IO79RSB2 J6 IO129RSB3 L10 GND N14 NC J7 VCC L11 GND N15 GND J8 GND L12 GDC1/IO72RSB1 N16 GDB0/IO75RSB1 J9 GND L13 GDB1/IO74RSB1 N17 GDC0/IO73RSB1 J10 GND L14 VCCIB1 P1 IO118RSB3 J11 VCC L15 IO70RSB1 P2 IO117RSB3 J12 GCB2/IO59RSB1 L16 IO68RSB1 P3 GND J13 GCB1/IO54RSB1 L17 IO67RSB1 P4 NC J14 IO62RSB1 M1 IO126RSB3 P5 NC J15 IO63RSB1 M2 VCCIB3 P6 IO106RSB2 J16 GCB0/IO55RSB1 M3 IO124RSB3 P7 IO99RSB2 v1.5 3 - 21 Package Pin Assignments 289-Pin CSP 289-Pin CSP Pin Number AGLP060 Function Pin Number AGLP060 Function P8 GND T12 IO82RSB2 P9 IO91RSB2 T13 NC P10 IO86RSB2 T14 GND P11 IO81RSB2 T15 NC P12 NC T16 TDI P13 VCCIB2 T17 TDO P14 NC U1 FF/GEB2/IO109RSB2 P15 GDA2/IO78RSB2 U2 GND P16 GDC2/IO80RSB2 U3 NC P17 VJTAG U4 IO107RSB2 R1 GND U5 IO105RSB2 R2 GEA2/IO110RSB2 U6 IO101RSB2 R3 NC U7 GND R4 NC U8 IO94RSB2 R5 NC U9 IO92RSB2 R6 VCCIB2 U10 IO87RSB2 R7 IO102RSB2 U11 IO85RSB2 R8 IO97RSB2 U12 GND R9 IO93RSB2 U13 NC R10 IO89RSB2 U14 NC R11 GND U15 NC R12 NC U16 TCK R13 NC U17 VPUMP R14 NC R15 NC R16 TMS R17 TRST T1 GEA1/IO112RSB3 T2 GEC2/IO108RSB2 T3 NC T4 GND T5 NC T6 IO103RSB2 T7 IO100RSB2 T8 IO95RSB2 T9 VCCIB2 T10 IO88RSB2 T11 IO84RSB2 3 -2 2 v1.5 IGLOO PLUS Packaging 289-Pin CSP 289-Pin CSP 289-Pin CSP Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function A1 GAB1/IO03RSB0 C5 VCCIB0 E9 IO32RSB0 A2 IO11RSB0 C6 IO17RSB0 E10 IO36RSB0 A3 IO08RSB0 C7 IO23RSB0 E11 VCCIB0 A4 GND C8 IO27RSB0 E12 IO56RSB0 A5 IO19RSB0 C9 IO33RSB0 E13 GBB1/IO60RSB0 A6 IO24RSB0 C10 GND E14 GBA2/IO63RSB1 A7 IO26RSB0 C11 IO43RSB0 E15 GBB2/IO65RSB1 A8 IO30RSB0 C12 IO45RSB0 E16 VCCIB1 A9 GND C13 IO50RSB0 E17 IO73RSB1 A10 IO35RSB0 C14 IO52RSB0 F1 GFC1/IO194RSB3 A11 IO38RSB0 C15 GND F2 IO196RSB3 A12 IO40RSB0 C16 GBA0/IO61RSB0 F3 IO202RSB3 A13 IO42RSB0 C17 IO68RSB1 F4 VCCIB3 A14 GND D1 IO204RSB3 F5 GAB2/IO209RSB3 A15 IO48RSB0 D2 IO205RSB3 F6 IO208RSB3 A16 IO54RSB0 D3 GND F7 IO14RSB0 A17 GBC0/IO57RSB0 D4 GAB0/IO02RSB0 F8 IO20RSB0 B1 GAA1/IO01RSB0 D5 IO07RSB0 F9 IO25RSB0 B2 GND D6 IO10RSB0 F10 IO29RSB0 B3 IO06RSB0 D7 IO18RSB0 F11 IO51RSB0 B4 IO13RSB0 D8 GND F12 IO53RSB0 B5 IO15RSB0 D9 IO34RSB0 F13 GBC2/IO67RSB1 B6 IO21RSB0 D10 IO41RSB0 F14 GND B7 VCCIB0 D11 IO47RSB0 F15 IO75RSB1 B8 IO28RSB0 D12 IO55RSB0 F16 IO71RSB1 B9 IO31RSB0 D13 GND F17 IO77RSB1 B10 IO37RSB0 D14 GBB0/IO59RSB0 G1 GFC0/IO193RSB3 B11 IO39RSB0 D15 GBA1/IO62RSB0 G2 GND B12 VCCIB0 D16 IO66RSB1 G3 IO198RSB3 B13 IO44RSB0 D17 IO70RSB1 G4 IO203RSB3 B14 IO46RSB0 E1 VCCIB3 G5 IO201RSB3 B15 IO49RSB0 E2 IO200RSB3 G6 IO206RSB3 B16 GBC1/IO58RSB0 E3 GAC2/IO207RSB3 G7 GND B17 GND E4 GAA2/IO211RSB3 G8 GND C1 IO210RSB3 E5 GAC1/IO05RSB0 G9 VCC C2 GAA0/IO00RSB0 E6 IO12RSB0 G10 GND C3 GAC0/IO04RSB0 E7 IO16RSB0 G11 GND C4 IO09RSB0 E8 IO22RSB0 G12 IO72RSB1 v1.5 3 - 23 Package Pin Assignments 289-Pin CSP 289-Pin CSP 289-Pin CSP Pin Number AGLP125 Function Pin Number AGLP125 Function Pin Number AGLP125 Function G13 IO64RSB1 J17 GCA1/IO83RSB1 M4 IO172RSB3 G14 IO69RSB1 K1 GND M5 GEB0/IO167RSB3 G15 IO78RSB1 K2 GFA0/IO189RSB3 M6 GEB1/IO168RSB3 G16 IO76RSB1 K3 GFB2/IO187RSB3 M7 IO159RSB2 G17 GND K4 IO179RSB3 M8 IO161RSB2 H1 VCOMPLF K5 IO175RSB3 M9 IO135RSB2 H2 GFB0/IO191RSB3 K6 IO177RSB3 M10 IO128RSB2 H3 IO195RSB3 K7 GND M11 IO121RSB2 H4 IO197RSB3 K8 GND M12 IO113RSB2 H5 IO199RSB3 K9 GND M13 GDA1/IO103RSB1 H6 GFB1/IO192RSB3 K10 GND M14 GDA0/IO104RSB1 H7 GND K11 GND M15 IO97RSB1 H8 GND K12 IO88RSB1 M16 IO96RSB1 H9 GND K13 IO94RSB1 M17 VCCIB1 H10 GND K14 IO95RSB1 N1 IO180RSB3 H11 GND K15 IO93RSB1 N2 IO178RSB3 H12 GCC1/IO79RSB1 K16 GND N3 GEC0/IO169RSB3 H13 IO74RSB1 K17 GCC2/IO87RSB1 N4 GEA0/IO165RSB3 H14 GCA0/IO84RSB1 L1 GFA2/IO188RSB3 N5 GND H15 VCCIB1 L2 GFC2/IO186RSB3 N6 IO156RSB2 H16 GCA2/IO85RSB1 L3 IO182RSB3 N7 IO148RSB2 H17 GCC0/IO80RSB1 L4 GND N8 IO144RSB2 J1 VCCPLF L5 IO173RSB3 N9 IO137RSB2 J2 GFA1/IO190RSB3 L6 GEC1/IO170RSB3 N10 VCCIB2 J3 VCCIB3 L7 GND N11 IO119RSB2 J4 IO185RSB3 L8 GND N12 IO111RSB2 J5 IO183RSB3 L9 VCC N13 GDB2/IO106RSB2 J6 IO181RSB3 L10 GND N14 IO109RSB2 J7 VCC L11 GND N15 GND J8 GND L12 GDC1/IO99RSB1 N16 GDB0/IO102RSB1 J9 GND L13 GDB1/IO101RSB1 N17 GDC0/IO100RSB1 J10 GND L14 VCCIB1 P1 IO174RSB3 J11 VCC L15 IO98RSB1 P2 IO171RSB3 J12 GCB2/IO86RSB1 L16 IO92RSB1 P3 GND J13 GCB1/IO81RSB1 L17 IO91RSB1 P4 IO160RSB2 J14 IO90RSB1 M1 IO184RSB3 P5 IO157RSB2 J15 IO89RSB1 M2 VCCIB3 P6 IO154RSB2 J16 GCB0/IO82RSB1 M3 IO176RSB3 P7 IO152RSB2 3 -2 4 v1.5 IGLOO PLUS Packaging 289-Pin CSP 289-Pin CSP Pin Number AGLP125 Function Pin Number AGLP125 Function P8 GND T12 IO124RSB2 P9 IO132RSB2 T13 IO122RSB2 P10 IO125RSB2 T14 GND P11 IO126RSB2 T15 IO115RSB2 P12 IO112RSB2 T16 TDI P13 VCCIB2 T17 TDO P14 IO108RSB2 U1 FF/GEB2/IO163RSB2 P15 GDA2/IO105RSB2 U2 GND P16 GDC2/IO107RSB2 U3 IO151RSB2 P17 VJTAG U4 IO149RSB2 R1 GND U5 IO146RSB2 R2 GEA2/IO164RSB2 U6 IO142RSB2 R3 IO158RSB2 U7 GND R4 IO155RSB2 U8 IO138RSB2 R5 IO150RSB2 U9 IO136RSB2 R6 VCCIB2 U10 IO133RSB2 R7 IO145RSB2 U11 IO129RSB2 R8 IO141RSB2 U12 GND R9 IO134RSB2 U13 IO123RSB2 R10 IO130RSB2 U14 IO120RSB2 R11 GND U15 IO117RSB2 R12 IO118RSB2 U16 TCK R13 IO116RSB2 U17 VPUMP R14 IO114RSB2 R15 IO110RSB2 R16 TMS R17 TRST T1 GEA1/IO166RSB3 T2 GEC2/IO162RSB2 T3 IO153RSB2 T4 GND T5 IO147RSB2 T6 IO143RSB2 T7 IO140RSB2 T8 IO139RSB2 T9 VCCIB2 T10 IO131RSB2 T11 IO127RSB2 v1.5 3 - 25 Package Pin Assignments Part Number and Revision Date Part Number 51700102-003-5 Revised January 2009 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Current Version (v1.5) Page v1.4 (August 2008) The "201-Pin CSP" pin table was revised to add a note regarding pins G1 and H1. 3-10 v1.3 The "128-Pin VQFP" package drawing and pin table are new. 3-1 (June 2008) The "176-Pin VQFP" package drawing and pin table are new. 3-4 v1.2 The "281-Pin CSP" package drawing is new. 3-12 (June 2008) The "281-Pin CSP" table for the AGLP125 device is new. 3-13 The "289-Pin CSP" package drawing was incorrect. The graphic was showing the CS281 mechanical drawing and not the CS289 mechanical drawing. This has now been corrected. 3-16 v1.1 (June 2008) The "289-Pin CSP" table for the AGLP030 device is new. 3-17 v1.0 The "289-Pin CSP" table for the AGLP060 device is new. 3-20 (January 2008) The "289-Pin CSP" table for the AGLP125 device is new. 3-23 3 -2 6 v1.5 IGLOO PLUS Packaging Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v1.5 3 - 27 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700102-005-10/4.09