DFPMU-DP - Digital Core Design - Datasheet.Directory

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Floating Point Coprocessor

Double Precision

ver 3.03

OVERVIEW

DFPMU-DP is a Floating Point Coprocessor,

designed to assist CPU in performing the

floating point mathematic computations.

DFPMU-DP directly replaces C software

functions, by equivalent, very fast hardware

operations, which significantly accelerate

system performance. It doesn’t require any

programming, so it also doesn’t require any

modifications made in the main software.

Everything is done automatically during soft-

ware compilation by the DFPMU-DP C driver.

DFPMU-DP was designed to operate with

DCD’s DP8051, but can also operate with

any other 8-, 16- and 32-bit processor. Driv-

ers for all popular 8051 C compilers are de-

livered together with the DFPMU-DP pack-

age.

DFPMU-DP uses the specialized CORDIC

and standard algorithms to compute math

functions. It supports addition, subtraction,

multiplication, division, square root, com-

parison, and trigonometric functions: sine,

cosine, tangent and arctangent. It has built-

in conversion instructions from integer type to

floating point type and vice versa. The input

numbers format is according to IEEE-754

standard. DFPMU-DP supports double and

single precision real numbers, 8-bit, 16-bit

and 32-bit integers. DFPMU-DP is prepared

to use with 8-, 16- and 32-bit processors.

Each floating point function can be turned

on/off at configuration level providing the

flexible scalability of DFPMU-DP module. It

allows save silicon space and provides exact

configuration required by certain application.

DFPMU-DP is a technology independent de-

sign that can be implemented in a variety of

process technologies.

APPLICATIONS

Math coprocessors

DSP algorithms

Embedded arithmetic coprocessor

Fast data processing & control

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FSIN, FCOS – sine, cosine

KEY FEATURES

Direct replacement for C double, float

software functions such as: +, -, *, /,==,

!=,>=, <=, <, >

Configurability of all available functions

C interface supplied for all popular compil-

ers: GNU C/C++, 8051 compilers

No programming required

IEEE-754 Double precision real format

support – double type

IEEE-754 Single precision real format

support – float type

8-bit, 16-bit 32-bit and 52-bit integers for-

mat supported – integer types

Flexible arguments and result registers

location

Performs the following functions:

FADD, FSUB – addition, subtraction

FMUL, FDIV – multiplication, division

FSQRT – square root

FXAM – examine input data

FUCOM – comparison

FTAN – tangent

FATAN – arctangent

FCLD, FILD – 8-bit, 16-bit integer to dou-

ble

FLLD, FELD – 32-bit, 52-bit integer to

double

FCST, FIST – double to 8-bit, 16-bi inte-

ger

FLST, FEST – double to 32-bit, 52-bit in-

teger

FFLD – float to double

FFST – double to float

Exceptions built-in routines

Masks each exception indicator:

Precision lack PE

Underflow result UE

Overflow result OE

Invalid operand IE

Division by z ero ZE

Denormal operan d DE

Fully configurable

Fully synthesizable, static synchronous

design with no internal tri-states

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted Netlist or/and

plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation mac-

ros

NCSim automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

● Phone & email support

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design license allows using IP Core in

single FPGA bitstream and ASIC implemen-

tation. It also permits FPGA prototyping be-

fore ASIC production.

Unlimited Designs license allows using IP

Core in unlimited number of FPGA bitstreams

and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

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Single Design license for

VHDL, Verilog source code called HDL

Source

○ Encrypted, or plain text EDIF called Netlist

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Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Desi gns

SYMBOL

PINS DESCRIPTION

PIN TYPE DESCRIPTION

clk Input Global system clock

rst Input Global system reset

cs Input Chip select for read/write

datai[31:0]1Input Data bus input

addr[4:2]2Input Register address to read/write

we Input Data write enable

datao[31:0]1Output Data bus output

irq Output Interrupt request indicator

1 – data bus can be configured as 8-, 16- or 32- bit

depends on processor’s bus size

2 – address bus is aligned to work with 8- (3:0), 16-

(3:1) or 32- (4:2) bit processors

BLOCK DIAGRAM

Mantissa – performs operations on mantissa

part of number. The addition, subtraction,

multiplication, division, square root, compari-

son and conversion operations are executed

in this module. It contains mantissas and

work registers.

CORDIC – performs trigonometric operations

on input data. The sine, cosine, tangent and

arctangent operations are executed in this

module. It contains three work registers.

Exponent – performs operations on expo-

nent part of number. The addition, subtrac-

tion, shifting, comparison and conversion

operations are executed in this module. It

contains exponents and work registers.

Align – performs the numbers analyze

against IEEE-754 standard compliance. In-

datai(31:0)

1

datao(31:0)

1

irqwe

rst

clk

addr(4:2)

2

cs

Mantissa

Align

Shifter

Exponent

Control

Unit

clk

rst

datai(31:0)

1

datao(31:0)1

irq

addr(4:2)2

we

cs

Interface

CORDIC

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formation about the data classes are passed

as result to appropriate internal module.

Shifter – performs mantissa shifting during

normalization, denormalization operations.

Information about shifted-out bits are stored

for rounding process.

Control Unit – manages execution of all

instructions and internal operation required to

execute particular function.

Interface – makes interface between exter-

nal device and DFPMU-DP internal 32-bit

modules. It contains data, control and status

registers. It can be configured to work with 8-,

16- and 32-bit processors.

PERFORMANCE

The following table gives a survey about

the Core area and performance in the AL-

TERA® devices after Place & Route (all key

features have been included):

Device Speed

grade Logic Cells Fmax

CYCLONE -6 7070 77 MHz

CYCLONE-II -6 7080 68 MHz

STRATIX -5 7070 82 MHz

STRATIX-II -3 5290 109 MHz

Core performance in ALTERA® devices

DFPMU-DP floating point instructions per-

formance has been compared to standard C

library functions delivered with every com-

mercial C compiler. Each program was exe-

cuted in the same system environments.

Number of clock periods were measured be-

tween input data loading into work registers

and output result storing after operation.

The results are placed in table below. Im-

provement has been computed as number of:

(NIOS-II CLK) divided by (NIOS-II+DFPMU-

DP CLK), required to execute particular in-

struction.

IEEE-754 FP Instruction Improvement

Addition 12.0

Subtraction 11.7

Multiplication 10.6

Division 15.0

Square Root 21.5

Sine 52.0

Cosine 60.8

Tangent 97.9

Arcs Tangent 78.7

Average speed improvement: 38.3

More details are available in core docu-

mentation.

The following table gives a survey about

the 32-bit NIOS-II+DFPMU-DP performance

compared to 32-bit NIOS-II.

Device Improvement

NIOS-II 1.0

NIOS-II+DFPMU (arithmetic) 14.1

NIOS-II+DFPMU (trigonometric) 72.4

NIOS-II+DFPMU (overall) 38.8

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are trademarks of their respective owners.

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1

10,2

72,4

38,8

0

10

20

30

40

50

32-bit NIOS-I I

NIOS-II+DFPMU-DP (arithmetic)

NIOS-II+DFPMU-DP (trigonometric)

NIOS-I I+DFPMU-DP (overall )

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: info@dcd.pl

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fax : +48 32 282 74 37

Distributors:

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