Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 OPAx348 1-MHz, 45-A, CMOS, Rail-to-Rail Operational Amplifiers 1 Features 3 Description * * * * * The OPAx348 series of amplifiers are single-supply, low-power, CMOS operational amplifiers. Featuring an extended bandwidth of 1 MHz, and a supply current of 45 A, the OPAx348 series is useful for low-power applications on single supplies of 2.1 V to 5.5 V. 1 * * Low IQ: 45 A (Typical) Rail-To-Rail Input and Output Single Supply: 2.1 V to 5.5 V Input Bias Current: 0.5 pA Micro Size Packages: - 5-Pin SC70 - 8-Pin SOT-23 - 14-Pin TSSOP Excellent Bandwidth-to-Power Consumption Trade-off Number of Channels: - OPA348: 1 - OPA2348: 2 - OPA4348: 4 A low supply current of 45 A and an input bias current of 0.5 pA, makes the OPAx348 series an optimal candidate for low-power applications such as smoke detectors and other high-impedance sensors. The OPA348 is available in the miniature 5-pin SC70 (SOT), 5-pin SOT-23 (SOT), and 8-pin SO (SOIC) packages. The OPA2348 is available in 8-pin SOT-23 (SOT) and 8-pin SO (SOIC) packages, and the OPA4348 is offered in space-saving 14-pin TSSOP and 14-pin SO (SOIC) packages. The extended temperature range of -40C to +125C over all supply voltages offers design flexibility. 2 Applications * * * * * Device Information(1) Portable Equipment Battery-Powered Equipment Smoke Alarms CO Detectors Medical Instrumentation PART NUMBER OPA348 OPA2348 OPA4348 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm SC70 (5) 2.00 mm x 1.25 mm SOIC (8) 4.90 mm x 3.91 mm SOT-23 (8) 2.90 mm x 1.63 mm VSSOP (8) 3.00 mm x 3.00 mm SOIC (14) 8.65 mm x 3.91 mm TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. ADC Input Driver +5 V 0.1 mF 8 V+ 500 W 0.1 mF 1 VREF DCLOCK +In ADS7822 12-Bit A/D OPA348 2 VIN -In 3300 pF DOUT CS/SHDN 3 7 6 5 Serial Interface GND 4 VIN = 0 V to 5 V for 0 V to 5 V output. NOTE: A/D Input = 0 to VREF RC network filters high frequency noise. Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6 6 6 7 7 7 7 9 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information: OPA348 .................................. Thermal Information: OPA2348 ................................ Thermal Information: OPA4348 ................................ Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................ Functional Block Diagram ....................................... Feature Description ................................................ Device Functional Modes........................................ 12 12 12 15 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Application .................................................. 18 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Device Support .................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 24 24 24 24 24 24 25 25 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (March 2013) to Revision H Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 * Changed OPA348 DCK package designator from SOT to SC70 to match Package Option Addendum information .......... 3 * Deleted Lead temperature specification from Absolute Maximum Ratings table .................................................................. 6 * Reformatted Thermal Information table note ......................................................................................................................... 7 * Changed second and third paragraphs of Driving A/D Converters section to eliminate redundancy .................................. 17 Changes from Revision F (October 2012) to Revision G * Page Changed 2nd footnote for Absolute Maximum Ratings table ................................................................................................. 6 Changes from Revision E (September 2012) to Revision F * 2 Page Deleted Packaging and Ordering information table data ...................................................................................................... 1 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 5 Pin Configuration and Functions OPA348 D Package 8-Pin SOIC Top View OPA348 DBV Package 5-Pin SOT-23 Top View NC 1 8 NC OUT 1 -IN 2 7 V+ V- 2 +IN 3 6 OUT +IN 3 V- 4 5 NC 5 V+ 4 -IN OPA348 DCK Package 5-Pin SC70 (Micro size) Top View +IN 1 5 V+ V- 2 -IN 3 4 OUT Pin Functions: OPA348 PIN NAME I/O DESCRIPTION DBV (SOT-23) DCK (SC70) D (SOIC) -IN 4 3 2 I Negative (inverting) input +IN 3 1 3 I Positive (noninverting) input NC -- -- 1, 5, 8 -- No internal connection (can be left floating) OUT 1 4 6 O Output V- 2 2 4 -- Negative (lowest) power supply V+ 5 5 7 -- Positive (highest) power supply Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 3 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com OPA2348 D, DCN, and DGK Packages 8-Pin SOIC, SOT, and VSSOP Top View OUT A 1 -IN A 2 +IN A 3 V- 4 A B 8 V+ 7 OUT B 6 -IN B 5 +IN B Pin Functions: OPA2348 PIN NAME D (SOIC) DCN (SOT-23) DGK (VSSOP) I/O -IN A 2 2 2 I Inverting input, channel A -IN B 6 6 6 I Inverting input, channel B +IN A 3 3 3 I Noninverting input, channel A +IN B 5 5 5 I Noninverting input, channel B OUT A 1 1 1 O Output, channel A OUT B 7 7 7 O Output, channel B V- 4 4 4 -- Negative (lowest) power supply V+ 8 8 8 -- Positive (highest) power supply 4 Submit Documentation Feedback DESCRIPTION Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 OPA4348 D and PW Packages 14-Pin SOIC and TSSOP Top View OUTA 1 INA 2 A 14 OUT D 13 IN D D +INA 3 12 +IN D V+ 4 11 V +IN B 5 10 +IN C B C IN B 6 9 IN C OUT B 7 8 OUT C Pin Functions: OPA4348 PIN NAME D (SOIC) PW (TSSOP) I/O DESCRIPTION -IN A 2 2 I Inverting input, channel A -IN B 6 6 I Inverting input, channel B -IN C 9 9 I Inverting input, channel C -IN D 13 13 I Inverting input, channel D +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B +IN C 10 10 I Noninverting input, channel C +IN D 12 12 I Noninverting input, channel D OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B OUT C 8 8 O Output, channel C OUT D 14 14 O Output, channel D V- 11 11 -- Negative (lowest) power supply V+ 4 4 -- Positive (highest) power supply Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 5 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Supply voltage, VS = (V+) - (V-) Voltage Signal input terminals, voltage (2) (V-) - 0.5 10 Output short-circuit (3) (1) (2) (3) mA Continuous Junction, TJ Temperature V (V+) + 0.5 Signal input terminals, current (2) Current UNIT 7.5 150 Operating, TA -65 150 Storage, Tstg -65 150 C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only. Functional operation of the device at these conditions, or beyond the specified operating conditions, is not implied. Input terminals are not diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current-limited to 10 mA or less. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage 2.1 5.5 V Specified temperature -40 125 C 6 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 6.4 Thermal Information: OPA348 OPA348 THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) D (SOIC) 5 PINS 5 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance 229 267 142 C/W RJC(top) Junction-to-case (top) thermal resistance 99 81 90 C/W RJB Junction-to-board thermal resistance 55 55 83 C/W JT Junction-to-top characterization parameter 7.7 1.2 40 C/W JB Junction-to-board characterization parameter 54 54 82 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- -- C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953). 6.5 Thermal Information: OPA2348 OPA2348 THERMAL METRIC (1) D (SOIC) DGK (VSSOP) DCN (SOT-23) UNIT 8 PINS 8 PINS 8 PINS RJA Junction-to-ambient thermal resistance 134 191 147 C/W RJC(top) Junction-to-case (top) thermal resistance 90 83 115 C/W RJB Junction-to-board thermal resistance 79 112 32 C/W JT Junction-to-top characterization parameter 30 18 38 C/W JB Junction-to-board characterization parameter 78 110 33 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- -- C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953). 6.6 Thermal Information: OPA4348 OPA4348 THERMAL METRIC (1) D (SOIC) PW (TSSOP) 14 PINS 14 PINS UNIT RJA Junction-to-ambient thermal resistance 78 121 C/W RJC(top) Junction-to-case (top) thermal resistance 35 49 C/W RJB Junction-to-board thermal resistance 33 63 C/W JT Junction-to-top characterization parameter 7 5.9 C/W JB Junction-to-board characterization parameter 33 62 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953). 6.7 Electrical Characteristics at VS = 2.5 V to 5.5 V, TA = 25C, RL = 100 k connected to VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1 5 UNIT OFFSET VOLTAGE VS = 5 V, VCM = (V-) + 0.8 V VOS Input offset voltage VS = 5 V, VCM = (V-) + 0.8 V, at TA = -40C to 125C dVOS /dT Input offset voltage drift At TA = -40C to 125C 4 VS = 2.5 V to 5.5 V, VCM < (V+) - 1.7 V PSRR Input offset voltage versus power supply Channel separation mV 6 60 At TA = -40C to 125C, VS = 2.5 V to 5.5 V, VCM < (V+) - 1.7 V V/C 175 300 V/V At dc 0.2 V/V At f = 1 kHz 134 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range (V-) - 0.2 Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 (V+) + 0.2 Submit Documentation Feedback V 7 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com Electrical Characteristics (continued) at VS = 2.5 V to 5.5 V, TA = 25C, RL = 100 k connected to VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER CMRR Common-mode rejection ratio TEST CONDITIONS MIN TYP (V-) - 0.2 V < VCM < (V+) - 1.7 V 70 82 (V-) < VCM < (V+) - 1.7 V, at TA = -40C to 125C 66 VS = 5.5 V, (V-) - 0.2 V < VCM < (V+) + 0.2 V 60 VS = 5.5 V, (V-) < VCM < (V+), at TA = -40C to 125C 56 MAX UNIT dB 71 INPUT BIAS CURRENT IB Input bias current 0.5 10 pA IOS Input offset current 0.5 10 pA INPUT IMPEDANCE Differential 1013 || 3 || pF Common-mode 1013 || 6 || pF NOISE Input voltage noise VCM < (V+) - 1.7 V, f = 0.1 Hz to 10 Hz 10 VPP en Input voltage noise density VCM < (V+) - 1.7 V, f = 1 kHz 35 nV/Hz in Input current noise density VCM < (V+) - 1.7 V, f = 1 kHz 4 fA/Hz OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 5 V, RL = 100 k, 0.025 V < VO < 4.975 V 94 VS = 5 V, RL = 100 k, 0.025 V < VO < 4.975 V, at TA = -40C to 125C 90 VS = 5 V, RL = 5 k, 0.125 V < VO < 4.875 V 90 VS = 5 V, RL = 5 k, 0.125 V < VO < 4.875 V, at TA = -40C to 125C 88 108 dB 98 OUTPUT RL = 100 k, AOL > 94 dB Voltage output swing from rail 18 RL = 100 k, AOL > 90 dB, at TA = -40C to 125C 25 RL = 5 k, AOL > 90 dB 100 RL = 5 k, AOL > 88 dB, at TA = -40C to 125C ISC Short-circuit current CLOAD Capacitive load drive 25 125 mV 125 10 mA See Typical Characteristics FREQUENCY RESPONSE GBP Gain-bandwidth product CL = 100 pF SR Slew rate CL = 100 pF, G = +1 Settling time, 0.1% CL = 100 pF, VS = 5.5 V, 2-V Step, G = +1 5 Settling time, 0.01% CL = 100 pF, VS = 5.5 V, 2-V Step, G = +1 7 Overload recovery time CL = 100 pF, VIN x Gain > VS Total harmonic distortion + noise CL = 100 pF, VS = 5.5 V, VO = 3 VPP, G = +1, f = 1 kHz tS THD+N 1 MHz 0.5 V/s s 1.6 s 0.0023% POWER SUPPLY VS Specified voltage 2.5 Operating voltage IQ 8 Quiescent current (per amplifier) Submit Documentation Feedback IO = 0 mA IO = 0 mA, at TA = -40C to 125C 5.5 V 2.1 5.5 V 45 65 75 A Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 6.8 Typical Characteristics at TA = 25C, RL = 100 k connected to VS / 2, and VOUT = VS / 2 (unless otherwise noted) 140 100 0 -45 80 Gain 60 Phase -90 40 20 PSRR, CMRR (dB) 80 100 Phase () Open-Loop Gain (dB) 120 -135 CMRR 60 40 PSRR 20 0 -20 0.1 1 10 100 1k 10k 100k 1M 0 -180 10M 10 100 1k Frequency (Hz) Figure 1. Open-Loop Gain and Phase vs Frequency 6 1M 10M Figure 2. PSRR and CMRR vs Frequency Channel Separation (dB) 5 Output Voltage (VPP) 100k 140 VS = 5.5 V VS = 5 V 4 10k Frequency (Hz) 3 2 VS = 2.5 V 120 100 80 1 60 0 1k 10 k 100 k 1M 10 10 M 100 1k 45 7 IQ 35 4 Output Voltage Swing (V) 10 Short-Circuit Current (mA) Quiescent Current (mA) 55 +125C 1 4 4.5 5 5.5 +25C 1.5 -40C 1 Sourcing Current 0.5 0 -0.5 -1 Sinking Current -40C -1.5 +25C -2 25 3.5 10M VS = 2.5 V 2 ISC 3 1M 2.5 13 2.5 100k Figure 4. Channel Separation vs Frequency Figure 3. Maximum Output Voltage vs Frequency 65 2 10k Frequency (Hz) Frequency (Hz) +125C -2.5 0 5 Supply Voltage (V) 10 15 20 Output Current (mA) Figure 5. Quiescent and Short-Circuit Current vs Supply Voltage Figure 6. Output Voltage Swing vs Output Current Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 9 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com Typical Characteristics (continued) at TA = 25C, RL = 100 k connected to VS / 2, and VOUT = VS / 2 (unless otherwise noted) 100 130 Open-Loop Gain and Power-Supply Rejection (dB) Common-Mode Rejection (dB) AOL, RL = 100 kW 90 V- < VCM < (V+) - 1.7 V 80 V- < VCM < V+ 70 60 50 120 AOL, RL = 5 kW 110 100 90 80 PSRR 70 60 -75 -50 -25 0 25 50 75 100 125 150 -75 -50 0 -25 Temperature (C) Figure 7. Common-Mode Rejection vs Temperature 14 ISC 55 12 45 10 IQ 35 8 25 6 15 4 -25 0 25 50 100 125 150 75 100 125 1k 100 10 1 0.1 150 -50 -75 0 -25 Temperature (C) 25 50 75 100 125 150 Temperature (C) Figure 9. Quiescent and Short-Circuit Current vs Temperature Figure 10. Input Bias (IB) Current vs Temperature 25 20 16 Percentage of Amplifiers (%) Typical production distribution of packaged units. 18 Percent of Amplifiers (%) 75 10k Input Bias Current (pA) Quiescent Current (mA) 65 -50 50 Figure 8. Open-Loop Gain and PSRR vs Temperature 16 Short-Circuit Current (mA) 75 -75 25 Temperature (C) 14 12 10 8 6 4 Typical production distribution of packaged units. 20 15 10 5 2 0 0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 1 2 3 Figure 11. Offset Voltage Production Distribution 10 Submit Documentation Feedback 4 5 6 7 8 9 10 11 12 Offset Voltage Drift (mV/C) Offset Voltage (mV) Figure 12. Offset Voltage Drift Magnitude Production Distribution Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 Typical Characteristics (continued) at TA = 25C, RL = 100 k connected to VS / 2, and VOUT = VS / 2 (unless otherwise noted) 60 60 50 50 40 40 Overshoot (%) Small-Signal Overshoot (%) G = -1 V/V, RFB = 100 kW 30 G = +1 V/V, RL = 100 kW 20 30 20 G = -1 V/V, RFB = 5 kW G = 5 V/V, RFB = 100 kW 10 10 0 0 10 100 1k 10 k 10 100 10 k Figure 13. Small-Signal Overshoot vs Load Capacitance Figure 14. Percent Overshoot vs Load Capacitance 20mV/div 500mV/div Load Capacitance (pF) 2ms/div 10ms/div G = +1 V/V, RL = 100 k, CL = 100 pF G = +1 V/V, RL = 100 k, CL = 100 pF Figure 15. Small-Signal Step Response Figure 16. Large-Signal Step Response 1k 100 iN eN 100 10 10 1 10 100 1k 10k 1 100k Total Harmonic Distortion + Noise (%) 1k 1.000 Current Noise (fAOHz) 10k Voltage Noise (nVOHz) 1k Load Capacitance (pF) 0.100 0.010 0.001 10 100 Frequency (Hz) 1k 10k 100k Frequency (Hz) Figure 17. Input Current and Voltage Noise Spectral Density vs Frequency Figure 18. Total Harmonic Distortion + Noise vs Frequency Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 11 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The OPAx348 series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. The OPAx348 series features wide bandwidth with rail-to-rail input and output for increased dynamic range. 7.2 Functional Block Diagram NCH Input Stage V+ +IN Bias Circuitry Folded Cascode and Gain Stage Output Stage OUT IN V PCH Input Stage t Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Operating Voltage The OPAx348 series op amps are fully specified and tested from 2.5 V to 5.5 V. However, supply voltage may range from 2.1 V to 5.5 V. Parameters are tested over the specified supply range which is an unique feature of the OPAx348 series. All temperature specifications apply from -40C to +125C. Most behavior remains virtually unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics section. 12 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 Feature Description (continued) 7.3.2 Common-Mode Voltage Range The input common-mode voltage range of the OPA348 series extends 200 mV beyond the supply rails. This extended range is achieved with a complementary input stage which is a N-channel input differential pair in parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically (V+) - 1.2 V to 300 mV above the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to approximately (V+) - 1.4 V. There is a small transition region, typically (V+) - 1.4 V to (V+) - 1.2 V, in which both pairs are on. This 200-mV transition region, shown in Figure 19, can vary 300 mV with process variation. Thus, the transition region (both stages on) ranges from (V+) - 1.7 V to (V+) - 1.5 V on the low end, up to (V+) - 1.1 V to (V+) - 0.9 V on the high end. Within the 200-mV transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation outside this region. OFFSET VOLTAGE vs FULL COMMON-MODE VOLTAGE RANGE 2 Offset Voltage (mV) 1.5 1 0.5 0 -0.5 -1 V+ V-1.5 -2 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Common-Mode Voltage (V) Figure 19. Behavior of Typical Transition Region at Room Temperature 7.3.3 Rail-To-Rail Input The input common-mode range extends from (V-) - 0.2 V to (V+) + 0.2 V. For normal operation, inputs must be limited to this range. The absolute maximum input voltage is 500 mV beyond the supplies. Inputs greater than the input common-mode range but less than the maximum input voltage, while not valid, do not cause any damage to the op amp. Unlike some other op amps, if input current is limited the inputs may go beyond the power supplies without phase inversion; see Figure 20. VIN G = +1V/V, VS = +5V 5V 1V/div VOUT 0V 10ms/div Figure 20. OPA348: No Phase Inversion with Inputs Greater Than The Power-Supply Voltage Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 13 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) Normally, input currents are 0.5 pA. However, large inputs (greater than 500 mV beyond the supply rails) can cause excessive current to flow in or out of the input pins. Therefore, as well as keeping the input voltage below the maximum rating, it is also important to limit the input current to less than 10 mA. This limiting is easily accomplished with an input voltage resistor, as shown in Figure 21. +5 V IOVERLOAD 10 mA max VOUT OPA348 VIN 5 kW Copyright (c) 2016, Texas Instruments Incorporated Figure 21. Input Current Protection for Voltages Exceeding the Supply Voltage 7.3.4 Rail-To-Rail Output A class AB output stage with common-source transistors is used to achieve rail-to-rail output. This output stage is capable of driving 5-k loads connected to any potential between V+ and ground. For light resistive loads (> 100 k), the output voltage can typically swing to within 18 mV from supply rail. With moderately resistive loads (10 k to 50 k), the output voltage can typically swing to within 100 mV of the supply rails while maintaining high open-loop gain (see Figure 6). 7.3.5 Capacitive Load and Stability The OPA348 in a unity-gain configuration can directly drive up to 250 pF pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads (see Figure 13). In unity-gain configurations, capacitive load drive can be improved by inserting a small (10- to 20-) resistor, RS, in series with the output, as shown in Figure 22. This small resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created, introducing a direct current (dc) error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RS / RL, and is generally negligible. V+ RS VOUT OPA348 VIN 10 W to 20 W RL CL Copyright (c) 2016, Texas Instruments Incorporated Figure 22. Series Resistor in Unity-Gain Buffer Configuration Improves Capacitive Load Drive 14 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 Feature Description (continued) In unity-gain inverter configuration, phase margin can be reduced by the reaction between the capacitance at the op amp input, and the gain setting resistors, thus degrading capacitive load drive. Best performance is achieved by using small valued resistors. For example, when driving a 500-pF load, reducing the resistor values from 100 k to 5 k decreases overshoot from 55% to 13% (see Figure 13). However, when large valued resistors cannot be avoided, a small (4-pF to 6-pF) capacitor, CFB, can be inserted in the feedback, as shown in Figure 23. This configuration significantly reduces overshoot by compensating the effect of capacitance, CIN, which includes the amplifier input capacitance and printed circuit board (PCB) parasitic capacitance. CFB RF RI VIN VOUT OPA348 CIN CL Copyright (c) 2016, Texas Instruments Incorporated Figure 23. Improving Capacitive Load Drive 7.4 Device Functional Modes The OPAx348 has a single functional mode and is operational when the power-supply voltage is greater than 2.1 V (1.05 V). The maximum power supply voltage for the OPAx348 is 5.5 V (2.75 V). Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 15 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPA348 amplifier is a single-supply, CMOS op amp with 1-MHz unity-gain bandwidth and supply current of only 45 A. Its performance is optimized for a lower power (2.1 V to 5.5 V), single-supply application, with its input common-mode voltage linear range extending 200 mV beyond the rails and the output voltage swing within 25 mV of either rail. The OPA348 series features wide bandwidth and unity-gain stability with rail-to-rail input and output for increased dynamic range. Figure 24 shows the input and output waveforms for the OPA348 in unity-gain configuration. Operation is from a single 5-V supply with a 100-k load connected to VS / 2. The input is a 5-VPP sinusoid. Output voltage is approximately 4.98 VPP. Power-supply pins must be bypassed with 0.01-F ceramic capacitors. G = +1 V / V, VS = 5 V Output (Inverted on Scope) 1 V/ div 5V 0V 20 ms / div Figure 24. OPA348 Features Rail-to-Rail Input and Output 16 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 Application Information (continued) 8.1.1 Driving A/D Converters The OPA348 series op amps are optimized for driving medium-speed sampling analog-to-digital converters (ADCs). The OPA348 op amps buffer the ADC input capacitance and resulting charge injection while providing signal gain. Figure 25 shows the OPA348 in a basic noninverting configuration driving the ADS7822. The ADS7822 is a 12-bit, microPOWER sampling converter in the MSOP-8 package. When used with the low-power, miniature packages of the OPA348, the combination is ideal for space-limited, low-power applications. In this configuration, an RC network at the ADC input can be used to provide both an anti-aliasing filter and charge injection current. +5 V 0.1 mF 0.1 mF 1 VREF 8 V+ DCLOCK 500 W +In ADS7822 12-Bit A/D OPA348 2 VIN -In CS/SHDN 3 3300 pF DOUT 7 6 Serial Interface 5 GND 4 VIN = 0 V to 5 V for 0 V to 5 V output. NOTE: A/D Input = 0 to VREF RC network filters high frequency noise. Copyright (c) 2016, Texas Instruments Incorporated Figure 25. OPA348 in Noninverting Configuration Driving ADS7822 Figure 26 illustrates the OPA2348 driving an ADS7822 in a speech-bandpass filtered data acquisition system. This small, low-cost solution provides the necessary amplification and signal conditioning to interface directly with an electret microphone. This circuit operates with VS = 2.7 V to 5 V with less than 250-A typical quiescent current. V+ = +2.7 V to 5 V Passband 300 Hz to 3 kHz R9 510 kW R1 1.5 kW R2 1 MW R4 20 kW C1 1000 pF 1/2 OPA2348 Electret (1) Microphone R3 1 MW R6 100 kW C3 33 pF R7 51 kW R8 150 kW VREF 1 8 V+ 7 1/2 OPA2348 C2 1000 pF +IN ADS7822 6 12-Bit A/D 5 2 -IN DCLOCK DOUT CS/SHDN Serial Interface 3 4 NOTE: (1) Electret microphone powered by R1. R5 20 kW G = 100 GND Copyright (c) 2016, Texas Instruments Incorporated Figure 26. OPA2348 as a Speech-Bandpass Filtered Data Acquisition System Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 17 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com 8.2 Typical Application Figure 27 shows the OPA348 in a typical noninverting application with input signal bandwidth limited by the input low-pass filter. RF RG R1 VIN VOUT OPA348 C1 Copyright (c) 2016, Texas Instruments Incorporated Figure 27. Single-Pole, Low-Pass Filter Equation 1 and Equation 2 show the relationships for the low-pass cutoff frequency and the low frequency gain and the passive elements surrounding the amplifier. 1 f-3 dB = 2pR1C1 (1) RF VOUT = 1+ RG VIN ( ( (1 + sR1 C ( 1 (2) 1 8.2.1 Design Requirements When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the amplifier, as shown in Figure 27. If a steeper attenuation level is required, a two-pole or higher-order filter may be used. 8.2.2 Detailed Design Procedure The design goals for this circuit include these parameters: * A noninverting gain of 10 V/V (20 dB) * Design a single-pole response circuit with -3-dB roll-off at 15.9 kHz and 159 Hz * Modify the design to increase attenuation level to -40-dB/decade (Sallen-Key Filter) Use these design values: * C1 = 0 nF, 10 nF, 1 F * R1 = 1 k * RG = 10 k * RF = 90 k 18 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 Typical Application (continued) Figure 28 shows how the output voltage of OPA348 changes over frequency depending on the value of C1 with a constant R1 of 1 k. Without any filtering of the input signal (C1 = 0), the -3-dB effective bandwidth is a function of the OPA348 unity-gain bandwidth and closed-loop gain, f(-3dB) = UGBW/ACL, where ACL is closed-loop gain and UGBW denotes unity-gain bandwidth. Thus, for a closed-loop gain = 10, f(-3dB) = 1 MHz/10 =100 kHz; refer to Figure 28. To further limit the output bandwidth, an appropriate choice of C1 must be made: for C1 = 10 nF, 1 1 = fC = 2p R1C1 2p 13 1-8 = 15.9 kHz. To further limit the bandwidth, a larger C1 must be used: choosing C1 = 1 F, fC = 1 1 = 2p R1C1 2p 13 1-6 = 159 Hz. See Figure 28. 8.2.3 Application Curve Gain = VOUT/VIN (dB) 40 C1 = 0 20 C1 = 10 nF 0 C1 = 1 m F -20 -40 1 10 100 1k 10 k 100 k 1M Frequency (Hz) Figure 28. OPA348 Single-Pole AC Gain vs Frequency Response If even more attenuation is required, a multiple pole filter is required. The Sallen-Key filter may be used for this task, as shown in Figure 29. For best results, the amplifier must have effective bandwidth that is at least 10 times higher than the filter cutoff frequency. Failure to follow this guideline results in a phase shift of the amplifier, which in turn leads to lower precision of the filter bandwidth. Additionally, in order to minimize the loading effect between multiple RC pairs on overall the filter cutoff frequency, choose R = 10 x R1 and C2 = C1/10; see Figure 29. R2 RG RF R1 OPA348 VOUT C1 VIN C2 Copyright (c) 2016, Texas Instruments Incorporated Figure 29. Two-Pole, Low-Pass Sallen-Key Filter Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 19 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com Typical Application (continued) Equation 3, Equation 4, and Equation 5 show the relationships for low-pass cutoff frequency, filter transfer function, and low frequency gain, and the surrounding passive elements. fC = 1 2p R1C1R2C2 (3) 2 VOUT(s) G(2pfc) = 2 2 VIN(s) s + 2z(2pfc)s + (2pfc) (4) R G + RF G= R G (5) Use these design values: * C1 = 10 nF and C2 = 1 nF * R1 = 1 k and R2= 10 k * RG = 10 k * RF = 90 k Figure 30 shows the Sallen-Key filter second-order response for different RC values: for R and C values above, 1 1 fC = = 3 -8 4 -9 2p R1C1R2C2 2p 1 1 1 1 = 15.9 kHz. To further limit the bandwidth, a larger RC value must be used: increasing C values 100 times, such as C1 = 1 F and C2 = 0.1 F, with unchanged resistors, results in the second-order roll-off at 1 1 fC = = 3 -6 4 -7 2p R1C1R2C2 2p 1 1 1 1 = 159 Hz. Refer to Figure 30. 40 Gain = VOUT/VIN (dB) C1 = 10 nF, C2 = 1 nF R1 = 1 kW, R2 = 10 kW 20 0 C1 = 1 mF, C2 = 0.1 mF R1 = 1 kW, R2 = 10 kW -20 -40 1 10 100 1k 10 k 100 k 1M Frequency (Hz) Figure 30. OPA348 Two-Pole, Low-Pass Sallen-Key AC Gain vs Frequency Response 20 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 9 Power Supply Recommendations The OPAx348 is specified for operation from 2.1 V to 5.5 V (1.05 V to 2.75 V); many specifications apply from -40C to +125C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 5.5 V can permanently damage the device (see the Absolute Maximum Ratings table). Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, see Layout. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: * Connect low equivalent series resistance (ESR), 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications. - Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. * Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. Separate grounding for analog and digital portions of circuitry is one of the simplest and mosteffective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. * In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. * Place the external components as close to the device as possible. As shown in Figure 31, keeping RF and RG close to the inverting input minimizes parasitic capacitance. * Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. * Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. * Clean the PCB following board assembly for best performance. * Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85C for 30 minutes is sufficient for most circumstances. Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 21 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com 10.2 Layout Example Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF N/C N/C GND IN V+ VIN +IN OUTPUT V N/C RG Use low-ESR, ceramic bypass capacitor GND VS GND Use low-ESR, ceramic bypass capacitor VOUT Ground (GND) plane on another layer Figure 31. Operational Amplifier Board Layout for Noninverting Configuration 22 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TITM (Free Software Download) TINATM is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TITM is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoftTM) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 DIP Adapter EVM The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5 and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits. 11.1.1.3 Universal Op Amp EVM The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits for a variety of device package types. The evaluation module board design allows many different circuits to be constructed easily and quickly. Five models are offered, with each model intended for a specific package type. PDIP, SOIC, MSOP, TSSOP and SOT-23 packages are all supported. NOTE These boards are unpopulated, so users must provide their own devices. TI recommends requesting several op amp device samples when ordering the Universal Op Amp EVM. 11.1.1.4 TI Precision Designs TI Precision Designs are analog solutions created by TI's precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. 11.1.1.5 WEBENCH(R) Filter Designer WEBENCH(R) Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web-based tool from the WEBENCH(R) Design Center, WEBENCH(R) Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 23 OPA348, OPA2348, OPA4348 SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 www.ti.com 11.2 Documentation Support 11.2.1 Related Documentation The following documents are relevant to using the OPAx348, and recommended for reference. All are available for download at www.ti.com unless otherwise noted. * Hardware Pace Using Slope Detection (SLAU511). * Mobile Phone Bank Card Reader Application Report (TIDU399). * TPS61040 Inverter Design (SLVA008). * Op Amp Performance Analysis (SBOA054). * Single-Supply Operation of Operational Amplifiers (SBOA059). * Tuning in Amplifiers (SBOA067). 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Related Links Table 1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA348 Click here Click here Click here Click here Click here OPA2348 Click here Click here Click here Click here Click here OPA4348 Click here Click here Click here Click here Click here 11.5 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.6 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.7 Trademarks TINA-TI, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. 24 Submit Documentation Feedback Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 OPA348, OPA2348, OPA4348 www.ti.com SBOS213H - NOVEMBER 2001 - REVISED NOVEMBER 2016 11.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.9 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2001-2016, Texas Instruments Incorporated Product Folder Links: OPA348 OPA2348 OPA4348 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) OPA2348AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 2348A OPA2348AIDCNR ACTIVE SOT-23 DCN 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B48 OPA2348AIDCNRG4 ACTIVE SOT-23 DCN 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B48 OPA2348AIDCNT ACTIVE SOT-23 DCN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B48 OPA2348AIDCNTG4 ACTIVE SOT-23 DCN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 B48 OPA2348AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 2348A OPA2348AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OUTQ OPA2348AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OUTQ OPA2348AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 2348A OPA2348AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 2348A OPA348AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 348A OPA348AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 A48 OPA348AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 A48 OPA348AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 A48 OPA348AIDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 A48 OPA348AIDCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 S48 OPA348AIDCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 S48 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) OPA348AIDCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 S48 OPA348AIDCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 S48 OPA348AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 348A OPA4348AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4348A OPA4348AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4348A OPA4348AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4348A OPA4348AIPWR ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 4348A OPA4348AIPWRG4 ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 4348A OPA4348AIPWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 4348A OPA4348AIPWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA 4348A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Aug-2018 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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OTHER QUALIFIED VERSIONS OF OPA2348, OPA348, OPA4348 : * Automotive: OPA2348-Q1, OPA348-Q1, OPA4348-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ OPA2348AIDCNR SOT-23 3000 179.0 DCN 8 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 3.2 3.2 1.4 4.0 W Pin1 (mm) Quadrant 8.0 Q3 OPA2348AIDCNT SOT-23 DCN 8 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA2348AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2348AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA348AIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA348AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 OPA348AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 OPA348AIDCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA348AIDCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 OPA348AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4348AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4348AIPWR TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4348AIPWT TSSOP PW 14 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA2348AIDCNR SOT-23 DCN 8 3000 203.0 203.0 35.0 OPA2348AIDCNT SOT-23 DCN 8 250 203.0 203.0 35.0 OPA2348AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 OPA2348AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA348AIDBVR SOT-23 DBV 5 3000 195.0 200.0 45.0 OPA348AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 OPA348AIDBVT SOT-23 DBV 5 250 445.0 220.0 345.0 OPA348AIDCKR SC70 DCK 5 3000 203.0 203.0 35.0 OPA348AIDCKT SC70 DCK 5 250 203.0 203.0 35.0 OPA348AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA4348AIDR SOIC D 14 2500 367.0 367.0 38.0 OPA4348AIPWR TSSOP PW 14 2500 367.0 367.0 35.0 OPA4348AIPWT TSSOP PW 14 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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