112 54F/74F 112 Dual JK Negative Edge-Triggered Flip-Flop Description The 'F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on Sp or Cy prevents clocking and forces Q or G HIGH, respectively. Simultaneous LOW signals on Sp and Cp force both Q and Q HIGH. Asynchronous Inputs: LOW input to Sp sets Q to HIGH level LOW input to Cp sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on Cp and S, makes both Q and Q HIGH Ordering Code: See Section 5 Logic Symbol 2 J ae al olcP oCP K Cp ap kK Co QP ? 1 Input Loading/Fan-Out: See Section 3 for U.L. definitions Connection Diagrams eG] = 16] Vcc ql re Lr pal ce EE] ite a | fides: so BE t [13] CP. a Ieee Hl : a. | [ KPa Lis: oO To of Yas Gno [6 L__ Ja: Pin Assignment for DIP and SOIC Q@ @ NC BH uv S76 & & am] Blk: GNO [id] [z] cr: we [17] Lil Nc a8 88.8 4} 5) fe) G7) (te) Joo Ke NC CP: Coz Pin Assignment for LCC and PCC S4FI74F(U.L.) Pin Names Description HIGHILOW Ji, Ja, Ky, Ke Data Inputs 0.5/0.375 CP, CP, Clock Pulse Inputs (Active Falling Edge) 0.5/1.5 Co; Cpe Direct Clear Inputs (Active LOW) 0.5/1.875 Sp1. Sp2 Direct Set Inputs (Active LOW) 0.5/1.875 Q,, Qz,Q,,G, | Outputs 25/12.5112 Truth Table Inputs Output @t, @t, +1 J K Q L L Q, L H L H=HIGH Voltage Level H L H L= LOW Voltage Level H H om t, = Bit Time before Clock Pulse tn41= Bit Time after Clock Pulse Logic Diagram (one half shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics over Operating Temperature Range (unless otherwise specified) 54F/74F Symbol Parameter Min Typ Max Units Conditions loc Power Supply Current 12 19 mA Voc = Max, Vcp=0 4-35112 AC Characteristics: See Section 3 for waveforms and load configurations 54F/74F 54F 74F Ta = +25C Ta: Voc = Ta Voc = Fi Symbol Parameter Voc = +5.0V Mil Com Units Ne. C, = 50 pF C, = 50 pF C, = 50 pF . Min Typ Max | Min Max Min Max fmax Maximum Clock Frequency 110 130 100 MHz 3-4 tet Propagation Delay 2.0 5.0 65 2.0 7.5 ns 3-1 try CP, to Q, or Q, 20 50 65 2.0 7.5 3-8 tery Propagation Delay 20 45 6.5 2.0 7.5 ns 3-1 try. Con Spr to Q,, Q, 2.0 45 65 20 7.5 3-9 AC Operating Requirements: See Section 3 for waveforms 54F/74F 5S4F 74F Ta =+ 25C Ta, Voc = Ta, Voc = . Fig. Symbol Parameter Voc = +5.0V Mil Com Units No. Min Typ Max | Min Max Min Max t,(H) Setup Time, HIGH or LOW 4.0 5.0 t,(L) J, or K, to CP, 3.0 3.5 ns 3-6 t,(H) Hold Time, HIGH or LOW 0 0 ty(L) J, or K, to CP, 0 0 tw(H) CP, Pulse Width 4.5 5.0 ns 38 tL) HIGH or LOW 4.5 5.0 Con or Son - ttl) Pulse Width, LOW 45 9.0 ns 39 Cp, OF Sp, to CP, ; trec Recovery Time 4.0 5.0 ns 3-11 4-36