Low Cost, Low Power,
True RMS-to-DC Converter
Data Sheet
AD8436
Rev. A
Info
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FEATURES
Delivers true rms or average rectified value of an ac waveform
Fast settling at all input levels
Accuracy: ±10 μV ± 0.5% of reading
Wide dynamic input range
100 μV rms to 3 V rms (8.5 V p-p) full-scale input range
Larger inputs with external scaling
Wide bandwidth:
1 MHz for −3 dB (300 mV)
65 kHz for additional 1% error
Zero converter dc output offset
No residual switching products
Specified at 300 mV rms input
Accurate conversion with crest factors up to 10
Low power: 300 µA typical at ±2.4 V
High-Z FET separately powered input buffer
RIN ≥ 1012 Ω, CIN
≤
2 pF
Precision dc output buffer
Wide power supply voltage range
Dual: ±2.4 V to ±18 V; single: 4.8 V to 36 V
4 mm × 4 mm LFCSP and 8 mm × 6 mm QSOP packages
ESD protected
FUNCTIONAL BLOCK DIAGRAM
VEE
CAVG
VCC
IGND
OUT
IBUFGN
RMS
IBUFOUT
IBUFIN+
SUM
8kΩ 100kΩ
16kΩ
100kΩ
OGND
10kΩ 10kΩ
FET OP AMP
10pF
IBUFIN–
OBUFOUT
OBUFIN+
OBUFIN– 16kΩ DC BUF FER
AD8436
–
+
RMS CO RE
–
+
CCF
10033-001
Figure 1.
GENERAL DESCRIPTION
The AD8436 is a new generation, translinear precision, low
power, true rms-to-dc converter loaded with options. It
computes a precise dc equivalent of the rms value of ac wave-
forms, including complex patterns such as those generated by
switch mode power supplies and triacs. Its accuracy spans a
wide range of input levels (see Figure 2) and temperatures.
The ensured accuracy of ≤±0.5% and ≤10 µV output offset
result from the latest Analog Devices, Inc., technology. The
crest factor error is <0.5% for CF values between 1 and 10.
The AD8436 delivers true rms results at less cost than
misleading peak, averaging, or digital solutions. There is no
programming expense or processor overhead to consider, and
the 4 mm × 4 mm package easily fits into tight applications.
On-board buffer amplifiers enable the widest range of options
for any rms-to-dc converter available, regardless of cost. For
minimal applications, only a single external averaging capacitor
is required. The built-in high impedance FET buffer provides
an interface for external attenuators, frequency compensation,
or driving low impedance loads. A matched pair of internal
resistors enables an easily configurable gain-of-two or more,
extending the usable input range even lower. The low power,
precision input buffer makes the AD8436 attractive for use in
portable multi-meters and other battery-powered applications.
The precision dc output buffer minimizes errors when driving
low impedance loads with extremely low offset voltages, thanks
to internal bias current cancellation.
Unlike digital solutions, the AD8436 has no switching circuitry
limiting performance at high or low amplitudes (see Figure 2). A
usable response of <100 µV and >3 V extends the dynamic range
with no external scaling, accommodating demanding low level
signal conditions and allowing ample overrange without clipping
.
1mV 10mV 1V100mV
AD8436
GREATER INPUT DYNAMI C RANGE
100µV 3V
ΔΣ SOLUTION
10033-002
Figure 2. Usable Dynamic Range of the AD8436 vs.
∆Σ
The AD8436 operates from single or dual supplies of ±2.4 V
(4.8 V) to ±18 V (36 V). A and J grades are available in a
compact 4 mm × 4 mm, 20-lead chip-scale package; A grade is
available in a 20-lead
QSOP package.
The operating temperature
ranges are −40°C to 125°C for A grade and 0°C to 70°C for
J grade.
AD8436 Data Sheet
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits ........................................................................................9
Theory of Operation ...................................................................... 10
Overview ..................................................................................... 10
Applications Information .............................................................. 12
Using the AD8436 ....................................................................... 12
AD8436 Evaluation Board ......................................................... 16
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/12—Rev. 0 to Rev. A
Added 20-Lead QSOP ........................................................ Universal
Changes to Features Section and General Description Section . 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 and added Figure 4 and added Table 4;
Renumbered Sequentially ................................................................ 5
Changes to Equation 1 and change to Column One Heading
in Table 5 .......................................................................................... 10
Changes to Averaging Capacitor Considerations—RMS
Accuracy and to Post Conversion Ripple Reduction Filter
and changes to Figure 27 Caption ................................................ 12
Changes to Figure 30 to Figure 32 ................................................ 13
Changes to Using the FET Input Buffer Section and Using the
Output Buffer Section .................................................................... 14
Changes to Figure 38 and Figure 41 and added Converting
to Rectified Average Value Section .............................................. 15
Changes to Figure 41 ...................................................................... 16
Changes to Figure 42 to Figure 46 ................................................ 17
Changes to Figure 47 and Figure 48 ............................................ 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/11—Revision 0: Initial Version
Data Sheet AD8436
Rev. A | Page 3 of 20
SPECIFICATIONS
eIN = 300 mV (rms), frequency = 1 kHz sinusoidal, ac-coupled, ±VS = ±5 V, TA = 25°C, CAVG = 10 µF, unless otherwise specified.
Table 1.
Parameter Conditions Min Typ Max Units
RMS CORE
Conversion Error Default conditions ±10 − 0.5 ±0 ± 0 ±10 + 0.5 μV/% rdg
Vs. Temperature −40°C < T < 125 C 0.006 %/°C
Vs. Rail Voltage ±2.4 V to ±18 V ±0.013 ±%/V
Input V
OS
DC-coupled −500 0 +500 μV
Output V
OS
AC-coupled input 0 V
Vs. Temperature
−40 C < T < 125°C
0.3
μV/°C
DC Reversal Error DC-coupled, V
IN
= ±300 mV −1.5 0 +1.5 %
Nonlinearity e
IN
= 2 mV to 500 mV ac −0.2 +0.2 %
Crest Factor Error (Additional)
1 < CF < 10 CCF = 0.1 μF −0.5 +0.5 %
Peak Input Voltage −V
S
− 0.7 +V
S
+ 0.7 V
Input Resistance 7.92 8 8.08 kΩ
Response V
IN
= 300 mV rms
1% Error (Additional) 65 kHz
3 dB Bandwidth 1 MHz
Settling Time
0.1% Rising/falling 148/341 ms
0.01% Rising/falling 158/350 ms
Output Resistance 15.68 16 16.32 kΩ
Supply Current No input 325 400 μA
INPUT BUFFER
Voltage Swing G = 1
Input AC- or dc-coupled −V
S
+V
S
V
Output AC-coupled to Pin RMS −V
S
+ 0.2 +V
S
− 0.2 mV
Offset Voltage −1 0 +1 mV
Input Bias Current 50 pA
Input Resistance 10
12
Ω
Response (Frequency)
0.1 dB 950 kHz
3 dB Bandwidth 2.1 MHz
Supply Current 100 160 200 μA
Optional Gain Resistor −9.9 +10 +10.1 kΩ
Gain Error G = ×1 0.05 %
OUTPUT BUFFER
R
L
=
∞
Offset Voltage Connected to Pin OUT −200 0 +200 μV
Input Current (I
B
) 2 51 nA
Output Swing (Voltage) −V
S
+ 50e-6 +V
S
− 1 V
Drive Current −0.5 (sink) +15 (source) mA
Gain Error 0.003 0.01 %
Supply Current 40 70 μA
SUPPLY VOLTAGE
Dual
±2.4
±18
V
Single 4.8 36 V
1IB max measured at power up. Settles to typical value in <15 seconds.
AD8436 Data Sheet
Rev. A | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage
Supply ±18 V
Input ±V
S
Differential Input +V
S
and −V
S
Power Dissipation
CP-20-10 LFCSP Without Thermal Pad 1.2 W
CP-20-10 LFCSP With Thermal Pad 2.1 W
RQ Package
1.1 W
Output Short-Circuit Duration Indefinite
Temperature
Operating Range −40°C to +125°C
Storage Range −65°C to +125°C
Lead Soldering (60 sec) 300°C
θ
JA
CP-20-10 LFCSP Without Thermal Pad 86°C/W
CP-20-10 LFCSP With Thermal Pad 48°C/W
RQ-20 Package 95°C/W
ESD Rating 2 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
ESD CAUTION
Data Sheet AD8436
Rev. A | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1620
15
106
AD8436
TOP VI EW
(No t t o Scal e)
11
PIN 1
INDICATOR
VEE
CAVG VCC
OBUFOUT
IGND
OBUFIN+
OBUFIN–
OBUFV+
OUTDNC
NOTES
1. DNC = DO NO T CO NNE CT. DO NO T CONNE CT T O T HIS P IN.
2. THE EX P OSE D P AD S HOUL D NOT BE CONNECT E D.
IBUFGN
DNC
IBUFOUT
IBUFIN+
SUM IBUFV+
RMS
CCF
OGND
IBUFIN–
1
5
10033-003
Figure 3. Pin Configuration, Top View, CP-20-10
Table 3. Pin Function Descriptions, CP-20-10
Pin No. Mnemonic Description
1 DNC Do Not Connect. Used for factory test.
2 RMS AC Input to the RMS Core.
3 IBUFOUT FET Input Buffer Output Pin.
4 IBUFIN– FET Input Buffer Inverting Input Pin.
5 IBUFIN+ FET Input Buffer Noninverting Input Pin.
6
IBUFGN
Optional 10 kΩ Precision Gain Resistor.
7 DNC Do Not Connect. Used for factory test.
8 OGND Internal 16 kΩ I-to-V Resistor.
9 OUT RMS Core Voltage or Current Output.
10 VEE Negative Supply Rail.
11 IGND Half Supply Node.
12 OBUFIN+ Output Buffer Noninverting Input Pin.
13 OBUFIN− Output Buffer Inverting Input Pin.
14 OBUFOUT Output Buffer Output Pin.
15 OBUFV+ Power Pin for the Output Buffer.
16 IBUFV+ Power Pin for the Input Buffer.
17 VCC Positive Supply Rail for the RMS Core.
18
CCF
Connection for Crest Factor Capacitor.
19 CAVG Connection for Averaging Capacitor.
20 SUM Summing Amplifier Input Pin.
EP DNC Exposed Pad Connection to Ground
Pad Optional.
NOTES
1. DNC = DO NO T CO NNE CT.
DO NOT CONNECT TO THIS PIN.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DNC
RMS
IBUFOUT
IBUFGN
IBUFIN+
IBUFIN–
SUM
CCF
VCC
IBUFV+
OBUFIN–
OBUFOUT
OBUFV+
OUT
OGND
DNC
VEE
IGND
OBUFIN+
CAVG
TOP VI EW
(No t t o Scal e)
AD8436
10033-104
Figure 4. Pin Configuration, RQ-20
Table 4. Pin Function Descriptions, RQ-20
Pin No. Mnemonic Description
1 SUM Summing Amplifier Input Pin.
2 DNC Do Not Connect. Used for factory test.
3 RMS AC Input to the RMS Core.
4 IBUFOUT FET Input Buffer Output Pin.
5 IBUFIN– FET Input Buffer Inverting Input Pin.
6 IBUFIN+ FET Input Buffer Noninverting Input Pin.
7 IBUFGN Optional 10 kΩ Precision Gain Resistor.
8 DNC Do Not Connect. Used for factory test.
9 OGND Internal 16 kΩ I-to-V Resistor.
10 OUT RMS Core Voltage or Current Output.
11 VEE Negative Supply Rail.
12 IGND Half Supply Node.
13 OBUFIN+ Output Buffer Noninverting Input Pin.
14 OBUFIN− Output Buffer Inverting Input Pin.
15 OBUFOUT Output Buffer Output Pin.
16
OBUFV+
Power Pin for the Output Buffer.
17 IBUFV+ Power Pin for the Input Buffer.
18 VCC Positive Supply Rail for the RMS Core.
19 CCF Connection for Crest Factor Capacitor.
20 CAVG Connection for Averaging Capacitor.
AD8436 Data Sheet
Rev. A | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, ±VS = ±5 V, CAVG = 10 µF, 1 kHz sine wave, unless otherwise indicated.
INPUT LEVEL (V rms)
1V
100 1k FREQUE NCY ( Hz ) 100k10k
10mV
5V
100µV
100mV
1mV
5M1M50
50µV
−3dB BW
10033-004
Figure 5. RMS Core Frequency Response (See Figure 21)
−3dB BW
V
S
= ±2. 4V
10033-005
1V
100 1k FREQUE NCY ( Hz ) 100k10k
10mV
5V
100µV
100mV
1mV
5M1M50
50µV
INPUT LEVEL (V rms)
Figure 6. RMS Core Frequency Response with VS = ±2.4 V (See Figure 21)
−3dB BW
V
S
= ±15V
10033-006
INPUT LEVEL (V rms)
1V
100 1k FREQUE NCY ( Hz ) 100k10k
10mV
5V
100µV
100mV
1mV
5M1M50
50µV
Figure 7. RMS Core Frequency Response with VS = ±15 V (See Figure 21)
−3dB BW
VS = 4.8V
10033-007
INPUT LEVEL (V rms)
1V
100 1k FREQUE NCY ( Hz ) 100k10k
10mV
5V
100µV
100mV
1mV
5M1M50
50µV
Figure 8. RMS Core Frequency Response with VS = +4.8 V (See Figure 22)
GAIN (d B)
12
100 1k FRE QUENCY ( Hz )
100k10k
0
15
3
9
6
5M1M
–15
–12
–3
–9
–6
e
IN = 3.5mV rms
10033-008
Figure 9. Input Buffer, Small Signal Bandwidth at 0 dB and 6 dB Gain
GAIN (d B)
12
100 1k FRE QUENCY ( Hz )
100k10k
0
15
3
9
6
5M1M
–15
–12
–3
–9
–6
e
IN = 300mV rms
10033-009
Figure 10. Input Buffer, Large Signal Bandwidth at 0 dB and 6 dB Gain
Data Sheet AD8436
Rev. A | Page 7 of 20
GAIN (d B)
12
100 1k FREQUENCY ( Hz )
100k10k
0
15
3
9
6
5M1M
–15
–12
–3
–9
–6
e
IN = 3.5mV rms
10033-010
Figure 11. Output Buffer, Small Signal Bandwidth
20
SUPPLY VOLT AGE (±V)
842 6 141210
0.3
0.5
0.4
0
–0.1
CAVG =10µF
8 SAMPLES
NORM ALIZED E RROR (%)
0
–0.3
–0.4
–0.2
0.2
0.1
–0.5 1816
10033-011
Figure 12. Additional Error vs. Supply Voltage
INPUT LEVEL (V rms)
4 6
SUPPLY VOLT AGE (±V)
108
0.8
2.0
1.2
0.4
14122
016 18
0
1.6
10033-012
Figure 13. Core Input Voltage for 1% Error vs. Supply Voltage
ADDITIONAL E RROR (% OF RE ADING)
CREST FACTO R RATI O
20
5
64
0
810
10
−5
−10
CAVG = 10µF
CAVG = 10µF
CCF = 0.1µ F
P
W
= 100µs
10033-013
Figure 14. Crest Factor Error vs. Crest Factor for CAVG and CAVG and CCF
Capacitor Combinations
ADDITIONAL E RROR (% OF RE ADING)
TEMPERATURE (°C)
250
0.50
0.25
0.75
75
50
0
100 125
1.00
–25–50
−0.50
−0.25
−0.75
−1.00
10033-014
Figure 15. Additional Conversion Error vs. Temperature
SUPP LY CURRENT (mA)
2.5
0.5 1.0
INP UT VO LT AGE ( V rms) 2.01.5
1.5
0.5
2.0
1.0
0
0
VS = ±2. 4V
VS = ±15V
VS = ±5V
10033-015
Figure 16. RMS Core Supply Current vs. Input for VS = ±2.4 V, ±5 V, and ±15 V
AD8436 Data Sheet
Rev. A | Page 8 of 20
BIAS CURRE NT (p A)
TEMPERATURE (°C)
250
70
60
80
7550
0
100 125
90
−25−50
40
50
30
20
10
−10
10033-016
Figure 17. FET Input Buffer Bias Current vs. Temperature
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
250
500
250
750
7550
0
100 125
1000
−500
−250
−750
−1000
−25−50
10033-018
Figure 18. Input Offset Voltage of FET Buffer vs. Temperature
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
250
100
250
150
50
7550
0
100 125
200
−100
−250
−150
−50
−200
−25−50
10033-019
Figure 19. Output Buffer VOS vs. Temperature
1kHz 300mV rms BURS T INP UT
TIME ( 50ms/DI V )
1kHz 1mV rms BURS T INP UT
300mV DC O UT
1mV DC O UT
CAVG = 10µF
0V
0V
0V
0V
10033-020
Figure 20. Transition Times with 1 kHz Burst at Two Input Levels
(See Theory of Operation Section)
Data Sheet AD8436
Rev. A | Page 9 of 20
TEST CIRCUITS
PRECISI ON DMM
SI GNAL S OURCE
OUT
RMS
+5V
10µF
AC-IN MONITOR
PRECISI ON DMM
4.7µF
VEE
CAV VCC
100kΩ
100kΩ
16kΩ
OGND –5V
IGND
RMS CORE
10033-021
Figure 21. Core Response Test Circuit Using Dual Supplies
PRECISI ON DMM
SI GNAL S OURCE
OUT
RMS
4.80V
10µF
AC-IN MONITOR
PRECISI ON DMM
4.7µF
4.7µF
VEE
CAV VCC
100kΩ
100kΩ
16kΩ
OGND
IGND
RMS CORE
10033-022
Figure 22. Core Response Test Circuit Using a Single Supply
FUNCTION G E NE RATO R
PRECISI ON DMM
OUT
RMS
+5V
10µF
AC-IN MONITOR
PRECISI ON DMM
4.7µF
VEE
CAV VCC
100kΩ
100kΩ
16kΩ
OGND
–5V
IGND
RMS CORE
10033-023
Figure 23. Crest Factor Test Circuit
AD8436 Data Sheet
Rev. A | Page 10 of 20
THEORY OF OPERATION
OVERVIEW
The AD8436 is an implicit function rms-to-dc converter that
renders a dc voltage dependent on the rms (heating value) of an
ac voltage. In addition to the basic converter, this highly integrated
functional circuit block includes two fully independent, optional
amplifiers, a standalone FET input buffer amplifier and a precision
dc output buffer amplifier (see Figure 1). The rms core includes
a precision current responding full-wave rectifier and a log-antilog
transistor array for current squaring and square rooting to imple-
ment the classic expression for rms (see Equation 1). For basic
applications, the converter requires only an external capacitor, for
averaging (see Figure 31). The optional on-board amplifiers
offer utility and flexibility in a variety of applications without
incurring additional circuit board footprint. For lowest power,
the amplifier supply pins are left unconnected.
Why RMS?
The rms value of an ac voltage waveform is equal to the dc voltage
providing the same heating power to a load. A common measure-
ment technique for ac waveforms is to rectify the signal in a
straightforward way using a diode array of some sort, resulting in
the average value. The average value of various waveforms (sine,
square, and triangular, for example) varies widely; true rms is
the only metric that achieves equivalency for all ac waveforms.
See Table 5 for non-rms-responding circuit errors.
The acronym “rms” means root-mean-square and reads as follows:
“the square root of the average of the sum of the squares” of the
peak values of any waveform. RMS is shown in the following
equation:
1
T
e
rms
= V(t)
2
dt
0
T
∫
(1)
For additional information, select Section I of the 2nd edition of
the Analog Devices RMS-to-DC Applications Guide.
RMS Core
The core consists of a voltage-to-current converter (precision
resistor), absolute value, and translinear sections. The translinear
section exploits the properties of the bipolar transistor junctions
for squaring and root extraction (see Figure 24). The external
capacitor (CAVG) provides for averaging the product. Figure 20
shows that there is no effect of signal input on the transition times,
as seen in the dc output. Although the rms core responds to input
voltages, the conversion process is current sensitive. If the rms
input is ac-coupled, as recommended, there is no output offset
voltage, as reflected in Table 1. If the rms input is dc-coupled, the
input offset voltage is reflected in the output and can be calibrated
as with any fixed error.
V–
AC IN V+
OUT
+
–
V+
5kΩ CAVG
ABSOLUTE
VALUE
CIRCUIT
V-TO-I
16kΩ
10033-024
Figure 24. RMS Core Block Diagram
Table 5. General AC Parameters
Waveform Type (1 V Peak) Crest Factor RMS Value
Reading of an Average Value Circuit
Calibrated to an RMS Sine Wave Error (%)
Sine 1.414 0.707 0.707 0
Square 1.00 1.00 1.11 11.0
Triangle 1.73 0.577 0.555 −3.8
Noise 3 0.333 0.295
Rectangular 2 0.5 0.278 −11.4
Pulse 10 0.1 0.011 −44
SCR −89
DC = 50% 2 0.495 0.354 −28
DC = 25% 4.7 0.212 0.150 −30
Data Sheet AD8436
Rev. A | Page 11 of 20
The 16 kΩ resistor in the output converts the output current to
a dc voltage that can be connected to the output buffer or to the
circuit that follows. The output appears as a voltage source in
series with 16 kΩ. If a current output is desired, the resistor
connection to ground is left open and the output current is
applied to a subsequent circuit, such as the summing node of
a current summing amplifier. Thus, the core has both current
and voltage outputs, depending on the configuration. For a
voltage output with 0 Ω source impedance, use the output
buffer. The offset voltage of the buffer is 25 μV or 50 μ V,
depending on the grade.
FET Input Buffer
Referring to Figure 1, the input resistance of the AD8436 is 8 kΩ,
and a voltage source input is preferred. The optional input buffer
is a wideband JFET input amplifier that minimally loads non-0 Ω
sources, such as a tapped resistor attenuator or voltage sensor.
Although the input buffer consumes only 150 μA, the supply is
pinned out and left unconnected to reduce power where needed.
Optional matched 10 kΩ input and feedback resistors are provided
on chip. Consult the Applications Information section to learn
how these resistors can be used. The 3 dB bandwidth of the input
buffer is 2.7 MHz at 10 mV rms input and approximately 1.5 MHz
at 1 V rms. The amplifier gain and bandwidth are sufficient for
applications requiring modest gain or response enhancement to
a few hundred kilohertz (kHz), if desired. Configurations of the
input buffer are discussed in the Applications Information
section.
Precision Output Buffer
The precision output buffer is a bipolar input amplifier, laser
trimmed to cancel input offset voltage errors. As with the input
buffer, the supply current is very low (<50 μA, typically), and the
power can be disconnected for power savings if the buffer is not
needed. Be sure that the noninverting input is also disconnected
from the core output (OUT) if the buffer supply pin is discon-
nected. Although the input current of the buffer is very low,
a laser-trimmed 16 kΩ resistor, connected in series with the
inverting input, offsets any self-bias offset voltage.
The output buffer can be configured as a single or two-pole low-
pass filter using circuits shown in the Applications Information
section. Residual output ripple is reduced, without affecting the
converted dc output. As the response approaches the low
frequency end of the bandwidth, the ripple rises, dependent on
the value of the averaging capacitor. Figure 27 shows the effects of
four combinations of averaging and filter capacitors. Although
the filter capacitor reduces the ripple for any given frequency, the
dc error is unaffected. Of course, a larger value averaging
capacitor can be selected, at a larger cost. The advantage of using
a low-pass filter is that a small value of filter capacitor, in
conjunction with the 16 kΩ output resistor, reduces ripple and
permits a smaller averaging capacitor, effecting a cost savings.
The recommended capacitor values for operation to 40 Hz are
10 µF for averaging and 3.3 µF for filter.
Dynamic Range
The AD8436 is a translinear rms-to-dc converter with exceptional
dynamic range. Although accuracy varies slightly more at the
extreme input values, the device still converts with no spurious
noise or dropout. Figure 25 is a plot of the rms/dc transfer function
near zero voltage. Unlike processor or other solutions, residual
errors at very low input levels can be disregarded for most
applications.
OUTPUT VOLTAGE (mV DC)
INP UT VO LT AGE ( mV DC)
30
20
10
0
0302010–10–20–30
ΔΣ OR OTHER DIGITAL
SO LUTIO NS CANNOT
WORK AT ZERO
VOLTS
AD8436
SOLUTION
10033-025
Figure 25. DC Transfer Function near Zero
AD8436 Data Sheet
Rev. A | Page 12 of 20
APPLICATIONS INFORMATION
USING THE AD8436
This section describes the power supply and feature options,
as well as the function and selection of averaging and filter
capacitor values. Averaging and filtering options are shown
graphically and apply to all circuit configurations.
Averaging Capacitor Considerations—RMS Accuracy
Typical AD8436 applications require only a single external
capacitor (CAVG) connected to the CAVG pin (see Figure 31).
The function of the averaging capacitor is to compute the mean
(that is, average value) of the sum of the squares. Averaging
(that is, integration) follows the rms core, where the input
current is squared. The mean value is the average value of the
squared input voltage over several input waveform periods.
The rms error is directly affected by the number of periods
averaged, as is the resultant peak-to-peak ripple.
The result of the conversion process is a dc component and a
ripple component whose frequency is twice that of the input. The
rms conversion accuracy depends on the value of C AVG, so the
value selected need only be large enough to average enough periods
at the lowest frequency of interest to yield the required rms
accuracy. Figure 28 is a plot of rms error vs. frequency for various
averaging capacitor values. For Figure 28, the additional error
was 0.001% at 40 Hz using a 10 µF metalized polyester capacitor.
Larger values yield diminished returns because the settling time
increases with negligible improvement in rms accuracy.
To use Figure 28, determine the minimum operating frequency
and accuracy of the application and then find the suggested
capacitor value on the chart. For example, for –0.5% rms at 100 Hz,
the capacitor value is 1 µF.
Post Conversion Ripple Reduction Filter
Input rectification included in the AD8436 introduces a residual
ripple component that is dependent on the value of CAVG and
twice the input signal frequency for symmetrical input wave-
forms. For sampling applications such as a high resolution ADC,
the ripple component may cause one or more LSBs to cycle, and
low value display numerals to flash.
Ripple is reduced by increasing the value of the averaging capacitor,
or by postconversion filtering. Ripple reduction following
conversion is far more efficient because the ripple average value
has been converted to its rms value. Capacitor values for post-
conversion filtering are significantly less than the equivalent
averaging capacitor value for the same level of ripple reduction.
This approach requires only a single capacitor connected to the
OUT pin (see Figure 26). The capacitor value correlates to the
simple frequency relation of ½ π R-C, where R is fixed at 16 kΩ.
OUT
16kΩ
OGND
CORE
CLPF
DC OUTPUT
9
8
10033-026
Figure 26. Simple One-Pole Post Conversion Filter
As seen in Figure 27, CAVG alone determines the rms error,
and CLPF serves purely to reduce ripple. Figure 27 shows a
constant rms error for CLPF values of 0.33 µF and 3.3 µF; only
the ripple is affected.
RMS E RROR (%)
FRE QUENCY ( Hz )
1
0
100 1k
–1
–2
10
–3
–4
–5
–6
–7
–8
–9
–10
CAVG = 10µF
CLP F = 0. 33µF OR 3.3µF
CAVG = 1µF
CLP F = 0. 33µF OR 3.3µF
10033-027
Figure 27. RMS Error vs. Frequency for Two Values of CAVG and CLPF
(Note that only CAVG value affects rms error; CLPF has no effect.)
CONVERSION ERROR (%)
1k
FRE QUENCY ( Hz )
100
–0.5
–1.5
0
–1.0
10
–2.0
47µF
10µF
CAVG = 0.22µ F
1µF
2.2µF
0.47µF
4.7µF
22µF
10033-028
Figure 28. Conversion Error vs. Frequency for Various Values of CAVG
Data Sheet AD8436
Rev. A | Page 13 of 20
For simplicity, Figure 29 shows ripple vs. frequency for four
combinations of CAVG and CLPF
RIPPLE ERROR (V p-p)
INPUT FRE QUENCY ( Hz )
1
0.0001 100 1k10
0.001
0.01
0.1
CAVG = 1µ F, CLPF = 0.33µF
CAVG = 10µ F, CLPF = 3.3µF
CAVG = 10µ F, CLPF = 0.33µF
CAVG = 1µ F, CLPF = 3.3µF
AC INPUT = 300mV rms
10033-029
Figure 29. Residual Ripple Voltage for Various Filter Configurations
Figure 30 shows the effects of averaging and post-rms filter
capacitors on transition and settling times using a 10-cycle,
50 Hz, 1 second period burst signal input to demonstrate time-
domain behavior. In this instance, the averaging capacitor value
was 10 µF, yielding a ripple value of 6 mV rms. A postconversion
capacitor (CLPF) of 0.68 μF reduced the ripple to 1 mV rms. An
averaging capacitor value of 82 μF reduced the ripple to 1 mV
but extended the transition time (and cost) significantly.
10033-130
INPUT
50Hz 10 CYCLE BURST
400mv/DIV
CAVG = 10µF FOR BOTH PLOTS,
BUT RED PLOT HAS NO LOW-PASS FILTER,
GRE E N P LOT HAS CLPF = 0.68µF
10mV/DIV
TIME ( 100ms/DI V )
CAVG = 82µF
Figure 30. Effects of Various Filter Options on Transition Times
Capacitor Construction
Although tolerant of most capacitor styles, rms conversion
accuracy can be affected by the type of capacitor that is selected.
Capacitors with low dc leakage yield best all around performance,
and many sources are available. Metalized polyester or similar
film styles are best, as long as the temperature range is appropriate.
For practical applications such as the rms-to-dc function in
DMMs or power monitoring circuits, surface mount tantalums
are the best over-all choice.
Basic Core Connections
Many applications require only a single external capacitor for
averaging. A 10 µF capacitor is more than adequate for acceptable
rms errors at line frequencies and below.
The signal source sees the input 8 kΩ voltage-to-current conversion
resistor at Pin RMS; thus, the ideal source impedance is a
voltage source (0 Ω source impedance). If a non-zero signal source
impedance cannot be avoided, be sure to account for any series
connected voltage drop.
An input coupling capacitor must be used to realize the near-zero
output offset voltage feature of the AD8436. Select a coupling
capacitor value that is appropriate for the lowest expected
operating frequency of interest. As a rule of thumb, the input
coupling capacitor can be the same as or half the value of the
averaging capacitor because the time constants are similar. For
a 10 μF averaging capacitor, a 4.7 μF or 10 μF tantalum capacitor
is a good choice (see Figure 31).
10033-131
2
RMS
9
OUT
AD8436
11
IGND
19
CAVG
10
VEE
–5V
8
OGND
17
VCC
4.7µF
OR 10µ F
+*
+5V
10µF
CAVG
+*
*FOR POLARIZED CAPACITOR STYLES.
Figure 31. Basic Applications Circuit
Using a Capacitor for High Crest Factor Applications
The AD8436 contains a unique feature to reduce large crest
factor errors. Crest factor is often overlooked when considering
the requirements of rms-to-dc converters, but it is very
important when working with signals with spikes or high peaks.
The crest factor is defined as the ratio of peak voltage to rms.
See Table 5 for crest factors for some common waveforms.
10033-132
2RMS 9
OUT
AD8436
11
IGND
19
CAVG
18
CCF
10
VEE
–5V
8
OGND
17
VCC
4.7µF
OR 10µ F
+*
+5V
10µF
CAVG
+*
0.1µF
CCF
*FOR POLARIZED CAPACITOR STYLES.
Figure 32. Connection for Additional Crest Factor Performance
Crest factor performance is mostly applicable for unexpected
waveforms such as switching transients in switchmode power
supplies. In such applications, most of the energy is in these
peaks and can be destructive to the circuitry involved, although
the average ac value can be quite low.
Figure 14 shows the effects of an additional crest factor
capacitor of 0.1 μF and an averaging capacitor of 10 μ F. The
larger capacitor serves to average the energy over long spaces
between pulses, while the CCF capacitor charges and holds the
energy within the relatively narrow pulse.
AD8436 Data Sheet
Rev. A | Page 14 of 20
Using the FET Input Buffer
The on-chip FET input buffer is an uncommitted FET input
op amp used for driving the 8 kΩ I-to-V input resistor of the
rms core. Pin IBUFOUT, Pin IBUFIN−, and Pin IBUFIN+ are
the I/O, Pin IBUFINGN is an optional connection for gain in
the input buffer, and Pin IBUFV+ connects power to the
buffer. Connecting Pin IBUFV+ to the positive rail is the
only power connection required because the negative rail is
internally connected. Because the input stage is a FET and
the input impedance must be very high to prevent loading
of the source, a large value (10 MΩ) resistor is connected from
midsupply at Pin IGND to Pin IBUFIN+ to prevent the input
gate from floating high.
For unity gain, connect the IBUFOUT pin to the IBUFIN− pin.
For a gain of 2×, connect the IBUFGN pin to ground. See Figure 9
and Figure 10 for large and small signal responses at the two
built-in gain options.
The offset voltage of the input buffer is ≤500 μ V, depending on
grade. A capacitor connected between the buffer output pin
(IBUFOUT) and the RMS pin is recommended so that the
input buffer offset voltage does not contribute to the overall
error. Select the capacitor value for least minimum error at the
lowest operating frequency. Figure 33 is a schematic showing
internal components and pin connections.
IBUFOUT
IBUFIN+
IBUFIN–
–
+
IBUFGN
10kΩ
10kΩ
10pF
6
5
4
3
2RMS
10µF
0.47µF
10MΩ
11 IGND
16
IBUFV+
10033-033
Figure 33. Connecting the FET Input Buffer
Capacitor coupling at the input and output of the FET buffer is
recommended to avoid transferring the buffer offset voltage to
the output. Although the FET input impedance is extremely high,
the 10 MΩ centering resistor connected to IGND must be taken
into account when selecting an input capacitor value. This is simply
an impedance calculation using the lowest desired frequency,
and finding a capacitor value based on the least attenuation desired.
Because the 10 kΩ resistors are closely matched and trimmed to
a high tolerance, the input buffer gain can be increased to several
hundred with an external resistor connected to Pin IBUFIN−.
The bandwidth diminishes at the typical rate of a decade per 20 dB
of gain, and the output voltage range is constrained. The small
signal response, as shown in Figure 9, serves as a guide. As an
example, suppose one wanted to detect small input signals at
power line frequencies? An external 10 Ω resistor connected from
IBUFIN− to ground sets the gain to 101 and the 3 dB bandwidth to
~30 kHz, which is more than adequate for amplifying power line
frequencies.
Using the Output Buffer
The AD8436 output buffer is a precision op amp optimized for
high dc accuracy. Figure 34 shows a block diagram of the basic
amplifier and I/O pins. The amplifier is often configured as a unity
gain follower but is easily configured for gain, as a Sallen-Key low-
pass filter (in conjunction with the built-in 16 kΩ I-to-V resistor).
Note that an additional 16 kΩ on-chip precision resistor in series
with the inverting input of the amplifier balances output offset
voltages resulting from the bias current from the noninverting
amplifier. The output buffer is disconnected from Pin OUT for
precision core measurements.
As with the input FET buffer, the amplifier positive supply is
disconnected when not needed. In normal circumstances, the
buffers are connected to the same supply as the core. Figure 35
shows the signal connections to the output buffer. Note that
the input offset voltage contribution by the bias currents are
balanced by equal value series resistors, resulting in near zero
offset voltage.
OBUFOUT
OBUFIN+
OBUFIN– 16kΩ
OUTPUT BUFFER
–
+
10033-034
Figure 34. Output Buffer Block Diagram
OUT
16kΩ
16kΩ
OGND
OBUFOUT
OBUFIN+
OBUFIN– –
+
CORE
IBIAS
9
8
IBIAS
14
13
12
10033-035
Figure 35. Basic Output Buffer Connections
For applications requiring ripple suppression in addition to the
single-pole output filter described previously, the output buffer
is configurable as a two-pole Sallen-Key filter using two external
resistors and two capacitors. At just over 100 kHz, the amplifier
has enough bandwidth to function as an active filter for low
frequencies such as power line ripple. For a modest savings in
cost and complexity, the external 16 kΩ feedback resistor can be
omitted, resulting in slightly higher VOS (80 μV).
Data Sheet AD8436
Rev. A | Page 15 of 20
16kΩ
16kΩ
16kΩ
16kΩ
OGND OBUFOUT
OBUFIN+
OBUFIN–
–
+
CORE C
8
14
13
129
OUT
10033-036
2C
Figure 36. Output Buffer Amplifier Configured as a Two-Pole, Sallen-Key
Low-Pass Filter
Configure the output buffer as shown in Figure 37 to invert the
dc output.
OUT
16kΩ
16kΩ
OGND OBUFOUT
OBUFIN+
OBUFIN–
CORE
32.4kΩ
8
14
12
13
9
–
+
10033-037
Figure 37. Inverting Output Configuration
Current Output Option
If a current output is required, connect the current output,
OUT, to the destination load. To maximize precision, provide a
means for external calibration to replace the internal trimmed
resistor, which is bypassed. This configuration is useful for conve-
nient summing of the AD8436 result with another voltage, or
for polarity inversion.
–
+
8kΩ
15kΩ
16kΩ
19
CAVG
18
CCF
9
OUT
2
RMS
8
OGND
DIRECTION OF
DC OUTPUT
CURRENT 2kΩ
(OPTIONAL)
INV E RTED DC
VOLTAGE
OUTPUT
32.4kΩ
DO NOT CONNECT FOR
CURRENT OUTP UT
CORE
10033-138
Figure 38. Connections for Current Output Showing Voltage Inversion
Single Supply
Connections for single supply operation are shown in Figure 39
and are similar to those for dual power supply when the device is
ac-coupled. The analog inputs are all biased to half the supply
voltage, but the output remains referred to ground because the
output of the AD8436 is a current source. An additional bypass
connection is required at IGND to suppress ambient noise.
IGND 4.7µF
RMS
10µF
0.47µF
VEE
CAV VCC
OGND
2
11
10
19
8
9
17
10MΩ
4
5
3
IBUFOUT
IBUFIN+
IBUFIN–
OUT
AD8436
4.7µF
10033-039
Figure 39. Connections for Single Supply Operation
Recommended Application
Figure 40 shows a circuit for a typical application for frequencies
as low as power line, and above. The recommended averaging,
crest factor and LPF capacitor values are 10 μF, 0.1 μF and
3.3 μF. Refer to the Using the Output Buffer section if additional
low-pass filtering is required.
AC IN
VCC
VEE
DC
OUT
10MΩ VEE
CAVG VCC
OBUFOUT
IGND
OBUFIN+
OBUFIN–
OBUFV+
OUTDNC
IBUFIN–
IBUFOUT
IBUFIN+
SUM IBUFV+
1
4
3
2
5
876 9
12
11
10
16
15
14
13
10µF
0.47µF
OGNDIBUFGN
CCF
10µF
+
19 18 1720
DNC
RMS
3.3µF
0.1µF
AD8436
10033-040
Figure 40. Typical Application Circuit
Converting to Average Rectified Value
To configure the AD8436 for converting ac waveforms to their
rectified average value, refer to Figure 41. If no capacitor CAVG
is connected, a very accurate full-wave rectified waveform
appears at the output and is converted to the average rectified
value of the ac input if a capacitor is connected to Pin CLPF. In
practice, a minimum capacitance of 470 pF must be connected
at Pin CAVG to stabilize the internal loop. To enable both
modes of operation, insert a switch between capacitor CAVG
and Pin CAVG as shown in Figure 41.
AD8436 Data Sheet
Rev. A | Page 16 of 20
10033-141
AC IN
VCC
VEE
DC
OUT
10MΩ VEE
CAVG VCC
OBUFOUT
IGND
OBUFIN+
OBUFIN–
OBUFV+
OUTDNC
IBUFIN–
IBUFOUT
IBUFIN+
SUM IBUFV+
1
4
3
2
5
876 9
12
11
10
16
15
14
13
10µF
0.47µF
OGNDIBUFGN
CCF
470pF
19 18 1720
DNC
RMS
CLPF
3.3µF
0.1µF
CAVG
10µF
+
AD8436
DIS CONNECT ING CAV G DEFAUL TS T HE
COMPUTED RESULT T O AVERAGE-VALUE.
A MI NIMUM OF 470pF CAP ACIT ANCE IS
REQUIRED TO MAINTAIN STABILITY.
CAPACI TOR CAV G CO M P UTES THE M E AN
IN THE IMPLICIT RMS EXPRESSION. FOR
SMALL V ALUES OF CAV G, THE AC I NP UT
WAVEFORM WILL STILL BE FULLY
RECI TIFI E D AND AP P E AR AT T HE OUT P UT.
CAPACI TOR CLPF, IN CO NJUNCTION W IT H
THE INTERNAL 16kΩ OUTPUT RESISTOR
FILTERS THE RECTIFIED OUTPUT, YIELDING
THE AV E RAGE RECTI FI E D V ALUE.
Figure 41. Configuration for Average Rectified Value
AD8436 EVALUATION BOARD
The AD8436-EVALZ provides a platform to evaluate AD8436
performance. The board is fully assembled, tested, and ready to
use after the power and signal sources are connected. Figure 47
is a photograph of the board. Signal connections are located on the
primary and secondary sides, with power and ground on the inner
layers. Figure 42 to Figure 46 illustrate the various design details of
the board, including basic layout and copper patterns. These
figures are useful for reference for application designs.
A Word About Using the AD8436 Evaluation Board
The AD8436-EVALZ offers many options, without sacrificing
simplicity. The board is tested and shipped with a 10 μF averaging
capacitor (CAVG), 3.3 μF low-pass filter capacitor (C8) and a
0.1 μF (COPT) capacitor to optimize crest factor performance.
To evaluate minimum cost applications, remove C8 and C OPT.
The functions of the five switches are listed in Table 6.
Table 6.
Switch
Function
CORE_BUFFER Selects core or input for the input signal
INCOUP Selects ac or dc coupling to the core
SDCOUT Selects the output buffer or the core
output at the DCOUT BNC.
IBUF_VCC Enable or disables the input buffer
OBUF_VCC Enable or disables the output buffer
All the I/Os are provided with test points for easy monitoring
with test equipment. The input buffer gain default is unity; for
2× gain, install a 0603 0 Ω resistor at Position R5. For higher
IBUF gains, remove the 0 Ω resistor at Position RFBH (there is
an internal 10 kΩ resistor from the OBUF_OUT to IBUFIN−)
and install a smaller value resistor in Position RFBL. A 100 Ω
resistor establishes a gain of 100×.
Single supply operation requires removal of Resistor R6 and
installing a 0.1 μF capacitor in the same position for noise
decoupling.
AD8436 Data Sheet
Rev. A | Page 18 of 20
10033-147
Figure 47. Photograph of the AD8436-EVALZ
10033-148
TSUM
TACIN
VCC
VEE
GND5GND4GND3GND2
DC
OUT
TIBUFOUT
TIBFIN+
VEE
CAVG VCC
OBUFOUT
IGND
OBUFIN+
OBUFIN–
OBUFV+
OUTDNC
IBUFIN–
IBUFOUT
IBUFIN+
SUM IBUFV+
1
4
3
2
5
876 9
12
11
10
16
15
14
13
TCAVG
CORE
BUF
CORE
BUF
TOBFOUT
GND1
+
TDCOUT
GND6
SDCOUT
CIN
10µF
DCAC
TRMSIN
TIBFIN–
TOGND TOUT
TIGND
TOBUFIN+
TOBUFIN−
TOBUFV+
TIBUFV+
EN
EN
DIS
IBUF_VCC
DIS
TBUFGN
OGND
BUF
GAIN
CCF
+
VEE
+
19 18 1720
INCOUP
DNC
RMS
TCCF
AD8436
+
C1
10µF
50V
–40°C TO +125°C
C6*
2.2µF
C7*
1.5µF
C3
0.1µF
CAVG
10µF CCF
0.1µF
X8R
C4
0.1µF
CLPF
3.3µF
C5
0.47µF
R3*
8.06kΩ
R4*
0Ω
R8
0Ω
R7
0Ω**
R6
0Ω
R2
0Ω
R5
0Ω
R1
10MΩ
RFBL
DNI
RFBH
0Ω
C2
10µF
50V
–40°C TO
+125°C
–V
(GRN)
+V
(RED)
OBUF_VCC
*COM P ONENT S IN G RAY ARE S E LECTED BY THE USE R.
** REMOVE R7 FOR CORE-ONLY TESTS.
CORE_BUF
AC_IN
Figure 48. Evaluation Board Schematic
Data Sheet AD8436
Rev. A | Page 19 of 20
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD.
061609-B
BOTTOMVIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
1516
5
Figure 49. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
(CP-20-10)
Dimensions shown in inches
COMPLIANT TO JEDEC STANDARDS MO-137-AD
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
20 11
101
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0.64)
BSC
0.041 (1.04)
REF
0.010 (0.25)
0.006 (0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
8°
0°
COPLANARITY
0.004 (0.10)
0.065 (1.65)
0.049 (1.25) 0.069 (1.75)
0.053 (1.35)
0.345 (8.76)
0.341 (8.66)
0.337 (8.55)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
08-19-2008-A
Figure 50. 20-Lead Lead QSOP Package [RQ_20]
(RQ-20)
Dimensions shown in inches
AD8436 Data Sheet
Rev. A | Page 20 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8436ACPZ-R7 −40°C to +125°C 20-Lead Lead Frame Chip Scale [LFCSP_WQ] CP-20-10
AD8436ACPZ-RL −40°C to +125°C 20-Lead Lead Frame Chip Scale [LFCSP_WQ] CP-20-10
AD8436ACPZ-WP −40°C to +125°C 20-Lead Lead Frame Chip Scale [LFCSP_WQ] CP-20-10
AD8436JCPZ-R7 0°C to +70°C 20-Lead Lead Frame Chip Scale [LFCSP_WQ] CP-20-10
AD8436JCPZ-RL 0°C to +70°C 20-Lead Lead Frame Chip Scale [LFCSP_WQ] CP-20-10
AD8436JCPZ-WP 0°C to +70°C 20-Lead Lead Frame Chip Scale [LFCSP_WQ] CP-20-10
AD8436ARQZ-R7 −40°C to +125°C 20-Lead QSOP [RQ_20] RQ-20
AD8436ARQZ-RL −40°C to +125°C 20-Lead QSOP [RQ_20] RQ-20
AD8436ARQZ −40°C to +125°C 20-Lead QSOP [RQ_20] RQ-20
AD8436-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10033-0-7/12(A)
